Applications: ADC Performance is Critical
Transcript of Applications: ADC Performance is Critical
ISSCC 2008 T t i lISSCC 2008 T t i lISSCC 2008 Tutorial
Pipelined A/D Converters:
ISSCC 2008 Tutorial
Pipelined A/D Converters:Pipelined A/D Converters:
The Basics
Pipelined A/D Converters:
The Basics
Sunday 03 Feb 2008
Aaron Buchwald, PhD
“Seamlessly Blending Analog and Digital”
y
Applications: ADC Performance is CriticalApplications: ADC Performance is Critical
Dramatic improvement in converter performance is
required for emerging IEEE communication standards
Data converters will be a key enabling technology to
realize ICs at the appropriate power
Broadband Wireless
Disc DrivesMobile Phones
ADC
Base Stations Networking
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Architecture vs. Speed and ResolutionArchitecture vs. Speed and ResolutionBits
SAR18
20
16
14
Calibrated Pipeline
Pipeline
14
12 Folding
10
8
Flash
6
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100MS/s 1GS/s 10GS/s
Pipelined vs. Folding: A Personal HistoryPipelined vs. Folding: A Personal HistoryBits
12
The year was 1994The goal was 10-bits 50-MS/s for Cable TV
CMOS Folding
11
10
CMOS PipelineCMOS Folding
Interpolating Averaging
10
9
8
7
JSSC 1995
Tom Cho, Paul Gray
10mm2
JSSC 1997
Klaas Bult,
Aaron Buchwald
1mm2
ISSCC 1992
Pieter Vorenkamp
ISSCC 1993
Bill Colleran,
Phan & Abidi
Bi l
6
Bipolar2-step Pipelined
Folding Flash
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25MS/s 50MS/s 100MS/s
Pipelined ADCs Speed and ResolutionPipelined ADCs Speed and Resolution
6 75 8 9 10 11 12 13 14 15 16 17 18 19432
1.E+10
1.E+11
ISSCC 1997-2006
VLSI 1997-2006
ISSCC 2007
VLSI 2007
6 75 8 9 10 11 12 13 14 15 16 17 18 19432
6-12.5 ENOB
6-14 bits
1.E+08
1.E+09
]
S/H with 1psrms jitter
Pipelined
2 500MS/s
1.E+06
1.E+07
BW
[H
z] 2-500MS/s
1 E+04
1.E+05
1.E+03
1.E+04
10 20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
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S [d ]
B. Murmann, "ADC Performance Survey 1997-2007," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
What is a “Pipelined” ADCWhat is a “Pipelined” ADC
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What is a “Pipelined” ADCWhat is a “Pipelined” ADC
Switched CapacitorSubranged
(overlapping / redundancy)
Residue
Amplification
Switched Capacitor
Amplification
Usually
but not
Pipelined Self-Similarnecessarily
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Efficient Calculation Machine Similar to Systolic Arrays – FFT Butterfly Calculation
5-bit Flash: Ruler Analogy5-bit Flash: Ruler Analogy
How does the Human Brain
Perform 5-bit Quantization?
LSB = 1cm = 100-miles
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S c 00 es
15-bit Spatial Sub-Ranging ADC15-bit Spatial Sub-Ranging ADCsample
C
vi
ADC
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Coarse Estimate – Center - AmplifyCoarse Estimate – Center - Amplify
Avi
sample
VREF
Residue
VREF
+
-C
ADC
clk
REF
DAC
clk
REF
clk clk
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2nd-Stage Sub-range2nd-Stage Sub-range
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Repeat Centering and Residue AmplificationRepeat Centering and Residue Amplification
Stage-1vi
VREF
Residue
VREF
+
-C
ADC
clk
REF
DAC
clk
REF
clk clk
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Self SimilaritySelf Similarity
Stage-1vi
C
VREF
Residue
VREF
+
-
ADC
clk
DAC
clk
Matryoshka / Russian Nesting Dolls Fractal Geometry of Nature
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3rd-Stage Sub-range3rd-Stage Sub-range
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4th Stage - Features Large Enough to Quantize4th Stage - Features Large Enough to Quantize
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4-Stage 15-bit Pipeline ADC4-Stage 15-bit Pipeline ADC
ADCStage-1vi
Stage-2 Stage-3 4b
5b 5b 4b
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Challenges in Pipeline ADCs: Offsets & DACChallenges in Pipeline ADCs: Offsets & DAC
Avi +
sample
Residue
ADCVREF VREF
VREF
C -
DACADC
clkclk
clk
REF REF
clkclk
Limitations in accuracy due to
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Comparator Offsets & Non-Linearity in DAC
Challenges in Pipeline ADCs: Gain and Non-linearityChallenges in Pipeline ADCs: Gain and Non-linearity
A
C
vi +
-
sample
Residue
ADCVREF VREF
VREF
DACADC
clkclk
clk
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Limitations in accuracy due to gain errors and amplifier non-linearity
ADC = DAC + ComparisonADC = DAC + Comparison
Successive Approximation &
Relationship to Pipelined ADCs
Successive Approximation &
Relationship to Pipelined ADCs
“Seamlessly Blending Analog and Digital”
Signal vs. DAC Comparison: Inverse Transfer FunctionSignal vs. DAC Comparison: Inverse Transfer Function
Approximation Error
REFSIG VCV ˆSIGV +
-REFV
Digital Output Code
for 0DACC SIGV
CodeDigitalCclk
DAC Limits AccuracyDrive DAC to minimize error
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ADC accuracy depends on DAC
Successive Approximation ADC (SAR)Successive Approximation ADC (SAR)
SIGV +SIG
-
C
REFVclk
DAC
CSIGV
SA
R
clk
LOGIC
Use Feedback to Drive Error to ZeroSuccessive Approximation
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Successive Approximation
Iteratively change DAC code until error is minimized
ADC Basics: DAC Successive ApproximationADC Basics: DAC Successive Approximation
SIGV++++++
DAC
-REFV
DAC
-REFV
DAC
-REFV
DAC
-REFV
DAC
-REFV
DAC
-REFV
clk
DAC
0C
DAC
1C
DAC
2C
DAC
3C
DAC
4C
DAC
5C
LOGICSAR
DACs are identicalError contribution from each DAC affects performance equally
Full precision required at each node
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ADC Basics: DAC Binary WeightingADC Basics: DAC Binary Weighting
SIGV++++++
DAC
-32REFV
DAC
-16REFV
DAC
-8REFV
DAC
-4REFV
DAC
-2REFV
DAC
-REFV
clk
0C
DAC
1C2C
DAC
3C
DAC
4C
DAC
5C
LOGICSAR
DACs are Binary WeightedError contribution from DAC mismatch is scaled by reference
MSB DACs must have better matching than LSB DACs
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Binary Weighting Using Gain BlocksBinary Weighting Using Gain Blocks
SIGV+
-
+
-
+
-
+
-
+
-
+
-
REFVREFVREFVREFVREFVREFV
01234 aaaaa012345 aaaaaa 0123 aaaa 012 aaa 01aa 0a
clk
DAC
ˆ
DAC
ˆ
DAC
ˆ
DAC
ˆ
DAC
ˆ
DAC
ˆ
LOGIC
0C
SAR
1C2C3C4C5C
DACs are identical, but see different gain to outputError contribution from each DAC is proportional to gain in signal path
MSB DAC is most critical
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Binary Weighting with Distributed Gain (a0=1)Binary Weighting with Distributed Gain (a0=1)
SIGV++++++
5a4a 3a
2a 1a
-
REFV
-
REFV
-
REFV
-
REFV
-
REFV
-
REFV
clk
DAC
C
DAC
C
DAC
C
DAC
C
DAC
C
DAC
C
LOGIC
0C
SAR
1C2C3C4C5C
DACs are identical: Gain is DistributedMSB DAC most critical because it sees largest gain
Feed-forward path is now modular. All sections are identical
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Dominant Error SourcesDominant Error Sources
SIGV+
-
+
-
+
-
+
-
+
-
+
-
5a4a 3a
2a 1a
d
DAC
REFV
DAC
REFV
DAC
REFV
DAC
REFV
DAC
REFV
DAC
REFV0dn
1dn2dn3dn4dn5dn
clk
DAC
0C
DAC
1C
DAC
2C
DAC
3C
DAC
4C
DAC
5C
12345
0
2345
1
345
2
45
3
5
45IN
aaaaa
dn
aaaa
dn
aaa
dn
aa
dn
a
dndnd
Noise SummaryThe larger the gain at the input less the impact
of noise in distortion from subsequent stages
Dominant Noise Term is from input stage
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Dominant Noise Term is from input stage
Transition from Feedback-Based to PipelineTransition from Feedback-Based to Pipeline
SIGV++++++
5a4a 3a
2a 1a
-
REFV
-
REFV
-
REFV
-
REFV
-
REFV
-
REFV0C
1C2C3C4C5C
clk
DACDACDACDACDACDAC
Broken feedback
LOGICSAR
Feedback not allowed for pipeline designCan not afford to wait for signal to propagate down the chain
Coefficients must be set by Feed-forward path
Error Sources and Expression of Analog Output of DACs do not change
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Error Sources and Expression of Analog Output of DACs do not change
Problem is now is to set Coefficients without overflow of internal nodes
Adding Analog Delay Allows PipelineAdding Analog Delay Allows Pipeline
V 5a aSIGV
clk
5a+
-
VC
S/H+
-
VC
S/H4a
clk
DAC
REFV4C
DAC
REFV5C
Sample and Hold as an Analog DelayWith analog memory each section works on a single residue
Latency increases, but throughput is high with one complete
conversion per clock cycle
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ADCs in Feed-Forward Path Replace FeedbackADCs in Feed-Forward Path Replace Feedback
SIGV 5a++ 4a
clk
-
REFVREFV
S/H
-
REFVREFV
S/H
clk
DAC
REF
4CADC
REF
DAC
REF
5CADC
REF
Final result does NOT depend on feed-forward ADCsProvided error “e” is minimized, accuracy is identical to SAR-based ADC
Coarse ADC job is to get “close” and avoid overflow at intermediate nodes
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Simple 1-bit-per-stage
Pipelined ADC
Simple 1-bit-per-stage
Pipelined ADCPipelined ADCPipelined ADC
“Seamlessly Blending Analog and Digital”
Simple Radix-2 Pipelined ADCSimple Radix-2 Pipelined ADC
refV
IV Stage
n-1
Stage
n-2
Stage
n-3
Stage
1
Stage
0SH
1nD 2nD 3nD1D 0D
2nV1nV 3nV2V 1V
1n 2n 3n 1 0
A2nV
3V
CMP
refV
D
3nV
DAC
1-bit
3nD
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Voltage Sub-Ranges: No OverlapVoltage Sub-Ranges: No Overlap
Vref
refV
1
2
0
0
1
0
1
2
refV0
2
-Vref
ref
in
VV
ref
in
VV refin VV2 refin VV2
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2in
2in refin f
Residue Plot: Input to Residue Transfer FunctionResidue Plot: Input to Residue Transfer Function
Vres
Vref
-Vref
VrefVin
-Vref
No margin in Coarse ADCOffset of coarse ADC must be at full accuracy
No over-range margin in amplitude
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Radix-2 Pipelined ADC: Residue VoltagesRadix-2 Pipelined ADC: Residue Voltages
CMPDAC
1-bit
2IV SH
3D
ref3IN3 2 VDVV
DAC
2
2D
ref2ref3IN2 22 VDVDVV
CMPDAC
1-bit
2
2D
ref1ref2ref3IN1 222 VDVDVDVV
CMPDAC
1-bit1D
ref1ref2ref3IN1
0DCMP
DAC
1-bit
2ref0ref1ref2ref3IN0 2222 VDVDVDVDVV
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Slice Architecture: Pipelined ADCSlice Architecture: Pipelined ADC
CMPDAC
1-bit
2IV SH
3D
DAC
2
2D
0123refIN0 2488
2DDDDVV
V
CMPDAC
1-bit
2
2D
8
CMPDAC
1-bit1D
1
2
4
8
10123
ref
IN DDDDV
V
0DCMP
DAC
1-bit
2
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1-bit-per-Stage ADC with Input Near Zero1-bit-per-Stage ADC with Input Near Zero
Vref
refV
1
2
0
0
1
0
Signal
0
2
refV
-Vref
Chosen Residue
2
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Voltage Sub-Ranges: Comparator OffsetVoltage Sub-Ranges: Comparator Offset
Vref
refV
1
2
Offset
0
0
1 1
Signal
0
2
refV
-Vref
Chosen Residue
2
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Chosen Residue
Clipping: Major Error
RedundancyRedundancy
“Seamlessly Blending Analog and Digital”
RedundancyRedundancy
“Seamlessly Blending Analog and Digital”
Long Division: Natalya’s 6th Grade HomeworkLong Division: Natalya’s 6th Grade Homework
IV Stage
4
Stage
3
Stage
2
Stage
1
Stage
0SH
refV
3V4V 2V 1V
3
1 0
. 1 5 6
4D 3D2D 1D 0D
Redundancy / Overlap
4 0 1 5 64 0 9 6 . 0 0 0 1 0 2
3 0 6
1 0 3 6 residue
= 4 0 . 1 5 6
1 0 2 0
1 6 0
1 0 2
5 8 0
5 1 0
7 0 0
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6 1 2
8 2
Voltage Sub-Ranges: With OverlapVoltage Sub-Ranges: With Overlap
Vref
refV
2
11
refV
01
10
4
refV
2
refV00
4
f
2
-Vref
refin VV2 refin VV2inV2
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refin fin
Residue Plot: with RedundancyResidue Plot: with Redundancy
Vres
Vref
2
refV
-Vref
VrefVin
2
refV
-Vref
2
Redundancy Relaxes Coarse ADC RequirementsOffset of coarse ADC need only be accurate to Vref/4
Half of the voltage swing is used for over-range
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Voltage Sub-Ranges: With OverlapVoltage Sub-Ranges: With Overlap
Vref
refV
2
11
refV
01
10
4
refV
2
refV00
4
f
Signal2
-Vref
refin VV2
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refin
Voltage Sub-Ranges: Offset Margin +/-Vref/4Voltage Sub-Ranges: Offset Margin +/-Vref/4
Vref
refV
2
11
refV
01
10
4
refV
2
refV00
4
Signal2
-Vref
inV2
Offset
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in
Residue Plot: with RedundancyResidue Plot: with Redundancy
Vres
Vref
2
refVoffset
margin
-Vref
VrefVin
2
refV
g
-Vref
2
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Voltage Sub-Ranges: 2-bit (4x Gain)Voltage Sub-Ranges: 2-bit (4x Gain)
Vref
85 REFV
83 REFV
0
8REFV
8REFV
83 REFV
85 REFV
-Vref
3/4
2/4
1/4
4V
r e
4V
re
4V
re
4V
re
4V
re
4V
re
4V
re
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Vre
f
Vre
f
Vre
f
ef +
3
ef +
2
ef +
1
ef +
0
ef -
1
ef -
2
ef -
3
Voltage Sub-Ranges: 3-bit (8x Gain)Voltage Sub-Ranges: 3-bit (8x Gain)
Vref
169V1611 REFV1613 REFV
-
-7/8
Vr
167 REFV
163 REFV16V
165 REFV
169 REFV -4/8
Vre
f
ref
016REFV16REFV163 REFV165 REFV167V
4/8
V
V
167 REFV169 REFV1611 REFV1613 REFV
7/8
Vre
f
Vre
f
-Vref 8V
ref +
3
8V
ref +
2
8V
ref +
1
8V
ref +
0
8V
ref -
1
8V
ref -
2
8V
ref -
3
8V
ref +
4
8V
ref +
5
8V
ref +
6
8V
ref +
7
8V
ref -
4
8V
ref -
5
8V
ref -
6
8V
ref -
7
Overhead is high (2x)Only using half the available voltage range
Can reduce redundancy and use more range
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Can reduce redundancy and use more range
at expense of potential over-range
Less than 1-bit-per-stage
Pipelined ADC
Less than 1-bit-per-stage
Pipelined ADCPipelined ADCPipelined ADC
“Seamlessly Blending Analog and Digital”
Voltage Sub-Ranges: Single ComparatorVoltage Sub-Ranges: Single Comparator
Vref
AVref
11
Full Scale Sub-Range Re-center Gain back to Full Scale
1
A
refVA
12
0
0
1
0
1
0
refVA
12
1
-Vref
refin VAAV 1A
VV refin
11
AVref
11
2forHolds A
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fA
Voltage Sub-Ranges: Example A=1.6Voltage Sub-Ranges: Example A=1.63
Vref
8
3refV
83refin VV 5
3refinin VVV
1
8
0
0
14
refV
0
1
4
refV
0
3
4
-Vref
83refin VV5
3
5
8refin VV
8
3refV
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55refin
Radix vs. MarginRadix vs. Margin
1.90
2.00
Gain Per Stage
1.70
1.80
n (
Ra
dix
)
1 50
1.60
Re
sid
ue
Ga
in
Trade-Off Redundancy vs.
EfficiencyOffset of coarse ADC need only be
accurate to Vref/4 at gain = 1 6
1.40
1.50R
accurate to Vref/4 at gain 1.6
1.20
1.30
0.00 0.20 0.40 0.60
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Comparator Margin
Pipelined ADC: Radix Less Than TwoPipelined ADC: Radix Less Than Two
CMPDAC
1-bit
A3IV SH
3D
DAC
A2
2DCMP
DAC
1-bit
A1
2D
1
1
12
123
0123
123ref
IN
A
AA
AAA
DDDDAAAV
V
CMPDAC
1-bit
1
1D1
0DCMP
DAC
1-bit
A0
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Doesn’t Need to Be Switched Cap Doesn’t Need to Be Switched Cap
Ken Poulton, Robert Neff, et al. , ISSCC 2002, ISSCC 2003
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Successive Approximation From Pipelined IdeasSuccessive Approximation From Pipelined Ideas
Switched Capacitor Implementation
Charge Sharing Principle
Vref
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Successive Approximation ADCSuccessive Approximation ADCvrefp
BBBB
vip
vrefnp
BBBB
+ -
AAA
C1 C2
A
CnC3
vacm
Ae+ -
Lo
gic
Ae
- +
C1 C2 CnC3
AA
BB
A
BB
vin
BB
A
BB
clk
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vrefnvrefp
SAR with RedundancySAR with Redundancy
8Radix 2
n2
1
2
4
8
111016
1
ref
IN
V
V
No Redundancy
Full settling on
each step
Once mistake is
made, you can’t
recover 1recover
10-bit SAR
10 steps
10*ln(2) time constants
69 tauSignal
6.1
6.1
6.1
0000101
2
3
4
5
5
INVRadix 1.6
69 tau
n6.1
1
6.1
6.1000010
6.125
0
ref
n
nVWith Redundancy
3-bit settling
Overlap of ranges
allows for recovering
from mistakes
Si l
10-bit SAR
14 steps
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Signal 3*ln(2) time constants
30 tau
Example Design
Switched Capacitor Based
Example Design
Switched Capacitor Based
10-bit
200-MS/s
10-bit
200-MS/s
“Seamlessly Blending Analog and Digital”
Summary of Design IssuesSummary of Design Issues
Capacitor size based on KT/CC total = 225fF
Opamp open-loop gainp p p p gAo < 60dB
Calibration or correlated double-sample can reduce gain requirement
JitterClock jitter < 1 25psClock jitter < 1.25ps
No Sample & HoldNeed care to ensure MDAC and CADC synchronization
2-Stage opampD l d f db k lDual common-mode feedback loop
Tail source on second-stage
2 bits per stage3-bit flash
Coarse ADCUse built-in reference to reduce capacitive load
Will require calibration
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Physical LimitationsPhysical LimitationsPhysical LimitationsPhysical Limitations
“Seamlessly Blending Analog and Digital”
ADC Basics: 3-Input DeviceADC Basics: 3-Input Device
REFVINV Clk
+-
V
ADC Core
REFV
INV
Clk
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ADC Performance depends on ALL THREE inputs
Thermal Noise LimitationsThermal Noise Limitations
nv
C
n
R
rv
sRCsVsV rn
1
1)()(
Transfer Function
Output Noise Spectral Density
2
21
1)()(
fRCjfSfS rn
21)()(
fRCjff rn
2141 kTkTR
Expected Noise Power
2
00 20 2
2 2
1
1
2
4
21
14 d
C
kTdx
xRC
kTRdf
fRCkTRvn
kTv
2Result is independent of R.
Implies a more f ndamental
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Cvn
Implies a more fundamental
physical law
Equipartition TheoremEquipartition Theorem
C
nvCircuit
In
Thermal
EquilibriumEquilibrium
Expected Value of Thermal Energy for 1-degree of freedomp gy g
kTE2
1
Expected Value of Electrical Energy Stored on Capacitor
2
2
1nCvE
2
Expected Value of Squared Voltage on Capacitor
kTv
2
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Cvn
RMS Quantization NoiseRMS Quantization Noise
LSB1 V
Quantization Error Probability Density Function
Uniform assumption for
Q ti ti i
LSB2
1V LSB
2
1V
Quantization noise
LSBLSB 289.012
VV
VQ rms Quantization Noise
12
V Where V is the full scale
122
PP
nQ
VV
Where VPP is the full-scale
Voltage and n is the # of bits
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Noise Requirements: Example CalculationNoise Requirements: Example Calculation
122
1
2
12
22
AMP
2 LSBKTT
V
Assume equal contribution of noise dominated from AMP and KT/C.
1 LSBLSB VV
7122AMP KT
For 1-Vpp input and a 10-bit ADC with a bandwidth of 1-GHz. The LSB is
approximately 1-mV so that the rms noise requirement of the amp andapproximately 1 mV so that the rms noise requirement of the amp and
KT/C is 144uV
2V144
KT2V144
C2
EQ V1444KTBR
fF225C 1100EQR
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Noise Requirements: 12-bit ExampleNoise Requirements: 12-bit Example
F 1 V i t d 12 bit ADC Th LSB i i t l 0 25 VFor 1-Vpp input and a 12-bit ADC. The LSB is approximately 0.25-mV so
that the rms noise requirement of the amp and KT/C is 36uV
KT 2V36
C
KT2
EQ V364KTBR
pF63C 70RpF6.3C 70EQR
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12-bit Example: High Vref and High Vdd12-bit Example: High Vref and High Vdd
For 2-Vpp input and a 12-bit ADC. The LSB is approximately 0.5-mV so
that the rms noise requirement of the amp and KT/C is 72uV
2V72
C
KT2
EQ V724KTBR
fF900C 275EQR
For High Accuracy ADCsThe higher the Vref the better
This requires large voltage (High Vdd is essential)q g g ( g )
gm of 1/70 requires a lot of current
Good to have gain in Sample & Hold to ease noise requirements of MDAC
Can give up some SNR performance to ease power requirements: Giving up
an additional 0.5-bits of noise cuts the cap in half and doubles Req
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Minimal Capacitance for a Given Ideal SNRMinimal Capacitance for a Given Ideal SNR
122n
pp
rms
V
C
kTvThermal Noise set to Quantization Noise
Minimum value of input capacitancen
ppV
kTC 2
22
12
1.E+03
1.E+05
3.6pF @ 80dB
1.E-01
1.E+01
Cap
ac
ita
nc
e(p
F)
Process limited signal
Capacitance ~ 50fF
1.E-05
1.E-03 Corner ~ 9-10bits
67 MOBIUS Confidential
1.E-07
10 20 30 40 50 60 70 80 90 100 110 120
SNR [dB] (no quantization)
67
Noise Limited Corner: Normalized Energy vs. SNRNoise Limited Corner: Normalized Energy vs. SNR
[6] B. Murmann, T. Sundstrom and Christer Svenson,
“On the Power Dissipation of High-Speed Analog-to-
Digital Converters," IEEE Trans. Circuits and Systems,Digital Converters, IEEE Trans. Circuits and Systems,
[to be published] submitted 26 Nov 2007.
Normalizing ADC power by the KT/C Limit (Ps) is useful
Clearly shows State of the Art with respect to Ps
Shows best high SNR ADCs ~ 100x Thermal Power Limit
68 MOBIUS Confidential68
Identifies noise limited circuit corner at roughly 11-bits
Limitations Due to Timing Jitter for Sine InputLimitations Due to Timing Jitter for Sine Input
)(2sinPP ttfV
t )(2sin2
in ttft
VPPV
tt
VV
t
]2cos[)( inPPin tfVfttV
69 MOBIUS Confidential
][)( inPPin ff
Expression for SNR due to JitterExpression for SNR due to Jitter
t
VPPV
22)(2sin
2
PP
2
inPP V
ttfV
avgVinrms
222]2[cos PP
inin
2
PPin
VtftfavgVftV rmsrmsrms
22
V 1rms
inrms
rms tfSNRV
Vin2
1
70 MOBIUS Confidential
Jitter Requirement for 10-bitJitter Requirement for 10-bit
t
VPPV SNR due to Quantization = 6.02(10) + 1.76 ~ 62dB
rmstfdB
in262
1
( )
fin = Nyquist @ fs =200-MHz
SNRSNR
Tt srms
ns5
ps26.1rmst
71 MOBIUS Confidential
prms
ADC Speed and ResolutionADC Speed and Resolution
1.E+10
1.E+11
ISSCC 1997-2006
VLSI 1997-2006
ISSCC 2007
VLSI 2007
1.E+08
1.E+09
]
S/H with 1psrms jitter
Pipelined
1.26ps
1.E+06
1.E+07
BW
[H
z]
1 E+04
1.E+05
1.E+03
1.E+04
10 20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
72 MOBIUS Confidential
S [d ]
B. Murmann, "ADC Performance Survey 1997-2007," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
Circuit Implementation
Switched Capacitor Based
Circuit Implementation
Switched Capacitor Based
10-bit
200-MS/s
10-bit
200-MS/s
“Seamlessly Blending Analog and Digital”
Pipelined ADC ArchitecturePipelined ADC Architecture
refV
IV Stage
n-1
Stage
n-2
Stage
n-3
Stage
1
Stage
0SH
1nD 2nD 3nD1D 0D
2nV1nV 3nV2V 1V
1n 2n 3n 1 0
A2nV
3VrefV
D
3nV
DACADC
3nD
74 MOBIUS Confidential
Thick Oxide vs. Thin OxideThick Oxide vs. Thin Oxide
Vdd = 2.5V
2
1
VC
2
ppV
Doubling voltage swing will reduce
Capacitive load by factor of 4x
Vdd = 1.2V
Capacitive load by factor of 4x
CMFB CMFB
75 MOBIUS Confidential
ScalingScaling
CC
A
C
2A
C
IV A A A
2 Noise contribution (input referred) of each stage is equal
1 Noise contribution is reduced by for each stage2Recommended scaling [1,2]
[1] Y. Chiu, "High-Performance Pipeline A/D Converter Design in Deep-
Submicron CMOS," PhD Dissertation, UC Berkeley,2004.
[2] D W Cline and P R Gray "A power optimized 13-b 5 MSamples/s
76 MOBIUS Confidential
[2] D. W. Cline and P. R. Gray, A power optimized 13-b 5 MSamples/s
pipelined analog-to-digital converter in 1.2µm CMOS," IEEE J. Solid-
State Circuits, vol. 31, no. 3, pp. 294-303, March 1996.
Open-Loop DC Gain RequirementOpen-Loop DC Gain Requirement
IV A0 OV
Closed loop Gain Accuracy Required Scales with Gain
0
11
1
1 AA
AA o
Closed loop Gain Accuracy Required Scales with Gain
00A
01 AAo
Normalized Gain Error
1
Closed Loop Gain Independent of
1
0
1
A
n
o
A 21
0
[3] 30.1 An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting
77 MOBIUS Confidential
[ ] g g
and an Opamp with 30dB Loop Gain
1:30 PM
B. Gregoire, U-K. Moon
Sample & Hold: Merged or SeperateSample & Hold: Merged or Seperate
No SHA: Total Input Referred Noise Power
22
nTOT vvADC
IV
C nTOT
SHA: Input Referred Noise Power
nv
222
ADCSHTOT vvv
p
IV ADCSH
2C
SHv ADCv2C
To achieve KT/C Noise Performance with No SHA2
v
SHv ADC
2
22 nADCSH
vvv
kTkTkT
Total Capacitance Increases with SHA by 4x
Total power increase 2-4x}78 MOBIUS Confidential
CCC 22}
Pipelined ADC with Merged Sample & HoldPipelined ADC with Merged Sample & Hold
+
-
IV
DAC
REFV
5CCADC
REFV
MDAC
MDAC
DACCADC MDAC
CADC
S li i t lSampling occurs in two places
Dual sampling must be synchronized to avoid skew
[5] 12.6 A 14b 100MS/s Pipelined ADC with a Merged Active S/H and
First MDAC 11:15 AM
[4] I. Mehr and L. Singer, “A 55-mW 10-bit 40-Msample/s Nyquist-rate
CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, pp. 318–325, Mar.
2000.
79 MOBIUS Confidential
B. Lee, B. Min, G. Manganaro, J. W. Valvano
Number of Bits Resolved per Stage: TauNumber of Bits Resolved per Stage: Tau
fV
IV Stage
1
Stage
2
Stage
3
Stage
n-1
Stage
n
refV
2V1V 3V2nV 1nV
1 2 3 n-1 n
1D 2D 3D 1nD nD
Closed loop time constant of MDAC amplifierClosed-loop time constant of MDAC amplifier
L CACCC 1211
2C
gm
mm
LL
m g
C
g
AC
CC
CCC
g
1
21
21 ;1
21
2
CC
C
1C LC
Feedback Factor
Load is reduced by scaling CACL
ACC 11 With scaling tau is roughly
Independent of gain
li htl f t ith ll t i
Load is reduced by scaling CACL
80 MOBIUS Confidential
mm gg slightly faster with smallest gain
Number of Bits Resolved per Stage: SettlingNumber of Bits Resolved per Stage: Settling
fV
IV Stage
1
Stage
2
Stage
3
Stage
n-1
Stage
n
refV
2V1V 3V2nV 1nV
1 2 3 n-1 n
1D 2D 3D 1nD nD
settling of MDAC amplifier
)2ln(nts
2 or 3 bits per stage is best choice
Shown in [1,2]
Agrees with survey of published ADCs
Beyond 3 bits the coarse flash
for A=2
3 C
for A=4
7 C
[1] Y. Chiu, "High-Performance Pipeline A/D Converter
Design in Deep- Submicron CMOS," PhD Dissertation,
UC Berkeley,2004.
[2] D W Cline and P R Gray "A power optimized 13 b
Beyond 3 bits, the coarse flash
becomes problematic)2ln(9
2
32
mg
Ct
Ct 36.92
)2ln(84
74
mg
Ct
Ct 7.94
81 MOBIUS Confidential
[2] D. W. Cline and P. R. Gray, A power optimized 13-b
5 MSamples/s pipelined analog-to-digital converter in
1.2µm CMOS," IEEE J. Solid- State Circuits, vol. 31, no.
3, pp. 294-303, March 1996.
mg2
mg4
Two-Stage Amplifier with Dual CMFBTwo-Stage Amplifier with Dual CMFB
k k
CMFB1 CMFB2
Reduced swing due to tail source
dual diffpair has advantages
common-mode does not affect bias
[7] A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS
[6] A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR
at Nyquist Input
Wenhua Yang, Dan Kelly,Iuri Mehr, Mark T. Sayuk, and Larry Singer,
IEEE JSSC, vol. 36, no. 12, Dec 2001. pp 1931-1936.
82 MOBIUS Confidential
[ ] g p p p p g
Andersen, T.N.; Hernes, B.; Briskemyr, A.; Telsto, F.; Bjornsen, J.; Bonnerud, T.E.; Moldsvor, O.
Solid-State Circuits, IEEE Journal of
Volume 40, Issue 7, July 2005 Page(s): 1506 - 1513
Pipelined ADC Switched Capacitor MDACPipelined ADC Switched Capacitor MDAC
++
-
VV
MDAC
IV
DAC
REFV
5CCADC
REFV
MDAC
CADCCADC
MDAC can be implemented efficiently as a
Switched Capacitor CircuitSwitched Capacitor Circuit
83 MOBIUS Confidential
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -
C/4 C/4 C/4 C/4
AeBe - +
A
B
A
BB
A
B
A
BB
vin
84 MOBIUS Confidential
vrefbvreft
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -
Sample the InputOpamp reset not shown
C/4 C/4 C/4 C/4
AeBe - +
A
B
A
BB
A
B
A
BB
vin
85 MOBIUS Confidential
vrefbvreft
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -
Top-Plate Switchingminimize signal dependent
charge injection
C/4 C/4 C/4 C/4
AeBe - +
g j
A
B
A
BB
A
B
A
BB
vin
86 MOBIUS Confidential
vrefbvreft
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -
Release Bottom PlateNon-overlapping clocks
C/4 C/4 C/4 C/4
AeBe - +
A
B
A
BB
A
B
A
BB
vin
87 MOBIUS Confidential
vrefbvreft
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -
Subtract Reference and
Multiply by 2xDecision directed by coarse ADC
C/4 C/4 C/4 C/4
AeBe - +
Decision directed by coarse ADC
A
B
A
BB
A
B
A
BB
vin
88 MOBIUS Confidential
vrefbvreft
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -
Multiply by 2xDecision directed by coarse ADC
C/4 C/4 C/4 C/4
AeBe - +
A
B
A
BB
A
B
A
BB
vin
89 MOBIUS Confidential
vrefbvreft
1-bit MDAC Stage1-bit MDAC Stagevreft
BBB BBB
vip
vrefb
AA AA
C/4 C/4 C/4 C/4
B + -Ae
Be
vacmvocm
+ -Add Reference and Multiply
by 2xDecision directed by coarse ADC
C/4 C/4 C/4 C/4
AeBe - +
y
A
B
A
BB
A
B
A
BB
vin
90 MOBIUS Confidential
vrefbvreft
Opamp Sharing: AdjacentOpamp Sharing: Adjacent
CC
IV
A2A
C
IV
A A AA
Shared on Alternate Clock PhasesShared on Alternate Clock Phases
91 MOBIUS Confidential
Opamp Sharing: Ping-PongOpamp Sharing: Ping-Pong
CC
A
C
2A
C
A A A
IV
A A A
C 2A
C
92 MOBIUS Confidential
C A
Opamp Sharing: Ping-PongOpamp Sharing: Ping-Pong
CC
CA
2A
C
IV A A A
C
C A
C 2A
C
All Opamps Shared on Alternate Clock PhasesRequires dual cap arrays
Incomplete settling causes signal dependant distortion
93 MOBIUS Confidential
Incomplete settling causes signal dependant distortion
Coarse ADCCoarse ADC
Vref
R Ladder SC Reference Gen, Abo [8] Built-in Mismatch
IV vacm
A
vipvrefp
BA
B
3CC
[12.3] A 150MS/s 133µW 7b ADC in 90nm
Digital CMOS Using a Comparator-Based
Asynchronous Binary-Search Sub-ADC
9:30 AM
G. Van der Plas, B. Verbruggen
Ae-
Ae+
3CC
vacm
clk
vacm
A
vipvrefp
BA
B
3CC
-Vref
p
Static Power dissipation Adds load to MDAC
Cap ratios get big beyond 2-3
Lowest power
Needs calibration
94 MOBIUS Confidential
p g g y
bits per stage
Design Issues: Advanced ConceptsDesign Issues: Advanced Concepts
B t t d it hBootstrapped switch
Not needed at 10-bits, but necessary beyond, Abo [8], Hui Pan [9]
Opamp Sharing – Ping PongOpamp Sharing Ping Pong
Use dual cap array to utilize opamp at all times, Gupta [10]
Be careful for charge sharing (cross-talk, or ISI)
Adaptive biasing
Power dissipation scaled optimally with sample rate, Geelen [11]
Time InterleavingTime Interleaving
Poulton [12], Gupta [10]
C lib i
Paradigm shift
Calibration
Big improvements in performance and huge power reduction
Boris Murmann, Ian Galton, Paul Gray, Steve Lewis, Bang Sup Song
95 MOBIUS Confidential
and more ….
Advanced Concepts ReferencesAdvanced Concepts References
[8] A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
Abo, A.M.; Gray, P.R.
Solid-State Circuits, IEEE Journal of
Volume 34, Issue 5, May 1999 Page(s):599 - 606
[9] A 3.3 V, 12b, 50MSample/s A/D converter in 0.6 µm CMOS with over80 dB SFDR
Hui Pan Segami, M. Choi, M. Jing Cao Hatori, F. Abidi, A.
JSSC, vol. 35, issue 12, dec 2000, pp. 1769-1780JSSC, vol. 35, issue 12, dec 2000, pp. 1769 1780
[10] A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High
Bandwidth Scalable Time-Interleaved Architecture
Gupta, S. K.; Inerfield, M. A.; Wang, J.
Solid-State Circuits, IEEE Journal of
Volume 41 Issue 12 Dec 2006 Page(s):2650 - 2657Volume 41, Issue 12, Dec. 2006 Page(s):2650 - 2657
[11] A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined
ADC with 0.5pJ/Conversion-Step, G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor, R. Verlinden
IEEE ISSCC, Digest of Tech Papers, feb 2006, paper # 12.1
[12] A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS[12] A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS
Poulton, K.; Neff, R.; Setterberg, B.; Wuppermann, B.; Kopley, T.; Jewett, R.; Pernillo, J.;
Tan, C.; Montijo, A. Solid-State Circuits Conference, 2003. Digest of Technical Papers.
ISSCC. 2003 IEEE International Volume , Issue , 9-13 Feb. 2003 Page(s): 318 - 496 vol.1
96 MOBIUS Confidential
BooksBooks
Digitally Assisted Pipeline ADCs
Murmann & Boser
Analog Integrated Circuit Design
Johns & Martin
CMOS Analog
Circuit Design:
Allen & Holberg
DataData
Converters
Franco
Maloberti
97 MOBIUS Confidential
BooksBooks
Data Conversion System Design
Behzad Razavi
CMOS Integrated Analog-to-Digital and
CDigital-to-Analog Converters
Rudy van de Plassche
CMOS Data Converters forCMOS Data Converters for
Communications
Gustavsson, Wikner and Tan
98 MOBIUS Confidential
BooksBooks
CMOS Mixed-Signal Circuit Design
R. Jacob Baker
The Data Conversion Handbook
Walt Kester
Analog Design Essentials:
Willy Sanseny
Analog Design
F CMOS VLSIFor CMOS VLSI
System
Franco Maloberti
99 MOBIUS Confidential
Thank YouThank You
Thanks to Steve Lewis [13] for inventing the pipelined ADC and countless othersThanks to Steve Lewis [13] for inventing the pipelined ADC and countless others
researchers and designers for years of continued improvement
[13] S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to digital
converter,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961,
M 1987
“Seamlessly Blending Analog and Digital”
Mar. 1987.