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Product Planning & Application Engineering The Leader in Memory Technology ELECTRONICS 1 APPLICATION NOTE for NAND Flash Memory (Revision 2.0) Memory Product & Technology Division 1999. 12. 28

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APPLICATION NOTE for NAND Flash Memory

(Revision 2.0)

Memory Product &Technology Division

1999. 12. 28

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TABLE OF CONTENTS

ยก รก INTRODUCTION

1. SYSTEM INTERFACING1-1. NAND Flash Architecture1-2. Designing for Systems with O/S1-3. Designing for O/S-less System1-4. ECC Design Guide1-5. Development Tool

2. INVALID BLOCK(S) MANAGEMENT2-1. Identifying Initial Invalid Block(s)2-2. Management of Additional Invalid Block(s)2-3. Wear- Leveling Algorithm2-4. Data Retention2-5. Effect of P/E Cycling on Performance

3. PROGRAM/ERASE ALGORITHM3-1. Erase Algorithm3-2. Program Algorithm3-3. Status Read Operation3-4. Partial Page Program

4. OPERATING WITH COMMANDS4-1. Prohibition of Unspecified Commands4-2. Pointer Control for '00H', '01H', '50Hโ€™4-3. Device Status after Read/Program/ Erase/Reset and Power-on4-4. Acceptable Commands after Sequential Input Command of '80Hโ€™

5. UTILIZING THE DEVICE IN THE SAME SYSTEM DESIGN5-1. Pin Assignment(4Mb,8Mb,16Mb, 32Mb,64Mb)5-2. Pin Assignment(128Mb,256Mb)5-3. Device ID Information5-4. Addressing Map : 4Mb ~ 256Mb5-5. Specification Comparison : 4Mb ~ 256Mb5-6. Upgrading to 512Mb and 1Gb

6. HARDWARE DESIGN CONSIDERATIONS6-1. Acceptable Don`t-Care Area in Each Operation6-2. VccQ/ Vcc Power Configuration6-3. Data Protection6-4. R/B : Termination for the R/B Pin

7. MISCELLANEOUS7-1. Device Behavior for WP/ Signal7-2. Device Behavior for Excess Data Input Cycles7-3. Reset Operation

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ยก รก INTRODUCTION

1-1. NAND Flash Architecture

The need for nonvolatile data Flash Memory storage is ever increasing as thecomputer systems are shifting toward the mobile domain. Ruggedness, low powerconsumption, small and light forms are the obvious advantage of Flash-based storageover disk-based technology. As the bit-cost of Flash decreases continuously, the Flashstorage is poised to benefit the performance and functionality of portable platforms andequipment. NAND Flash is becoming the core of this Flash disk technology.

1. SYSTEM INTEFACING

This section provides a brief overview of implementing NAND Flash Memory into thesystem. It covers the following.

โ€ข NAND Flash Architectureโ€ข Designing for systems with O/Sโ€ข Designing for O/S-less systemsโ€ข ECC design guide

NAND Flash is optimized for storage applications. 16 neighboring cells are seriallyconnected without any contact area in-between to offer high density. Electron tunnelingis used for both programming and erasing, providing low power consumption. This cellstructure provides high scalability, making NAND Flash as the leader in the capacityrace. Because the electron tunneling occurs across the whole channel area of cell,charge trapping density per unit area is lower than other Flash technologies, resultingin superior endurance in Program/Erase cycles. Programming and reading areperformed on a sector or a page unit of 512 byte to emulate the popular sector size.

1.2 Designing for systems with O/S

Samsungโ€™s NAND Flash provides the highest performance and the most cost-effectivesolution for solid-state mass storage. When the host system has an operating system ,the Flash disk operates as one of standard peripheral components and thus beconnected to a host CPUโ€™s system bus through I/O interface like a IDE-disk drive.Since the host sees the Flash disk no different from hard disk drive, the native filesystem such as FAT (File Allocation Table) resides on the host operating system and atranslator of host requests to the Flash disk is needed. The translator, embedded intothe firmware of a controller directly interfacing Flash Memory, is commonly calledFlash-Translation-Layer (FTL) and includes the following features.

โ€ข Converts the sector addresses addressed by the host to physical addresses of Flash Memoryโ€ข Converts host requests into the programming/erasing algorithms of associated Flash technologyโ€ข Detects the error and replaces the encountered bad sectors with the good by mapping them out

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์„นํ„ฐ๋ฐฉ์‹ ์ฃผ์†Œ(ํ˜ธ์ŠคํŠธ์—์„œ์˜) -> ํ”Œ๋ ˆ์‰ฌ์˜ ์‹ค์ œ ์ฃผ์†Œ๋ฐฉ์‹์œผ๋กœ ๋ฐ”๊ฟ”์ค€๋‹ค. ํ˜ธ์ŠคํŠธ ์š”๊ตฌ -> ์‹ค์ œ ํ”Œ๋ ˆ์‰ฌ์—์„œ์˜ ์“ฐ๊ธฐ/์†Œ๊ฑฐ ๋™์ž‘์œผ๋กœ ์ „ํ™˜ํ•˜์—ฌ ์ค€๋‹ค. ์—๋Ÿฌ ๊ฐ์ง€,๋ฐฐ๋“œ์„นํ„ฐ ๊ต์ฒด-> ๊ทธ ๋‚ด์šฉ๋“ค์„ ๋งตํ•‘์‹œ์ผœ ๋†“๋Š”๋‹ค.
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NOR-type Flash requires a very long erasing time. Block-erasure of NOR-type Flashtakes about several-hundreds of millisecond while less than 2 ms with NAND Flash. Toreduce the time overhead, FTL for NOR-type Flash normally includes the backgrounderasure and garbage collection. When data of a block needs to be updated, the block iscopied to another free or erased block with the updates. The new block is mapped asvalid and the old as deleted. The deleted blocks are not actually erased. As theremaining erased blocks are decreased and below the pre-defined limit, the deletedblocks need to be reclaimed as free by being erased. Since the erasing takes too muchtime, it is processed as background operation when the controller is free from othertasks. This reclaiming process is called garbage collection. Because of its fast erasingtime, the garbage-collection is not usually used with NAND Flash unless a very highperformance is required. Figure 1-1 shows a typical block diagram of Flash disk as I/Odevice.

FIG. 1-1 TYPICAL BLOCK DIAGRAM of FLASH DISK as I/O DEVICE

Controller (KS32P6632)

NAND Flashcomponents

Controller (KS32P6632)

Master-IDE Slave-IDE

South Bridge

MemoryFSB

PCI Bus

Host Bus

SystemControllerProcessor

1.3 Designing for O/S-less systems

When the Flash Memory is used as storage disk for embedded systems, FTLincorporating a complete file system is necessary. The translation table from logical tophysical address - necessary for FTL with O/S environment - is not necessary. ThusFTL could be in much smaller footprint. Figure 1-2 is a comparison in architecture ofFlash file system between for O/S system and O/S-less.

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NOR-type Flash requires a very long erasing time.
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To
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reduce the time overhead, FTL for NOR-type Flash normally includes the background
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erasure and garbage collection.
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NORํƒ€์ž… ํ”Œ๋ ˆ์‰ฌ๋Š” ์†Œ๊ฑฐ ์‹œ๊ฐ„์ด ๋งค์šฐ ๊ธธ๋‹ค. ์ˆ˜๋ฐฑ ๋ฐ€๋ฆฌ์„ธ์ปจ๋“œ(๋‚ธ๋“œ๋Š” 2๋ฏธ๋ฆฌ) ์‹œ๊ฐ„์ƒ์˜ ์˜ค๋ฒ„ํ—ค๋“œ๋ฅผ ์ค„์ด๊ธฐ์œ„ํ•ด nor์—์„œ๋Š” ๋ฐฑ๊ทธ๋ผ์šด๋“œ ์†Œ๊ฑฐ์™€ ์“ฐ๋ ˆ๊ธฐ์ˆ˜์ง‘๋ฐฉ์‹์„ ์“ด๋‹ค. ๋ธ”๋Ÿญ์˜ ๋‚ด์šฉ์„ ๊ฐฑ์‹ ํ•ด์•ผ๋  ๋•Œ free or erased๋ธ”๋Ÿญ์— ๊ฐฑ์‹ ๋œ ๋‚ด์šฉ์„ ์นดํ”ผํ•˜๋Š” ๋ฐฉ์‹์œผ๋กœ ์ˆ˜ํ–‰ํ•œ๋‹ค. ์ƒˆ๋ธ”๋Ÿญ์ด ๋งตํ•‘๋˜๊ณ  ์ด์ „๊ฑฐ๋Š” ์‚ญ์ œ๋œ๋‹ค.์‹ค์ œ๋กœ๋Š” ์‚ญ์ œ๋˜์ง€๋Š” ์•Š๋Š”๋‹ค. ๊ทธ๋ ‡๊ฒŒ ์†Œ๊ฑฐ๋˜๋Š” ๋ธ”๋Ÿญ์ด ์ผ์ •๋Ÿ‰์ด ๋˜๋ฉด ๊ต์ •ํ•˜์—ฌ ๋นˆ ๋ธ”๋Ÿญ์œผ๋กœ ๋งŒ๋“ ๋‹ค. ์†Œ๊ฑฐ๋Š” ๋งŽ์€ ์‹œ๊ฐ„์ด ๊ฑธ๋ฆฌ๋ฏ€๋กœ ์ปจํŠธ๋กค๋Ÿฌ๊ฐ€ ํ•œ๊ฐ€ํ•œ ์‹œ๊ฐ„์— ๋ฐฑ๊ทธ๋ผ์šด๋“œ ์ž‘์—…์œผ๋กœ ์ด๋ค„์ง€๊ฒŒ ๋œ๋‹ค. ์ด๊ฒƒ์„ garbage collection์ด๋ผ ๋ถ€๋ฅธ๋‹ค. ๋‚ธ๋“œ๋ฐฉ์‹ํ”Œ๋ ˆ์‰ฌ๋Š” ์†Œ๊ฑฐ ์‹œ๊ฐ„์ด ๋ฌด์ฒ™ ์งง์•„์„œ ๊ณ ์„ฑ๋Šฅ์„ ์š”๊ตฌํ•˜๋Š” ๊ฒฝ์šฐ์—๋ผ๋„ ์ด๋Ÿฐ ๊ฐ€๋น„์ง€์ปฌ๋ ‰์…˜์€ ํ•˜์ง€ ์•Š๋Š”๋‹ค.
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ํ”Œ๋ ˆ์‰ฌ๋ฉ”๋ชจ๋ฆฌ๊ฐ€ ์ž„๋ฒ ๋””๋“œ ์‹œ์Šคํ…œ์—์„œ ์ €์žฅ๋””์Šคํฌ๋กœ ์“ฐ์ธ๋‹ค๋ฉด, FTL์„ ํฌํ•จํ•œ ํŒŒ์ผ์‹œ์Šคํ…œ์ด ํ•„์š”ํ•˜๋‹ค. ๋…ผ๋ฆฌ์ฃผ์†Œ -> ์‹ค์ œ์ฃผ์†Œ์˜ ๋ณ€ํ™˜ ํ…Œ์ด๋ธ”์€ ํ•„์š”์น˜ ์•Š๋‹ค. (๋ฐ˜๋ฉด os ๋ฐฉ์‹์˜ ํ™˜๊ฒฝ์—์„œ๋Š” ํ•„์š”ํ•˜๋‹ค.) ๊ทธ๋ž˜์„œ FTL์˜ ํฌ๊ธฐ๊ฐ€ ์ž‘์•„์งˆ ์ˆ˜ ์žˆ๋‹ค. ๊ทธ๋ฆผ1-2์— O/S ๋ฐฉ์‹๊ณผ O/S-less ๋ฐฉ์‹์˜ ๋น„๊ต๊ฐ€ ์žˆ๋‹ค.
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FIG. 1-2 FILE SYSTEM COMPARISON for O/S and O/S-less SYSTEM

APPLICATION

NATIVE FILE SYSTEM

FTL

(Flash Translation Layer)

FLASH MEDIA

โ€ข Open/ Close Fileโ€ข Read/ Write Fileโ€ข Find/ Delete File

โ€ข Read/ Write Sector

โ€ข Flash Socket Control

APPLICATION

FTL

(Flash Translation Layer)

FLASH MEDIA

โ€ข Open/ Close Fileโ€ข Read/ Write Fileโ€ข Find/ Delete File

โ€ข Flash Socket Control

( O/S System ) ( O/S-less System )

For its implementations, host MCU interfaces Flash directly and executes FTL usingthe working RAM. The FTL is stored in the firmware ROM. Figure 1-3 illustrates atypical structure of Flash disk in embedded systems.

FIG. 1-3 FLASH DISK TYPICAL STRUCTURE in EMBEDDED SYSTEM

I/O Logic NAND Flashcomponents

CPU WorkingRAMMain Code

FTL

ROM

I/O LogicMay include ECC forhigh performance, oraltogether be mergedinto other ASIC

Host Bus

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The interface and associated timings for NAND Flash and the features of FTL need tobe customized depending on the CPU performance and system requirements. NANDFlash requires only eight I/Oโ€™s and five control clocks for operation. Standard WE/ andOE/ available from MCU may be also easily used for WE/ and RE/ of NAND Flash. CE/,CLE and ALE may be controlled by spare addresses. Because CE/ may be inactiveduring the sequential data-loading or burst-reading, interleaving between NAND Flashand other memory devices can be easily implemented. Spare 16 bytes of each page ofNAND Flash can be utilized for keeping block status information such as good or badstatus of each page, ECC parity and the number of P/E cycles. FTL for NAND Flashcan be developed by system developers to tailor the system need or can be purchasedfrom several companies including from M-Systems, Phoenix Technologies and Tokyo-Electron Device.

1.4 ECC Design Guide

To ensure highly reliable Flash disk, ECC is required for NAND Flash. One bit errorcorrection per each page or sector would serve the purpose given the failure modes oflong-term life test. Two types of failures could occur : write-failure or read-failure. Write-failure is the case when the programming of a page or erasing of a block returns thefailure status. This is easily detected by checking the write status bit from Flash. Read-failure is the case when the written data changes after the successful writing. Thefailure mode is single bit error, mostly due to leakage of the oxide surrounding floatinggate of cell. Hamming code ECC is recommended to recover the error. If the targetsystem has the right performance, the algorithm can be implemented in software. Areference algorithm can be found in the Samsung Flash web-site. Since it only requiresa few thousand gates, ECC may be integrated into other ASIC. A recommended blockdiagram is shown in Figure 1-4 where ECC block interfaces host MCU in parallel withNAND Flash, providing minimal footprint and flexibility for supporting multiple NANDFlash chips. The operating timing diagram is shown in Figure 1-5 and 1-6. VHDL modelof this reference architecture may be provided by Samsung. In addition, an ASIC forthis ECC is also available from Samsung.

MCU

ECC Chip

NAND Flash

FIG. 1-4 ECC BLOCK DIAGRAM

ECC chip executes only parity generation and Flash/ SmartMedia is directlycontrolled by MCU.

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write-failure
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Readfailure
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ํ”Œ๋ ˆ์‰ฌ๋””์Šคํฌ ์‹ ๋ขฐ์„ฑ ํ™•๋ณด๋ฅผ ์œ„ํ•ด ECC๊ฐ€ ํ•„์š”ํ•˜๋‹ค. -- ๋‘๊ฐ€์ง€ ํ˜•ํƒœ์˜ ์‹คํŒจ๋ชจ๋“œ๊ฐ€ ์žˆ๋‹ค. ์“ฐ๊ธฐ์‹คํŒจ, ์ฝ๊ธฐ์‹คํŒจ ์“ฐ๊ธฐ์‹คํŒจ๋Š” ํŽ˜์ด์ง€์“ฐ๊ธฐ๋‚˜ ๋ธ”๋Ÿญ์†Œ๊ฑฐ๋ฅผ ํ•œ ํ›„ failure status๋ฅผ ๋ณด์ผ๋•Œ์ด๋‹ค. ์ฝ๊ธฐ์‹คํŒจ๋Š” ์˜จ์ „ํ•œ ์“ฐ๊ธฐ๊ฐ€ ์ผ์–ด๋‚œ ํ›„์— ๊ทธ ์“ฐ์—ฌ์ง„ ๋ฐ์ดํ„ฐ๊ฐ€ ๋ฐ”๋€๊ฒฝ์šฐ์ด๋‹ค. ๋Œ€๊ฐœ์˜ ์˜ค๋ฅ˜๋Š” ์‹ฑ๊ธ€๋น„ํŠธ์—๋Ÿฌ์ธ๋ฐ ์ด๊ฒƒ์€ ํŠน์ •์…€์˜ ํ”Œ๋กœํŒ…๊ฒŒ์ดํŠธ ์ฃผ๋ณ€์˜ ์˜ฅ์‚ฌ์ดํŠธ(์‚ฐํ™”๋ฌผ) ๊ฒฐํ•์œผ๋กœ ์ผ์–ด๋‚œ๋‹ค.(๋ญ”๋ง์ด์ง€๋Š” ๋ชจ๋ฅด๊ฒ ๋‹ค). ํ—ค๋ฐ์ฝ”๋“œ ๋ฐฉ์‹์ด ์—๋Ÿฌ๋ณต๊ตฌ์— ์“ฐ์ธ๋‹ค. ํƒ€๊ฒŸ์‹œ์Šคํ…œ์˜ ์„ฑ๋Šฅ์ด ์ข€ ๊ดœ์ฐฌ๋‹ค๋ฉด ์†Œํ”„ํŠธ์›จ์–ด ๋ฐฉ์‹์˜ ๊ตฌํ˜„๋„ ์žˆ๋‹ค. ๋ ˆํผ๋Ÿฐ์Šค๋Š” ์‚ผ์„ฑ ์‚ฌ์ดํŠธ์— ์žˆ๋‹ค. ์ˆ˜์ฒœ๊ฒŒ์ดํŠธ๋ฐ–์— ์•ˆ ๋˜๋ฏ€๋กœ asic์œผ๋กœ ๊ตฌํ˜„๋  ์ˆ˜๋„ ์žˆ๋‹ค. ECC block์€ MCU์™€ NAND Flash์‚ฌ์ด์— ๋™๋“ฑํ•œ ํ˜•ํƒœ๋กœ ์œ„์น˜ํ•ด ์žˆ์–ด์„œ ์ฃผ๋ณ€์— ๋ณ„ ๋ถ€๋‹ด์„ ์•ˆ ์ฃผ๊ณ  ์—ฌ๋Ÿฌ๊ฐœ์˜ ๋‚ธ๋“œ์นฉ์— ์œ ์—ฐํ•˜๊ฒŒ ๋Œ€์‘ํ•  ์ˆ˜ ์žˆ๋‹ค. ์•„๋ž˜ ๊ทธ๋Ÿผ์— ํƒ€์ด๋ฐ์ด ๋‚˜์™€์žˆ๋‹ค. VHDL model๋„ ์‚ผ์„ฑ์ด ์ œ๊ณตํ•  ์ˆ˜ ์žˆ๋‹ค. ECC์นฉ๋„ ์‚ผ์„ฑ์ด ๊ณต๊ธ‰ํ•  ์ˆ˜ ์žˆ๋‹ค.
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FIG. 1-5 OPERATING TIMING DIAGRAM (PROGRAM)

CLE

ALE

WE/

RE/

I/OActivate

ECCData

loadingFetchParity

Dataloading

Fetch

Parity

SpareData

10H80H Add

256Byte 3Byte 256Byte 3Byte 16Byte

ActivateECC

FIG. 1-6 OPERATING TIMING DIAGRAM (READ)

CLE

ALE

WE/

RE/

I/OActivate

ECC

Data

Output

Fetch

Parity

Data

Output

Fetch

Parity

Spare

Data00H Add

256Byte 3Byte 256Byte 3Byte 16Byte

Activate

ECC

CE/

Read Parityfrom ECC Chip

Read Parityfrom ECC Chip

Program Parityto Flash Memory

CE/

ReadOriginalParity fromFlash

1.5 Development Tool

In order to help development of the software to be used in a system, Samsung isproviding ISA board and sample source code which can control a Flash Memory inbasic operations such as erase, program and read. For the details, please refer to theFlash section of Samsung`s web site (www.intl.samsungsemi.com) which branched tomemory\flash\application note\available software.

Read Parityfrom ECC Chip

Read Parityfrom ECC Chip

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2. INVALID BLOCK(S) MANAGEMENT

2-1. Identifying Initial Invalid Block(s)

The SAMSUNG NAND Flash may contain invalid blocks. The maximum number ofinvalid blocks is 3 to 35 depending on the device density(Refer to the Data Sheet). Thesystem allowing imperfect memory cells is to maximize manufacturing yield andminimize the die costs. The devices with invalid blocks have the same quality levelsas devices with all valid blocks and have the same all AC and DC characteristics.The system designer must be able to mask out the invalid block(s) from addressmapping. An invalid block(s) do not affect the performance of valid block(s) becauseit could be isolated from the bit line and the common source line by a select transistor.

All device locations are erased(FFh) except locations where the invalid blockinformation is written prior to shipping. Since the invalid block information is alsoerasable in most cases, it is impossible to recover the information once it hasbeen erased. Therefore, the system must be able to recognize the invalid block(s)based on the original invalid block information and create the invalid block table via thefollowing suggested flow chart(Fig.2-1). Any intentional erasure of the original invalidblock information is prohibited.

Start

Set BlockAddress to โ€˜0โ€™

No

Yes

Yes

For the 1st and the 2nd page

Increment Block Address

Create(or update)invalid block(s) table

No

Check `FFh` ?

Last Block ?

End

FIG. 2-1 FLOW CHART TO CREATE INVALID BLOCK TABLE

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๋‚ธ๋“œ๋Š” ์˜ค๋ฅ˜๋ธ”๋Ÿญ์„ ๊ฐ€์งˆ ์ˆ˜๊ฐ€ ์žˆ๋‹ค. ์˜ค๋ฅ˜๋ธ”๋Ÿญ์˜ ์ˆ˜๋Š” ๋””๋ฐ”์ด์Šค ์šฉ๋Ÿ‰์— ๋”ฐ๋ผ 3๊ฐœ์—์„œ 35๊ฐœ๊นŒ์ง€ ๋  ์ˆ˜ ์žˆ๋‹ค. ์นฉ ์ƒ์‚ฐ ์ˆ˜์œจ์„ ํฌ๊ฒŒํ•˜๊ณ  ๊ณผ ๋‹ค์ด์ฝ”์ŠคํŠธ๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•ด ๋ถˆ์™„์ „ํ•œ ๋ฉ”๋ชจ๋ฆฌ ์…€์„ ๊ฐ€์ง„ ์นฉ์„ ํ—ˆ์šฉํ•œ๋‹ค. ์˜ค๋ฅ˜๋ธ”๋Ÿญ์€ ์˜จ์ „ํ•œ๋ธ”๋Ÿญ๊ณผ ๋™์ผํ•œ ํŠน์„ฑ์„ ๊ฐ€์ง„๋‹ค. ์˜ค๋ฅ˜๋ธ”๋Ÿญ์€ select transistor์— ์˜ํ•ด ๊ฒฉ๋ฆฌ๋˜๋ฏ€๋กœ ์˜จ์ „ํ•œ ๋ธ”๋Ÿญ์— ์˜ํ–ฅ์€ ์ฃผ์ง€ ์•Š๋Š”๋‹ค. ์„ค๊ณ„์ž๋Š” ์˜ค๋ฅ˜๋ธ”๋Ÿญ์˜ ์–ด๋“œ๋ ˆ์Šค ๋งตํ•‘ ๋ฐ์ดํ„ฐ๋ฅผ ๋งŒ๋“ค๊ณ  ์œ ์ง€ํ•ด์•ผ ํ•œ๋‹ค.
juc23
์˜ค๋ฅ˜ ๋ธ”๋Ÿญ์„ ์ œ์™ธํ•œ ๋ชจ๋“  ์˜์—ญ์€ ๊ณต์žฅ ์ถœํ•˜์‹œ์— erased(FFh)๋˜์–ด ์žˆ๋‹ค. ์˜ค๋ฅ˜๋ธ”๋Ÿญ์ •๋ณด๋Š” ์ง€์›Œ์งˆ ์ˆ˜๋„ ์žˆ๋Š”๋ฐ ํ•œ ๋ฒˆ ์ง€์›Œ์ง„ ์ •๋ณด๋Š” ๋ณต๊ตฌ๊ฐ€ ๋ถˆ๊ฐ€๋Šฅํ•˜๋‹ค. ๊ทธ๋ž˜์„œ ์‹œ์Šคํ…œ์€ ์›๋ณธ ์˜ค๋ฅ˜๋ธ”๋Ÿญ์ •๋ณด๋ฅผ ์•Œ๊ณ  ์žˆ์–ด์•ผํ•˜๊ณ  ์•„๋ž˜ ๋ฐฉ์‹์— ์˜ํ•ด ํ…Œ์ด๋ธ”์„ ์ƒ์„ฑ์‹œ์ผœ์•ผ ํ•œ๋‹ค. ์˜๋„์ ์ธ ์›๋ณธ ์˜ค๋ฅ˜์ •๋ณด์˜ ์‚ญ์ œ๋Š” ํ•˜์ง€ ๋งˆ๋ผ.
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ELECTRONICS9

2-2. Management of Additional Invalid Block(s)

The bad blocks other than those identified by factory can be increased at the customerside. The system should be designed to replace some additional failing blocks with thereserved blocks. As described in the datasheet, the error-detection mechanism isneeded for both write (program/erase) and read. After program or erase, the cells mustbe verified to detect any write-related failure. The following possible failure modesshould be considered when implementing a highly reliable system.

After write, a single bit can be changed due to the loss of charge, which should bedetected and corrected by ECC. Regarding ECC, we generally recommend single bitcorrection for a sector (512bytes). Sample ECC based on Hamming Code is available.

Failure Modes

ECC : Error Correcting Code Hamming Code etc. Example : 1 bit correction & 2 bit detection

Program Failure (Page)

Erase Failure

Countermeasure

When an error happens in block A,try to reprogram the data intoanother block B by loading it from anexternal buffer. Then, prevent furthersys tem access to b lock A bycreating a 'Bad Block' table or otherappropriate scheme.

When an error occurs after an erase operation, prevent future accesses to this badblock by creating a table within the system or by using other appropriate scheme.

Program Failure (Single Bit)

Buffermemory

error occurs

Block B

Block A

Failure Mode Detection and Countermeasure sequence

WriteStatus Read after Erase Block ReplacementErase Failure

Status Read after Program Block ReplacementProgram Failure

Read Verify ECC ECC CorrectionSingle Bit Failure

TABLE 2-1 FAILURE MODE AND COUNTERMEASURE

FIG. 2-2 BLOCK REPLACEMENT DURING OPERATION

juc23
์˜ค๋ฅ˜ ๋ธ”๋Ÿญ์€ ์‚ฌ์šฉ์ž ์ธก์—์„œ ์ถ”๊ฐ€๋กœ ๋ฐœ์ƒํ•  ์ˆ˜ ์žˆ๋‹ค. ์˜ค๋ฅ˜ ๋ธ”๋Ÿญ์€ ๋”ฐ๋กœ ์ง€์ •๋œ ๋ธ”๋Ÿญ๊ณผ ๋Œ€์ฒด๋  ์ˆ˜ ์žˆ๋„๋ก ์„ค๊ณ„๊ฐ€ ๋˜์–ด์•ผ ํ•œ๋‹ค. ๋ฐ์ดํ„ฐ์‰ฌํŠธ์—๋„ ์„ค๋ช…ํ•œ๋ฐ”์™€ ๊ฐ™์ด ์—๋Ÿฌ๊ฒ€์ถœ ๋ฃจํ‹ด์€ ์ฝ๊ธฐ์™€ ์“ฐ๊ธฐ ๋™์ž‘ ๋ชจ๋‘์— ์ ์šฉ์ด ๋˜์–ด์•ผ ํ•œ๋‹ค. ์“ฐ๊ธฐ์™€ ์†Œ๊ฑฐ ํ›„์—๋Š” ํ•ด๋‹น ์…€๋“ค์€ ์“ฐ๊ธฐ ๊ด€๋ จ๋œ ์˜ค๋ฅ˜๊ฐ€ ์žˆ๋Š”์ง€ ๊ฒ€์ฆํ•ด์•ผ ํ•œ๋‹ค. ๋‹ค์Œ์˜ ์—๋Ÿฌ ๋ชจ๋“œ๋Š” ์‹ ๋ขฐ์„ฑ ์žˆ๋Š” ์‹œ์Šคํ…œ์„ ์œ„ํ•ด์„œ๋Š” ๊ณ ๋ ค๊ฐ€ ๋˜์–ด์•ผํ•œ๋‹ค.
juc23
Erase Failure ์†Œ๊ฑฐ ๋™์ž‘ํ›„์˜ ์—๋Ÿฌ๋Š” ํ–ฅํ›„ ์—ฌ๊ธฐ์— ์ ‘๊ทผํ•˜๋Š”๊ฒƒ์„ ๋ง‰๊ธฐ์œ„ํ•ด ํ…Œ์ด๋ธ”์„ ์ƒ์„ฑ์‹œํ‚ค๊ฑฐ๋‚˜ ๋˜๋‹ค๋ฅธ ๋ฐฉ๋ฒ•์„ ์ด์šฉํ•˜๋ฉด ๋œ๋‹ค. Program Failure (Page) A๋ธ”๋Ÿญ์— ์“ฐ๋Š” ๋„์ค‘ ์—๋Ÿฌ๊ฐ€ ๋ฐœ์ƒํ•˜๋ฉด ๋‹ค๋ฅธ ๋ธ”๋Ÿญ(B)์„ ์ •ํ•ด์„œ ์™ธ๋ถ€๋ฒ„ํผ์˜ ๋‚ด์šฉ์„ ๋‹ค์‹œ ์จ์•ผํ•œ๋‹ค. A๋Š” ์˜ค๋ฅ˜๋ธ”๋Ÿญ ํ…Œ์ด๋ธ”์— ๊ทธ ์œ„์น˜๋ฅผ ๊ธฐ๋กํ•˜๊ฑฐ๋‚˜ ๋‹ค๋ฅธ ๋ฐฉ๋ฒ•์„ ์จ์„œ ์ฒ˜๋ฆฌํ•ด์•ผ ํ•œ๋‹ค. Program Failure (Single Bit) ์“ฐ๊ธฐ ๋™์ž‘ํ›„์— loss of charge๋กœ ์ธํ•ด ์‹ฑ๊ธ€ ๋น„ํŠธ๊ฐ€ ๋ณ€ํ•  ์ˆ˜ ์žˆ๋Š”๋ฐ ์ด๊ฒƒ์€ ECC์— ์˜ํ•ด์„œ ๊ฒ€์ถœํ•˜๊ณ  ๊ต์ •ํ•  ์ˆ˜ ์žˆ๋‹ค. ECC์— ์˜ํ•œ ์„นํ„ฐ๋‹น ์‹ฑ๊ธ€๋น„ํŠธ ๊ต์ •์„ ๊ถŒ์žฅํ•œ๋‹ค. ํ—ค๋ฐ์ฝ”๋“œ ๋ฐฉ์‹์˜ ์ƒ˜ํ”Œ ECC๋ฅผ ์ด์šฉํ•  ์ˆ˜ ์žˆ๋‹ค.
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In NAND flash memory, erase/ program operation is accomplished by the F-N (Fowler -Nordheim) tunneling algorithm using high voltage of about 20V. Erase/ programoperation by the high voltage can cause oxide degradation and a failure if it is repeatedwithout limit. By this reason, the number of program/ erase cycling(called asendurance) is guaranteed up to 1E6 cycles if the system adopts an ECC and a realtime mapping algorithm. The designer should be careful not to exceed the endurance.Most applications would not need this much endurance. For write-intensiveapplications, a popular wear-leveling algorithm like monitoring erase/ program cyclesper block or spreading write algorithm may be utilized. Updating data of a block into aphysically different block with the new link list also help alleviates repetitive cycling.

2-3. Wear-Leveling Algorithm

The controller should monitor each block counter not to use specific blocksrepeatedly.

FIG. 2-3 WEAR-LEVELING

002 Cluster

005 Cluster

Bad Block

Empty Block

003 Cluster

Block 5

Block 6

Block 7

Block 8

Block 9

RAM

002 Cluster

Erased

Bad Block

005 Cluster(new)

003 Cluster

Update page data

Copy updated datato the empty block

2-4. Data Retention

Data retention, in flash memory, is classified by two modes. One is pure data retentionwithout any bias and the other is read retention without erase/ program operation. Puredata retention of NAND Flash products is guaranteed for more than 10 years asdocumented by HTS (High Temperature Storage Test) data contained in Samsung`squalification report. Repetitive reading, without erasing the blocks, hardly affects thedata integrity. The number of read retention test is verified up to 1E6 cycles duringqualification. The readout cycles may be reduced with high density products due to theexcessively long test time. For the details, please refer to the qualification report.

juc23
Wear-Leveling Algorithm (** wear : ๋งˆ๋ฉธ(๋งˆ๋ชจ)๋˜๋‹ค. ์˜ค๋ž˜์จ์„œ ๋‹ฌ์•„์ง€๋‹ค๋ผ๋Š” ์˜๋ฏธ) ์šฐ๋ฆฌ๋ง๋กœ ํ•˜๋ฉด '๋งˆ๋ชจ๋„ ์ธก์ • ์•Œ๊ณ ๋ฆฌ์ฆ˜'์ •๋„๋กœ ํ•ด์„ํ•˜๋ฉด ๋ ๊ฒƒ๊ฐ™๋‹ค. ๋‚ธ๋“œํ”Œ๋ ˆ์‰ฌ์˜ ์“ฐ๊ธฐ์™€ ์†Œ๊ฑฐ๋Š” 20๋ณผํŠธ์˜ ๊ณ ์ „์••์„ ์ด์šฉํ•˜๋Š” F-N ํ„ฐ๋„ ๋ฐฉ์‹์„ ์ด์šฉํ•˜์—ฌ ๊ตฌํ˜„๋œ๋‹ค. ๊ณ ์ „์••์„ ์ด์šฉํ•˜๋Š” ์“ฐ๊ธฐ์™€ ์†Œ๊ฑฐ๋Š” ์˜ฅ์‚ฌ์ด๋“œ ๊ฐ์†Œ๋ฅผ ์ผ์œผํ‚ฌ ์ˆ˜ ์žˆ๊ณ  ๊ทธ๊ฒƒ์ด ๋ฌดํ•œ๋ฐ˜๋ณต๋˜์–ด ์—๋Ÿฌ๋ฅผ ์ผ์œผํ‚ค๊ฒŒํ•œ๋‹ค. ์ด๋Ÿฐ ์ด์œ ๋กœ ์ธํ•ด ECC์™€ ์‹ค์‹œ๊ฐ„ ๋งตํ•‘ ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ์ด์šฉํ•˜๋Š” ์‹œ์Šคํ…œ์—์„œ๋Š” program/ erase cycling(endurance,๋‚ด๊ตฌ์„ฑ)์„ 100๋งŒ๋ฒˆ์œผ๋กœ ๋ณด์ฆํ•œ๋‹ค. ์„ค๊ณ„์ž๋Š” ์ด ๋‚ด๊ตฌํšŸ์ˆ˜๋ฅผ ๋„˜์ง€์•Š๊ฒŒ ์ฃผ์˜ํ•ด์•ผํ•œ๋‹ค. ๋Œ€๋ถ€๋ถ„์˜ ์ œํ’ˆ์—์„œ๋Š” ์ด๋งŒํผ์˜ ๋‚ด๊ตฌ์„ฑ๊นŒ์ง€๋Š” ์‚ฌ์‹ค ํ•„์š”์—†๋‹ค. ์“ฐ๊ธฐ ์ค‘์‹ฌ์˜ ์ œํ’ˆ์ผ ๊ฒฝ์šฐ ๋ธ”๋Ÿญ๋‹น ์†Œ๊ฑฐ/์“ฐ๊ธฐํšŒ์ˆ˜๋ฅผ ๋ชจ๋‹ˆํ„ฐ๋งํ•˜๋Š” wear-leveling algorithm์„ ์ด์šฉํ•˜๊ธฐ๋„ ํ•˜๊ณ  ๋˜๋Š” ํ™•์žฅ๋œ ํ˜•ํƒœ์˜ ์“ฐ๊ธฐ ์•Œ๊ณ ๋ฆฌ์ฆ˜์„ ์ด์šฉํ•˜๊ธฐ๋„ ํ•œ๋‹ค. ํ•œ ๋ธ”๋Ÿญ์˜ ๋ฐ์ดํ„ฐ๋ฅผ ์ƒˆ๋กœ์šด ๋งํฌ๋ฅผ ๋งŒ๋“ค์–ด์„œ ์‹ค์ œ ๋ฌผ๋ฆฌ์ ์œผ๋กœ ๋‹ค๋ฅธ ์—ฌ๋Ÿฌ ๋ธ”๋Ÿญ์— ๋‚˜๋ˆ  ์—…๋ฐ์ดํŠธ๋˜๊ฒŒ ํ•จ์œผ๋กœ์„œ ๋ฐ˜๋ณต ์‚ฌ์ดํด์„ ์™„ํ™”์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค.
juc23
์ปจํŠธ๋กค๋Ÿฌ๋Š” ํŠน์ •ํ•œ ๋ธ”๋Ÿญ๋งŒ์ด ๋ฐ˜๋ณต๋˜์–ด ์“ฐ์ด์ง€ ์•Š๊ฒŒ ๊ฐ ๋ธ”๋Ÿญ์„ ๋ชจ๋‹ˆํ„ฐํ•ด์•ผํ•œ๋‹ค.
juc23
๋ฐ์ดํ„ฐ ๋ณด์กด์€ ๋‘ ๊ฐ€์ง€ ๋ถ€๋ฅ˜๋กœ ๋‚˜๋ˆ ์„œ ๋ณผ ์ˆ˜ ์žˆ๋‹ค. ํ•˜๋‚˜๋Š” ๋ณ„๋‹ค๋ฅธ ๋ฐ”์ด์–ด์Šค(?)์—†์ด ๋ฐ์ดํ„ฐ ์ž์ฒด๊ฐ€ ๋ณด์กด๋  ์ˆ˜ ์žˆ๋Š๋ƒ์˜ ๊ฒƒ์ด๊ณ  ๋‹ค๋ฅธ ํ•˜๋‚˜๋Š” ์“ฐ๊ธฐ/์†Œ๊ฑฐ๊ฐ€ ์—†๋Š” ์ƒํƒœ์—์„œ ์–ผ๋งˆ๋งŒํผ ์ฝ๊ธฐ์œ ์ง€๊ฐ€ ๊ฐ€๋Šฅํ•˜๋ƒ์˜ ๊ฒƒ์ด๋‹ค. ๋ฐ์ดํ„ฐ ์ž์ฒด์˜ ๋ณด์กด์€ 10๋…„ ์ด์ƒ์„ ๋ณด์ฆํ•œ๋‹ค. ๋ธ”๋Ÿญ์†Œ๊ฑฐ ์—†์ด ๋ฐ˜๋ณต๋˜๋Š” ์ฝ๊ธฐ ๋™์ž‘์—์„œ๋Š” ์ข…์ข… ๋ฐ์ดํ„ฐ ๋ฌด๊ฒฐ์„ฑ์— ์˜ํ–ฅ์„ ์ฃผ๊ธฐ๋„ ํ•œ๋‹ค. ๊ทธ๋ž˜์„œ read retention์€ ๋ฐฑ๋งŒ๋ฒˆ ์ด์ƒ์„ ๋ณด์ฆํ•œ๋‹ค. ๊ณ ์ง‘์  ์ œํ’ˆ๊ฐ™์€ ๊ฒฝ์šฐ์—๋Š” ํ…Œ์ŠคํŠธ ํƒ€์ž„์ด ๊ทน๋‹จ์ ์œผ๋กœ ๋Š˜์–ด๋‚˜๋ฏ€๋กœ readout cycles์„ ์ค„์ผ์ˆ˜ ๋„ ์žˆ๋‹ค.
juc23
Pure
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data retention
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read retention
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2-5. Effect of P/E Cycling on Performance

NAND Flash goes through internal qualification process with endurance up to 1E6cycles. The erase time does not change at all regardless of endurance up to 1E6cycles.

-3.5

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

1.E0 1.E1 1.E2 1.E3 1.E4 1.E5 1.E6 1.E7

Number of P/E Cycles

Cel

l Vth

(V

)

Programmed Cell

Erased Cell

1.E+1

1.E+2

1.E+3

1.E+4

1.E+0 1.E+2 1.E+4 1.E+6

Number of P/E Cycles

Tim

e (

uS)

Erase Time

Program Time

FIG. 2-4 Cell Vth Shift vs. No of P/E Cycles

FIG. 2-5 Program/ Erase Time Variation vs. No of P/E Cycles

juc23
๋ฐฑ๋งŒ๋ฒˆ ์ •๋„์˜ ๋‚ด๊ตฌ์„ฑ์„ ๋‚˜ํƒ€๋‚ด๋Š”๋ฐ ์†Œ๊ฑฐํ•˜๋Š”๋ฐ ๊ฑธ๋ฆฌ๋Š” ์‹œ๊ฐ„์€ ์ด ํšŸ์ˆ˜์™€ ๋ฌด๊ด€ํ•˜๋‹ค..
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3-1. Erase Algorithm

3-2. Program Algorithm

3. PROGRAM/ERASE ALOGORITHM

START

WRITE 60H

WRITE BLOCK ADD. ( 2 CYCLE )

ERASE COMPLETED

YES

WRITE D0H

WRITE 70H

ERASE ERROR

YESIf erase operation results in an error, map out thefailing block and replace it with another block.

START

WRITE 80H

WRITE ADD. ( 3 CYCLE )

WRITE DATA( 0 to 527 BYTE )

PROGRAM COMPLETED

YES

WRITE 10H

PROGRAMERROR

NO

YES

WRITE 70H

NO SR 6 = 1 ?or R/B =1 ?

SR 0 = 0 ?

SR 6 = 1 ?or R/B =1 ?

SR 0 = 0 ?

WRITE 00H

WRITE ADDRESS

WIAT FOR TR TIME

VERIFY DATA NO PROGRAM

ERROR

YES

If ECC is used, this verificationOperation is not needed

PROGRAM ERROR : If program operation results in an error, map out the blockincluding the page in error and copy the target data to another block

NO

FIG. 3-1 ERASE ALGORITHM

FIG. 3-2 PROGRAM ALGORITHM

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3-3. Status Read Operation

TABLE 3-1 STATUS REGISTER DEFINITIION

The device automatically implements the execution and verification of the program anderase operations. The status read function is used to monitor the Ready/Busy status ofthe device, determines the pass/fail result of a program or erase operation. The devicestatus is can be read through the I/O port using the RE/ clock after a โ€œ70Hโ€ commandinput. The Pass/Fail status on I/O 0 is only valid when the device is in the ready state.The resulting information is outlined in Table 3-1.

The Ready/Busy(S.R.6) status can be read by inputting the status read command โ€˜70Hโ€™during the Read Mode. Once the device is set to the status Read Mode after '70Hโ€™command input, the device does not return to the read mode. In order to restore thedevice to the read mode after the device changes from Busy to Ready state, the readcommand โ€˜00Hโ€™ without address input must be written. In this case, the data outputstarts from address N.The status bit "0" indicates that the internal verification circuit did not find error inprogramming. But, the internal verification circuit inside Flash detects only "1"s that arenot successfully programmed to "0". If a cell is to retain the erase state of "1" butchanged to โ€œ0" by any reason, this error is not detected by the internal circuit. This iscalled program-disturb, very rare cases. If it occurs, it is single bit error in a page.Therefore, if single bit error-detection and correction (ECC) is adopted, compare afterprogramming is not needed. And in case of voice or graphic application, single bit errormay be ignored : so for those application, neither comparing nor ECC is needed.However, if the data integrity is very critical, comparing is recommended, otherwiseECC should be used.

Status Register Status Definition

I/O0 Program/Eraseโ€œ0โ€ : Successful Program / Erase(Pass)

โ€œ1โ€ : Error in Program / Erase(Fail)

I/O1

Reserved for Future use

โ€œ0โ€

I/O2 โ€œ0โ€

I/O3 โ€œ0โ€

I/O4 โ€œ0โ€

I/O5 โ€œ0โ€

I/O6 โ€œ0โ€ : Busy โ€œ1โ€ : ReadyDevice Operation

I/O7 โ€œ0โ€ : Protected โ€œ1โ€ : Not ProtectedWrite Protect

00HCommand 00H 70H

CE/

WE/

RE/N address

Status read command

S.R.6=0 0 1 N N+1

Data output

FIG. 3-3 STATUS READ TIMING

R/B

juc23
์“ฐ๊ธฐ์™€ ์†Œ๊ฑฐ ๋™์ž‘์˜ ์‹คํ–‰๊ณผ ๊ฒ€์ฆ์€ ์ž๋™์œผ๋กœ ์‹คํ˜„๋œ๋‹ค. ์ƒํƒœ ๋ ˆ์ง€์Šคํ„ฐ๋Š” ๋””๋ฐ”์ด์Šค์˜ Ready/Busy์ƒํƒœ๋ฅผ ๋ชจ๋‹ˆํ„ฐํ•˜๊ธฐ ์œ„ํ•ด ์“ฐ์ด๊ณ  ์“ฐ๊ธฐ๋‚˜ ์†Œ๊ฑฐ ๋™์ž‘์ด ์„ฑ๊ณตํ–ˆ๋Š”์ง€ ์‹คํŒจํ–ˆ๋Š”์ง€๋ฅผ ๊ฒฐ์ •ํ•œ๋‹ค. ๋””๋ฐ”์ด์Šค ์ƒํƒœ๋Š” 70H ์ปค๋ฉ˜๋“œ๋ฅผ ์ฃผ๊ณ  RE/์‹ ํ˜ธ๋ฅผ ์คŒ์œผ๋กœ์„œ ์•„์ด์˜คํ•€์„ ํ†ตํ•ด ์ฝ์„ ์ˆ˜ ์žˆ๋‹ค. ๋””๋ฐ”์ด์Šค๊ฐ€ ready state ์ผ๋•Œ I/O 0ํ•€์„ ํ†ตํ•ด ์ƒํƒœ๋ฅผ ์•Œ์•„๋‚ผ ์ˆ˜ ์žˆ๋‹ค.
juc23
Ready/Busy(S.R.6) ์ƒํƒœ๋Š” ์ฝ๊ธฐ ๋ชจ๋“œ ์ƒํƒœ์—์„œ ์ปค๋ฉ˜๋“œ 70h๋ฅผ ๋‚ ๋ฆฌ๋ฉด ์ฝ์–ด๋‚ผ ์ˆ˜ ์žˆ๋‹ค. ์ผ๋‹จ 70 ์ปค๋ฉ˜๋“œ๊ฐ€ ์ธ๊ฐ€๋˜์–ด ์ƒํƒœ์ฝ๊ธฐ ๋ชจ๋“œ์— ์ง„์ž…ํ•˜๋ฉด ๋‹ค์‹œ ์ฝ๊ธฐ ๋ชจ๋“œ๋กœ ๋ณต๊ท€ํ•˜์ง€ ์•Š๋Š”๋‹ค. Busy ์—์„œ Ready ์ƒํƒœ๋กœ ๋ฐ”๋€Œ์–ด ๋””๋ฐ”์ด์Šค๊ฐ€ ์ฝ๊ธฐ๋ชจ๋“œ๋กœ ๋˜๋Œ์•„๊ฐ€๋ ค๋ฉด ์–ด๋“œ๋ ˆ์Šค๋Š” ์ค„ ํ•„์š”์—†์ด 00 ์ปค๋ฉ˜ํŠธ๋งŒ ์ฃผ๋ฉด ๋œ๋‹ค. ์œ„์˜ ๊ฒฝ์šฐ์—” ์ฃผ์†Œ N ๋ฒˆ์ง€๋ถ€ํ„ฐ ๋ฐ์ดํ„ฐ๊ฐ€ ์ฝํ˜€์ง€๊ฒŒ ๋œ๋‹ค. ์ƒํƒœ๋น„๋“œ๊ฐ€ 0 ์ธ ์ƒํƒœ๋Š” ์“ฐ๊ธฐ ๋™์ž‘์ค‘์— ๋‚ด๋ถ€ ๊ฒ€์ฆ๊นŒ์ง€ ์ด์ƒ์—†์ด ์ง„ํ–‰๋˜์—ˆ๋‹ค๋Š” ๊ฒƒ์„ ์˜๋ฏธํ•œ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ๊ฒฐ๊ณผ๊ฐ€ 1 ์ด ๋‚˜์˜จ๋‹ค๋ฉด ๊ทธ๊ฒƒ์€ 0 ์œผ๋กœ ์“ฐ๊ธฐ๊ฐ€ ์„ฑ๊ณตํ•˜ ์ง€ ๋ชปํ–ˆ๋‹ค๋Š” ๊ฒƒ์„ ์˜๋ฏธํ•œ๋‹ค. ์–ด๋–ค ์…€์ด ์ง€์›Œ์ง„ ์ƒํƒœ์ธ 1 ์„ ์œ ์ง€ํ•ด์•ผ ํ•˜๋Š”๋ฐ ์–ด๋–ค ์ด์œ ์—์„œ๋“  0 ์œผ๋กœ ๋ฐ”๋€Œ์–ด ์žˆ๋‹ค๋ฉด ์ด๋Ÿฐ ์—๋Ÿฌ๋Š” ๋‚ด๋ถ€๋กœ์ง์œผ๋กœ๋Š” ๋ฐœ๊ฒฌํ•  ์ˆ˜ ์—†๋‹ค. ์ด๋Ÿฐ ๊ฒฝ์šฐ๋ฅผ program-disturb๋ผ๊ณ  ํ•˜๋Š”๋ฐ ๋งค์šฐ ๋“œ๋ฌธ ๊ฒฝ์šฐ์ด๋‹ค. ๋งŒ์ผ ์ด๋Ÿฐ๊ฒŒ ์ผ์–ด๋‚ฌ๋‹ค๋ฉด ๊ทธ๊ฒƒ์€ ์‹ฑ๊ธ€ ๋น„ํŠธ ์—๋Ÿฌ์ด๋‹ค. ๊ทธ๋ž˜์„œ ECC๊ฐ€ ์ ์šฉ๋˜์–ด ์žˆ๋Š” ๊ฒฝ์šฐ๋ผ๋ฉด ์“ฐ๊ธฐ ํ›„์— ๋น„๊ตํ•  ํ•„์š”๋„ ์—†๋‹ค. ์Œ์„ฑ์ด๋‚˜ ๊ทธ๋ž˜ํ”ฝ ์ œํ’ˆ์—์„œ๋Š” ์‹ฑ๊ธ€๋น„ํŠธ์—๋Ÿฌ๋Š” ๋ฌด์‹œ๋  ์ˆ˜ ์žˆ๋‹ค. ๊ทธ๋Ÿฐ ๊ฒฝ์šฐ์—๋Š” ์‹ฌ์ง€์–ด ๋น„๊ต๋‚˜ ECC๋„ ํ•„์š”์น˜ ์•Š๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ๋ฐ์ดํ„ฐ ๋ฌด๊ฒฐ์„ฑ์€ ๋งค์šฐ ๋ฏผ๊ฐํ•œ ๊ฒƒ์ด๋ฏ€๋กœ ๋น„๊ต๋ฅผ ๊ถŒ์žฅํ•˜๊ณ  ๋˜ ECC๋ฅผ ์ด์šฉํ•ด์•ผ ํ•œ๋‹ค.
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ELECTRONICS14

CE1/

RE/

An application example with multiple devices is shown in Figure 3-4 :

CLE

ALE

WE/

CEN/

I/O

Status onDevice 1

Status onDevice N

System Design Note : If the Ready/Busy pin signals of multiple devices are common-wired as shown in the diagram, the status read function can be used to determine thestatus of each individually selected device.

Busy

70H 70H

CE 1 CE 2 CE 3 CE N

CLE

ALEWE/RE/

I/O

Device 1 Device 2 Device 3 Device 4

FIG. 3-4 STATUS READ TIMING APPLICATION EXAMPLE

R/B

R/B

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ELECTRONICS15

3-4. Partial Page Program

1st programming Data pattern 1

2nd programming Data pattern 2

Data pattern 1010th programming

Data pattern 10Data pattern 1 Data pattern 2Result

Regarding the data for unprogrammed or previously programmed page segments,there are two ways to take care of this. First is to input โ€œ1โ€ for all the other bytes thanthe currently selected segment. Second is to skip this dummy data input cycles byspecifying the column address to the start of selected segment. Upon the commandinput of 80H(Sequential Data Input command) the internal circuitry of NAND Flash setsthe data of all page buffers to โ€œ1โ€ by default. The page buffers with no data input keepthe โ€œ1โ€ state.Therefore only the bytes to be programmed need to be loaded and theothers bytes outside data pattern do not need to be loaded,with the data of โ€œ1โ€. If thestart column address is higher than 255(as explained in Section 3-2),an appropriatepointer command should be inputted before 80H command.

The flash memory allows a page to be divided into several segments. The number ofsegmentation is limited and varies by product densities as follows :

FIG. 3-5 PARTIAL PAGE PROGRAM for 4Mb/ 16Mb/ 32Mb/ 64Mb

Data pattern 11stProgramming

2ndProgramming

Data pattern 2

Data pattern 3

Data pattern 4

Data pattern 5

3rdProgramming

4thProgramming

5thProgramming

Result

Main Array ( 512B Column) Spare Array ( 16B Column)

Data pattern 2Data pattern 1 Data pattern 5Data pattern 4Data pattern 3

โ€œ1โ€ or may be skipped

โ€œ1โ€ or may be skipped

The number of consecutive partial page programming operation within the same pagewithout an intervening erase operation should not exceed 2 for main array and 3 forspare array. If some parts of spare array were used during the main cell beingprogrammed, the additional NOP of spare array should be restricted by 2.

FIG. 3-6 PARTIAL PAGE PROGRAM for 128Mb/ 256Mb

juc23
ํ”Œ๋ ˆ์‰ฌ ๋ฉ”๋ชจ๋ฆฌ๋Š” ํ•œ ํŽ˜์ด์ง€๋ฅผ ์—ฌ๋Ÿฌ๊ฐœ์˜ ์กฐ๊ฐ์œผ๋กœ ๋‚˜๋ˆ„๋Š”๊ฒƒ์„ ํ—ˆ์šฉํ•œ๋‹ค. ์กฐ๊ฐ์˜ ๊ฐฏ์ˆ˜๋Š” ์ œํ’ˆ์˜ ์ข…๋ฅ˜์— ๋”ฐ๋ผ ๋‹ค์–‘ํ•  ์ˆ˜ ์žˆ๋‹ค. ์“ด ์ ์ด ์—†๋Š” ํŽ˜์ด์ง€ ์กฐ๊ฐ์ธ์ง€ ์ด์ „์— ์“ฐ์—ฌ์ง„๊ฒŒ ์žˆ๋Š” ํŽ˜์ด์ง€ ์กฐ๊ฐ์ธ์ง€์— ๋”ฐ๋ผ ๋ฐ์ดํ„ฐ๋Š” ๋‘ ๊ฐ€์ง€ ๋ฐฉ์‹์œผ๋กœ ์ž˜ ๋‹ค๋ค„์•ผํ•œ๋‹ค. ๋จผ์ € ํ˜„์žฌ ์„ ํƒ๋œ ์กฐ๊ฐ์ด์™ธ์˜ ๋‹ค๋ฅธ ๋ชจ๋“  ๊ณณ์— 1์„ ๋„ฃ๋Š”๋‹ค. ๋‹ค์Œ์—” ์„ ํƒ๋œ ์กฐ๊ฐ์˜ ์‹œ์ž‘ ์นผ๋Ÿผ ์ฃผ์†Œ๋ฅผ ์ง€์ •ํ•ด์คŒ์œผ๋กœ์„œ ๋”๋ฏธ ๋ฐ์ดํ„ฐ ์ž…๋ ฅ ์‚ฌ์ดํด์„ ์•ˆ ๋„ฃ์„ ์ˆ˜ ์žˆ๋‹ค. 80 ์ปค๋ฉ˜๋“œ๊ฐ€ ์ฃผ์–ด์ง€๋ฉด ํ”Œ๋ ˆ์‰ฌ์˜ ๋‚ด๋ถ€์—์„œ๋Š” ๋ชจ๋“  ํŽ˜์ด์ง€ ๋ฒ„ํผ๋ฅผ 1๋กœ ์ฑ„์›Œ๋†“๋Š”๋‹ค. ๋ฐ์ดํ„ฐ ์ž…๋ ฅ์ด ์—†๋Š” ํŽ˜์ด์ง€ ๋ฒ„ํผ์˜ ๊ณต๊ฐ„์€ 1 ์„ ์œ ์ง€ํ•˜๊ฒŒ ๋œ๋‹ค. ๊ทธ๋ž˜์„œ ์˜ค์ง ์จ์•ผ๋  ๋ฐ”์ดํŠธ๋งŒ์„ ๋กœ๋“œ์‹œํ‚ค๋ฉด ๋˜๊ณ  ์จ์•ผ๋  ๋ฐ์ดํ„ฐ ํŒจํ„ด ์ด์™ธ์˜ ๋‹ค๋ฅธ ๋ฐ”์ดํŠธ๋“ค์€ ๋กœ๋“œ์‹œํ‚ฌ ํ•„์š”๊ฐ€ ์—†๋‹ค. (1์„ ๊ฐ€์ง€๊ณ  ์žˆ๊ฒŒ ๋œ๋‹ค) ์‹œ์ž‘ ์นผ๋Ÿผ ์–ด๋“œ๋ ˆ์Šค๊ฐ€ 255 ๋ณด๋‹ค ํฌ๋ฉด 80 ์ปค๋ฉ˜๋“œ๋ฅผ ์ฃผ๊ธฐ ์ „์— ์ ๋‹นํ•œ ํฌ์ธํ„ฐ ์ปค๋ฉ˜๋“œ๋ฅผ ๋จผ์ € ์ฃผ๋ฉด ๋œ๋‹ค.
juc23
๋™์ผํŽ˜์ด์ง€ ๋‚ด์—์„œ ์ค‘๊ฐ„์— ์†Œ๊ฑฐ ๋™์ž‘์ด ์—†์ด ํ•  ์ˆ˜ ์žˆ๋Š” (๊ฐ„๊ฒฉ์—†์ด) ์—ฐ์†๋˜๋Š” ๋ถ€๋ถ„ ์“ฐ๊ธฐ๋Š” ๋ฉ”์ธ์˜์—ญ์—์„œ๋Š” 2ํšŒ, ์ŠคํŽ˜์–ด ์˜์—ญ์—์„œ๋Š” 3ํšŒ๋ฅผ ๋„˜์„ ์ˆ˜ ์—†๋‹ค. ๋งŒ์ผ ๋ฉ”์ธ ์˜์—ญ ์“ฐ๊ธฐ ์ค‘์— ์ŠคํŽ˜์–ด ์˜์—ญ์˜ ์ผ๋ถ€๊ฐ€ ์“ฐ์ธ๋‹ค๋ฉด ์ŠคํŽ˜์–ด ์˜์—ญ์— ๋Œ€ํ•œ ์ถ”๊ฐ€ ์“ฐ๊ธฐ ํšŸ์ˆ˜๋Š” 2ํšŒ๋กœ ์ œํ•œ๋œ๋‹ค.
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ELECTRONICS16

4. OPERATING WITH COMMANDS

4-1. Prohibition of Unspecified Commands

4-2. Pointer Control for '00H', '01H', '50H'

The operation commands are listed in Table 4-1. Input of a command other than thosespecified in Table 4-1 is prohibited. Stored data may be corrupted if an unspecifiedcommand is entered during the command cycle.

Note : 1) The 00H Command defines starting Address on the 1st half of Registers. The 01H Command defines starting Address on the 2nd half of Registers. After data access on the 2nd half of register by the 01H command, the status pointer is automatically moved to the 1st half register (00H) on the next cycle. 4Mb,8Mb and 16Mb NAND Flash do not support 01H command. 2) The 50H command is valid only When the SE/ is low level.(4Mb NAND Flash do not support 50H command.)

Three Read Modes are available with 32Mb~256Mb to set the destination of the pointerin either the main memory area of a page or the spare area. The pointer can bedesignated at any location between 0 and 255 in Read Mode 1 and between 256 and511 in Read Mode 2 and between 512 and 527 in Read Mode 3. Figure 4-1 shows theblock diagram of pointer operation for 32Mb,64Mb, 128Mb and 256Mb NAND Flash.

Function 1st. Cycle 2nd. CycleAcceptable Command

during Busy State

Sequential Data Input 80H -

Read 1 00/01H -(1)

Read 2 50H -(2)

Read ID 90H -

Reset FFH -

Auto Page Program 10H -

Auto Block Erase 60H D0H

Read Status 70H -

Table 4-1 COMMAND SETS

FIG. 4-1 POINTER CONTROL : 32Mb~256Mb

0 255 256 527

Pointer control00H

50H

A,B : Main Memory AreaC : Spare Area

511 512

01H

*Because 01H command is temporary, the device is set to 00H at the next page sequential read.

B(01H)* C(50H)A(00H)

juc23
์ง€์ •๋˜์ง€ ์•Š์€ ์ปค๋ฉ˜๋“œ๋Š” ์“ฐ์ง€๋งˆ๋ผ. ๊ทธ๋ ‡์ง€ ์•Š์œผ๋ฉด ์ €์žฅ๋œ ๋ฐ์ดํ„ฐ์˜ ์›ํ˜•์ด ์†์ƒ๋  ์ˆ˜๋„ ์žˆ๋‹ค. 1. 00 ์ปค๋ฉ˜๋“œ๋Š” ์‹œ์ž‘์ฃผ์†Œ๊ฐ€ 1st half of Registers์ž„์„ ๋‚˜ํƒ€๋‚ธ๋‹ค. 01 ์ปค๋ฉ˜๋“œ๋Š” ์‹œ์ž‘์ฃผ์†Œ๊ฐ€ 2st half of Registers์ž„์„ ๋‚˜ํƒ€๋‚ธ๋‹ค. 01์ปค๋ฉ˜๋“œ์— ์˜ํ•ด ํ›„๋ฐ˜ ๋ฐ์ดํ„ฐ๋ฅผ ์•ก์„ธ์Šคํ•˜๊ณ  ๋‚œ ๋‹ค์Œ์—๋Š” ์ƒํƒœํฌ์ธํ„ฐ๋Š” ๋‹ค ์Œ์‚ฌ์ดํด์— ์ž๋™์œผ๋กœ 01๋กœ ์ด๋™ํ•œ๋‹ค. 4,8,16 ๋ฉ”๊ฐ€ ํ”Œ๋ ˆ์‰ฌ๋Š” 01์ปค๋ฉ˜๋“œ๋ฅผ ์ง€ ์›ํ•˜์ง€ ์•Š๋Š”๋‹ค. 2. 50 ์ปค๋ฉ˜๋“œ๋Š” SE/๊ฐ€ ๋กœ์šฐ ๋ ˆ๋ฒจ์ผ๊ฒฝ์šฐ์—๋งŒ ์œ ํšจํ•˜๋‹ค(4๋ฉ”๊ฐ€๋Š” ์ง€์›ํ•˜์ง€ ์•Š ๋Š”๋‹ค.
juc23
32๋ฉ”๊ฐ€์—์„œ 256๋ฉ”๊ฐ€์˜ ํ”Œ๋ ˆ์‰ฌ๋Š” ๋ฉ”์ธ,์ŠคํŽ˜์–ด ์˜์—ญ์„ ์ง€์ •ํ•˜๋Š” ํฌ์ธํ„ฐ๋ฅผ ์ด์šฉํ•˜๋Š”๋ฐ 3๊ฐ€์ง€ ์ฝ๊ธฐ๋ชจ๋“œ๊ฐ€ ์žˆ๋‹ค. ๋ชจ๋“œ 1์—์„œ๋Š” 0-255 ์‚ฌ์ด, ๋ชจ๋“œ2์—์„œ๋Š” 256-511, ๋ชจ๋“œ3์—์„œ๋Š” 512-517 ์‚ฌ์ด์˜ ์œ„์น˜๋ฅผ ์ง€์ •ํ•  ์ˆ˜ ์žˆ๋‹ค. ์•„๋ž˜ ๊ทธ๋ฆผ์€ ๊ทธ๊ฒƒ์„ ์„ค๋ช…ํ•˜๊ณ  ์žˆ๋‹ค.
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ELECTRONICS17

50H

C area

Start point A area

Add

10H

Add

00H 80H 80H 10H

A area A area A area DIN

Start point A area

DIN

00H

A area

Start point B area

Add

10H

Add

01H 80H 80H 10H

B area B area A area DIN

Start point A area

DIN

00H

A area

Start point C area

Add

10H

Add

50H 80H 80H 10H

C area C area C area DIN

Start point C area

DIN

0 255 263

Pointer control00H

50H

A: Main Memory Area B : Spare Area

256

Note 1 ) 01H command is valid just one time when it is used as a pointer for program/erase.

8Mb and 16Mb do not have 01H pointer and 4Mb has no pointer. Figure 4-3 shows theblock diagram of pointer operation for 8Mb and 16Mb NAND Flash.

The pointer is set to region 'A' by the '00H' command and to region B by the โ€œ01Hโ€command, and to region 'C' by the '50H'command. The '00Hโ€™ command must be input toset the pointer back to region 'A' when the pointer is in region 'C'.

A(00H) B(50H)

FIG. 4-3 POINTER CONTROL : 8Mb,16Mb

FIG. 4-2 EXAMPLE FOR POINTER SET : 32Mb~256Mb

Operation Pointer status after operation

Program/EraseWith previous 00H, Device is set to 00H Plane

With previous 01H, Device is set to 00H Plane (1)With previous 50H, Device is set to 50H Plane

Reset โ€œ00Hโ€ Plane(โ€œAโ€ area)

Power Up โ€œ00Hโ€ Plane(โ€œAโ€ area)

juc23
-- ํฌ์ธํ„ฐ๊ฐ€ ํ˜„์žฌ c์˜์—ญ์— ์žˆ๋‹ค๋ฉด a ์˜์—ญ์œผ๋กœ ๋Œ์•„์˜ค๊ธฐ์ „์— 00 ์ปค๋ฉ˜๋“œ๋ฅผ ๋จผ์ € ์ค˜์•ผ ํ•œ๋‹ค. (์ด ๋ถ€๋ถ„์€ ๋ฐ์ดํ„ฐ์‰ฌํŠธ์˜ ๋‚ด์šฉ๊ณผ ์•ฝ๊ฐ„ ๋‹ค๋ฅด๊ฒŒ ํ•ด์„๋œ๋‹ค.์ฐธ๊ณ ) 00,50์€ ๋™์ž‘ํ›„์—๋„ ๊ทธ๋Œ€๋กœ ํฌ์ธํ„ฐ๊ฐ€ ์œ ์ง€๋˜๊ณ  01์€ ๋™์ž‘ํ›„์— ํฌ์ธํ„ฐ๊ฐ€ ์ž๋™์œผ๋กœ 00์œผ๋กœ ๋ณต๊ท€๋œ๋‹ค.
juc23
juc23
์•ž์˜ ํฌ์ธํ„ฐ๊ฐ€ 01 ์ด์—ˆ์œผ๋ฏ€๋กœ ๋ฐ”๋กœ ์ด ์ง€์ ์—์„œ ํฌ์ธํ„ฐ๊ฐ€ 00์œผ๋กœ ์ž๋™์œผ๋กœ ๋ณต๊ท€๋˜์–ด ํ˜„์žฌ a ์˜์—ญ์„ ๊ฐ€๋ฆฌํ‚ค๊ฒŒ ๋œ๊ฒƒ์ด๋‹ค.
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4-3. Device Status after Read/Program/Erase/Reset and Power-on

(2)

(1)

(2)

(2)

4-4. Acceptable Commands after Sequential Input Command of '80H'

If any commands other than '10H' are inputted, the program operation is not performed.

80H XX 10H

Other command Programming cannot be executed.

In case of this operation, FFH(Reset) command is needed.

*(1) : 01H Command is valid just one time when it is used as a pointer for program/erase.*(2) : After execution of Program/Erase/Reset command, '00H' '01H' or '50H' read commands are required to select either Read 1 or Read 2 mode.

After the sequential input command (80H) input, do not input any commands otherthan the program execution command (10H) or the reset command (FFH) duringprogramming.

80H FFH

WE/

Address Input

RB/

TABLE 4-2. STATUS DESCRIPTION

Execution Command Device Status after executed CMD.

Read 1(00H or 01H) Read 1 (00H Plane) *

Read 2 (50H) Read 2 (50H Plane)

Program Wait *

Erase Wait *

Reset Wait *

Power on Read 1(00H Plane)

FIG. 4-4 RIGHT USING OF PROGRAMMING COMMAND

juc23
์ปค๋ฉ˜๋“œ 80์ด ๋‚˜๊ฐ„๋’ค์—๋Š” ์‹คํ–‰์ปค๋ฉ˜๋“œ 10 ์ด๋‚˜ ๋ฆฌ์…‹์ปค๋ฉ˜๋“œ ์ด์™ธ์—๋Š” ์ฃผ์ง€ ๋งˆ๋ผ. ๋งŒ์ผ 10 ์ด์™ธ์˜ ์ปค๋ฉ˜๋“œ๊ฐ€ ์˜ค๋ฉด ์“ฐ๊ธฐ ๋™์ž‘์ด ์ˆ˜ํ–‰๋˜์ง€ ์•Š๋Š”๋‹ค. ํ˜น์‹œ ๋งจ ์•„๋ž˜์˜ ๊ฒฝ์šฐ๊ฐ€ ์ฒ˜ํ–ˆ๋‹ค๋ฉด ๋ฆฌ์…‹ ์ปค๋ฉ˜๋“œ๋กœ ์ƒํ™ฉ์„ ๋น ์ ธ๋‚˜์™€์•ผ ํ•œ๋‹ค.
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5. UTILIZING THE DEVICE IN THE SAME SYSTEM DESIGN

5-1. Pin Assignment(4Mb,8Mb,16Mb,32Mb,64Mb)

Vcc CE/ RE/ R/B SE/* NC NC NC NC NC

NC NC NC NC NCI/O7I/O6I/O5I/O4Vcc

Vss CLE ALE WE/ WP/ NC NC NC NC NC

NC NC NC NC NCI/O0I/O1I/O2I/O3Vss

12345678910111213141516171819202122

GND

SE* :Low Level Input : 528 Byte/Page Operation High Level Input : 512 Byte/Page Operation

SAMSUNG has been manufacturing the 4Mb,8Mb,16Mb, 32Mb and 64Mb NAND Flashin the same package, 44(40) TSOP 2. It allows the system developer to utilize the4Mb~64Mb NAND devices in Flash design boards without any hardware changes.The following is a pin assignment comparison between the SAMSUNG`s 4Mb~64MbNAND Flash devices.

44434241403938373635343332313029282726252423

32Mb & 64Mb

4Mb,8Mb,16Mb

44-TSOP II

FIG. 5-1 PIN ASSIGNMENT for 4Mb,8Mb,16Mb,32Mb,64Mb

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5-2. Pin Assignment(128Mb ~ 256Mb)

N.C N.C N.C N.C N.C SE/ R/B RE/ CE/ N.C N.C Vcc Vss N.C N.C CLE ALE WE/ WP/ N.C N.C N.C N.C N.C

N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C

123456789101112131415161718192021222324

484746454443424140393837363534333231302928272625

48-TSOP I

-1220F

5-3. Device ID Information

4Mb

8Mb

16Mb

32Mb

64Mb

128Mb

256Mb

DensitySAMSUNG

A4H

-

EAH

E3H

E6H

-

-

A4H

-

64H

E5H

-

-

-

-

-

-

-

E6H

73H

75H

A4H

6EH

EAH

E3H

-

-

-

3.3V 5.0V 2.7V~3.6V 2.7V~5.5V

Device Part Number => 3.3V : KM29V ~, 5.0V : KM29N ~, 2.7V~3.6V : KM29U ~,2.7V~5.5V : KM29W ~ Device ID of 256Mb and beyond may be changed according totheir feature.

FIG. 5-2 PIN ASSIGNMENT for 128Mb ~ 256Mb

TABLE 5-1. DEVICE ID

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5-4. Addressing Map : 4Mb ~ 256Mb

- 4M Flash

1st Cycle 2nd Cycle 3rd Cycle

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

A0

A8

A16

A1

A9

A17

A2

A10

A18

A3

A11

A4

A12

X*

A5

A13

X*

A6

A14

X*

A7

A15

X*X* X*

- 8M,16M Flash

1st Cycle 2nd Cycle 3rd Cycle

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

A0

A15

A1

A8

A16

A2

A9

A17

A3

A10

A4

A11

A19

A5

A12

A20

A6

A13

X*

A7

A14

X*A18 X*

X* : Can be High or Low.

Col. Add.(A0~A4)Frame Add.(A5~A6)

Row Add.(A7~A11)Block Add.(A12~A18)

Col. Add.(A0~A7)

Row Add.(A8~A11)

8M Block Address : A12 ~ A19(A20 : X*), 16M Block Address : A12 ~ A20

8M16M

- 32M,64M,128M,256M Flash

32M Row Address : A9 ~ A12, 32M Block Address : A13 ~ A21(A22 ~ A24 : X*)64M Row Address : A9 ~ A12, 64M Block Address : A13 ~ A22(A23, A24 : X*)128M Row Address : A9 ~ A13, 128M Block Address : A14 ~ A23(A24 : X*),256M Row Address : A9 ~ A13, 256M Block Address : A14 ~ A24A8 : Initially set to "Low" or "High" by the 00H or 01H Command

1st Cycle 2nd Cycle 3rd Cycle

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

A0

A16

A1

A9

A17

A2

A10

A18

A3

A11

A4

A12

A20

A5

A13

A21

A6

A14

A22

A7

A15

A24A19 A23

X* : Can be High or Low.

32M64M

128M256M

Col. Add.(A0~A7)

The address map for the 4Mb ~ 256Mb devices are shown in table 5-2 :

TABLE 5-2. ADDRESS MAP for 4Mb ~ 256Mb

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5-5. Specification Comparison : 4Mb ~ 256Mb

Note * : 1 Page = 4 Frames = 128 Byte

4Mb 8Mb

Page size

Block size

Number of page

per block

Organiza-tion

32 Byte(Frame size)*

4K Byte

32 pages

(256 + 8) Byte

(4K + 128) Byte

16 pages

Operating voltage

Package

2.7V~5.5V

44 (40) Pin 400 mil Width 0.8mm Pitch TSOP Type II

tR

Cycle time

Main cha-racteristics

15 us Max.

120 ns Min.

10 us Max.

80 ns Min.

16 pages

(4K+128 ) Byte

(256 + 8) Byte

16Mb

10 us Max.

80 ns Min.

3.3V,5V,2.7V~5.5V 3.3V,5V,2.7V~5.5V

tPROG

tBERS

0.5 ms Typ. 0.25 ms Typ. 0.25 ms Typ.

6.0 ms Typ. 2.0 ms Typ. 2.0 ms Typ.

32Mb 64Mb 128Mb/256Mb

48 TSOP I

Page size

Block size

Number of page

per block

Organiza-tion

(512 + 16) Byte

(8K + 256) Byte

16 pages

(512 + 16) Byte

(8K + 256) Byte

16 pages

Operating voltage

Package

2.7V~3.6V

44 (40) Pin 400 mil 0.8mm Pitch TSOP Type II

tR

Cycle time

Main cha-racteristics

10 us Max.

50 ns Min.

7 us Max.

50 ns Min.

32 pages

(16K+512 ) Byte

(512 + 16) Byte

10 us Max.

50 ns Min.

3.3V,5V,2.7V~5.5V 2.7V ~ 3.6V

tPROG

tBERS

0.25 ms Typ. 0.2 ms Typ. 0.2 ms Typ.

2.0 ms Typ. 2.0 ms Typ. 2.0 ms Typ.

TABLE 5-4. SPECIFICATION COMPARISON for 32Mb ~ 256Mb

TABLE 5-3. SPECIFICATION COMPARISON for 4Mb ~ 16Mb

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5-6. Upgrading to 512Mb ~ 1Gb

All for 256Mb except following items, hardware and software conditions, is effective in512Mb to 1Gb flash memory.

- Address Map

A8 : Initially set to "Low" or "High" by the 00H or 01H Command

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

1st Cycle A0 A1 A2 A3 A4 A5 A6 A7

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

4th Cycle A25 A26

512Mb

1Gb

- Device ID

512Mb 1Gb

ID 76h 79h

TABLE 5-5. EXLPANSION for 256Mb/1Gb

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6. Hardware Design Considerations

The device allows any don`t-care states during read, program and erase operation asfollows.

6-1. Acceptable Don`t-Care Area in each Operation

โ€ข Program Operation

R/B

I/O 0~ 7 80H Add. Input 10H

tPROG

RE/

CLE

CE/

WE/

ALE

Data Input

don`t-care

โ€ข Read Operation

R/B

RE/

I/O 0~ 7 00H Start Add. (3Cycle) Data Output (Sequential)

CLE

CE/

WE/

ALE

don`t-care

โ€ข Block Erase Operation

R/B

I/O 0~ 7 60H Add. Input D0H

tBERS

RE/

CLE

CE/

WE/

ALE

70H Dout Dout

don`t-care

FIG. 6-1 DON`T CARE AREA

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6-2. VccQ/Vcc Power Connecting

โ€ข If System VCC=3.3V

MCUNANDFlash

VCCQ VCCVCC

System VCC(3.3V)

โ€ข If System VCC=5V

MCUNANDFlash

VCCQ VCCVCC

System VCC(5V)DC/DC

MCUNANDFlash

VCCVCC

System VCC(5V)

DC/DC

3.3V

3.3V

The NAND Flash can be utilized on either 3.3V or 5.0V interface by connecting 3.3V or5.0V power supply on the VccQ. The VccQ for I/O interface power line is electricallyisolated from main chip's power line. It is not required to shift logic level between the5V system and 3.3V NAND Flash. The Vcc power line has to be connected to 3.3Vpower supply on the system side. If system Vcc could change between 3.3V and 5Vdepending on its host system power, wide range products(2.7V~5.5V) available from4Mb ~ 32Mb NAND Flash can be proper choices to eliminate DC-DC converter. Somedensities and generations do not support 5V I/O interface. To get exact information fora specific product, refer to the specifications on Flash section of Samsung`s web-site.

FIG. 6-2 POWER CONNECTING

juc23
ํ˜„์žฌ๋Š” 3.3 ๋ณผํŠธ ๋ฒ„์ ผ๋งŒ์„ ์ด์šฉํ•˜๋ฏ€๋กœ ์ด ๋ถ€๋ถ„์€ ๋ณ„ ์˜๋ฏธ๊ฐ€ ์—†๋‹ค. ํ˜„์žฌ๋Š” ์ €์ „์•• ๋””๋ฐ”์ด์Šค(1.8๋ณผํŠธ)๋„ ๋‚˜์˜ค๊ณ  ์žˆ์œผ๋ฏ€๋กœ ์ด ๋ถ€๋ถ„์€ ์‹ ๊ทœ ๋ฐ์ดํ„ฐ ์‰ฌํŠธ๋ฅผ ์ฐธ์กฐํ•˜๋ฉด ๋œ๋‹ค.
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โ€ข VccQ/Vcc Power Start Up Sequence

Vcc

VccQ

Vcc

VccQ

Vcc

VccQ

DC power consumed

DC power consumed

No DC path occurred

When the system is started up, Flash device may be powered with each of VccQ andVcc at different instant. At this case, DC power under 20mA range may be consumeduntil the power reach their final level. It is recommended to start each Vcc and VccQpower simultaneously.

6-3. Data Protection

NAND Flash is designed to offer protection from any involuntary program/ erase duringpower transitions. An internal voltage detector disables all functions whenever Vcc isbelow about 2V. WP/ pin provides hardware protection and is recommended to be keptat VIL during power-up and power down as shown following figure. The 2step commandsequence for program/ erase provides additional software protection.

Vcc

WP/

~ 2.5V ~ 2.5V

VIH

VIL

ยก รณ

ยก รณ

AC Waveform for Power Transition

FIG. 6-3 POWER SEQUENCE

FIG. 6-4 DATA PROTECTION

juc23
ํ”Œ๋ ˆ์‰ฌ๋Š” ๋น„์•ˆ์ • ํŒŒ์›Œ ๊ตฌ๊ฐ„์—์„œ ๊ณ ์˜๊ฐ€ ์•„๋‹Œ ์“ฐ๊ธฐ๋‚˜ ์ฝ๊ธฐ๊ฐ€ ์ผ์–ด๋‚˜๋Š” ๊ฒƒ์„ ๋ง‰๊ธฐ์œ„ํ•œ ์žฅ์น˜๊ฐ€ ๋˜์–ด์žˆ๋‹ค.vcc๊ฐ€ 2๋ณผํŠธ ์ดํ•˜๋กœ ๋‚ด๋ ค๊ฐ€๋ฉด ๋‚ด๋ถ€ ์ „์•• ๋””ํ…ํ„ฐ๊ฐ€ ๋ชจ๋“  ๊ธฐ๋Šฅ์˜ ๋™์ž‘์„ ๋ชปํ•˜๊ฒŒ ๋งŒ๋“ ๋‹ค. WP/ํ•€์ด ํ•˜๋“œ์›จ์–ด์ ์œผ๋กœ ๋ณดํ˜ธ๋ฅผ ํ•ด์ฃผ๋Š”๋ฐ ํŒŒ์›Œ์—…์ด๋‚˜ ํŒŒ์›Œ ๋‹ค์šด์—์„œ ํ•ด๋‹น ํ•€์€ ๋กœ์šฐ ๋ ˆ๋ฒจ์„ ์œ ์ง€ํ•˜๊ณ  ์žˆ์–ด์•ผํ•œ๋‹ค. ์“ฐ๊ธฐ๋‚˜ ์†Œ๊ฑฐ ๋™์ž‘์ผ๋•Œ ๋‘ ๋‹จ๊ณ„๋ฅผ ๊ฑฐ์น˜๋Š” ๊ฒƒ๋„ ์†Œํ”„ํŠธ์›จ์–ด์ ์ธ ๋ณดํ˜ธ๊ธฐ๋Šฅ์œผ๋กœ ๋ณผ ์ˆ˜ ์žˆ๋‹ค.
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6-4. R/ B : Termination for the Ready/Busy Pin

A pull-up resistor needs to be used for termination because the Ready/Busy bufferconsist of an open drain circuit.

Vcc

Vss

R

CL

R/BDevice

tf tr

Ready

Busy

Vcc

Falling time(tf) may vary a little by device. We recommend that you use this data as areference when selecting a resistor value.

1K 2K 3K 4K R:(ohm)

1.5us

1.0us

0.5us

tr tf

tr

5ns

4ns

3ns

Vcc=3.3V Ta=25'C CL=100pF

Ris

ing

time

(ns)

tfF

allin

g tim

e (n

s)

0.189

0.096

0.2900.381

4.214.224.234.25

0.8V

2.0V

FIG. 6-5 READY/BUSY SIGNAL SIMULATION

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ELECTRONICS28

7-1. Device Behavior for WP/ Signal

Program Operation

I/O

7. Miscellaneous

Erase and program operations are compulsively reset if WP/ goes low when thecommand sets are given as following Fig. 7-1 and 7-2.

80h

WP/

10h

FIG. 7-1 WP/ GOES LOW DURING COMMAND INPUT

Timing Diagram

Erase D0h

WP/

FIG. 7-2 WP/ GOES LOW DURING ERASE/PROGRAM OPERATION

R/B

Program 10h

Compulsive Reset

The previous operation is aborted even if WP/ returns to thehigh state and the device is ready for the next command.

80h 10hI/O

WP/

Program operation does not start Program operation start normally

I/O 60h

WP/

D0h 60h D0hI/O

WP/

Erase operation does not start Erase operation start normally

Erase Operation

I/O 00h

WP/

Add1

Read operation can be executed normally regardless of WP/ status.

Read Operation

Add2 Add3

juc23
์†Œ๊ฑฐ๋‚˜ ์“ฐ๊ธฐ ๋™์ž‘ ์ปค๋ฉ˜๋“œ ๋ช…๋ น์ด ์ธ๊ฐ€๋˜์–ด ์žˆ๋Š” ๋„์ค‘์— wp ๋ ˆ๋ฒจ์ด ๋ฐ”๋€Œ๋ฉด(๋กœ์šฐ๋กœ) ๊ฐ•์ œ์ ์œผ๋กœ ๋ฆฌ์…‹๋˜๊ฒŒ ๋˜์–ด ์žˆ๋‹ค. ์•„๋ž˜ ๊ทธ๋ฆผ์„ ๋ณด๋ฉด ์ปค๋ฉ˜๋“œ ๋„์ค‘์— ๋ ˆ๋ฒจ์ด ๋ฐ”๋€Œ๋Š” ๊ฒฝ์šฐ ํ•ด๋‹น ๋™์ž‘์ด ์•„์˜ˆ ์‹œ์ž‘๋˜์ง€๋„ ์•Š๋Š”๊ฒƒ์„ ๋ณผ ์ˆ˜ ์žˆ๋‹ค. ๊ทธ๋Ÿฌ๋‚˜ ์ฝ๊ธฐ ๋™์ž‘์—์„œ๋Š” ์•„๋ฌด๋Ÿฐ ํ•ด๋‹น ์‚ฌํ•ญ์ด ์—†๋‹ค.
juc23
์“ฐ๊ธฐ๋‚˜ ์†Œ๊ฑฐ ๋ช…๋ น์˜ ๋‘ ๋ฒˆ์งธ ํ™•์ธ ์ปค๋ฉ˜๋“œ๊ฐ€ ๋‚˜๊ฐ€์„œ ์‹ค์ œ ๋™์ž‘์ด ์ง„ํ–‰์ค‘์ผ๋•Œ wp ๋ ˆ๋ฒจ์ด ๋ฐ”๋€Œ๋ฉด ์–ด๋–ป๊ฒŒ ๋˜๋Š”๊ฐ€.. wp๊ฐ€ ๋‹ค์‹œ ํ•˜์ด๋กœ ์˜ฌ๋ผ๊ฐ€๋„ ํ•ด๋‹น ์ง„ํ–‰์ค‘์ด๋˜ ๋™์ž‘์€ ๋ฌด์‹œ๋˜๊ณ  ๋‹ค์Œ ๋™์ž‘์„ ๊ธฐ๋‹ค๋ฆฌ๊ฒŒ ๋œ๋‹ค.
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7-2. Device Behavior for Excess Data Input Cycles

In erase/program/read operation, the extra data are ignored if extra data are given asfollowing Fig. 7-3.

Read

ALE

I/O

Programming (Address Input)

Data input

ALE

I/O

Address input

Erase

ALE

I/O

Block Address input

00H Add1 Add2 Add3 Add4

80H Add1 Add2 Add3 Add4 Add5

60H Add2 Add3 Add4 Add5 D0H

Ignored(~ 256Mb)

Programming (Data Input)

WE/

ALE

I/O80H 10H

Data 528 Ignored

D527D0 D1 D2 D528 D529

Address

Instead of 528 toggles with 32Mb and beyond, 8Mb and 16Mb NAND Flash functionthe same way after 264 toggles.

FIG. 7-3 EXCESS DATA INPUT

Add5

Ignored (512Mb ~ )

Ignored(~ 256Mb) Ignored

(512Mb ~ )

Ignored(~ 256Mb) Ignored

(512Mb ~ )

juc23
๊ทœ์ •๋œ ์‚ฌ์ดํด๋ณด๋‹ค ๋งŽ์€ ๋ฐ์ดํ„ฐ๊ฐ€ ์ธ๊ฐ€๋˜๋ฉด ์–ด๋“œ๋ ˆ์Šค์ด๊ฑด, ๋ฐ์ดํ„ฐ์ด๊ฑด ๋ชจ๋‘ ๋ฌด์‹œ๋œ๋‹ค.
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7-3. Reset Operation

โ€ข Address Register : All '0โ€ข Data Register : All '1โ€ข Operation Mode : Wait State

The response after 'FFH' reset command input during each operation is as follows :

(1) In the case that reset command is input during programming.

Internal Vpp

R/B

10H FFH 00H

About 10us

Internal Vpp

R/B

FFH 00H

About 500us

(2) In the case that reset command is input during erasing.

R/B

FFH 00H

About 5us

(3) In the case that reset command is input during read operation.

D0H

80H

00H

Reset mode stops all operations compulsorily. For example, in the case of Program orErase operation, the regulated voltage is discharged to 0 volts and the device will go tothe wait state. The address and data registers are set after a reset as follows.

FIG. 7-4 RESET OPERATION

juc23
๋ฆฌ์…‹์€ ๋ชจ๋“  ๋™์ž‘์„ ๊ฐ•์ œ์ ์œผ๋กœ ๋ฉˆ์ถ”๊ฒŒ ํ•œ๋‹ค. ์˜ˆ๋ฅผ ๋“ค์–ด ์“ฐ๊ธฐ๋‚˜ ์†Œ๊ฑฐ ๋™์ž‘์ค‘์— ๋ฆฌ์…‹์ด ์ธ๊ฐ€๋˜๋ฉด ํ˜•์„ฑ๋œ ๋‚ด๋ถ€ ์ „์••์€ ๋ฐฉ์ „๋˜๊ณ  ๋””๋ฐ”์ด์Šค๋Š” ๋Œ€๊ธฐ ๋ชจ๋“œ๋กœ ๋“ค์–ด๊ฐ„๋‹ค. ์–ด๋“œ๋ ˆ์Šค๋‚˜ ๋ฐ์ดํ„ฐ ๋ ˆ์ง€์Šคํ„ฐ๋Š” ์•„๋ž˜์˜ ๊ฐ’์„ ๊ฐ–๊ฒŒ ๋œ๋‹ค. ๊ฐ ๋™์ž‘์ค‘์— ๋ฆฌ์…‹์ด ์ธ๊ฐ€๋œ ํ›„์˜ ๋ฐ˜์‘์€ ์•„๋ž˜ ๊ทธ๋ฆผ๊ณผ ๊ฐ™๋‹ค.