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““Pay it ForwardPay it Forward””, is it worth it?, is it worth it?Alan Romriell (Spansion) & Amy Leong (FormFactor)Alan Romriell (Spansion) & Amy Leong (FormFactor)

San Diego, CA USA June 4San Diego, CA USA June 4thth 20072007

SWTW 2007 - 2 - Spansion and FormFactor

AgendaAgenda

▪▪Wafer Test Cost CrisisWafer Test Cost Crisis▪▪Opportunities for Test InnovationOpportunities for Test Innovation▪▪Case StudyCase Study

▫▫ Proposed Test Flow RepartitioningProposed Test Flow Repartitioning▫▫ AssumptionsAssumptions▫▫ Scenario 1: Reduce Package CostScenario 1: Reduce Package Cost▫▫ Scenario 2: Reduce Test CostScenario 2: Reduce Test Cost▫▫ Scenario 3: Improve Product YieldScenario 3: Improve Product Yield▫▫ Case Study SummaryCase Study Summary

▪▪ConclusionsConclusions


Wafer Test Cost CrisisWafer Test Cost CrisisDangerous trend in device ASP and test costDangerous trend in device ASP and test cost

*Source: Gartner & FFI Marketing

NOR ASP is declining at much faster rate than wafer test cost!

Aver

age P

rice &

Wafe

r Tes

t Cos

t Av

erag

e Pric

e & W

afer T

est C

ost

per M

b ($)

per M

b ($)

20022002 20032003 20042004 20052005 20062006 20072007 20082008 20092009 20102010 20112011

NOR ASP NOR ASP

CAGR (2002CAGR (2002--06): 06): --33%33%

NOR Test CostNOR Test Cost

CAGR (2002CAGR (2002--06): 06): --18%18%


Wafer Test Cost CrisisWafer Test Cost CrisisCost challenges lead to industry consolidationCost challenges lead to industry consolidation

11

22

33

44

55

66

77

88

99

1010

??


20042004 20072007 20102010

??[[ ]]


Wafer Test Cost CrisisWafer Test Cost Crisis

DangerDanger OpportunityOpportunity

CHINESE CHARACTERS FOR CHINESE CHARACTERS FOR ““CRISISCRISIS””


Opportunities for Test InnovationOpportunities for Test Innovation

Sort 1

Assy

FT

Sort n

Test Flow

100% Cost

<50% Cost

• Test Innovation: Migrate test upstream

• Cost reduction can move ahead of device ASP decline

Burn-in


Case StudyCase StudyProposed Test Flow RepartitioningProposed Test Flow Repartitioning

BURNBURN--ININ SORTSORTTEMP NTEMP N

@ SPEED@ SPEEDTESTTEST

PKGPKGBIBI

FINALFINALTESTTESTPKGPKG’’INGINGSORTSORT

TEMP 1TEMP 1

SORTSORT22

PKGPKGBIBI

FINALFINALTESTTESTPKGPKG’’INGINGSORTSORT

11

Typical Test FlowTypical Test Flow

Proposed Test FlowProposed Test Flow


Case StudyCase StudyProbe Card ProductsProbe Card Products

FFI High Frequency Probe Card (HFTAP)FFI UPStream Probe Card

Wafer Level BI At speed Test


Case Study Case Study AssumptionsAssumptions

▪▪Die/200mm Wafer Die/200mm Wafer EqvEqv: 800 : 800 dpwdpw▫▫ Typical Devices: 70nm 512Mb DDR2, 90nm 256Mb NORTypical Devices: 70nm 512Mb DDR2, 90nm 256Mb NOR

▪▪Run Rate: 100,000 Run Rate: 100,000 wspmwspm (200mm (200mm eqveqv.).)▫▫ Typical 300mm fab maximum capacity: ~40Typical 300mm fab maximum capacity: ~40--45k WSPM45k WSPM

▪▪ Yield Assumptions:Yield Assumptions:▫▫ 95% Wafer Test Yield95% Wafer Test Yield▫▫ 95% Package Yield95% Package Yield▫▫ 98% Final Test Yield 98% Final Test Yield


Scenario 1: Reduce Package CostScenario 1: Reduce Package Cost

Scenario 1: WLBI eliminates more nonScenario 1: WLBI eliminates more non--repairable diesrepairable dies▫▫ Save package cost for the nonSave package cost for the non--repairable diesrepairable dies


Scenario 1: Reduce Package CostScenario 1: Reduce Package CostWafer Test Opportunity to Reduce Packaging CostWafer Test Opportunity to Reduce Packaging Cost

13% 17%21% 26%

0%10%

20%30%

40%50%

60%70%

80%90%

100%

SDRAM DDR DDR-2 DDR-3

Raw Wafer Front-end Processing Testing Costs Packaging Costs

▪▪ Increasing packaging cost as Increasing packaging cost as % in product cost % in product cost

▪▪ 1% wasted package = $12M 1% wasted package = $12M annual revenue loss annual revenue loss

▫▫ BGA: BGA: --> $1 per unit> $1 per unit▫▫ 300 Million Units/Qtr300 Million Units/Qtr



Scenario 1: Reduce Package CostScenario 1: Reduce Package CostTradeTrade--off Questionsoff Questions

Question: But I have to spend more $ on wafer test Capex and probe card. How does it compare to the package cost saving?

Answer is …


Scenario 1: Reduce Package Cost Scenario 1: Reduce Package Cost Packaging Cost Saving vs. Increased Wafer Test InvestmentPackaging Cost Saving vs. Increased Wafer Test Investment

$9.7

$19.4

$29.1

$38.8

$0

$10

$20

$30

$40

$50

1.00% 2.00% 3.00% 4.00%

Economically Economically worthwhile to worthwhile to increase wafer increase wafer test to reduce test to reduce package costpackage cost

Annual Investment for BI at Wafer Annual Investment for BI at Wafer Level (Level (CapexCapex + Consumable)+ Consumable)

Annual Package Cost Saving by EliminatingAnnual Package Cost Saving by EliminatingNonNon--repairable Bad Dies at Wafer Testrepairable Bad Dies at Wafer Test

% of bad die in package% of bad die in package

Pack

aging

Cos

t Sav

ing ($

m)Pa

ckag

ing C

ost S

aving

($m)

6 min WLBI

2 min WLBI


Scenario 2: Reduce WLBI Test CostScenario 2: Reduce WLBI Test CostIntroduce High Temp BI at Wafer LevelIntroduce High Temp BI at Wafer Level

Case 2: Add High temperature WLBI to reduce BI costCase 2: Add High temperature WLBI to reduce BI cost▫▫ Reduce package BI timeReduce package BI time▫▫ Detect more early life failuresDetect more early life failures▫▫ Earlier and more data for feedback to FabEarlier and more data for feedback to Fab


Scenario 2: Reduce WLBI Test CostScenario 2: Reduce WLBI Test CostBI Test Cost ReductionBI Test Cost Reduction

▪▪Decreased total test costDecreased total test cost▫▫ 41% with WLSBI @ 12541% with WLSBI @ 125°°CC▫▫ 64% with WLSBI @ 14064% with WLSBI @ 140°°CC

▪▪ Increased yieldIncreased yield▫▫ 2% yield increase after package BI2% yield increase after package BI

▪▪Reduced package BI timeReduced package BI time▫▫ BI time cut in half with 140BI time cut in half with 140°°CC

Cost/

Unit

+2% Yield

Conventional BI

WLBI (300s@125C)

+2% Yield

WLBI (180s@ 140C)

100%

59%

36%


Scenario 2: Reduce WLBI Test CostScenario 2: Reduce WLBI Test CostTradeTrade--off Questionsoff Questions

Question: Can the probe card work reliably at high Question: Can the probe card work reliably at high temperature in production environment?temperature in production environment?

Answer is …


Scenario 2: Reduce WLBI Test CostScenario 2: Reduce WLBI Test CostHigh Temperature BI Probe CardHigh Temperature BI Probe Card

FFI proprietary thermally optimized system for

stable planarity at high temperature

Selection of high temperature electronic

component

MicroSpring™ optimized for tight pitch at high temperature

▪ WLBI probe card needs to be optimized for ▫ High temperature▫ High parallelism▫ Low pad damage


Scenario 3: Improve Product YieldScenario 3: Improve Product YieldMigrate Partial Final Test to Wafer LevelMigrate Partial Final Test to Wafer Level

▪▪ Scenario 3: Moving some final test to wafer Scenario 3: Moving some final test to wafer ▫▫Detect and repair more dies to improve product yieldDetect and repair more dies to improve product yield▫▫Higher probing temperature to replicate final test conditionsHigher probing temperature to replicate final test conditions▫▫At speed test to validate device performanceAt speed test to validate device performance


Scenario 3: Improve Product YieldScenario 3: Improve Product YieldTradeTrade--off Questionsoff Questions

Question: High speed testers are very expensive. How much yield gain do I need to make it worthwhile?

Answer is …


BREAKBREAK--EVEN POINTEVEN POINT

Scenario 3: Improve Product YieldScenario 3: Improve Product YieldYield Gain vs. Increased Wafer Test InvestmentYield Gain vs. Increased Wafer Test Investment

$33.6

$67.2

$105.6

$139.2

$0

$30

$60

$90

$120

$150

1.00% 2.00% 3.00% 4.00%

Economically Economically worthwhile to worthwhile to increase wafer increase wafer test to Improve test to Improve

yieldyield

Annual Product Revenue Gain byAnnual Product Revenue Gain byMigrating Final Test to Wafer for Yield GainMigrating Final Test to Wafer for Yield Gain

As expensive as high speed wafer sort sounds, 1%

product yield gain would make it all worthwhile!% of die gain by repair at wafer level% of die gain by repair at wafer level

Prod

uct R

even

ue G

ain ($

m)Pr

oduc

t Rev

enue

Gain

($m)

Typical range of annual Wafer Test Typical range of annual Wafer Test Investment for High Speed Wafer Investment for High Speed Wafer

Sort (Sort (CapexCapex + Consumable)+ Consumable)



Question: Will high frequency sort work in high parallelism? Where are the limits?

Answer is …



▪▪ Answer Answer ……▫▫ Simulations look promisingSimulations look promising▫▫ FFI has proven expertise on high frequency probingFFI has proven expertise on high frequency probing

−−Demonstrated x2 TRE @ 100MHz (SWTW Paper 2004)Demonstrated x2 TRE @ 100MHz (SWTW Paper 2004)−−Demonstrated up to 500MHz for non TREDemonstrated up to 500MHz for non TRE

▫▫ So there is only one way to find out whether it works: So there is only one way to find out whether it works: Try it!Try it!▫▫ The benefits are there, go for them! The benefits are there, go for them!

Question: Will high frequency sort work in high parallelism? Where are the limits?


Case Study SummaryCase Study SummaryEconomics BenefitsEconomics Benefits

Annual Product Cost Benefit by Test Flow OptimizationAnnual Product Cost Benefit by Test Flow Optimization

Economically Economically worthwhile if gain > 1% worthwhile if gain > 1%

yield differenceyield difference

$33.6

$9.7

$67.2

$19.4

$105.6

$29.1

$139.2

$38.8

$0

$30

$60

$90

$120

$150

1.00% 2.00% 3.00% 4.00%

Scenario 3: Product Revenue GainScenario 1: Package Cost Saving


Case Study SummaryCase Study SummaryEconomics Benefits for MCPEconomics Benefits for MCP

▪▪ Economic benefits for MCP will be Economic benefits for MCP will be even bigger!even bigger!

▪▪ 1% yield delta for single chip = 5% 1% yield delta for single chip = 5% yield delta for 5yield delta for 5--die MCPdie MCP

Picture of Multi-chip-package (MCP)

MCP Yield Curve vs. Single Die Yield


ConclusionsConclusions

▪▪ Memory device market price pressure calls for test innovation toMemory device market price pressure calls for test innovation to reduce product reduce product costcost

▪▪ Migrating test upstream can provide earlier feedback for improveMigrating test upstream can provide earlier feedback for improved yield and d yield and downdown--stream manufacturing cost savings for the nonstream manufacturing cost savings for the non--repairable device on waferrepairable device on wafer

▪▪ The incremental increase in wafer test spending can be easily juThe incremental increase in wafer test spending can be easily justified if >1% stified if >1% yield difference is realizedyield difference is realized

▪▪ The benefits are there, go for them!The benefits are there, go for them!

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