Anti-islanding

Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System

Satabdy Jena, Gayadhar Panda and Rangababu Peesapati

Presented by:

Dr. Rangababu Peesapati

Assistant Professor

National Institute of Technology Meghalaya

India.

Outline

Introduction

Topology of the system

DG Inverter Control

DG Islanding & Anti-islanding protection schemes for grid connected inverter system

Simulation Study

HIL co-simulation of grid-connected inverter system

Conclusion

Future Scope

References211/13/2016 Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System

Introduction

11/13/2016 Investigation on FPGA based Passive Anti-Islanding Protection Schemes for Grid Interfaced Distributed Generation System 3

• Conventional resources are under immense pressure due to increasing population

and increasing demand.

• Renewable energy resources have emerged as the most promising alternative.

• Grid Interfaced Distributed Generation (DG) possess the potential to meet local

demand of power as well as feed the excess power to the grid.

• Safety of critical loads, devices and personnel: Reliable tripping is required.

• Anti-islanding detection.


Fig.1. Topology of system

MPPT PWMSPWM MAF-

PLL

Modulating

Signal

Generation

DC-

LINK

PI

PV

+-

V*dc

vdc

3-ф

Inverter

Filter

Inductance

Isolation

Transformer

ia,b,c

ua,b,c

iq*

id*

iq

uq

Grid

abc

dq

ud* uq*

DC/DC

Boost

Converter

LfRf

Cf LtRt

ϴ ϴ

Reference

Signal

Generation

md

q

Xilinx System Generator

ipv

vpv LOAD

Anti-islanding

Protection

B2B1

TripTrip

Trip

f

PCC

id

iq

+

+

-

-

PI

PI

id

ud

ωL

+

+

+

++

-

ωL

Decoupling

Technique

MATLAB/Simulink

FPGA ML605

Evaluation platform


Moving Average Filter (MAF) : linear-phase finite impulse response filter

• Easy to realize in practice

• Effective in terms of computational burden

• 𝐺𝑀𝐴𝐹 =1

𝑁

1−𝑧−𝑁

1−𝑧−1

* *u * K (i i ) K (i i )dt ωLi uq p q q i q q d q

* *u * K (i i ) K (i i )dt ωLi ud p d d i d d q d

Decoupling Control : Control of d-q axes currents

DG Inverter Control

ωf

PI + ʃ

0

ω'θ

-+abc

dq

uq++

Z-1 Z-N

1

N+-

MAF

Kf

ua,b,c

Fig.2. MAF-Phase Locked Loop


DG Islanding

Islanding: DG continues to supply power to a location even though the electric utility is not present.

Types-

• Intentional

• Unintentional

Problems-

• Safety concerns

• End-user equipment damage

• Degradation of electrical components

• Out of phase reclosing of DG

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Remote Protection Schemes: Active and Passive.

Employed Schemes-

DC-Link protection

Over and Under frequency protection

Rate of change of frequency

The FPGA implementation enables for the automation of

the grid.

>

>

>

OR

OR

+-

(a)

(b)

(c)

˂

˂

z-1

d

dt β

vdc

vdc,high

vdc,low

flow

fhigh

f

f

Trip

Trip

Trip

Fig.3. AI Protection Schemes


Anti islanding Protection Schemes

The following cases were investigated :

• Loads less than the PV generation

• Resistive (P = 50 kW)

• Inductive (P = 50 kW, Q = 10 kVAr)

• Capacitive (P = 50 kW, Q = 10 kVAr)

• Loads greater than the PV generation




• Loads equal to PV generation





Simulation Study

System parameters Value System parameters Value

Series connected modules 7 DC Link voltage 750 V

Parallel connected

modules

40 Filter inductance and resistance 1 mH, 3 mΩ

MPP Voltage 54.7 V Grid inductance and resistance 16 mH, 0.8929 Ω

MPP Current 5.58 A Transformer inductance and

resistance

0.06 mH, 0.002 mΩ

Open-circuit voltage 64.2 V Inverter switching frequency 5 .5 kHz

Short-circuit current 5.96 A Boost switching frequency 5 kHz

Maximum PV power

(STC, S = 1000 W/m2)

85 kW Grid voltage 400 V

DC Link capacitor 5000 μF Grid frequency 50 Hz


Table 1. System parameters

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Local loads less than PV generation: (a) Resistive load (P=50 kW)

(b) Inductive load (P=50 kW, Q=10 kVAr)Fig.4. Power exchange Fig.5. Relay response

Fig.6. Power exchange Fig.7. Relay response


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(c) Capacitive load (P=50 kW, Q=10 kVAr)

Fig.9. Relay responseFig.8. Power Exchange

Fig.10. Frequency deviation Fig.11. Voltage deviation


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Local loads greater than PV generation: (a) Resistive load (P=110 kW)

(b) Inductive load (P=110 kW, Q=50 kVAr)

Fig.12. Power Exchange Fig.13. Relay response

Fig.15. Relay responseFig.14. Power Exchange


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Fig.16. Power Exchange Fig.17. Relay Response

Fig.18. Frequency deviationFig.19. Voltage deviation


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Local loads equal to PV generation: (a) Active load (P=80 kW)

(b) Inductive load (P=80 kW, Q=50 kVAr)




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Fig.25. Relay ResponseFig.24. Power Exchange

Fig.26. Frequency deviationFig.27. Voltage deviation


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Table 2. Comparison of Relay Response

Gen-load

Relay

Load less than PV power Load more than PV power Load equals PV power

Resistive

(Relay

Time (s))

Inductive

(Relay

Time (s))

Capacitive

(Relay

Time (s))

Resistive

(Relay

Time (s))

Inductive

(Relay

Time (s))

Capacitive

(Relay

Time (s))

Resistive

(Relay

Time (s))

Inductive

(Relay

Time (s))

Capacitive

(Relay Time

(s))

Over-

Frequency

No

Trip

0.0792 No

Trip

0.1107 0.0732 0.0438 0.0764 0.0735 No

Trip

Under-

Frequency

0.3407 No

Trip

0.177 0.3417 No

Trip

No

Trip

0.3774 No

Trip

0.1077

ROCOF 0.0121 0.0864 0.0293 0.0296 0.0315 0.0293 0.0429 0.0486 0.0084

DC-Link 0.07123 0.0132 0.0295 0.0297 0.0317 0.0295 0.0431 0.0487 0.0085



Simulink as FPGA design tool is easy to use as there is no need of learning HDL.

Hardware co-simulation is achieved by Xilinx System Generator which puts hardware into Simulink

design.

It enables automatic data exchange.

It supports FPGA chips with JTAG programming.

HIL Co-simulation study

Fig.28. FPGA building blocks Fig.29. Configuration of each logic block


HIL Implementation

Fig.30. Ani-islanding protection schemes in XSG


Fig.31. PLL, Reference Signal generation and Voltage controller in XSG


Fig.32. Behavioral simulation for (a) PLL (b) Current Controller (c) SPWM


Design Slice

Registers

(301440)

Slice

LUTs

(150720)

LUT FF

Pairs

Slices

(37680)

IOBS

(600)

Memory

(58,400)

Critical Path delay

ns

( Maximum Freq

MHz)

PLL 139(1%) 962(1%) 123(12%) 283(1%) 59(10%) 33 (1%) 1.695

SPWM 0(0%) 57(1%) 0(0%) 20(1%) 92(15%) 0(0%) 3.220

Current

Controller

96(1%) 6410(4%) 62(1%) 1947(5%) 257(42%) 0(0%) 0.559

Voltage

Controller

48(1%) 1905(1%) 31(1%) 568(1%) 65(10%) 0(0%) 0.552

PWM 0 8(1%) 0(0%) 3(1%) 33(5%) 0(0%) 2.209

Reference

Signal

Generation

2306 (1%) 4765 (3%) 2250 (46%) 1374 (3%) 307 (51%) 25 (0%) 9.484

Table 3. Resource Utilization by the blocks


Fig.34. Experimental Testbed

• ML605• XILINX 14.2• Matlab 2012a


Fig.35. Relay response for load demand more than PV generation (a) Resistive (b) Inductive load

Fig.36. Relay response for load demand less than PV generation (a) Resistive (b) Inductive load

(a)

(a) (b)

(b)


Fig.37. Relay response for load demand equal to PV generation (a) Resistive (b) Capacitive load

(a) (b)


Gen-load

Relay

Load less than PV power Load more than PV power Load equals PV power

Resistive

(Relay

Time (s))

Inductive

(Relay

Time (s))

Capacitive

(Relay

Time (s))

Resistive

(Relay

Time

(s))

Inductive

(Relay

Time (s))

Capacitive

(Relay

Time (s))

Resistive

(Relay

Time (s))

Inductive

(Relay

Time (s))

Capacitive

(Relay

Time (s))

Over-

Frequency

No

Trip

0.3448 No

Trip

0.1107 0.0655 0.077 0.0942 0.0977 No

Trip

Under-

Frequency

0.381 0.069 0.0718 0.3417 0.381 No

Trip

No

Trip

0.4963 0.1086

ROCOF 0.0256 0.03 0.0293 0.02 0.0267 0.02 0.02 0.03 0.003

DC-Link 0.0655 0.0224 0.0295 0.0401 0.03 0.06 0.0401 0.0501 0.0501

Table 4. Comparison of Relay Response in HIL


The synchronization of DG inverter with the grid was made possible by the help

of Decoupling Control and MAF-PLL.

The performance of the DG inverter control and the anti-islanding detection

schemes was studied under various conditions in time-domain simulation using

Matlab/Simulink.

The effectiveness of the proposed controllers and islanding detection schemes was

validated by developing a hardware-in-loop simulation using XSG.

The HIL response of the employed schemes were found to conform to its

simulation counterpart.

Conclusion

Application of signal processing techniques for detection of islanding.

Real time implementation of the proposed system.


Future Scope

References


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generation,” IEEE Transactions on Power & Energy Systems, vol. 29,no. 2, pp. 873-880,2014.

[2] Soummya Kar and Subhransu R Samantaray,“Data-mining-based intelligent anti-islanding protection relay for

distributed generations,” IET Generation, Transmission & Distribution,vol.8, no.4, pp.629-639,2014.

[3] Antonis G Tsikalakis and Nikos D Hatziargyriou, ,“Operation of microgrids with demand side bidding and

continuity of supply for critical loads,” European Transactions on Electrical Power, vol.21.,No.2, PP.1238-1254, 2011.

[4] J A Pecas Lopes, N Hatziargyriou, J Mutale, P Djapic, and N Jenkins,“Integrating distributed generation into electric

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[5] Morris Brenna, Federica Foiadelli, Paola Petroni, Gianluca Sapienza,and Dario Zaninelli,“Distributed Generation

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IEEE PES,pp.1-6,2012.

[6] IEEE Std. 1547-2003, “IEEE Standard for Interconnecting Distributed Resources With the Electric Power System,”

[7] Mehrnoosh Vatani,Turaj Amraee, Ali Mohammad Ranjbar, and Babak Mozafari,“Relay logic for islanding detection

in active distribution systems,” IET Generation, Transmission & Distribution, vol. 9, no.12, pp.1254-1263,2015

[8] Nahla E Zakzouk,Mohamed A Elsaharty,Ahmed K Abdelsalam,Ahmed A Helal, and Barry W Williams, ,“Improved

performance low-cost incremental conductance PV MPPT technique,” IET Renewable Power Generation,2016.

[9] Dong Dong, Bo Wen, Dushan Boroyevich, Paolo Mattavelli, and Yaosuo Xue, ,“Analysis of phase-lockedloop low-frequency stability in three-phase grid-connected power converters considering impedanceinteractions,” IEEE Transactions on Industrial Electronics,vol.62 ,no.1,pp.310-321,2015

[10] S.J.Huang and F.S.Pai,“Design and operation of grid connected phototvoltaic system with power factorcontrol and active islanding detection,” IEEE Proceedings on Generation, Transmission,Distribution,vol.48,No.2,2001.

[11] Rajasekar Selvamuthukumaran and Rajesh Gupta, “Rapid prototyping of power electronics converters forphotovoltaic system application using Xilinx System Generator,” IET Power Electronics,vol.7,no.9,pp.22692278,2014, 2011.


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Anti-islanding

Engineering

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