ANSYS Chip Model Creation & Validation for PI/SI/EMI · Why Advanced CPM Model is Necessary ns...
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1 © 2015 ANSYS, Inc. February 10, 2017 ANSYS Confidential ANSYS Chip Model Creation & Validation for PI/SI/EMI
Transcript of ANSYS Chip Model Creation & Validation for PI/SI/EMI · Why Advanced CPM Model is Necessary ns...
1 © 2015 ANSYS, Inc. February 10, 2017 ANSYS Confidential
ANSYS Chip Model Creation & Validation for PI/SI/EMI
2 © 2015 ANSYS, Inc. February 10, 2017 ANSYS Confidential
1. Each port (or bump) reflects the current flow
associated with that port (or bump)
reflecting the on-die activity
2. Parasitics are associated with every port (or
bump)
3. Each port (or bump) are coupled with every
other port
Active Current SignaturePassive RC Values
ANSYS Conventional CPM(Chip Power Model)
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Why Advanced CPM Model is Necessary
ns order
Dynamic Switching Scenario
On-die Decap
0.1 ~ 100MHz
Large Current Change from a sort of Clock Gating
Package DeCap, Board Decap
> 100Mhz
us order
Covered by Conventional ANSYS CPM
By chip PDN
By Package & Board Design
Can not covered by Conventional Ansys CPM
Long transitionVector limited
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• Advance CPM Creation Tool for Power Integrity
• Post CPM creation compassing overall frequencies of full PDN for sign-off or failure diagnosis
• Early CPM creation without physical design in the early design stage for performance checking of full PDN
• Easy full PDN connection
• Create automated SPICE deck generation
• Enables user to do AC analysis and check impedance at resonant frequency
• Enable user to do transient analysis and check voltage drop & current at chip bump/pad, package ball or PMIC output
ANSYS CMA(Chip Model Analyzer)
Post CPMCreation
AC & Transient
Analysis of full PDN
Early CPM Creation
Import package
board Info
Full PDN Connection
Automated Spice deck generation
ANSYSCMA
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ANSYS CMA GUI Overview
CPM Extension by
Manual Mode
CPM Extension by
Random Mode
Current spectrum vs.
extension mode
Z profile of full PDN after AC analysis
Voltage Ripple after transient analysis
Current Waveform after transient analysis
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CPM Extension & Validation Flow
Import CPM generated by Redhawk/Totem
Current Waveform Extension
Import Package & Board
Define VRM or Supply Voltage Level
AC Analysis
Transient Analysis
Configure Full PDNby Connecting
Chip, Package, Board & VRM
Set up simulation & generate Spice deck
Impedance Profile of Full PDN after AC Analysis
Voltage Drop & Current after Transient Analysis
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Manual Mode
Random Mode
voltage drop at package ball
voltage drop at chip bump
supply current at chip bump
Current envelop of new CPM
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ANSYS CSM(Chip Signal Modeling)
ANSYSCSM
IO model
(CIOM/IBIS/Xtor)
generation
On-die PDN modeling
Model Validation through
system level analysis
Advanced CSM for
System level EMI analysis
IO-CPM generation
Chip Signal Model
generation
• Chip Model creation & validation tool for system level power noise induced DDR timing analysis and EMI analysis
• Validation includes JEDEC compatible timing, noise, jitter, slew reporting covering single ended and differential type IOs
• Customized 3DIC, HBM, WLP(Wafer Level Package) target CSM generation & validation
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ANSYS Chip Signal Model for DDR Timing Analysis
Core PDN
IOPDN
• Including RDL, on-die de-caps
• Multiple power domains
• Per pad/bump broadband model
• Compact model enables fast
simulation in spice
CIOM(Chip IO Model)
– Non-linear device I/O buffer macro-model
– Spice-level accuracy with full I/O bank capacity
– Captures impact of P/G noise on signal
– Load independent
– Layout and circuit IP encryption
– Also IBIS 5.0 Generation available
Chip Signal ModelCdev
ESR
Intrinsic capacitance extraction of IO Cell
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ANSYS CSM GUI Overview
CIOM Generation and Validation
Decap Modeling
On-die PDN parasitic extraction
CSM Creation & Channel Connection for Validation
CSM Validation through system level analysis
Jitter Analysis based on Jedec Spec
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CSM Creation and Validation Flow
CIOM Generation and Validation
IO Decap Modeling
Parasitic Extraction and Power Integrity Analysis of on-chip PDN
CSM(Chip Signal Model) Creation
Simulation env. set up for CSM validation
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