Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG...

39
Announcements Final projects due 11pm, Thursday

Transcript of Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG...

Page 1: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

AnnouncementsFinal projects due 11pm, Thursday

Page 2: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

0

15

30

45

60

0 10 20 30 40

Chart 1

Page 3: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

0

15

30

45

60

0 10 20 30 40

Chart 1

Page 4: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

0

15

30

45

60

0 10 20 30 40

Chart 1

Page 5: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM
Page 6: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM
Page 7: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Pipelined Processor

Same control unit as single-cycle processor

Signal preserved for pipeline stage where used

Page 8: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

PipeliningREG WRITE

Cont

rol

Logi

c

PC

0en0000002c

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

CLK

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

Page 9: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Single-Cycle vs. Pipelined Performance

Page 10: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Pipelining Abstraction

Page 11: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE DSTAGE F STAGE E STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

lw $s2,40($0)add $s3, $t1, $t2

sub $s4, $s1, $s5and $s5, $t5, $t6

sw $s6, 20($s1)

Page 12: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Data Hazards and Forwarding

Page 13: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE DSTAGE F STAGE E STAGE M

STAGE W

add $s0, $s2, $s3 and $t0, $s0, $s1

or $t1,$s4,$s0 sub $t2, $s0, $s5

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

Page 14: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Stalling

Page 15: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE DSTAGE F STAGE E STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

lw $s0, 40($0) and $t0, $s0, $s1

or $t1,$s4,$s0 sub $t2, $s0, $s5

Page 16: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE DSTAGE F STAGE E STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

lw $s0, 40($0) and $t0, $s0, $s1

or $t1,$s4,$s0

Page 17: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

lw $s0, 40($0) and $t0, $s0, $s1

or $t1,$s4,$s0

Page 18: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

rs(D) == rt(E) || rt(D) == rt(E) && MemtoReg(E)

stall =

Page 19: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

and $t0, $s0, $s1 or $t1,$s4,$s0

sub $t2, $s0, $s5

lw $s0, 40($0)

Page 20: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

and $t0, $s0, $s1 or $t1,$s4,$s0

sub $t2, $s0, $s5

lw $s0, 40($0)

Page 21: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

rs(D) == rt(E) || rt(D) == rt(E) && MemtoReg(E)

stall =

Page 22: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Control Hazards

Page 23: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Control Hazards: Original Pipeline

Page 24: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Control Hazards: Early Branch Resolution

Introduced another data hazard in Decode stage

Page 25: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Control Hazards: Early Branch Resolution

Introduces another data hazard in Decode stage

Page 26: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

Copyright © 2007 Elsevier 7-<>

Control Hazards: Early Branch Resolution

Introduces another data hazard in Decode stage

Page 27: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

20 beq$t1,$t2,40

Page 28: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

20 beq$t1,$t2,40 24 and$t0,$s0,$s1

Page 29: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

20 beq$t1,$t2,40 24 and$t0,$s0,$s1

64 slt $t3, $s2, $s3

Page 30: Announcements - Computer Sciencedept.cs.williams.edu/~tom/courses/237/notes/Lect35.pdfPipelining REG WRITE l c PC en0 0000 002c c in c out Mem To Reg ALU Src IMM MemToRegE CLK rt RegWriteM

STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

20 beq$t1,$t2,40

64 slt $t3, $s2, $s3

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STAGE ESTAGE DSTAGE F STAGE M

STAGE W

REG WRITE

Cont

rol

Logi

c

PC

0en00000010

c inc out

Mem To Reg

ALU Src

Mem To Reg

IMM

MemToRegE

CLK

rt

RegWriteM

MemToRegE

OP Code

rd

HAZARD UNIT

RESET0

brancheq

RegWriteM

MemWriteMemWrite

=

00000004

02

CLK

brancheq

CLK

ALU Control

REG WRITE

datamemory

D

ADRQ

WE

MemWrite

FUNCT

ALU Src

CLK

0MUX

0MUX

CLK

c inc out

0MUX

do

ed

ic

etns

instructionmemory

CLK

RST

ALU

RSTRegWriteE

0MUX

CLK

0MUX

CLK

Mem To Reg

REG WRITE

RegWriteE

registerbank

A1A2

A3WD

RD1

RD2

WE

RST

CLK

Reg Dst

MemToRegM

rs

ALU Control

Reg Dst

branch

MemToRegM

0MUX

0MUX

0MUX

20 beq$t1,$t2,40

64 slt $t3, $s2, $s368 ...

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Delayed Branches

Branch Prediction

Compiler Optimization

Vector/SIMD Machines

Superscalar Organization

Other Techniques

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Copyright © 2007 Elsevier 7-<>

Superscalar

• Multiple copies of datapath execute multiple instructions at once

• Dependencies make it tricky to issue multiple instructions at once

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Copyright © 2007 Elsevier 7-<>

Superscalar Example

lw $t0, 40($s0)

add $t1, $t0, $s1

sub $t0, $s2, $s3 Ideal IPC: 2and $t2, $s4, $t0 Actual IPC: 2or $t3, $s5, $s6

sw $s7, 80($t3)

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Limits

1/x = ?∑x=1n ⃗ ∞

limn

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Limitsint main( int argc, char * argv[] ) {

float total = 0, x; int low = 1; int high = 10000000;

for ( x = low; x <= high; x++ ) { total = total + 1/x; } printf( "total = %g\n", total );}

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Limitsint main( int argc, char * argv[] ) {

float total = 0, x; int low = 1; int high = 10000000;

for ( x = high; x >= low; x-- ) { total = total + 1/x; } printf( "total = %g\n", total );}

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Associating

(A + (B + C)) = ((A + B) + C)

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Scientific Notation

6.022 × 1023 mol−1

2.9979 x 108 m/s

mantissa exponent


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Reg Flashcards

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