Anatomy of a 400GE FEC - Keysight · KP4 FEC Decoding PCS Alignment Marker Lock, Deskew, and...
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Anatomy of a 400GE FEC ©2017 Keysight. All rights reserved. 915-8115-01. October 2017 TRANSMIT PATH RECEIVE PATH Transmit Transcoder Reduces line encoding overhead Receive Transcoder expands bit stream to original 64/66b format self-synchronizing, reconstitutes original bit stream Descrambler Gearboxing facilitates FEC symbol boundaries IEEE 802.3bs specifies 16 PCS lanes across both 400GAUI-16 & 400GAUI-8 electrical interfaces 256b/257b 256b/257b scrambled 256b/257b scrambled 256b/257b 0 1 2 ... 15 14 13 0 1 2 ... 15 14 13 Pre-FEC Symbol Distributor Symbol = 10 bits PCS Lane PCS Lane 0 1 2 ... 15 14 13 Physical Lane ... ... ... ... ... ... ... ... ... ... ... ... Transmit MAC Scrambler Self-synchronizes, ensures no long runs of 1s & 0s Different markers are created for each of the 16 PCS lanes 64/66 64/66 64/66 64/66 64/66 bit Codewords 64/66 bit Codewords ... Alignment Marker Group Insertion ... Alignment Marker Group Removal Corrects up to 15 symbol errors per FEC codeword KP4 FEC Decoding PCS Alignment Marker Lock, Deskew, and Reorder process ... ... ... 257 320 257 320 FEC a KP4 FEC Encoding 30 check symbols are calculated & inserted per FEC codeword FEC Codeword Interleaving & Distribution FEC De-interleaving Corrected FEC Codeword Interleaving FEC b FEC a FEC b Alignment Lock State Machine Deskew FIFO Alignment Lock State Machine Reorder MUX Receive MAC Deskew FIFO A Keysight Business The IEEE 802.3bs Task Group defines specifications for 400 Gigabit per second Ethernet, where Forward Error Correction (FEC) is mandatory. See how a 400GBASE-R Reed-Solomon RS-544 (KP4 FEC) encode/decode works in operation.
Transcript of Anatomy of a 400GE FEC - Keysight · KP4 FEC Decoding PCS Alignment Marker Lock, Deskew, and...
Anatomy of a 400GE FEC
©2017 Keysight. All rights reserved. 915-8115-01. October 2017
TRANSMIT PATH
RECEIVE PATH
Transmit Transcoder
Reduces line encoding overhead
Receive Transcoder
expands bit stream to original
64/66b format
self-synchronizing, reconstitutes
original bit stream
Descrambler
Gearboxing facilitates FEC symbol boundaries
IEEE 802.3bs specifies 16 PCSlanes across both 400GAUI-16
& 400GAUI-8 electrical interfaces
256b/257b
256b/257b
scrambled 256b/257b
scrambled 256b/257b
012...
151413
012...
151413
Pre-FECSymbol Distributor
Symbol = 10 bits
PCS Lane
PCS Lane
012...
151413
PhysicalLane
...
...
...
...
...
...
...
...
...
...
...
...
TransmitMAC
Scrambler
Self-synchronizes, ensures no long runs of 1s & 0s
Di�erent markers are created for eachof the 16 PCS lanes
64/66
64/66
64/66
64/6664/66 bit Codewords
64/66 bit Codewords
...
Alignment Marker Group Insertion
...
Alignment Marker Group Removal
Corrects up to 15symbol errors per FEC
codeword
KP4 FEC Decoding
PCS Alignment
Marker Lock, Deskew, and Reorder process
...
...
...
257
320
257
320
FEC a
KP4 FEC Encoding
30 check symbols are calculated & inserted
per FEC codeword
FEC CodewordInterleaving
& Distribution
FEC De-interleaving
Corrected FEC
Codeword Interleaving
FEC b
FEC a
FEC b
AlignmentLock StateMachine
DeskewFIFO
AlignmentLock StateMachine
ReorderMUX
ReceiveMAC
DeskewFIFO
A Keysight Business
The IEEE 802.3bs Task Group defines specifications for 400 Gigabit per second Ethernet, where Forward Error Correction (FEC) is mandatory. See how a 400GBASE-R Reed-Solomon RS-544 (KP4 FEC) encode/decode works in operation.
