Roadway Design Models: Streamlining Conversion for Driving Simulation
Analysis of state machines & Conversion of models
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Transcript of Analysis of state machines & Conversion of models
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Analysis: Example 2 - New State Machine
• This is now a Moore machine– output MAXS depends only on state (Q0 and Q1)
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MAXS = Q0 Q1
MAXS
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Analysis: Example 2 - New Table/Diagram
• Updated State/Output Table & Diagram– Moore machine state diagram
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output associated with state, not transitionoutput associated with state, not transition
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Analysis: Example 2 - Timing Diagram• Timing Diagram for State Machine
– Compare outputs MAX and MAXS for the Mealy and Moore machine implementations
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Conversion of Models
• Mealy to Moore machine– If all the transitions in a Mealy model to a particular state are
associated with the same output then in the corresponding Moore model that output becomes the state output.
A B
T1
T2
T3 T4
1/0
1/0
0/0
1/0
0/1
T1
T2
T3 T4
1
1
0
1
00
A
0
B
Mealy Moore
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Conversion of Models
• Mealy to Moore machine– If the outputs of all the transitions in a Mealy model to a
particular state are not the same, then in the corresponding Moore model we need to insert intermediate states
A B
T1
T2
T3 T4
0/0
1/0
1/1
1/0
0/1
T1
T2
T3
T4
0
1
1
1
0
0
0A
0
B
1
1A
T4
1
0
Mealy
Moore
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Conversion of Models
• Moore to Mealy machine– If the state transition from two different states of the same
input leads to common state then one state can be eliminated
A B
T1
T2
T3
0/0
1/0
1/1
1/0
T1
T2
T3
0
1
1
10
0A
0
B
1
1A 1
MealyMoore
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Conversion of Models
• Moore to Mealy machine– If the state transition from two different states of the same
input does not lead to the same state, then state output becomes the output corresponding to each input transition of that state
A B
T1
T2
T3
0/0
1/0
1/0
0/0
T1
T2
T3
0
1
1
00
A
0
B
1
C1 1/1
CMealyMoore
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J Q
QK
J Q
QK
X Y Q0
Q0'
Q1
Q1'
Clk
Q0
Q1
Z
J1
K1
J0
K0
J0 = X·Y'
K0 = X·Y' + Y·Q1
J1 = X·Q0 + Y
Z = X·Q0·Q1 + Q0'·Q1'·YK1 = Y·Q0' + X·Y'·Q0
Analysis: Example 3 - State Machine
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1. Determine the excitation equations for the flip flop inputs
YXJ 0 YQXJ 01
10 QYYXK 001 QYXQYK
2. Substitute the excitation equations into the flip flop characteristic equations to obtain transition equations.
0000*0 QKQJQ characteristic equations
transition equations
1111*1 QKQJQ
010*0 QQYYXQYXQ
10010*1 QQYXQYQYQXQ
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010*0 QQYYXQYXQ Simplifying the transition equations
101000*0 QQYQQXQYXQYXQ
010*0 QQYYXQYXQ
010*0 QQYYXQYXQ
010*0 QQYYXQYXQ
010*0 QQYYXQYXQ
0110*0 QQYYYQXYXQYXQ
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Simplifying the transition equations
10010*1 QQYXQYQYQXQ
101010
1110*1
QQYQQXQQY
QYXQYQQXQ
3. Determine the output equations.
1010 QQYQQXZ output equation
10010*1 QQYXQYQYQXQ
100110*1 QQYXQYQYQQXQ
100110*1 QQYXQYQYQQXQ
100110*1 QQYXQYQYQQXQ
100000110*1 QQQYQQXQYYYYXQYQXQQ
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4. Use transition equations and output equations to construct transition/output table.
State Input XY
Q1Q0 00 01 10 11
00 00,0 10,1 01,0 10,1
01 01,0 11,0 10,0 11,0
10 10,0 00,0 11,0 00,0
11 11,0 10,0 00,1 10,1
Next State Q1*Q0*, Z
Transition/output table
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6. Name the states and substitute state names for state – variable combinations in the transition/output table to obtain the state/output table.
Substituting the state names as ‘A’ for Q1Q0 = 00,‘B’ for Q1Q0 = 01, ‘C’ for Q1Q0 = 10,‘D’ for Q1Q0 = 11. S is current state & S* is next state.
State/output table
State Input XY
S 00 01 10 11
A A,0 C,1 B,0 C,1
B B,0 D,0 C,0 D,0
C C,0 A,0 D,0 A,0
D D,0 C,0 A,1 C,1
Next State S*, Z
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State diagram
A B00/0 00/0
10/0
01,11/0
D C00/0
11/1
01/0
10/0
00/0
10/0
10/1
01,11/1
01,11/0
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Synchronous Design Process1. Construct a state diagram and/or state/output table
corresponding to the word description or specification
2. Minimize the number of states
3. Choose a set of state variables and assign state variable combinations to the named states
4. Obtain the transition/output table
5. Determine the number of flip-flops and select the type of flip-flop to be used (D is often the default)
6. Construct the excitation table
7. Derive excitation equations
8. Derive output equations
9. Draw the logic diagram that realizes the equations
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Design a clocked synchronous state machine
which accepts two serial strings of digits of
arbitrary length, starting with LSB and produces
the sum and carry of the two bit streams as its
output. The input bit streams could come from
two shift registers clocked simultaneously.
Let the inputs be X and Y
Let the outputs be S and C
Assuming Mealy machine design
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Obtaining the state DiagramAssume initial condition to be SC = 00Let the state be represented by state AIf XY = 00, then output SC = 00, Same state A
= 01, then output SC = 10, goes to state B= 10, then output SC = 10, goes to state B= 11, then output SC = 01, goes to state C
A B
11/01
01,10/1000/00
XY/SC
C
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Obtaining the state DiagramAssume machine has moved to state BIf XY = 00, then output SC = 00, goes to state A
= 01, then output SC = 10, same state B= 10, then output SC = 10, same state B= 11, then output SC = 01, goes to state C
A B
11/01
01,10/10
C
01,10/10
11/01
00/00
XY/SC
00/00
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Obtaining the state DiagramAssume machine has moved to state CIf XY = 00, then output SC = 10, goes to state B
= 01, then output SC = 01, same state C= 10, then output SC = 01, same state C= 11, then output SC = 11, goes to state D
A B
11/01
01,10/10
C
01,10/10
D11/11
00/00
XY/SC
11/01
00/00
01,10/0100/10
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Obtaining the state DiagramAssume machine has moved to state DIf XY = 00, then output SC = 10, goes to state B
= 01, then output SC = 01, goes to state C= 10, then output SC = 01, goes to state C= 11, then output SC = 11, same state D
A B
11/01
01,10/1000/00
XY/SC
C
01,10/10
D11/1101,10/0100/10
01,10/01
11/11
00/1011/01
00/00
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Obtaining the state/output table
State/output table
State Input XY
S 00 01 10 11
A A,00 B,10 B,10 C,01
B A,00 B,10 B,10 C,01
C B,10 C,01 C,01 D,11
D B,10 C,01 C,01 D,11
Next State S*, SC
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Equivalent States
Two states are equivalent if it is impossible to distinguish them by observing only the current and future outputs of the machine .
A pair of equivalent states can be replaced by a single state.
Two states S1 and S2 are equivalent if two conditions are true.1. S1 and S2 must produce the same values at the state machine output(s) for all input combinations.2. For each input combination S1 and S2 must have either the same next state or equivalent next states.
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State Minimization
State/output table
State Input XY
S 00 01 10 11
A A,00 B,10 B,10 C,01
B A,00 B,10 B,10 C,01
C B,10 C,01 C,01 D,11
D B,10 C,01 C,01 D,11
Next State S*, SC
Equivalent states
Equivalent states
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Minimized state/output table & state diagramState/output table
State Input XY
S 00 01 10 11
A A,00 A,10 A,10 D,01
D A,10 D,01 D,01 D,11
Next State S*, SC
A D11/0100/00
00/10
01/1010/10
01/0110/0111/11
State diagram
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Assigning state variable to obtain transition/output
tableTransition/output table
State Input XY
Q 00 01 10 11
0 0,00 0,10 0,10 1,01
1 0,10 1,01 1,01 1,11
Next State Q*, SC
Encoding A = 0 and D = 1
Choosing D type flip flop
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Constructing the excitation table
Excitation/output table
State Input XY
Q 00 01 10 11
0 0,00 0,10 0,10 1,01
1 0,10 1,01 1,01 1,11
D, SC
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Transferring onto K-maps to derive excitation &
output equations Excitation/output table
State Input XY
Q 00 01 10 11
0 0,00 0,10 0,10 1,01
1 0,10 1,01 1,01 1,11
D, SCState Input XY
Q 00 01 11 10
0 0 0 1 0
1 0 1 1 1
D = X·Y + X·Q +Y·Q
C = X·Y + X·Q +Y·Q
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Transferring onto K-maps to derive excitation &
output equations Excitation/output table
State Input XY
Q 00 01 10 11
0 0,00 0,10 0,10 1,01
1 0,10 1,01 1,01 1,11
D, SCState Input XY
Q 00 01 11 10
0 0 1 0 1
1 1 0 1 0
QYXQYX
QYXQYXS
QYXS
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D = X·Y + X·Q +Y·Q
C = X·Y + X·Q +Y·QQYXS
Circuit (logic) diagram
excitation equation
output equations
D Q
Q
X
S
Y QC
Clk