Analysis of Power Delivery network of Multiple Stacked ...€¦ · Analysis of Power Delivery...
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Reduced area Increased performance signal transmission pathways Heterogeneous die assembly: functionalities (memory, processor, power management,…) technologies (ideally the best techno for each module) Analysis of Power Delivery network of Multiple Stacked ASICs using TSV and Micro-bumps Lise Doyen 1 , Jasmina Antonijevic 1 , Damien Riquet 1 ,Nicolas Vialle 2 , Aveek Sarkar 2 1 ST Microelectronics, Crolles, France. 2 Apache Design Solutions, San Jose CA. Package Ball Bump backside TSV Pillar bump top Stack via TSV M1 land Pillar bump bottom RDL backside TOP DIE flipped BOTTOM DIE upward Schematic of 3D TSV Stack with face-to-face die Introduction: 3D Integration • Missing full-design database of one or more die • Support dies of different technologies • Early analysis to optimize TSV density and placement 3D Power Integrity Solution 3D Power Integrity Results Two Simulation approaches Concurrent Simulation Flow: Full design database available for both dies Model Based Simulation Flow: a Chip Power Model (CPM) replaces the design database of the missing die # Import data import bot_die import top_die setup design # Calculate power # PG grid extraction # Static IR analysis Design Data Libraries Package User Conf File Techfile Design Data Libraries User Conf File Techfile Bottom die Top die Reports Voltage drop and other maps Challenges: TSV placement optimization - Package TOP DIE flipped 4 1 2 3 5 - Package TOP DIE flipped 1 2 3 5 4 3D integration new challenges in Power Delivery Network (PDN): Thermal Integrity Signal Integrity Bottom die switching and package distance noise impact on top die Power Integrity … need 3D Design Solutions Why ? What ? How ? Power Integrity flow TSV Optimization flow Static and Dynamic results Early: User defined region & power consumption TSV location Floor planning: User define power consumption TSV location Signoff: Full Layout Static IR-Drop analysis to optimize current distribution of the top die Flow overview 2 die stack Different technology support Voltage Source Location files: bot_die.ploc: define bottom die location and metal layer where the package is plugged (for both top and bottom die power/ground nets) Top_die.tsv: define top die position and connexion to the bottom die Top_die.tsv bot_die.ploc Schamatic and Result comparison of concurrent and model based simulation of a two-die stacked design Dynamic drop results from bottom die and top die PG mesh (VDD and GND) Dynamic drop results from bottom die and top die PG mesh (VDD and GND) Bottom die IR map with top die included Top Die IR map with bottom die included Schematic of face-to-face connexion from package to top die 3D Design description: logic/logic face-to-face stack 32 nm top die 65 nm bottom die package Voltage source at the die periphery Bump/TSV matrix added at the die center Optimization of Bump/TSV matrix Bottom die upward (vdd_io / gnd_io) Top die flipped (vdd / gnd) 32 nm 32 nm 32 nm 32 nm 32 nm 32 nm 32 nm 32 nm 65 nm 65 nm 65 nm 65 nm 65 nm 65 nm 65 nm 65 nm Package bump TSV Stacked vias ball Back bump Conclusion Dynamic and Static IR Drop analysis Two stacked dies + package Heterogeneous technology system Two simulation approaches TSV placement optimization Extend the number of stacked die analysis Heterogeneous functionality : memory/ASIC New topics to investigate: Signal Integrity, Reliability, Thermo-Mechanical effects,… ASIC 32 nm ASIC 65 nm Package MEMORY ASIC Package ASIC ASIC Package MEMORY … TODAY … ... TOMORROW Scanning Electron Microscope (SEM) image of TSV and pillar bumps Concurrent Approach Package Die 1 Die 2 Model Based Approach Package Die 1 Die 2 Bump_MB MB TSV M1 Stacked via AP Bump_AP (bot) From package Bump_AP (top) AP Copper pillar M1 Worst DvD (Bottom Die) Worst DvD (top die) GND nets VDD nets VDD pad locations GND pad locations
Transcript of Analysis of Power Delivery network of Multiple Stacked ...€¦ · Analysis of Power Delivery...
� Reduced area� Increased performance� � signal transmission pathways� Heterogeneous die assembly:
� functionalities (memory, processor, power management,…)
� technologies (ideally the best techno for each module)
Analysis of Power Delivery network of Multiple Stac ked ASICs using TSV and Micro-bumps
Lise Doyen1, Jasmina Antonijevic1, Damien Riquet1,Nicolas Vialle2, Aveek Sarkar2
1ST Microelectronics, Crolles, France. 2Apache Design Solutions, San Jose CA.
Package
Ball Bump backside
TSV
Pillar bump top Stack via
TSV M1 land
Pillar bump bottom
RDL backside
TOP DIE flipped
BOTTOM DIEupward
Schematic of 3D TSV Stack with face-to-face die
Introduction: 3D Integration
• Missing full-design database of one or more die
• Support dies of different technologies
• Early analysis to optimize TSV density and placement
3D Power Integrity Solution 3D Power Integrity Results
Two Simulation approachesConcurrent Simulation Flow: Full design database available for both dies
Model Based Simulation Flow: a Chip Power Model (CPM) replaces the design database of the missing die
# Import data
import bot_dieimport top_diesetup design
# Calculate power
# PG grid extraction
# Static IR analysis
Design Data
Libraries
Package
User Conf File
Techfile
Design Data
Libraries
User Conf File
Techfile
Bottom die Top die
Reports Voltage drop and other maps
Challenges:
TSV placement optimization -
Package
TOP DIE flipped
4
1 2
3
5
-
Package
TOP DIE flipped
1 2
3
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3D integration � new challenges in PowerDelivery Network (PDN):� Thermal Integrity� Signal Integrity
� Bottom die switching and package distance � noise impact on top die
� Power Integrity� …� need 3D Design Solutions
Why ?
What ? How ?
Power Integrity flow
TSV Optimization flow
Static and Dynamic results
Early:User defined region & power consumption
TSV location
Floor planning:User define power consumption
TSV location
Signoff:Full Layout
Static IR-Drop analysis to optimize current distribution of the top dieFlow overview� 2 die stack
� Different technology support
� Voltage Source Location files:
� bot_die.ploc: define bottom die location and metal layer where the package is plugged (for both top and bottom die power/ground nets)
� Top_die.tsv: define top die position and connexion to the bottom die
Top_die.tsv
bot_die.ploc
Schamatic and Result comparison of concurrent and model based simulation of a two-die stacked design
Dynamic drop results from bottom die and top die PG mesh (VDD and GND)
Dynamic drop results from bottom die and top die PG mesh (VDD and GND)
Bottom die IR map with top die included
Top Die IR map with bottom die included
Schematic of face-to-face connexion from package to top die
3D Design description:� logic/logic face-to-face stack
� 32 nm top die
� 65 nm bottom die
� package
Voltage source at the die periphery
Bump/TSV matrix added at the die center
Optimization of Bump/TSV matrix
Bottom die upward (vdd_io / gnd_io )
Top die flipped (vdd / gnd )32 nm32 nm32 nm32 nm32 nm32 nm32 nm32 nm
65 nm65 nm65 nm65 nm65 nm65 nm65 nm65 nm
Package
bump
TSV
Stacked vias
ball
Back bump
Conclusion� Dynamic and Static IR Drop analysis
� Two stacked dies + package
� Heterogeneous technology system
� Two simulation approaches
� TSV placement optimization
� Extend the number of stacked die analysis
� Heterogeneous functionality : memory/ASIC
� New topics to investigate: Signal Integrity, Reliability, Thermo-Mechanical effects,…
ASIC 32 nmASIC 65 nm
Package
MEMORYASIC
PackageASICASIC
Package
MEMORY
…
TODAY … ... TOMORROW
Scanning Electron Microscope (SEM) image of
TSV and pillar bumps
Con
curr
ent A
ppro
ach
Package
Die 1
Die 2
Mod
el B
ased
App
roac
h
Package
Die 1
Die 2
Bump_MB
MBTSV
M1Stacked via
APBump_AP (bot)
From package
Bump_AP (top)
AP
Copper pillar
M1
Worst DvD (Bottom Die) Worst DvD (top die)
GND netsVDD nets
VDD pad locations
GND pad locations
