Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal...
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![Page 1: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/1.jpg)
Analysis and Synthesis of Synchronous Sequential Circuits
• A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the circuit
• When noclock – thecircuit is asynchronous:
![Page 2: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/2.jpg)
Analysis and Synthesis of Synchronous Sequential Circuits
• The “state” of a synchronous sequential circuit:– All the FF/memory element outputs– Can change only upon clock transition (pulse/edge)
• Two models for synchronous sequential circuits:– Mealy model
• Outputs are a function of state and inputs
– Moore model• Outputs are a function of state only
![Page 3: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/3.jpg)
Mealy model
• Next state (Y1,…,Yr) achieved on clock transition
![Page 4: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/4.jpg)
Mealy model
• Input (x1,…,xn), output (z1,…,zm), present state (y1,…,yr) and next state (Y1,…,Yr) are
where gi and hi are Boolean functions, or in vector form
![Page 5: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/5.jpg)
Moore model
Combinational logic
Combinational logic
Memory
x1
xn
Y1
Yr
y1
yr
z1
zm
clock
![Page 6: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/6.jpg)
Mealy machine example
• State diagram and state table
• Assumes transitions
Problem?
![Page 7: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/7.jpg)
Moore machine example
• State diagram and state table
• Output is f(state) only• Inputs – no effect
![Page 8: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/8.jpg)
Mealy vs. Moore
• Representations can be transformed into each other
• Advantages and disadvantages
Mealy Moore
- glitches + no glitches
- problem sampling
+ easier to design
+ lesser total # states
![Page 9: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/9.jpg)
Analysis precedes synthesis
• Analysis of logic diagrams of sequential circuits– Inputs, state variables, outputs, logic equations ?– Mealy or Moore type?
![Page 10: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/10.jpg)
Analysis
– Input sequence: x = 01101000
yxyxyxY
xyz
![Page 11: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/11.jpg)
Analysis
• Deriving state diagram and state table– Given circuit diagram Boolean equations
• Notation: yk represents y(k t)• k = integer; t = clock period
• May assign numbers to states: 0 state A; 1 state B
![Page 12: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/12.jpg)
Analysis
• Deriving state table from K-maps
Map for Yk=yk+1 Map for zk
![Page 13: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/13.jpg)
Analysis example
• Synchronous sequential circuit with flip-flops– Negative edge-
triggered– Inputs?– States?– Outputs?– Logic equations?
![Page 14: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/14.jpg)
Analysis example
• Timing diagram
![Page 15: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/15.jpg)
Analysis example
• State table and K-maps
![Page 16: Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.](https://reader036.fdocuments.us/reader036/viewer/2022062805/5697bfdb1a28abf838cb098b/html5/thumbnails/16.jpg)
Analysis example
• Combining the K-maps into state table