Analog Layout Synthesis: What’s Missing? · PDF fileAnalog Layout Synthesis:...
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Analog Layout Synthesis:What’s Missing?
Rob A. RutenbarBliss Professor and Head
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The Mixed-Signal Design ProblemCommercial Mixed Signal ASIC
Analog
Digital% Design Effort
Digital
Analog
Slide 2© Rob A. Rutenbar 2010
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Why this Matters Total worldwide market for non-memory ICs in 2008: $167B Mixed-signal portion (some analog/RF) was $107B in 2008; ~ 66%
Projected to grow to 70+% in 2012
Growth rate higher than overall non-memory IC marketplace
66%
34%Mixed-signalNon-mixed-signal
Slide 3© Rob A. Rutenbar 2010
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To Start Off On A Positive Note… Yes, there are real tools in this space, doing real circuits Help size, optimize for perform/yield, layout, migrate …
But, tools far from perfect, lots of problems unsolved…
STMicroelectronics result [Shah, Dugalleix, Lemery DATE02]
Both sizing and layout
0.12 mmArea: ~4000 µm2
Power: 1.1mW
Area: ~9000 µm2
Power: 9.15mW Auto Sizing
Auto Sizing
Auto Layout
Auto Layout
180nm
120nm
BIASING AMPLIFIER
[Source: Cadence]
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About this Talk…
Accomplish 3 things (not entirely in sequential order):
A very brief tour of what “analog layout” looks like
Explain some facts about how/why analog layout is different
Offer some ideas about what are the open problems
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About Analog: Layout Happens at 3 Levels
Two of these look familiar
One of them probably looks odd to you…
Slide 6
AnalogFrontend
CELL
SYSTEM
DEVICE
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About Analog: Layout Happens at 3 Levels
Devices play a role like gate-level cells in digital
They tend to be the “smallest” units of layout
But, they are extremely complex, highly diverse Because all analog is about
electrical precision
Devices are how we harness, manage essential nonlinearities
CELL
SYSTEM
DEVICE
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Circuit/Cell Level Layout Flow (Simplified)
Designcell footprint& floorplan
vdd
vssDesign
individualdevice geometries
Place & route devices, optimize area,coupling, etc.
From sized
schematic
FundamentalAssumptions
Manual& easy
Simplegenerators
Essentialalgorithms
Orange assumptions are problematic…
Slide 8© Rob A. Rutenbar 2010
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Difference #1: Circuit Designer != Layout Designer
Nobody is surprised that folks who write 1,000,000 lines of Verilog are NOT THE SAME folks who do physical design
So, you should not be surprised same is true in analog world…
Slide 9
Courtesy Juergen Koehl, IBM
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Analog Circuit Designer != Layout Designer
(Not universally the case, but often, and it complicates things)
Slide 10
Circuit designerAn engineer
(Maybe grad degree)Hack transistors, creatively
Layout designerMay be a technician, not engineer
(Maybe no degree)Hack rectangles, creatively
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Difference #2: Analog Space is Bifurcating
This is a picture of Texas Instrument’s new analog fab They are very proud of it
It was the only big fab built in the US in 2009
It was the industry’s very first 300mm analog fab
Slide 11
What technology node?
0.25 micron linear BiCMOS
5 full nodes behindleading-edge digital
Source: Bill Krenik, Chief Technologist, TI SLL
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Bifurcating Analog Space
“Fully depreciated” analog Need the function, cheap
Don’t need SOC integration
Don’t need 10M gates of logic
PRO Cheap, fewer nm effects
CON Can’t integrate lots of gates
“Fully scaled” analog Need function AND integration
Essential for high-volume parts in cheap digital processes
PRO Easy access to 10M+ gates
CON Nanometer grief is worse here
Slide 12
−+
Different kinds of layoutproblems in each space
© Rob A. Rutenbar 2010
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Difference #3: Nanometer Grief Hurts More
Since analog is always about manipulating electrical quantities in precise ways, the nm effects hurt more
Interesting result: Lots of focus on device-level automationSlide 13
Source: Cao and McAndrew, ICCAD 2007 tutorial, andP. G. Drennan, M. L. Kniffin, and D. R. Locascio, CICC 2006
ID vs VGS vs proximity to well edge
ID vs VDS Src/Drain asymmvs proximity to well edge “WPE”
© Rob A. Rutenbar 2010
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Opportunity: Device-Level Automation
Shapes complexity 1 schematic device many
physical devices (“fingers”) N schematic devices single
physical layout structures Complex spatial constraints
(symmetries, matching, wells) Routing problem is integral to
the device gen/placement too
Physics complexity As nm effects worsen, need
optimization to do these right
Example: Cadence MODGEN
Slide 14
Image provided by ©2010 Cadence Design Systems, Inc.
All rights reserved worldwide
© Rob A. Rutenbar 2010
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Opportunity: Device-Level Automation
If you push analog polygons for a living, you love these tools Automation doesn’t threaten creativity; helps get hard stuff right
Slide 15
Images provided by ©2010 Cadence Design Systems, Inc.
All rights reserved worldwide
© Rob A. Rutenbar 2010
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Difference #4: Layout Style Variations
Only a slight simplification to say all digital ASICs look alike Lots of gates in rows, in between lot of macros (SRAMs, etc)
Some diversity in the spread of sizes of macro; some regularity
Courtesy Juergen Koehl, IBM Courtesy Zhong Xiu, CMU Courtesy Zhong Xiu, CMU
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Layout Style Variations in Analog: Wide…
Slide 17
Source: B. Tsang, Y. Chiu, B. Nikolić UCB
Source: P. Gray, UCB
Source: H.-S. Lee, C. Sodini, MIT
Source: Cadence
Source: Cadence
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First-Gen Layout Algorithms…. Essential formulation was: Floorplanning + Routing Devices have large, variable shape (since FETS fold many ways)
Pack the shapes, then route the shapes
Minimize wirelen+area, while respecting constraints (symmetry)
Slide 18
Autorouted resultAutorouted resultAutoplaced result
Source: Cadence
Necessary, but not sufficient…© Rob A. Rutenbar 2010
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What Did We Not Get (Entirely) Right…? Constraint extraction and
tradeoff management Critical stuff in real designs
often never written down
Exists implicitly in design group’s legacy portfolio and human resources
Organic integration: devices, place, power, routenot done sequentially Design steps less independent,
less sequential than digital
Usually optimizing across N steps simultaneously
vs
Slide 19© Rob A. Rutenbar 2010
More comments
in your code!
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Constraint Extraction/Mgt: Industrial Example Proprietary CMOS comparator block Lots of critical electrical / geometric constraints – none explicit on
schematic, all extracted (arduously) from designer interaction
[Source: Cadence]
Slide 20
Opportunity: “Low-hassle” constraint harvesting/miningfrom good designs
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Opportunity: Every Step In Every Flow: Fast, Incremental, and Deterministic
Need very fast “what if…” for all electrical/geometric steps This is not how today’s “deep optimizer” algorithms are done Req for fast+deterministic is also a huge challenge
Improvement
Gain
Bandwidth
Gain
Bandwidth
??Ga
in
Bandwidth
Gain
Bandwidth
!!
Note – these are not std cells. Small changes can have big impacts on ckt
Slide 21
[Source: Cadence]
© Rob A. Rutenbar 2010
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Difference #5: Aesthetic Engineering This does not happen with you lay out 50M digital gates…
Slide 22
Copyright © 1993, The National Gallery, LondonCopyright © 1993, The National Gallery, London
Gosh, does wire #1,034,237 look
odd to you…?
Oh Brad – I was just thinking
the same thing!
© Rob A. Rutenbar 2010
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Aesthetic Engineering: Two Nuances
Entire designs often fit on one screen People pay attention to things
they can grasp in one look
Aesthetics is often a surrogate for correctness Not everything that we’d like
to check has a robust script
Slide 23
Hey, why is thatFold in that
device, right there?
…and I reallydon’t like the
look of that via!
© Rob A. Rutenbar 2010
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Opportunity: Incremental Tools + New Use Models Adobe Photoshop offers an
interesting vision of this This is “Image variations”
A palette of incremental changesto base image
Can I do this for analog layout? For critical analog metrics?
Shorter wires? Straighter signal path? Simpler power routing?More like schematic? More critical signal isolation? Farther from well-edge? Etc etc?
Slide 24© Rob A. Rutenbar 2010
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Summary
My own personal journey Publishing 20 years ago
Commercializing 10 years ago
Happy to see real use today…
But lots left to do Organic, integrated place,
route, power, integrity, etc
Everything incremental, everything simultaneous
Hassle-free constraint mgt
Aesthetic engineering
Slide 25© Rob A. Rutenbar 2010