Application ReportSBAA160AMarch 2009Revised April 2010

Analog Front-End Design for ECG Systems UsingDelta-Sigma ADCs

Karthik Soundarapandian, Mark Berarducci......................................................... Data Acquisition Products

ABSTRACT

This document discusses the characteristics of electrocardiogram (ECG) signals and different front-endapproaches for ECG signal acquisition. The tradeoffs between different approaches and the effects onoverall system design are discussed. The report also includes descriptions of potential implementations ofthe front-end architecture using the ADS1258 and ADS1278 and respective noise measurement results.

Contents1 Introduction .................................................................................................................. 12 Nature of the ECG Signal and System Design Implications .......................................................... 23 System Approaches ........................................................................................................ 34 ECG AFE with Low-Resolution ( 16-bit) ADCs ........................................................................ 45 Simplified Low-Cost ECG AFE with 24-bit Delta-Sigma ADCs ....................................................... 56 Sequential Sampling Measurements with the ADS1258 .............................................................. 77 Simultaneous Sampling Measurements with the ADS1278 ........................................................... 98 References ................................................................................................................. 10

List of Figures

1 ECG Signal Characteristics................................................................................................ 22 System Approaches Based on ADC Resolution ........................................................................ 33 Typical SAR-Based ECG Signal Chain (Sequential Sampling)....................................................... 44 -Based, Low-Cost ECG Signal Chain (Sequential Sampling) ..................................................... 55 -Based, Low-Cost ECG Signal Chain (Simultaneous Sampling).................................................. 66 Test Setup Using the ADS1258........................................................................................... 77 Measured Time Domain Data ............................................................................................. 88 Test Setup Using the ADS1278........................................................................................... 99 ADS1278 with Simulated 2-mV Cardiac Test Input................................................................... 10

1 Introduction

Electrocardiogram (ECG) system analog front-end (AFE) devices are typically designed with discreteoff-the-shelf components from various semiconductor vendors or custom-designed as application-specificintegrated circuits (ASICs). The costs of an ASIC design could run into millions of dollars by the time thedevice reaches full production, and may not be practical for many small- and medium-sized companies.The primary components of a traditional discrete ECG AFE include instrumentation amplifiers, operationalamplifiers that implement active filters, and analog-to-digital converters (ADCs).

All trademarks are the property of their respective owners.

1SBAA160AMarch 2009Revised April 2010 Analog Front-End Design for ECG Systems Using Delta-Sigma ADCsSubmit Documentation Feedback

Copyright 20092010, Texas Instruments Incorporated

http://focus.ti.com/docs/prod/folders/print/ads1258.htmlhttp://focus.ti.com/docs/prod/folders/print/ads1278.htmlhttp://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBAA160A

Common-

Mode

50 Hz to 60 Hz

1.5 V

0 V

Electrode

Offset300 mV

ECG

Signal

ECG

Signal2.5 mV

0.05 Hz to 150 Hz

2.5 mV

0.05 Hz to 150 Hz

Nature of the ECG Signal and System Design Implications www.ti.com

Recent technology advancements have resulted in ADCs with a combination of speeds, resolution, andpower that were impossible before. At the same time, the necessity for low-cost and low-power ECGmachines has increased, imposing constraints on engineers and designers to make systems more andmore affordable. This article examines how to use the latest high-performance delta-sigma () ADCsfrom Texas Instruments as components of an ECG AFE system, and discusses how to optimize the costof an ECG AFE from a system design perspective.

2 Nature of the ECG Signal and System Design Implications

The first step in any system design is to fully understand the signal that is to be processed by the system.This step is espeically true for an ECG AFE system. Figure 1 shows the widely accepted details of theECG signal as it appears at the input of the ECG measurement system (see Ref 1). It consists of threecomponents: the actual (differential) ECG signal, the differential electrode offset, and the common-modesignal.

The actual differential ECG signal that appears between the electrodes in any lead configuration is limitedto 5 mV in magnitude and 0.05 Hz to 150 Hz in frequency. The magnitude of this actual ECG signal,together with the resolution required from the ECG signal, determines the dynamic range requirement ofthe front-end. The frequency content of this signal determines the bandwidth requirements of the analogfront-end.

The skin-electrode interface gives an additional dc offset of approximately 300 mV. This offset must bemanipulated such that the signal chain is not saturated. There are two ways of managing this offset,depending on the type of ADC used in the system: either eliminate it completely or preserve it. Thisapplication note analyzes the advantages and disadvantages of both methods.

Figure 1. ECG Signal Characteristics

In addition to these two signals, the human body can pick up large interference signals from power lines,fluorescent lights, and so forth. This interference can manifest itself as either a normal-mode signal or acommon-mode signal. Normal-mode interference can be mitigated by a software-implemented,50-Hz/60-Hz notch filter. Common-mode interference, on the other hand, is generally countered in one ofthree ways:

Increasing the isolation of the ground of the front-end electronics from the earth ground as much aspossible;

Increasing the common-mode rejection of the signal processing circuitry (on the order of 100 dB); Driving the patient body with an out-of-phase common-mode signal (also called as the right leg drive).

One of the primary specifications of an ECG front-end is the input-referred noise. It is typically specified tobe less than 30 mVRMS for the entire system over a bandwidth of 150 Hz (IEC60601-2-51,27). Thefrequency content of the signal determines the 3-dB cutoff frequencies required for the system filters.

2 Analog Front-End Design for ECG Systems Using Delta-Sigma ADCs SBAA160AMarch 2009Revised April 2010Submit Documentation Feedback

Copyright 20092010, Texas Instruments Incorporated

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBAA160A

Am

plit

ude

Signal Chain

At

electrode

At

electrode

High gain

with

low-noise

amplifiers

At

ADC

At

ADC

Noise-free

dynamic range

Noise-free

dynamic range

Amp

noise

ADC

Noise

Am

plit

ude

Signal Chain

Low gain

(a) (b)

www.ti.com System Approaches

Apart from these issues, the signal from the ECG electrodes usually have motion artifacts and pacerpulses. These additional sources of interference must be removed by using appropriate filtering, either inthe analog domain (before the ADC) or in the digital domain (after the ADC). Typically, ECG machineshave a means to detect the presence of pacemakers. Pacer detection can be done either by usingdedicated hardware or by using software. The software approach requires the front-end to have higherbandwidth and the ADC to have a higher sampling rate. However, one of the advantages of usingsoftware pace detection is that as pacemaker devices evolve, the detection thresholds can be dynamicallychanged via software, instead of having to modify the system hardware.

3 System Approaches

3.1 Low-Resolution ( 16-bit) ADCs vs High-Resolution (24-bit) ADCsBased on the resolution of the ADC used in the signal chain, there are two different approaches toprocessing the ECG signal. One approach is to use low-noise amplifiers and to gain the input signalsignificantly (approximately 500), and thus use a low-resolution (approximately 16-bit) ADC, as shown inFigure 2a. In this case, care must be taken so that the noise of the amplifier that gets amplified does notdominate the overall system noise. The other approach would be to use a lower gain (approximately 5)and a high-resolution (approximately 24-bit) ADC, as shown in Figure 2b. In both approaches, thenoise-free dynamic range at the ADC output remains the same.

Figure 2. System Approaches Based on ADC Resolution

The other way to consider this result is that the system noise referred to the input is the same in bothcases. Therefore, the recorded signal quality would not be compromised. However, a decision about usingone of these approaches significantly affects the specifications of the individual components of the system,and consequently the overall cost, as explained in the next section. The high-resolution ADC approachsignificantly reduces the required hardware, which implies both a lower cost and lower powerrequirements.

3.2 Sequential Sampling vs Simultaneous Sampling

Two different solution