Analog Automatic Test Pattern Generation For

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Contents

1. INTRODUCTION

2. TEST STRATEGY DEFINITION

3. QUASI-STATIC STRUCTURAL TEST

3.1. Network Analysis and Global Process variations3.2. Spatial Correlation Model

3.3. Defect and Fault Model Definition

3.4.Discrimination Analysis

3.5. Test Stimuli Optimization4. APPLICATION EXAMPLE

5. CONCLUSION

6. REFERENCES


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INTRODUCTION

Its a new approach for structural, fault-oriented analogtest generation .

It test for the presence of manufacturing- related

defects.

In the SoC, it is difficult to access all of their ports and

as such existing test practices are not always applicable,

or need to be revised.

Faults which shift the operating point of a transistor-level analog circuit can be detected by inexpensive DC

testing or power supply current monitoring.


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Cont..

The fault detection based on Bayes decision rule for DCtesting is presented by combining the a prioriinformation and the information from testing.

By iteratively conducting the tests and applying the

Bayesian analysis, the occurrence probability of eachfault is found.

The Bayes risk is computed for all stimuli and for eachfault in the fault list.

The stimuli for which the Bayes risk is minimal, is takenas the test vector for the fault under consideration.


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TEST STRATEGY DEFINITION

In our approach, the circuit under test is excited with aquasi-static stimulus to sample the response atspecified times to detect the presence of a fault.

First, a tolerance window is derived according to teststimuli and test program.

The circuit is simulated without any faults and theresults of this test are saved in a database.

The next step is to sequentially inject the selectedfaults into the circuit and simulate .

To derive necessary stimuli for the ATPG, the teststimuli optimization is performed on the results

available in the database.


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1. Network Analysis and Global Process Variations

2. Spatial Correlation Model

3. Defect and Fault Model Definition

4. Discrimination Analysis

5. Test Stimuli Optimization


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Network Analysis and Global

Process Variations

General differential-algebraic equations, whichdescribe the circuits electrical behavior, have beenwidely investigated.

It allows us to decompose the circuits unknowns(node voltages, currents through branches) into adifferential component y for time dependent

solutions and an algebraic component z for quasi-static analysis.


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The nominal voltages and currents are obtained by

where,

B, CQand FQare functions of the deterministic initialsolution,

y0 is an arbitrary initial state of the circuit and

i and v are the independent current and voltagesources, respectively


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There is only one solution of z0.Due to processvariations, the manufactured values of processparameters will differ; hence, we model themanufactured values of the parameters

for transistor as a random variable.

where

and are the mean value and standard deviation

of the parameter pi, respectively,is the stochastic process corresponding to

parameter p, di denotes the location of transistor i onthe die with respect to a point origin and is the die

on which the transistor lies.


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Cont..

Table I shows some typical transistor parameters withtheir mean and spread values.


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Spatial Correlation Model The large data sets of process parameters obtained

through parameter extraction

This allows the study and modeling of the variationand correlation between process parameters, which isof crucial importance to obtain realistic values of themodeled circuit unknowns.

As an illustration we first show in Fig. 2 the parameterstatistics of a batch with three different threshold-adjust implantations.


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C t


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Cont.. The use of KarhunenLove expansion has generated

interest because of its bi-orthogonal property.

Here both the deterministic basis functions and thecorresponding random coefficients are orthogonal.

Assuming that pi is a zero-mean Gaussian process andusing the KarhunenLove expansion,

where is a vector of zero-mean uncorrelated

Gaussian random variablesis the eigenfunctions

is the eigenvalues


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Defect and Fault Model Definition

A defect model, accounting for voltage and current

shifts due to random manufacturing variations intransistor dimensions and process parameters definedas

Where, is the function of changes in nodevoltages and branch currents,

v defines a fitting parameter estimated from theextracted data,

w* and l* represent the geometrical deformation dueto manufacturing variations

p* models electrical parameter deviations from theircorresponding nominal values,


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Cont.. This defect model is used to generate a corresponding

circuit fault model by including the term of (5) into(1), written in matrix form as

Where z0 is a matrix of the nominal data

a random vector accounting for device

tolerances.


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Cont.. The fault model shifts the dc nodal voltages (dc branch

currents) out of their ideal state.

An obvious limitation of the fault model is that itcannot capture a faulty transient behavior of thecircuit under test.


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Discrimination Analysis

The first step is to choose and fix the significance levelof the test

Establish the critical region of the test correspondingto

This region depends both on the distribution of thetest statistic T and on whether the alternative

hypothesis is one- or two-sided. Based on this statistics, a decision is made to accept or

reject the data sample.


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Test Stimuli Optimization

Two approaches to test stimuli ordering areconsidered:

In the first stage, the test stimuli are ordered so thatthe test stimuli detecting the most-faulty parametersthat are detected by no other test stimuli areperformed

In the second stage, going from top to bottom, teststimuli, which do not increase the cumulativecoverage, are moved to the bottom of the list.


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Cont.. Following the steps described,


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Cont..where , tswap is a time required to introduce the fault

into circuitry, tcircuit simulate the circuit netlist,

ttolerance derive the boundaries of circuit response

tanalysis perform the NeymanPearson test

Nnodes denote the number of the nodes in the circuit

Nbias, Nsupply, Ninput, and Nreferencedesignate thenumber of bias, supply, input and reference nodes

where a quasi-static stimulus is applied, respectively, Nfault indicate the number of the faults

Npermutationdesignate the number of permutations ofthe test stimuli set


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APPLICATION EXAMPLE

Power-Scan Chain DfT

Fine ADC


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Power-Scan Chain DfT


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Fine ADC

Cont


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Cont..


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Analog Automatic Test Pattern Generation For

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