AN5113, Powering an i.MX 6SL based system using the ...Schematic Powering an i.MX 6SL based system...
20
NXP Semiconductors Application Note Document Number: AN5113 Rev. 1.0, 7/2016 © 2016 NXP B.V. 1 Introduction The PF3000 is a SMARTMOS highly integrated Power Management IC, ideally suited to power NXP's i.MX 6SL, i.MX 6S, i.MX 6DL, and the i.MX 7 series of application processors. This application note discusses the power tree configuration for powering an i.MX6SL based system using the PF3000. Powering an i.MX 6SL based system using the PF3000 PMIC Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 PF3000 voltage regulators . . . . . . . . . . . . . . . . . . . . . . 2 3 i.MX 6SL power management using the PF3000 . . . . . 3 4 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transcript of AN5113, Powering an i.MX 6SL based system using the ...Schematic Powering an i.MX 6SL based system...
NXP SemiconductorsApplication Note
Document Number: AN5113Rev. 1.0, 7/2016
© 2016 NXP B.V.
1 IntroductionThe PF3000 is a SMARTMOS highly integrated Power Management IC, ideally suited to power NXP's i.MX 6SL, i.MX 6S, i.MX 6DL, and the i.MX 7 series of application processors. This application note discusses the power tree configuration for powering an i.MX6SL based system using the PF3000.
Powering an i.MX 6SL based system using the PF3000 PMIC
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 PF3000 voltage regulators . . . . . . . . . . . . . . . . . . . . . . 2
3 i.MX 6SL power management using the PF3000 . . . . . 3
4 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PF3000 voltage regulators
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 2
2 PF3000 voltage regulatorsTable 1. shows a summary of the voltage regulators in the PF3000. Output voltage and startup sequence of the regulators is programmed into the PMIC through One Time Programmable (OTP) memory. For more details refer to the product datasheet.
Table 1. PF3000 voltage regulators
Regulator Output voltage range Load current rating
SW1A 0.7 V to 1.425 V; 1.8 V; 3.3 V 1000 mA
SW1B 0.7 V to 1.475 V 1750 mA
SW2 1.5 V to 1.85 V; 2.5 V to 3.3 V 1250 mA
SW3 0.9 V to 1.65 V 1500 mA
SWBST 5.0 V to 5.15 V 600 mA
VSNVS 3.0 V 1.0 mA
VLDO1 1.8 V to 3.3 V 100 mA
VLDO2 0.8 V to 1.55 V 250 mA
VLDO3 1.8 V to 3.3 V 100 mA
VLDO4 1.8 V to 3.3 V 350 mA
VCC_SD 1.8 V to 1.85 V; 2.85 V to 3.3 V 100 mA
V33 2.85 V to 3.3 V 350 mA
VREFDDR VINREFDDR/2 10 mA
i.MX 6SL power management using the PF3000
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 3
3 i.MX 6SL power management using the PF3000The i.MX 6SL processor features NXP's advanced implementation of the a single ARM® Cortex®-A9 MPCore™ multicore processor, which operates at speeds up to 1.0 GHz. Table 2. shows how PF3000 can be used to power an i.MX 6SL based system. This include the voltage rails required by the processor as well as memory and common peripherals. Being a programming PMIC, the PF3000 can be used in a number of ways to power the i.MX 6SL. Table 2. lists one of the many possibilities. Based on end application requirements, the power tree can be optimized. Contact your NXP representative for a BSP patch for the PF3000 with i.MX 6SL.
Table 2. PF3000 + i.MX 6SL power tree
Regulator Voltage Sequence Load domain
SW1A 1.375 1 VDDCORE
SW1B 1.375 1 VDDSOC
SW2 3.15 2VDDHIGH, VCC-eMCC, VCCQ-eMMC, MIC_VDD, EPDC Expansion Port, LCD Expansion Port, Mini-PCIe HMC, Debug UART to USB, Ethernet Transceiver, VCC_SPI_NOR_Flash
SW3 1.2 4 DRAM_PWR, VDD2_LPDDR2, NVCC_1.2V
SWBST 5.0 6 SYS_5V (OTG/Host, EPDC Expansion, LCD Expansion)
VSNVS 3.0 Always On VDD_SNVS_IN
VLDO1 1.8 3 VDD1_LPDDR2, Audio Codec
VLDO2 1.5 Off CMOS Camera, EPDC Expansion port,
VLDO3 3.0 Off N/A
VLDO4 1.8 3 NVCC_1.8V, EPDC Expansion Port, LCD Expansion Port, WEIM Expansion
VCC_SD 3.15 2 VCC_SD1, VDD-SD2, VDD-SD3
V33 2.85 Off CMOS Camera
VREFDDR 0.6 4 DRAM_VREF
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 4
4 Schematic
Figure 1. MCIMX6SLEVK-P3 board diagram
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 5
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DC JACK
5V
Over Voltage
Protection
Lithium Charger
PWR Cut Switch
For SW Development
Lithium single cell
battery connectors
Over-Voltage
LED
Main PWR
LED
I2C
AD
DR
: 0x
92
wall_filter
SHU
TDO
WN
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all_
ov_b
ase
wal
l_ct
l_ba
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wal
l_ct
l_ba
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wal
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L_O
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led1
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led1
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BAT
CH
G_O
UT_
SM54
18
BAT_
SNS
VDD
IO
GN
D
WAL
L_5V
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KPS
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1_5.
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GN
D
GN
DG
ND
WAL
L_5V
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K
GN
D
GN
D
GN
D
0
0
PGN
D
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ND
PGN
DPG
ND
PGN
D
PGN
D
PGN
D0
PGN
D
PSU
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5.0V
PF01
00_V
IN
SYS_
4V32
5
GN
D
BATT
P3V1
5_VD
DH
IGH
_SW
2
I2C
1_SC
L(6
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I2C
1_SD
A(6
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Dra
win
g Ti
tle:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
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of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
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BI:
SCH
-285
49 P
DF:
SPF
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MC
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oard
C
Mon
day,
Mar
ch 3
0, 2
015
SYS
Pow
er
316
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t Num
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Dat
e:Sh
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of
Page
Titl
e:
ICAP
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ssifi
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n:FC
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BI:
SCH
-285
49 P
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Mon
day,
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Rev
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Page
Titl
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Mon
day,
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SYS
Pow
er
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___
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2
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GO
UT_
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C5
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GO
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D5
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GO
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GN
DC
3
INT
B5
LX_C
1C
1
LX_D
1D
1
NO
BA
TC
2
PG
ND
_E1
E1
PG
ND
_E2
E2
PM
IDB
1
SH
DN
D3
SC
LA
4S
DA
A5
VB
US
_A1
A1
VB
US
_A2
A2
VIO
B4
VL
A3
VS
YS
_D4
D4
VS
YS
_E3
E3
VS
YS
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E4
R79
10
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910
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R79
00
0402
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R22
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5
4
1 2 3
D6
LED
Red
A C
R78
71.
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C6
DN
P0.
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VBAT
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 6
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SW1A
SW1B
SW1B
SW1A
SW3A - DNP
SW2
SW4
PMIC-ON
LED
LDO decouples are 4.7 uF
for BOM consolidation.
Not
e: J
17Sh
unt 1
-2 fo
r SYS
_5V
from
PM
IC: 6
00m
A li
mite
dSh
unt 2
-3 fo
r SYS
_5V
from
wal
l ada
pter
GPIO
pmic
_pw
r_on
_led
PF0
100_
5V
PF0
100_
5V
PF0
100_
5V
P1V
375_
VD
DA
RM
_SW
1AB
P1V
375_
VD
DS
OC
_SW
1C
pf01
00_s
w2_
out
p1V
2_sw
3_ou
t
pf01
00_v
hlf
GN
D
GN
D
PF0
100_
VIN
PF0
100_
VIN
GN
D VC
OR
ED
IG
GN
D
GN
D
GN
DG
ND
GN
D
PF0
100_
VIN
GN
D
SY
S_5
V
PS
U_V
1_5.
0VG
ND
GN
D
GN
D
P3V
15_L
ICE
LL
GN
D
GN
DP
F010
0_V
IN
PF0
100_
VIN
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
PF0100_VIN
GN
D
PF0
100_
VIN
GN
DG
ND
DR
AM
_VR
EF
GN
D
GN
DG
ND
GN
D
P3V
15_L
ICE
LL
GN
D
GN
D
PF0
100_
VIN
PF0
100_
VIN
GN
D
GN
D
GN
D
GN
D
PF0
100_
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GN
D
GN
D
GN
D
GN
D
V33
P3V
15_V
DD
HIG
H_S
W2
P3V
0_S
TBY
VD
D_A
RM
_IN
VD
D_S
OC
_IN
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15_V
DD
HIG
H_S
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P1V
2_D
DR
_SW
3
P1V
2_D
DR
_SW
3
P3V
0_V
SN
VS
VC
C_S
DX
P3V
15_V
DD
HIG
H_S
W2P3V
15_V
DD
HIG
H_S
W2
P1V
5_V
GE
N2
P1V
5_V
LDO
2
P1V
8_V
GE
N3
P1V
8_V
LDO
1
P3V
15_V
DD
HIG
H_S
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P1V
8_V
GE
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P1V
8_V
LDO
4
P2V
8_V
GE
N6
V33
P3V
0_V
LDO
3
P1V
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I2C
1_S
CL
(6,1
1)
I2C
1_S
DA
(6,1
1)
PM
IC_O
N_R
EQ
(6)
PO
R_B
(6,8
,11,
13)
PM
IC_S
TBY
_RE
Q(6
)
RE
F_C
LK_2
4M(6
)
Dra
win
g Ti
tle:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
8549
PD
F: S
PF-
2854
9A
MC
IMX6
SLEV
K-P
3 bo
ard
Cus
tom
Mon
day,
Mar
ch 3
0, 2
015
PMIC
416
___
___
XD
raw
ing
Title
:
Siz
eD
ocum
ent N
umbe
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ev
Dat
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heet
of
Pag
e Ti
tle:
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P C
lass
ifica
tion:
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UB
I:
SC
H-2
8549
PD
F: S
PF-
2854
9A
MC
IMX6
SLEV
K-P
3 bo
ard
Cus
tom
Mon
day,
Mar
ch 3
0, 2
015
PMIC
416
___
___
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raw
ing
Title
:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
8549
PD
F: S
PF-
2854
9A
MC
IMX6
SLEV
K-P
3 bo
ard
Cus
tom
Mon
day,
Mar
ch 3
0, 2
015
PMIC
416
___
___
X
C61
0.1U
F
16V
0402
_CC
J14
HD
R 1
X2
1 2
C41
4.7u
F06
03_C
C10
V
C46
4.7u
F06
03_C
C10
V
C34
4.7u
F
6.3V
0402
_CC
SH
2
SO
LDE
R S
HO
RT
SH
0805
_40
C53
22U
F
6.3V
0603
_CC
C37
0.1U
F
16V
0402
_CC
R51
006
03_C
CD
NP
C41
54.
7uF
0603
_CC
10V
C65
22U
F
6.3V
0603
_CC
R54
006
03_C
C
SH
5
SO
LDE
R S
HO
RT
SH
0805
_40
C60
0.1U
F
16V
0402
_CC
C41
44.
7uF
C47
4.7u
F06
03_C
C10
V
C32
0.22
uF04
02_C
C16
V
C62
0.1U
F
16V
0402
_CC
R55
0D
NP
C33
4.7u
F
C31
4.7u
F
C23
0.22
UF
6.3V
0201
_CC
C59
0.1U
F
16V
0402
_CC
C41
30.
1UF
16V
0402
_CC
R74
547
KD
NP
0402
_CC
L8
2.2u
H
12
R57
330
0402
_CC
C27
0.22
uF
C43
22U
F
6.3V
0603
_CC
C69
10uF
10V
C54
22U
F
6.3V
0603
_CC
C21
1.0U
F
10V
C22
1.0U
F10
V
R43
004
02_C
C
C66
4.7u
F06
03_C
C10
V
C68
0.1U
F
16V
0402
_CC
L4 1UH
ind_
vls2
5201
0
12
L3
1UH
ind_
vls3
012_
sm12
C40
0.22
UF
C35
4.7u
F
C39
0.1U
F
16V
0402
_CC
C49
22U
F
6.3V
0603
_CC
U35
MC
32P
F300
XE
P
VDDIO47
VCOREREF44
SW2LX17
GNDREF40
SW
1BFB
11
VLDO2IN16
GN
DR
EF1
12
VCOREDIG43
PWRON48
SCL46
VIN42
SW
1ALX
8
SW
1BIN
10
STA
ND
BY
4
ICTE
ST
5
SW
1AIN
7S
W1A
FB6
SW
1BLX
9
SDA45
VDDOTP39
VLDO1IN13
VLDO114
VIN238
LIC
ELL
36
SWBSTFB37
SW
BS
TLX
35
VC
C_S
D33
VS
NV
S34
V33
32
LDO
G30
VP
WR
31
SW
3LX
29
SW
3FB
27S
W3I
N28
VR
EFD
DR
25G
ND
RE
F226
VLDO422
VLDO34IN21
VCORE41
SW2IN18
SW2FB19
VLDO320
VLDO215
INT
1
SD
_VS
EL
2
RE
SE
TBM
CU
3
VHALF23
VINREFDDR24
EPAD49
R53
006
03_C
CD
NP
R56
0
C28
0.22
uF
R52
006
03_C
C
R40
0
0402
_CC
C50
22U
F
6.3V
0603
_CC
L5
1UH
ind_
vls2
5201
0
12
R78
40
C70
47uF
C30
4.7u
F
6.3V
0402
_CC
R78
30
0402
_CC
D12
MB
R14
0SFT
AC
R48
004
02_C
C
C38
0.1U
F
L7
1UH
ind_
vls3
012_
sm12
C41
2
0.22
UF
R49
004
02_C
C
C24
1.0U
F10
V
C55
0.1U
F
16V
0402
_CC
SH
1
SO
LDE
R S
HO
RT
SH
0805
_40
D15
LED
Gre
en
AC
SH
3
SO
LDE
R S
HO
RT
SH
0805
_40
J17
HD
R_1
X3
123
C64
22U
F
6.3V
0603
_CC
C56
0.1U
F
16V
0402
_CC
C57
0.1U
F
16V
0402
_CC
C42
22U
F
6.3V
0603
_CC
C36
1.0U
F
10V
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 7
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Note:
VDD_SOC_CAP1 to 6 and
VDD_SOC_CAP7 to 9 can be
connected together. If
split, proper
corresponding decoupling
capacitance needs to be
placed for each group of
pins.
D24 ensures VDD_SNVS_IN
is always powered whenever
VDDHIGH_IN is powered to meet
data sheet spec even if
P3V0_STBY faults to 0 V.
GN
D
VD
D_S
NV
S_C
AP GN
D
GN
D
GN
D
VD
D_H
IGH
_CA
P
VD
D_P
LL_C
AP
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
VD
D_H
IGH
_CA
P
GN
D
GN
D
GN
D
VD
D_A
RM
_CA
P
VD
D_S
OC
_CA
P
GN
D
GN
D
GN
D
GN
D
VD
D_S
OC
_CA
P1
VD
D_P
U_C
AP
GN
D
P1V
8_V
GE
N4
P1V
2_D
DR
_SW
3
P1V
2_D
DR
_SW
3
VD
D_A
RM
_IN
VD
D_S
OC
_IN
P3V
15_V
DD
HIG
H_S
W2
VD
D_3
V15
_IN
P3V
0_S
TBY
P3V
0_V
SN
VS
P3V
0_V
LDO
3
Dra
win
g Ti
tle:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
8549
PD
F: S
PF-
2854
9A
MC
IMX6
SLEV
K-P
3 bo
ard
B
Mon
day,
Mar
ch 3
0, 2
015
IMX6
SL_P
ower
516
___
___
XD
raw
ing
Title
:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
8549
PD
F: S
PF-
2854
9A
MC
IMX6
SLEV
K-P
3 bo
ard
B
Mon
day,
Mar
ch 3
0, 2
015
IMX6
SL_P
ower
516
___
___
XD
raw
ing
Title
:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
8549
PD
F: S
PF-
2854
9A
MC
IMX6
SLEV
K-P
3 bo
ard
B
Mon
day,
Mar
ch 3
0, 2
015
IMX6
SL_P
ower
516
___
___
X
C92
0.22
UF
6.3V
0201
_CC
C97
0.22
UF
6.3V
0201
_CC
C40
14.
7uF
6.3V
0402
_CC
C94
0.22
UF
6.3V
0201
_CC
C10
20.
22U
F
6.3V
0201
_CC
C39
64.
7uF
6.3V
0402
_CC
C39
04.
7uF
6.3V
0402
_CC
C90
0.22
UF
6.3V
0201
_CC
U1H
MC
IMX
6L8D
VN
10A
A
NV
CC
_1V
8_1
E14
NV
CC
_1V
8_2
E15
NV
CC
_1V
8_3
M20
NV
CC
_1V
8_4
Y11
NV
CC
_3V
3_1
H10
NV
CC
_3V
3_2
H11
NV
CC
_3V
3_3
H14
NV
CC
_3V
3_4
H15
NV
CC
_3V
3_5
L18
NV
CC
_3V
3_6
M18
NV
CC
_3V
3_7
T19
VD
D_H
IGH
_IN
1R
12
VD
D_H
IGH
_IN
2R
13
VD
D_H
IGH
_IN
3T1
2
VD
D_H
IGH
_IN
4T1
3
VD
D_H
IGH
_CA
P1
R14
VD
D_H
IGH
_CA
P2
R15
VD
D_H
IGH
_CA
P3
T14
VD
D_H
IGH
_CA
P4
T15
VD
D_S
OC
_IN
1J1
0
VD
D_S
OC
_IN
2J1
1
VD
D_S
OC
_IN
3K
10
VD
D_S
OC
_IN
4K
11
VD
D_A
RM
_IN
1J1
2
VD
D_A
RM
_IN
2J1
3
VD
D_A
RM
_IN
3J1
4
VD
D_A
RM
_IN
4K
12
VD
D_A
RM
_IN
5K
13
VD
D_A
RM
_IN
6K
14
VD
D_A
RM
_CA
P1
J15
VD
D_A
RM
_CA
P2
J16
VD
D_A
RM
_CA
P3
J17
VD
D_A
RM
_CA
P4
J18
VD
D_A
RM
_CA
P5
K15
VD
D_A
RM
_CA
P6
K16
VD
D_A
RM
_CA
P7
K17
VD
D_A
RM
_CA
P8
K18
VD
D_S
OC
_CA
P1
J7
VD
D_S
OC
_CA
P2
J8
VD
D_S
OC
_CA
P3
J9
VD
D_S
OC
_CA
P4
K7
VD
D_S
OC
_CA
P5
K8
VD
D_S
OC
_CA
P6
K9
VD
D_P
U_I
N1
R10
VD
D_P
U_I
N2
R11
VD
D_P
U_I
N3
T10
VD
D_P
U_I
N4
T11
VD
D_P
U_C
AP
1R
7
VD
D_P
U_C
AP
2R
8
VD
D_P
U_C
AP
3R
9
VD
D_P
U_C
AP
4T7
VD
D_P
U_C
AP
5T8
VD
D_S
NV
S_I
NA
C20
VD
D_S
NV
S_C
AP
AD
20
NV
CC
_1.2
VW
7
DR
AM
_PW
R1
E6
DR
AM
_PW
R2
G7
DR
AM
_PW
R3
H6
DR
AM
_PW
R4
J6
DR
AM
_PW
R5
N6
DR
AM
_PW
R6
P7
DR
AM
_PW
R7
T6
DR
AM
_PW
R8
U6
DR
AM
_PW
R_2
P5
M6
VD
D_P
LL_C
AP
Y19
VD
D_P
U_C
AP
6T9
VD
D_S
OC
_CA
P7
N18
VD
D_S
OC
_CA
P8
P18
VD
D_S
OC
_CA
P9
R18
VD
D_S
OC
_IN
5R
16
VD
D_S
OC
_IN
6R
17
VD
D_S
OC
_IN
7T1
6
VD
D_S
OC
_IN
8T1
7
VD
D_S
OC
_IN
9T1
8
NV
CC
_3V
3_8
U10
NV
CC
_3V
3_9
U11
DR
AM
_PW
R9
V7
DR
AM
_PW
R10
Y6
C93
0.22
UF
6.3V
0201
_CC
C76
22U
F
6.3V
0603
_CC
C39
74.
7uF
6.3V
0402
_CC
C39
44.
7uF
6.3V
0402
_CC
C82
0.22
UF
6.3V
0201
_CC
C40
54.
7uF
6.3V
0402
_CC
C81
22U
F
6.3V
0603
_CC
C40
34.
7uF
6.3V
0402
_CC
C39
94.
7uF
6.3V
0402
_CC
C10
10.
22U
F
6.3V
0201
_CC
C39
84.
7uF
6.3V
0402
_CC
C99
0.22
UF
6.3V
0201
_CC
C72
0.22
UF
6.3V
0201
_CC
U1I
MC
IMX
6L8D
VN
10A
A
GN
D1
A1
GN
D2
A4
GN
D3
A7
GN
D4
A24
GN
D5
C6
GN
D6
C10
GN
D7
C14
GN
D8
C19
GN
D9
D1
GN
D10
D2
GN
D11
E5
GN
D12
G1
GN
D13
G8
GN
D14
G9
GN
D15
G10
GN
D16
G11
GN
D17
G13
GN
D18
G14
GN
D19
G15
GN
D20
G17
GN
D21
G18
GN
D22
H3
GN
D23
H7
GN
D24
H18
GN
D25
H22
GN
D26
J5
GN
D27
K1
GN
D28
N3
GN
D29
L7
GN
D30
L9
GN
D31
L10
GN
D32
L11
GN
D33
L12
GN
D34
L13
GN
D35
L14
GN
D36
L15
GN
D37
L16
GN
D38
M17
GN
D39
M5
GN
D40
M7
GN
D41
M8
GN
D42
M9
GN
D43
M10
GN
D44
M11
GN
D45
M12
GN
D46
M13
GN
D47
M14
GN
D48
M15
GN
D49
M16
GN
D50
N17
GN
D51
N7
GN
D52
N8
GN
D53
N9
GN
D54
N10
GN
D55
N11
GN
D56
N12
GN
D57
N13
GN
D58
N14
GN
D59
N15
GN
D60
N16
GN
D61
P9
GN
D62
P10
GN
D63
P11
GN
D64
P12
GN
D65
P13
GN
D66
P14
GN
D67
P15
GN
D68
P16
GN
D69
R1
GN
D70
N22
GN
D71
T5G
ND
72U
3G
ND
73U
7G
ND
74U
18G
ND
75V
1G
ND
76V
8G
ND
77V
9G
ND
78V
10G
ND
79V
11G
ND
80V
12G
ND
81V
13G
ND
82V
14G
ND
83V
15G
ND
84V
16G
ND
85V
17G
ND
86V
18G
ND
87Y
5G
ND
88A
A1
GN
D89
AA
2G
ND
90U
22G
ND
91A
B10
GN
D92
AB
14G
ND
93A
B18
GN
D94
AC
18G
ND
95A
D24
GN
D96
AD
1G
ND
97A
D4
GN
D98
AD
7
C77
0.22
UF
6.3V
0201
_CC
D24
BA
T54C
-7-F
2
3
1C
880.
22U
F
6.3V
0201
_CC
R58
006
03_C
C
C80
22U
F
6.3V
0603
_CC
C91
0.22
UF
6.3V
0201
_CC
C95
0.22
UF
6.3V
0201
_CC
C38
94.
7uF
6.3V
0402
_CC
C96
0.22
UF
6.3V
0201
_CC
C79
22U
F
6.3V
0603
_CC
C40
44.
7uF
6.3V
0402
_CC
SH
4
SO
LDE
R S
HO
RT
SH
0805
_40
C75
22U
F
6.3V
0603
_CC
C40
04.
7uF
6.3V
0402
_CC
C98
0.22
UF
6.3V
0201
_CC
R78
50
0603
_CC
DN
P
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 8
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ON
/OFF
RES
ET
32.768kHz
24MHz
POR Reset
On/Off
I2C pullups
i.MX6SL
LCD
EPD
CSD
Aud
io,U
AR
T,FE
CK
eypa
d,H
SIC
,PW
M
Con
trol
USB
Note: Watchdog reset is
being taken care of
internally.
3G Card Enable
3G Card Reset
Charger-Ok Status
Charger-fault status
Charging status
Ethernet power enable
3GCARD_USB_D_P
SD1 Card Detect
SD1 Write Protect
USB_5V_OTG Over-current Flag
USB_5V_OTG Enable
USB_5V_HOST Enable
USB_OTG1_ID
USB_5V_HOST Over-current Flag
SD2 Card Detect
SD2 Write Protect
SD3 Card Detect
Headphone detect
3GCARD_USB_D_N
Primary Use
Primary Use
Primary Use
Primary Use
Primary Use
Capacitive Touch Interrupt
UART_TX
UART_RX
SPDIF
ONOFF
LCD_Power_EN
Accelerometer Interrupt
Capacitive Touch Reset
LCD_Brightness
Debug LED
PMIC INT
Note: Pull-up resistor must be
sized to meet the signal rise
times and also the Vil spec of
all the bus components.
Due to board loadings this
resistor was reduced.
Validate your design, with the
largest allowable resistor to
reduce current usage.
Pin 1
Default
Pin 1
Default
HSI
C_S
TRO
BE
IMX_
OTG
_VBU
S
XTAL
O
RTC
_XTA
LIR
TC_X
TALO
XTAL
I
GAN
AIO
CLK
1PC
LK1N
IMX_
OTG
_VBU
S
TAM
PER
TAM
PER
GAN
AIO
HSI
C_D
AT
HSI
C_D
AT_G
PIO
HSI
C_S
TRO
BE_G
PIO
CLK
1NC
LK1P
XTAL
OR
TC_X
TALO
RTC
_XTA
LIXT
ALI
ON
OFF H
SIC
_DAT
_GPI
O
HSI
C_S
TRO
BEH
SIC
_DAT
HSI
C_D
AT
HSI
C_S
TRO
BE
MX_
USB
_HO
ST_D
_P
MX_
USB
_HO
ST_D
_N
GN
D
VDD
_USB
_CAP
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
LCD
_CLK
(11)
LCD
_EN
ABLE
(11)
LCD
_HSY
NC
(11)
LCD
_VSY
NC
(11)
LCD
_RES
ET(1
1)LC
D_D
AT0
(11,
13)
LCD
_DAT
1(1
1,13
)LC
D_D
AT2
(11,
13)
LCD
_DAT
3(1
1,13
)LC
D_D
AT4
(11,
13)
LCD
_DAT
5(1
1,13
)LC
D_D
AT6
(11,
13)
LCD
_DAT
7(1
1,13
)LC
D_D
AT8
(11,
13)
LCD
_DAT
9(1
1,13
)LC
D_D
AT10
(11,
13)
LCD
_DAT
11(1
1,13
)LC
D_D
AT12
(11,
13)
LCD
_DAT
13(1
1,13
)LC
D_D
AT14
(11,
13)
LCD
_DAT
15(1
1,13
)LC
D_D
AT16
(11,
13)
LCD
_DAT
17(1
1,13
)LC
D_D
AT18
(11,
13)
LCD
_DAT
19(1
1,13
)LC
D_D
AT20
(11,
13)
LCD
_DAT
21(1
1,13
)LC
D_D
AT22
(11,
13)
LCD
_DAT
23(1
1,13
)
AUD
_RXF
S(1
2)AU
D_R
XC(1
2)AU
D_R
XD(1
0)AU
D_T
XC(1
0)AU
D_T
XFS
(10)
AUD
_TXD
(10)
AUD
_MC
LK(1
0)
UAR
T1_R
XD(1
4)U
ART1
_TXD
(14)
I2C
1_SC
L(4
,6,1
1)I2
C1_
SDA
(4,6
,11)
I2C
2_SC
L(6
,10,
11)
I2C
2_SD
A(6
,10,
11)
ECSP
I1_S
CLK
(8)
ECSP
I1_M
OSI
(8)
ECSP
I1_M
ISO
(8)
ECSP
I1_S
S0(8
)EC
SPI2
_SC
LK(8
,9,1
1)EC
SPI2
_MO
SI(3
,11)
ECSP
I2_M
ISO
(3,1
1)EC
SPI2
_SS0
(3,1
1)
FEC
_MD
IO(1
5)FE
C_T
X_C
LK(1
5)FE
C_R
X_ER
(10)
FEC
_CR
S_D
V(1
5)FE
C_R
XD1
(15)
FEC
_TXD
0(1
5)FE
C_M
DC
(15)
FEC
_RXD
0(1
5)FE
C_T
X_EN
(15)
FEC
_TXD
1(1
5)FE
C_R
EF_C
LK(1
5)
SD1_
CLK
(8)
SD1_
CM
D(8
)SD
1_D
AT0
(8)
SD1_
DAT
1(8
)SD
1_D
AT2
(8)
SD1_
DAT
3(8
)SD
1_D
AT4
(8)
SD1_
DAT
5(8
)SD
1_D
AT6
(8)
SD1_
DAT
7(8
)
SD2_
RST
(8,1
1)SD
2_C
LK(8
)SD
2_C
MD
(8)
SD2_
DAT
0(8
)SD
2_D
AT1
(8)
SD2_
DAT
2(8
)SD
2_D
AT3
(8)
SD2_
DAT
4(8
,11)
SD2_
DAT
5(8
,11)
SD2_
DAT
6(8
)SD
2_D
AT7
(8)
SD3_
CLK
(8)
SD3_
CM
D(8
)SD
3_D
AT0
(8)
SD3_
DAT
1(8
)SD
3_D
AT2
(8)
SD3_
DAT
3(8
)
KEY_
RO
W0
(11,
12)
KEY_
RO
W1
(11,
12)
KEY_
RO
W2
(11,
12)
KEY_
RO
W3
(11)
KEY_
RO
W4
(9,1
1)KE
Y_R
OW
5(1
1)KE
Y_R
OW
6(1
1)KE
Y_R
OW
7(8
,11)
KEY_
CO
L0(1
1,12
)KE
Y_C
OL1
(11,
12)
KEY_
CO
L2(1
1,12
)KE
Y_C
OL3
(8,1
1)KE
Y_C
OL4
(9,1
1)KE
Y_C
OL5
(9,1
1)KE
Y_C
OL6
(11)
KEY_
CO
L7(8
,11)
PWM
1(1
1)
REF
_CLK
_32K
(8)
USB
_OTG
1_D
_P(9
)U
SB_O
TG1_
D_N
(9)
USB
_Hos
t_VB
US
(9)
JTAG
_TR
STB
(14)
JTAG
_TD
I(1
4)JT
AG_T
MS
(14)
JTAG
_TC
K(1
4)JT
AG_T
DO
(14)
JTAG
_MO
D(1
4)
EPD
C_P
WR
WAK
EUP
(11)
EPD
C_P
WR
INT
(11)
EPD
C_V
CO
M0
(11)
EPD
C_D
0(1
1)
EPD
C_D
8(1
1)EP
DC
_D9
(11)
EPD
C_D
11(1
1)EP
DC
_D12
(11)
EPD
C_D
13(1
1)
EPD
C_D
15(1
1)EP
DC
_D14
(11)
EPD
C_P
WR
CTR
L3(1
1)
EPD
C_V
CO
M1
(11)
EPD
C_D
10(1
1)
EPD
C_D
4(1
1)
EPD
C_D
1(1
1)EP
DC
_D2
(11)
EPD
C_D
3(1
1)
EPD
C_D
5(1
1)EP
DC
_D6
(11)
EPD
C_D
7(1
1)
EPD
C_G
DSP
(11)
EPD
C_G
DO
E(1
1)EP
DC
_GD
CLK
(11)
EPD
C_G
DR
L(1
1)
EPD
C_S
DC
LK(1
1)EP
DC
_SD
LE(1
1)
EPD
C_S
DSH
R(1
1)EP
DC
_SD
OE
(11)
EPD
C_S
DC
E0(1
1)EP
DC
_SD
CE1
(11)
EPD
C_P
WR
CO
M(9
,11)
EPD
C_P
WR
STAT
(11)
EPD
C_P
WR
CTR
L0(1
1)EP
DC
_PW
RC
TRL1
(11)
EPD
C_P
WR
CTR
L2(1
1)
EPD
C_S
DC
E3(1
1)
EPD
C_B
DR
1(1
1)EP
DC
_BD
R0
(11)
EPD
C_S
DC
E2(1
1)
REF
_CLK
_24M
(4)
ON
OFF
(6)
BOO
T_M
OD
E0(1
3)BO
OT_
MO
DE1
(13)
PMIC
_ON
_REQ
(4)
PMIC
_STB
Y_R
EQ(4
)PO
R_B
(4,6
,8,1
1,13
)
WD
OG
_B(6
)
USB
_OTG
1_VB
US
(9)
I2C
1_SD
A(4
,6,1
1)
I2C
1_SC
L(4
,6,1
1)
I2C
2_SD
A(6
,10,
11)
I2C
2_SC
L(6
,10,
11)
ON
OFF
(6)
WD
OG
_B(6
)
POR
_B(4
,6,8
,11,
13)
JTAG
_nSR
ST(1
4)
WD
OG
_B(6
)
HSI
C_S
TRO
BE_G
PIO
(14)
USB
_Hos
t_D
_N(9
)
USB
_Hos
t_D
_P(9
)
PCIE
_USB
_Hos
t_D
_P(1
2)
PCIE
_USB
_Hos
t_D
_N(1
2)
Dra
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tle:
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Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
IMX6
SL_S
oC
616
___
___
XD
raw
ing
Title
:
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umen
t Num
ber
Rev
Dat
e:Sh
eet
of
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Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
IMX6
SL_S
oC
616
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
IMX6
SL_S
oC
616
___
___
X
GND2
GND1
Y3
24M
HZ
123
4
R77
82.
21M
0603
_CC
SH12
0
SW2
SPST
PB
13 4
2
R84
1.0K
1%
SW1
SPST
PB
13 4
2
C19
716
PF 50V
0603
_CC
R86
1.0K
1%
C19
616
PF 50V
0603
_CC
LCD
U1C
MC
IMX6
L8D
VN10
AA
LCD
_CLK
T22
LCD
_EN
AB
LEJ2
4
LCD
_HS
YN
CH
23
LCD
_VS
YN
CJ2
3
LCD
_RE
SE
TH
24
LCD
_DA
T0Y
24
LCD
_DA
T1W
23
LCD
_DA
T2W
24
LCD
_DA
T3V
23
LCD
_DA
T4V
24
LCD
_DA
T5U
21
LCD
_DA
T6U
23
LCD
_DA
T7U
24
LCD
_DA
T8T2
3
LCD
_DA
T9T2
4
LCD
_DA
T10
R23
LCD
_DA
T11
R24
LCD
_DA
T12
P23
LCD
_DA
T13
P24
LCD
_DA
T14
N21
LCD
_DA
T15
N23
LCD
_DA
T16
N24
LCD
_DA
T17
M22
LCD
_DA
T18
M23
LCD
_DA
T19
M24
LCD
_DA
T20
L23
LCD
_DA
T21
L24
LCD
_DA
T22
K23
LCD
_DA
T23
K24
R50
0 0603
_CC
R37
31.
0M04
02_C
CD
NP
J20
128-
0711
-20
DN
P
2 3
1
D20
BAT5
4A-7
-F
2
3
1
C40
24.
7uF
6.3V
0402
_CC
SH13
0
JTAG
SYSTEM
WDOG
ANATOP
U1A
MC
IMX6
L8D
VN10
AA
JTA
G_T
RS
TA
A15
JTA
G_T
DI
W14
JTA
G_M
OD
Y14
JTA
G_T
CK
AA
14JT
AG
_TM
SY
15
JTA
G_T
DO
W15
TAM
PE
RY
18
PM
IC_O
N_R
EQ
AD
15
PM
IC_S
TBY
_RE
QA
D16
PO
RA
C16
ON
OFF
W18
BO
OT_
MO
DE
0A
C15
BO
OT_
MO
DE
1A
B15
TES
T_M
OD
EU
15
WD
OG
F18
XTA
LOA
C21
XTA
LIA
D21
RTC
_XTA
LOA
A19
RTC
_XTA
LIA
B19
CLK
1PA
C23
CLK
1NA
D23
GA
NA
IOA
D22
EPDC
U1B
MC
IMX6
L8D
VN10
AA
EP
DC
_D0
A18
EP
DC
_D1
A17
EP
DC
_D2
B17
EP
DC
_D3
A16
EP
DC
_D4
B16
EP
DC
_D5
A15
EP
DC
_D6
B15
EP
DC
_D7
C15
EP
DC
_D8
D15
EP
DC
_D9
F15
EP
DC
_D10
G16
EP
DC
_D11
F14
EP
DC
_D12
D14
EP
DC
_D13
B14
EP
DC
_D14
A14
EP
DC
_D15
A13
EP
DC
_SD
CLK
B10
EP
DC
_SD
LEB
8
EP
DC
_SD
OE
E7
EP
DC
_SD
CE
0C
11
EP
DC
_SD
CE
1A
10
EP
DC
_SD
CE
3A
9E
PD
C_S
DC
E2
B9
EP
DC
_GD
CLK
A12
EP
DC
_GD
OE
B13
EP
DC
_GD
RL
B12
EP
DC
_GD
SP
A11
EP
DC
_VC
OM
0C
7
EP
DC
_VC
OM
1D
7
EP
DC
_BD
R0
C18
EP
DC
_BD
R1
B18
EP
DC
_PW
RC
TRL0
D11
EP
DC
_PW
RC
TRL1
E11
EP
DC
_PW
RC
TRL2
F11
EP
DC
_PW
RC
TRL3
G12
EP
DC
_PW
RC
OM
B11
EP
DC
_PW
RIN
TF1
0
EP
DC
_PW
RS
TAT
E10
EP
DC
_PW
RW
AK
EU
PD
10
EP
DC
_SD
SH
RF7
R59
0 0603
_CC
DN
P
R85
1.0K
1%
R39
310
K04
02_C
CD
NPR38
004
02_C
C
R46
0 0603
_CC
DN
P
J136
HD
R 2
X4
12
34 6
5 78
Q30
IRLM
L640
1
1
32
R87
1.0K
1%
PWM
USB_HSIC
KEY
CLKOUT
U1G
MC
IMX6
L8D
VN10
AA
HS
IC_D
AT
AA
6
HS
IC_S
TRO
BE
AB
6
PW
M1
Y7
KE
Y_R
OW
0G
24
KE
Y_R
OW
1F2
4
KE
Y_R
OW
2E
24
KE
Y_R
OW
3E
21
KE
Y_R
OW
4E
19
KE
Y_R
OW
5D
23
KE
Y_R
OW
6C
24
KE
Y_R
OW
7B
24
KE
Y_C
OL0
G23
KE
Y_C
OL1
F23
KE
Y_C
OL2
E23
KE
Y_C
OL3
E22
KE
Y_C
OL4
E20
KE
Y_C
OL5
D24
KE
Y_C
OL6
D22
KE
Y_C
OL7
C23
RE
F_C
LK_2
4MA
C14
RE
F_C
LK_3
2KA
D14
Y132
.768
kHz
12
SD1
SD2
SD3
U1E
MC
IMX6
L8D
VN10
AASD
1_C
LKB
20
SD
1_C
MD
B21
SD
1_D
AT0
B23
SD
1_D
AT1
A23
SD
1_D
AT2
C22
SD
1_D
AT3
B22
SD
1_D
AT4
A22
SD
1_D
AT5
A21
SD
1_D
AT6
A20
SD
1_D
AT7
A19
SD
2_R
ST
Y23
SD
2_C
LKA
C24
SD
2_C
MD
AB
24
SD
2_D
AT0
AB
22
SD
2_D
AT1
AB
23
SD
2_D
AT2
AA
22
SD
2_D
AT3
AA
23
SD
2_D
AT4
AA
24
SD
2_D
AT5
Y20
SD
2_D
AT6
Y21
SD
2_D
AT7
Y22
SD
3_C
LKA
B11
SD
3_C
MD
AA
11
SD
3_D
AT0
AC
11
SD
3_D
AT1
AD
11
SD
3_D
AT2
AC
12
SD
3_D
AT3
AD
12
Q31
2N70
02
3
1
2
R60
004
02_C
C
UART
AUDIO
I2C
ENET
SPI
U1D
MC
IMX6
L8D
VN10
AA
AU
D_R
XFS
J19
AU
D_R
XC
J21
AU
D_R
XD
J20
AU
D_T
XFS
H21
AU
D_T
XC
H20
AU
D_T
XD
J22
AU
D_M
CLK
H19
UA
RT1
_RX
DB
19
UA
RT1
_TX
DD
19
I2C
1_S
CL
AC
13
I2C
1_S
DA
AD
13
I2C
2_S
CL
E18
I2C
2_S
DA
D18
EC
SP
I1_S
CLK
N19
EC
SP
I2_S
CLK
U19
EC
SP
I1_M
OS
IN
20
EC
SP
I1_M
ISO
M19
EC
SP
I1_S
S0
M21
EC
SP
I2_M
OS
IU
20
EC
SP
I2_M
ISO
T20
EC
SP
I2_S
S0
T21
FEC
_MD
IOA
B7
FEC
_MD
CA
A7
FEC
_TX
_CLK
AC
8
FEC
_RX
_ER
AD
9
FEC
_CR
S_D
VA
C9
FEC
_RX
D1
AC
10
FEC
_TX
D0
Y10
FEC
_RX
D0
AA
10
FEC
_TX
_EN
AD
10
FEC
_TX
D1
W11
FEC
_RE
F_C
LKW
10
C10
00.
22U
F
6.3V
0201
_CC
R41
010
K04
02_C
C
C19
518
pF 25V
0402
_CC
ANATOP
U1J
MC
IMX6
L8D
VN10
AA
US
B_O
TG2_
VB
US
AD
18
US
B_O
TG2_
DP
AC
17
US
B_O
TG2_
DN
AD
17
US
B_O
TG1_
VB
US
AA
18
US
B_O
TG1_
DP
AC
19
US
B_O
TG1_
DN
AD
19
US
B_O
TG1_
CH
DA
C22
VD
D_U
SB
_CA
PU
14
J19
128-
0711
-20
DN
P
2 3
1
C19
418
pF 25V
0402
_CC
D19
BAT5
4A-7
-F
2
3
1
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 9
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
8Gb
400M
Hz
cloc
k
LPDDR2
DD
Ri.MX6SL
Not
e:So
me
dual
-die
LPD
DR
2 pa
ckag
esre
quire
a s
epar
ate
ZQ a
t pin
AC
11.
Mic
ron
M
T42L
256M
32D
2LG
-25
WT:
A
DR
AM_D
0D
RAM
_D1
DR
AM_D
2D
RAM
_D3
DR
AM_D
4D
RAM
_D5
DR
AM_D
6D
RAM
_D7
DR
AM_D
24D
RAM
_D25
DR
AM_D
26D
RAM
_D27
DR
AM_D
28D
RAM
_D29
DR
AM_D
30D
RAM
_D31
DR
AM_D
16D
RAM
_D17
DR
AM_D
18D
RAM
_D19
DR
AM_D
20D
RAM
_D21
DR
AM_D
22D
RAM
_D23
DR
AM_D
9D
RAM
_D8
DR
AM_D
10D
RAM
_D11
DR
AM_D
12D
RAM
_D13
DR
AM_D
14D
RAM
_D15
DR
AM_A
0D
RAM
_A1
DR
AM_A
2D
RAM
_A3
DR
AM_A
4D
RAM
_A5
DR
AM_A
6D
RAM
_A7
DR
AM_A
8D
RAM
_A9
DR
AM_S
DQ
S0_N
DR
AM_S
DQ
S0_P
DR
AM_D
QM
0
DR
AM_D
QM
1
DR
AM_S
DQ
S1_P
DR
AM_S
DQ
S1_N
DR
AM_D
QM
2D
RAM
_SD
QS2
_ND
RAM
_SD
QS2
_P
DR
AM_D
QM
3
DR
AM_S
DQ
S3_P
DR
AM_S
DQ
S3_N
DR
AM_C
S1
DR
AM_C
S0
DR
AM_S
DC
LK0_
PD
RAM
_SD
CLK
0_N
DR
AM_S
DC
KE0
IMX_
RAM
_CAL
IBR
ATIO
N
DR
AM_S
DC
KE1
DR
AM_Z
Q1
DR
AM_S
DC
KE0
DR
AM_S
DC
KE1
DR
AM_D
QM
1D
RAM
_DQ
M1
DR
AM_D
QM
2D
RAM
_DQ
M2
DR
AM_D
QM
3D
RAM
_DQ
M3
DR
AM_S
DC
LK0_
PD
RAM
_SD
CLK
0_N
DR
AM_C
S1
DR
AM_D
0D
RAM
_D1
DR
AM_D
2D
RAM
_D3
DR
AM_D
4D
RAM
_D5
DR
AM_D
6D
RAM
_D7
DR
AM_D
8D
RAM
_D9
DR
AM_D
10D
RAM
_D11
DR
AM_D
12D
RAM
_D13
DR
AM_D
14D
RAM
_D15
DR
AM_D
16D
RAM
_D17
DR
AM_D
18D
RAM
_D19
DR
AM_D
20D
RAM
_D21
DR
AM_D
22D
RAM
_D23
DR
AM_D
24D
RAM
_D25
DR
AM_D
26D
RAM
_D27
DR
AM_D
28D
RAM
_D29
DR
AM_D
30D
RAM
_D31
DR
AM_C
S0D
RAM
_CS0
DR
AM_A
0D
RAM
_A0
DR
AM_A
1D
RAM
_A2
DR
AM_A
2D
RAM
_A3
DR
AM_A
3D
RAM
_A4
DR
AM_A
4D
RAM
_A5
DR
AM_A
5D
RAM
_A6
DR
AM_A
6D
RAM
_A7
DR
AM_A
7D
RAM
_A8
DR
AM_A
8D
RAM
_A9
DR
AM_A
9
DR
AM_S
DQ
S2_N
DR
AM_S
DQ
S3_P
DR
AM_S
DQ
S3_N
DR
AM_S
DQ
S0_N
DR
AM_S
DQ
S1_P
DR
AM_S
DQ
S1_N
DR
AM_S
DQ
S2_P
DR
AM_S
DQ
S0_P
DR
AM_D
QM
0D
RAM
_DQ
M0
DR
AM_Z
Q0
DR
AM_V
REF
GN
D
GN
D
GN
D
DR
AM_V
REF
GN
D
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
GN
D
P1V8
_VLD
O1
P1V2
_DD
R_S
W3
P1V2
_DD
R_S
W3
Dra
win
g Ti
tle:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
LPDD
R2
716
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
LPDD
R2
716
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
LPDD
R2
716
___
___
X
C21
20.
1UF
16V
0402
_CC
C11
10.
1UF
16V
0402
_CC
C12
50.
01uF
6.3V
0201
_CC
R41
410
K04
02_C
C
C11
40.
01uF
6.3V
0201
_CC
U1F
MC
IMX6
L8D
VN10
AA
DR
AM
_VR
EF
N5
DR
AM
_D00
AC
2
DR
AM
_D01
AC
1
DR
AM
_D02
AB
2
DR
AM
_D03
AB
1
DR
AM
_D04
AA
3
DR
AM
_D05
Y3
DR
AM
_D06
Y1
DR
AM
_D07
Y2
DR
AM
_D08
E2
DR
AM
_D09
E1
DR
AM
_D10
E3
DR
AM
_D11
D3
DR
AM
_D12
C1
DR
AM
_D13
C2
DR
AM
_D14
B1
DR
AM
_D15
B2
DR
AM
_D16
AD
8
DR
AM
_D17
AC
7
DR
AM
_D18
AD
6
DR
AM
_D19
AC
6
DR
AM
_D20
AD
5
DR
AM
_D21
AC
5
DR
AM
_D22
AC
4
DR
AM
_D23
AD
3
DR
AM
_D24
A3
DR
AM
_D25
B4
DR
AM
_D26
B5
DR
AM
_D27
A5
DR
AM
_D28
B6
DR
AM
_D29
A6
DR
AM
_D30
B7
DR
AM
_D31
A8
DR
AM
_SD
QS
3B
3
DR
AM
_SD
QS
3A
2
DR
AM
_DQ
M3
C3
DR
AM
_SD
QS
2A
C3
DR
AM
_SD
QS
2A
D2
DR
AM
_DQ
M2
AB
3
DR
AM
_A1
U5
DR
AM
_A2
T3
DR
AM
_A3
T4
DR
AM
_A4
N4
DR
AM
_A5
M3
DR
AM
_A6
M4
DR
AM
_A7
H4
DR
AM
_A8
J3
DR
AM
_A9
J4
DR
AM
_A10
J2
DR
AM
_A11
T2
DR
AM
_A12
U2
DR
AM
_A13
H5
DR
AM
_A14
R2
DR
AM
_A15
K2
ZQP
AD
H2
DR
AM
_CA
SP
1
DR
AM
_CS
0N
2
DR
AM
_CS
1L2
DR
AM
_RA
SN
1
DR
AM
_RE
SE
TD
6
DR
AM
_A0
U4
DR
AM
_SD
BA
0J1
DR
AM
_SD
BA
1T1
DR
AM
_SD
BA
2H
1
DR
AM
_SD
CLK
_0L1
DR
AM
_SD
CLK
_0M
1D
RA
M_S
DC
KE
0P
2D
RA
M_S
DO
DT0
Y4
DR
AM
_SD
CK
E1
M2
DR
AM
_SD
OD
T1E
4
DR
AM
_WE
U1
DR
AM
_SD
QS
0W
2
DR
AM
_SD
QS
0W
1
DR
AM
_DQ
M0
V2
DR
AM
_SD
QS
1F1
DR
AM
_SD
QS
1F2
DR
AM
_DQ
M1
G2
C11
20.
1UF
16V
0402
_CC
C11
50.
1UF
16V
0402
_CC
C40
822
UF
6.3V
DN
P06
03_C
C
R93
240
1%RC
0402
_25
R41
610
K04
02_C
C
C10
80.
1UF
16V
0402
_CC
R88
240
1%RC
0402
_25
C11
30.
1UF
16V
0402
_CC
C12
20.
1UF
16V
0402
_CC
C11
60.
01uF
6.3V
0201
_CC
R94
240
1%RC
0402
_25
DN
P
C12
30.
1UF
16V
0402
_CC
C12
00.
1UF
16V
0402
_CC
C11
80.
01uF
6.3V
0201
_CC
C12
60.
1UF
16V
0402
_CC
C11
90.
01uF
6.3V
0201
_CC
C12
10.
1UF
16V
0402
_CC
C10
90.
1UF
16V
0402
_CC
C11
022
UF
6.3V
0603
_CC
C21
10.
01uF
6.3V
0201
_CC
C11
722
UF
6.3V
0603
_CC
U2 MT4
2L25
6M32
D2
CK
Y1
CS
0A
B3
CS
1A
B4
CA
0A
C6
CA
1A
B6
CA
2A
C7
CA
3A
B8
CA
4A
B9
CA
5W
1
CA
6V
2
CA
7U
1
CA
8T2
CA
9T1
CK
Y2
CK
E0
AC
3
CK
E1
AC
4
DQ
S0
P22
DQ
S1
K23
DQ
S2
AC
19
DQ
S3
A19
DM
0N
23
DM
1L2
3
DM
2A
B20
DM
3B
20
VS
S1
A21
VS
S10
/NC
AC
9
VS
S11
AC
21
VS
S2
B10
VS
S3
C1
VS
S4
M2
VS
S5
M23
VS
S6
R1
VS
S7
AA
1
VS
S8
AB
11
VS
S9
AC
5
VS
SC
A1
V1
VS
SC
A2
AB
7
VS
SQ
1A
12
VS
SQ
10A
C12
VS
SQ
11A
C15
VS
SQ
12A
C18
VS
SQ
2A
15
VS
SQ
3A
18
VS
SQ
4C
23
VS
SQ
5F2
3
VS
SQ
6J2
3
VS
SQ
7P
23
VS
SQ
8U
23
VS
SQ
9Y
23
ZQP
1
NC
_A10
A10
NC
_A3
A3
NC
_A4
A4
NC
_A5
A5
NC
_A6
A6
NC
_A7
A7
NC
_A8
A8
NC
_A9
A9
NC
_AC
10A
C10
NC
_AC
11A
C11
NC
_B4
B4
NC
_B5
B5
NC
_B6
B6
NC
_B7
B7
NC
_B8
B8
NC
_B9
B9
NC
_D1
D1
NC
_D2
D2
NC
_E1
E1
NC
_E2
E2
NC
_F1
F1
NC
_F2
F2
NC
_G1
G1
NC
_G2
G2
NC
_H1
H1
NC
_H2
H2
NC
_J1
J1
NC
_J2
J2
NC
_K1
K1
NC
_K2
K2
NC
_L1
L1
NC
_L2
L2
NC
_M1
M1
NC
_N1
N1
VD
D1_
1A
11
VD
D1_
2A
20
VD
D1_
3B
3
VD
D1_
4N
2
VD
D1_
5N
22
VD
D1_
6A
B5
VD
D1_
7A
C20
VD
D2_
1B
11
VD
D2_
2B
21
VD
D2_
3C
2
VD
D2_
4L2
2
VD
D2_
5R
2
VD
D2_
6A
A2
VD
D2_
7A
B10
VD
D2_
8A
B21
VD
DQ
1B
13
VD
DQ
10A
B13
VD
DQ
11A
B16
VD
DQ
12A
B19
VD
DQ
2B
16
VD
DQ
3B
19
VD
DQ
4D
22
VD
DQ
5G
22
VD
DQ
6K
22
VD
DQ
7R
22
VD
DQ
8V
22
VD
DQ
9A
A22
VR
EFC
AP
2
VR
EFD
QM
22
VD
DC
A1
U2
VD
DC
A2
W2
VD
DC
A3
AC
8
DQ
0A
A23
DQ
1Y
22
DQ
10G
23
DQ
11F2
2
DQ
12E
22
DQ
13E
23
DQ
14D
23
DQ
15C
22
DQ
16A
B12
DQ
17A
C13
DQ
18A
B14
DQ
19A
C14
DQ
2W
22
DQ
20A
B15
DQ
21A
C16
DQ
22A
B17
DQ
23A
C17
DQ
24B
17
DQ
25A
17
DQ
26A
16
DQ
27B
15
DQ
28B
14
DQ
29A
14
DQ
3W
23
DQ
30A
13
DQ
31B
12
DQ
S0
R23
DQ
S1
J22
DQ
S2
AB
18
DQ
S3
B18
DN
U1
A1
DN
U2
A2
DN
U3
A22
DN
U4
A23
DN
U5
B1
DN
U6
B2
DN
U7
B22
DN
U8
B23
DN
U9
AB
1
DN
U10
AB
2
DN
U11
AB
22
DN
U12
AB
23
DN
U13
AC
1
DN
U14
AC
2
DN
U15
AC
22
DN
U16
AC
23
DQ
4V
23
DQ
5U
22
DQ
6T2
2
DQ
7T2
3
DQ
8H
22
DQ
9H
23
C21
30.
01uF
6.3V
0201
_CC
C12
422
UF
6.3V
0603
_CC
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 10
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
8GB
eM
MC
4-bi
t BO
OT
SD
Note: Place next to J21
SD2 - For Boot Code
8-bi
t SD
SD1 - For Primary External Card Slot
For W
iFi
usdh
c3.C
D
SD3 - for WiFi and SD Accessories
eMMC Footprint
low voltage IO cards
requires power-cycling
the card from
sd1_rst_b.
4MB SPI NOR FLASH
emm
c_vd
di
norfl
ash_
wp
SD2_
CO
N_C
LK
SD2_
CD
SD2_
WP
SD1_
CO
N_C
LK SD3_
CO
N_C
LK
sd1_
rst_
b
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
GN
D
P3V1
5_VD
DH
IGH
_SW
2P3
V15_
VDD
HIG
H_S
W2
GN
D
GN
D
VCC
_SD
1
GN
D
GN
D
GN
D
GN
D
VCC
_SD
X
VCC
_SD
XVCC
_SD
1
VCC
_SD
X
VCC
_SD
1
VCC
_SD
X
VCC
_SD
X
VCC
_SD
X
P3V1
5_VD
DH
IGH
_SW
2
VCC
_SD
X
SD2_
DAT
2(6
,8)
SD2_
DAT
1(6
,8)
SD2_
DAT
0(6
,8)
SD2_
DAT
3(6
,8)
SD2_
CLK
(6,8
)SD
2_C
MD
(6,8
)
SD2_
DAT
6(6
,8)
SD2_
DAT
7(6
,8)
ECSP
I1_S
S0(6
)
ECSP
I1_M
OSI
(6)
ECSP
I1_S
CLK
(6)
ECSP
I1_M
ISO
(6)
SD2_
DAT
1(6
,8)
SD2_
DAT
2(6
,8)
SD2_
DAT
4(6
,11)
SD2_
DAT
5(6
,11)
SD2_
DAT
0(6
,8)
SD2_
DAT
6(6
,8)
SD2_
DAT
7(6
,8)
SD2_
DAT
3(6
,8)
SD2_
CM
D(6
,8)
SD2_
CLK
(6,8
)
SD2_
RST
(6,1
1)
KEY_
RO
W7
(6,1
1)
SD1_
CLK
(6)
KEY_
CO
L7(6
,11)
SD1_
DAT
0(6
)SD
1_D
AT1
(6)
SD1_
DAT
4(6
)SD
1_D
AT3
(6)
SD1_
DAT
7(6
)
SD1_
DAT
2(6
)
SD1_
DAT
6(6
)SD
1_D
AT5
(6)
SD1_
CM
D(6
)
SD3_
CLK
(6)
SD3_
CM
D(6
)R
EF_C
LK_3
2K(6
)
SD3_
DAT
3(6
)SD
3_D
AT2
(6)
SD3_
DAT
1(6
)SD
3_D
AT0
(6)
ECSP
I2_S
CLK
(6,9
,11)
KEY_
CO
L3(6
,11)
POR
_B(4
,6,1
1,13
)
Dra
win
g Ti
tle:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
EMM
C, S
D an
d SP
I NO
R
816
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
EMM
C, S
D an
d SP
I NO
R
816
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
EMM
C, S
D an
d SP
I NO
R
816
___
___
X
R16
50
0402
_CC
DN
P
R12
410
K04
02_C
C
DN
P
U5B
SDIN
5C2-
8G_N
RN
D
DN
P
NC
_A4
A4
NC
_A6
A6
NC
_A9
A9
NC
_A11
A11
NC
_B2
B2
NC
_B13
B13
NC
_D1
D1
NC
_D14
D14
NC
_H1
H1
NC
_H2
H2
NC
_H6
H6
NC
_H7
H7
NC
_H8
H8
NC
_H9
H9
NC
_H10
H10
NC
_H11
H11
NC
_H12
H12
NC
_H13
H13
NC
_H14
H14
NC
_J1
J1
NC
_J7
J7
NC
_J8
J8
NC
_J9
J9
NC
_J10
J10
NC
_J11
J11
NC
_J12
J12
NC
_J14
J14
NC
_J13
J13
NC
_K1
K1
NC
_R1
R1
NC
_R2
R2
NC
_R3
R3
NC
_R5
R5
NC
_R12
R12
NC
_R14
R14
NC
_R13
R13
NC
_T1
T1
NC
_T2
T2
NC
_T3
T3
NC
_T5
T5
NC
_T12
T12
NC
_T13
T13
NC
_T14
T14
NC
_U1
U1
NC
_U2
U2
NC
_U3
U3
NC
_U6
U6
NC
_U7
U7
NC
_U10
U10
NC
_U12
U12
NC
_U13
U13
NC
_U14
U14
NC
_V1
V1
NC
_V2
V2
NC
_V3
V3
NC
_V12
V12
NC
_V13
V13
NC
_V14
V14
NC
_W1
W1
NC
_W2
W2
NC
_W3
W3
NC
_W7
W7
NC
_W8
W8
NC
_W9
W9
NC
_W10
W10
NC
_W11
W11
NC
_W12
W12
NC
_W13
W13
NC
_W14
W14
NC
_Y1
Y1
NC
_Y3
Y3
NC
_Y6
Y6
NC
_Y7
Y7
NC
_Y8
Y8
NC
_Y9
Y9
NC
_Y10
Y10
NC
_Y11
Y11
NC
_Y12
Y12
NC
_Y13
Y13
NC
_Y14
Y14
NC
_AA
1A
A1
NC
_AA
2A
A2
NC
_AA
7A
A7
NC
_AA
8A
A8
NC
_AA
9A
A9
NC
_AA
10A
A10
NC
_AA
11A
A11
NC
_AA
12A
A12
NC
_AA
13A
A13
NC
_AA
14A
A14
NC
_AE
1A
E1
NC
_AE
14A
E14
NC
_AG
2A
G2
NC
_AG
13A
G13
NC
_AH
4A
H4
NC
_AH
6A
H6
NC
_P12
P12
NC
_P13
P13
NC
_P10
P10
NC
_P3
P3
NC
_P2
P2
NC
_P1
P1
NC
_N14
N14
NC
_N13
N13
NC
_N12
N12
NC
_N10
N10
NC
_K3
K3
NC
_K5
K5
NC
_K7
K7
NC
_K8
K8
NC
_K9
K9
NC
_K10
K10
NC
_K11
K11
NC
_K12
K12
NC
_K13
K13
NC
_K14
K14
NC
_L1
L1
NC
_L2
L2
NC
_L3
L3
NC
_L4
L4
NC
_L12
L12
NC
_L13
L13
NC
_L14
L14
NC
_M1
M1
NC
_M2
M2
NC
_M3
M3
NC
_M5
M5
NC
_M8
M8
NC
_M9
M9
NC
_M10
M10
NC
_M12
M12
NC
_M13
M13
NC
_M14
M14
NC
_N1
N1
NC
_N2
N2
NC
_N3
N3
NC
_P14
P14
NC
_AH
9A
H9
NC
_AH
11A
H11
C12
94.
7uF
6.3V
0402
_CC
J23 C
ON
N C
RD
19
DA
T29
DA
T31
CM
D2
VS
S1
3
VD
D4
CLK
5
VS
S2
6
DA
T07
DA
T18
DA
T410
DA
T511
DA
T612
DA
T713
CD
14
GN
D1
S1
WP
15
GN
D2
S2
GN
D3
S3
GN
D4
S4
GN
D5
S5
GN
D6
S6
GN
D7
S7
R41
310
K04
02_C
C
C13
90.
1UF
16V
0402
_CC
J22 C
ON
N C
RD
19
DA
T29
DA
T31
CM
D2
VS
S1
3
VD
D4
CLK
5
VS
S2
6
DA
T07
DA
T18
DA
T410
DA
T511
DA
T612
DA
T713
CD
14
GN
D1
S1
WP
15
GN
D2
S2
GN
D3
S3
GN
D4
S4
GN
D5
S5
GN
D6
S6
GN
D7
S7
TP25
C13
10.
1UF
16V
0402
_CC
U5A
SDIN
5C2-
8G_N
RN
D
DN
P
DA
T7J6
VCCQ3K6
VCC3T10 VCC4U9
VCCQ5Y4
VCCQ4W4
VSSQ3K4
VSSQ2AA6
VCCQ2AA5
VSS3R10VSS4
U8
RE
SE
TU
5
VSS2P5
VCCQ1AA3
VSS1M7
VSSQ5Y5
VSSQ4Y2
DA
T6J5
VCC1M6 VCC2N5
CM
DW
5
VSSQ1AA4
CLK
W6
DA
T0H
3D
AT1
H4
DA
T2H
5D
AT3
J2D
AT4
J3D
AT5
J4
VDDIK2
R12
60
0402
_CC
J21 C
ON
N C
RD
19
DA
T29
DA
T31
CM
D2
VS
S1
3
VD
D4
CLK
5
VS
S2
6
DA
T07
DA
T18
DA
T410
DA
T511
DA
T612
DA
T713
CD
14
GN
D1
S1
WP
15
GN
D2
S2
GN
D3
S3
GN
D4
S4
GN
D5
S5
GN
D6
S6
GN
D7
S7
U32 NC
7SZ0
8P5
DN
P
1 24
5 3
R74
947
K
DN
P
0402
_CC
U13
M25
P32-
VMW
6TG
S1
Q2
W/V
PP
3
VS
S 4
D5
C6
HO
LD7
VC
C8
R15
30
0402
_CC
R12
20
0402
_CC
C13
00.
1UF
16V
0402
_CC
C14
647
uF
U33
FDC
6331
LD
NP
V_I
N_R
14
ON
_OFF
5
R1_
C1
6R
21
V_O
UT_
C1_
22
V_O
UT_
C1_
13
C13
30.
1UF
16V
0402
_CC
C15
80.
1UF
16V
0402
_CC
R17
50
0402
_CC
R11
510
K04
02_C
C
DN
P
C14
40.
1UF
16V
0402
_CC
C16
310
uF
10V
C13
70.
1UF
16V
0402
_CC
SH11
SOLD
ER S
HO
RT
SH08
05_4
0
C13
64.
7uF
6.3V
0402
_CC
C86
1.0U
F10
V
R12
510
K04
02_C
C
C13
40.
1UF
16V
0402
_CC
C14
510
uF
10V
C13
24.
7uF
6.3V
0402
_CC
R16
60
0402
_CC
DN
P
R12
310
K04
02_C
C
C13
810
uF
10V
R38
01.
0K
1%
C13
50.
1UF
16V
0402
_CC
R12
10
0402
_CC
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 11
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
USB Boot/Debug
Micro USB-AB Receptacle
USBOTG1_ID
Layo
ut:
Rou
te 9
0oh
m D
IFF
Layo
ut:
Rou
te 9
0oh
m D
IFF
USB Host Port
USB Boot/Host/Device Port
USB 5V Control
usbo
tg2_
oc
usbo
tg1_
oc
usbo
tg2_
pwr
host
usb_
c_d_
N
host
usb_
c_d_
P
otgu
sb_c
_d_N
otgu
sb_c
_d_P
host
usb_
c_d_
Nho
stus
b_c_
d_P
otgu
sb_c
_d_P
otgu
sb_c
_d_N
otg_
usb_
id
usbo
tg1_
pwr
otg_
usb_
id
GN
D
GN
D
GN
D
USB
_5V_
HO
ST
GN
DG
ND
USB
_5V_
OTG
USB
_5V_
HO
STG
ND
USB
_5V_
OTG
SYS_
5V
GN
D
GN
D
P3V1
5_VD
DH
IGH
_SW
2
KEY_
CO
L4(6
,11)
KEY_
CO
L5(6
,11)
USB
_Hos
t_D
_N(6
)
USB
_Hos
t_D
_P(6
)
USB
_Hos
t_VB
US
(6)
USB
_OTG
1_D
_N(6
)
USB
_OTG
1_D
_P(6
)
EPD
C_P
WR
CO
M(6
,11)
USB
_OTG
1_VB
US
(6)
KEY_
RO
W4
(6,1
1)
ECSP
I2_S
CLK
(6,8
,11)
Dra
win
g Ti
tle:
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eet
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Titl
e:
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ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
USB
916
___
___
XD
raw
ing
Title
:
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umen
t Num
ber
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e:Sh
eet
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Titl
e:
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ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
USB
916
___
___
XD
raw
ing
Title
:
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umen
t Num
ber
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Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
USB
916
___
___
X
L11
120O
HM
0603
_CC2
1
R18
947
K
DN
P
0402
_CC
D14
ESD
9L5.
0ST5
G
AC
R18
20
0402
_CC
L15
90O
HM
21 4
3
+C
150
150
UF
10V
DN
PC
C73
43A
C15
40.
1UF
16V
0402
_CCL1
0
120O
HM
0603
_CC2
1R
179
330
0402
_CC
R19
047
K
DN
P
0402
_CC
C15
510
uF
10V
R19
747
K04
02_C
C
U18
SRV0
5-4
4
25
316
R19
10
0402
_CC
R19
30
0402
_CC
C14
910
uF
10V
C15
22.
2uF
16V
CC
0603
U19
MIC
2026
-1YM
EN
A1
FLG
A2
FLG
B3
EN
B4
OU
TB5
GN
D6
IN7
OU
TA8
C15
32.
2uF
16V
CC
0603
C14
810
uF
10V
R19
20
0402
_CC
R19
40
0402
_CC
L14
90O
HM
21 4
3
5VD-
D+ID
G
MIC
RO
USB
AB
5J9
1
2
3
4
S2
5
S1
S3
S4
U17
SRV0
5-4
4
25
316
R19
847
K04
02_C
C
C15
12.
2uF
16V
CC
0603
VD-
D+G
USB
_TYP
E_A
J10
S1
A1
A2
A3
A4
S2
R17
833
004
02_C
C
D13
ESD
9L5.
0ST5
G
AC
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 12
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
HeadPhone
Speaker
Out
Layout note:
Zobel Networks(c216,c217,r771,r772) close to WM8962
layout note:
the positioning of C374 is very important
should be as close to the WM8962 as possible.
layout note:
Widen the trace SPKVDD
Max ~0.6A
HP_DET
Audio CODEC
or WM-63PR
or CMC-2242PBL-A
When bypassing the I2C level shifter you must :
- change the DBVDD supply voltage to 3V15
- change the MX6SL IO pin supply voltage for
all the codec digital pins
- I2C2_SCL, & SDA
- AUD_TXC, TXFS, TXD, RDX, & MCLK
If you do not have any other devices at
greater than 1.8V on the I2C bus, you can set
the powers to 1.8V and bypass the level
shifter. You will need to remove the 3V15
pull-ups on sheet 6 (R86 and R87).
HPO
UTR
HPO
UTL
MIC
VDD
MIC
BIAS
code
c_i2
c_sd
aco
dec_
i2c_
scl
code
c_vm
idc
CPV
OU
TPC
PVO
UTN
CPC
B
CPC
A
SPKO
UTR
NSP
KOU
TRP
SPKO
UTL
PSP
KOU
TLN
HPO
UTR
MIC
BIAS
HPO
UTL
HPOUTL_ZOBEL
HPOUTR_ZOBEL
A_C
OD
EC_1
V8
SPKO
UTL
P
SPKO
UTR
PSP
KOU
TLN
SPKO
UTR
N
IN3R
I2C
2_SC
L
I2C
2_SD
A
I2C
2_SC
L
I2C
2_SD
A
MEC
H
SPKV
DD
CO
DEC
_1V8
CO
DEC
_3V1
5
GN
D
CO
DEC
_1V8
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
D
CO
DEC
_3V1
5
PF01
00_V
IN
GN
D
GN
D
CO
DEC
_3V1
5
GN
DG
ND
CO
DEC
_1V8
CO
DEC
_3V1
5C
OD
EC_1
V8
CO
DEC
_1V8
P1V8
_VLD
O1
P3V1
5_VD
DH
IGH
_SW
2
AUD
_MC
LK(6
)
AUD
_TXD
(6)
AUD
_RXD
(6)
AUD
_TXC
(6)
AUD
_TXF
S(6
)
FEC
_RX_
ER(6
)
I2C
2_SC
L(6
,11)
I2C
2_SD
A(6
,11)
Dra
win
g Ti
tle:
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umen
t Num
ber
Rev
Dat
e:Sh
eet
of
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Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
Audi
o
1016
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
Audi
o
1016
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
Audi
o
1016
___
___
X
C37
42.
2uF
16V
CC
0603
C16
61.
0UF
10V
R72
02.
2K04
02_C
C
L17
120O
HM
0603
_CC2
1
C17
40.
1UF
16V
0402
_CC
R78
1
1.0K
1%DN
P
L19
120O
HM
0603
_CC
21
C14
7
1.0U
F10
V
R20
410
K04
02_C
C
DN
P
R20
710
K04
02_C
C
R21
60
0402
_CC
DN
P
R78
2
1.0K
1%DN
P
C15
61.
0UF
10V
SH16
SOLD
ER S
HO
RT
SH08
05_4
0
C21
70.
1UF
16V
0402
_CC
C15
94.
7uF
0603
_CC
10V
L18
120O
HM
0603
_CC
21
R20
610
K04
02_C
C
DN
P
C16
04.
7uF
0603
_CC
10V
R20
510
K04
02_C
C
DN
PR
772
20 RC
0603
R21
50
0402
_CC
DN
P
U34
TXS0
102
OE
6B
21
B1
8
VCCB7
VCCA3
A1
5
A2
4
GND2
OU
T
GN
D
P4 WM
-64P
CT
21
R77
120 R
C06
03
C15
74.
7uF
6.3V
0402
_CC
R77
90
0603
_CC
DN
P
SH15
SOLD
ER S
HO
RT
SH08
05_4
0
C37
62.
2uF
16V
CC
0603
C16
44.
7uF
6.3V
0402
_CC
CO
N50
0
SM04
B-SR
SS-T
B
44
33
22
11
SID
E1
5
SID
E2
6
C21
60.
1UF
16V
0402
_CC
R78
00
0603
_CC
C40
60.
22U
F
6.3V
0201
_CC
C16
14.
7uF
6.3V
0402
_CC
J130
Audi
o Ja
ck
6 514
C21
50.
1UF
16V
0402
_CC
U6
WM
8962
AV
DD
D6
DC
VD
DG
2
DB
VD
DG
3
CP
VD
DC
6
SP
KV
DD
1A
2
SP
KV
DD
2C
2
MIC
VD
DA
3
PLL
VD
DG
4
IN1L
C4
IN1R
D4
IN2L
D5
IN2R
E5
IN3L
F5
IN3R
F6
IN4L
E6
IN4R
E7
SC
LKF1
SD
AE
2
CIF
MO
DE
F2
BC
LKE
1
LRC
LKD
3
DA
CD
AT
D1
AD
CD
AT
D2
MC
LK/X
TIG
7
XTO
F7
AG
ND
D7
DG
ND
F3
CP
GN
DC
7
SP
KG
ND
1B
1
SP
KG
ND
2C
1
PLL
GN
DG
5
HP
OU
TLB
5
HP
OU
TRA
5
HP
OU
TFB
B4
SP
KO
UTL
NB
3
SP
KO
UTL
PA
1
SP
KO
UTR
NC
3
SP
KO
UTR
PB
2
CP
CA
B6
CP
CB
B7
CP
VO
UTN
A7
CP
VO
UTP
A6
CLK
OU
T2/G
PIO
2E
4
CLK
OU
T3/G
PIO
3F4
GP
IO5
G1
CS
/GP
IO6
E3
CLK
OU
T5G
6
VM
IDC
C5
MIC
BIA
SA
4
C16
54.
7uF
6.3V
0402
_CC
C40
70.
22U
F
6.3V
0201
_CC
C16
24.
7uF
6.3V
0402
_CC
CO
N4
HD
R 1
X4D
NP
1234
C37
52.
2uF
16V
CC
0603
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 13
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
The camera connector (J24) and the EPDC
connector (J12) share the same signals and
CANNOT be used at the same time.
One of these two peripherals MUST BE REMOVED
when a developer wishes to use the other.
Imp
orta
nt
Not
e:
GPIO
GPIO
CAP_TOUCH_INT
51EXP_csi_D0
51EXP_csi_D1
51EXP_csi_D2
51EXP_csi_D3
51EXP_csi_D4
51EXP_csi_D5
51EXP_csi_D6
51EXP_csi_D7
51EXP_csi_D8
51EXP_csi_D9
51EXP_csi_MCLK
51EXP_csi_PIXCLK
51EXP_csi_HSYNC
51EXP_csi_VSYNC
hdmi_spdif_out
51EXP_GPIO
51EXP_CAM_PWDN
51EXP_RESET
hdmi_card_int
lcd_display_clk
lcdif.WR_RWN
lcdif.RD_E
lcdif.CS
lcdif.RS
lcd_pwr_en
CAP_TOUCH_RST
3_AXIS_INT
I2C3_SDA
I2C3_SCL
CMOS_RESET_B
CSI_PIXCLK
CSI_VSYNC
CSI_HSYNC
CMOS_PWDN
CSI_D9
CSI_D8
CSI_D7
CSI_D6
CSI_D5
CSI_D4
CSI_D3
CSI_D2
CSI_D1
CSI_D0
Layout Note: Place next to J12
COMS_DVDD
CMOS_XCLK
51EXP_spdif_out
EPDC Expansion Port
LCD Expansion Port
Camera Expansion Connector
Use Omnivision OV5642 5M Pixel
Sensor with this connector
(not included)
51EX
P_ua
rt2_R
X
epd_
i2c_
scl
epd_
i2c_
sda
EPD
_TO
UC
H_X
1EP
D_T
OU
CH
_Y0
EPD
_TO
UC
H_X
0
EPD
_TO
UC
H_Y
1
uart2
_RXD
uart2
_TXD
lcd_
spi_
sclk
spdi
f_ou
t
spdi
f_in
VCM
SIN
KC
OM
S_AV
DD
51EX
P_ua
rt2_T
X
51EX
P_i2
c_sd
a
lcd_
i2c_
scl
lcd_
i2c_
sda
lcd_
brig
htne
ss_c
tlep
d_br
ight
ness
_ctl
AF_V
CC
51EX
P_i2
c_sc
l
lcd_
int
GN
DG
ND
GN
DG
ND
GN
D
GN
DG
ND
GN
DG
ND
GN
D
AF_G
ND
CM
OS_
AGN
D
CM
OS_
AGN
DAF
_GN
DG
ND
GN
D
SYS_
5V
SYS_
5V
PF01
00_V
IN
PF01
00_V
IN
SYS_
5V
SYS_
5V
SYS_
5V
PF01
00_V
IN
PF01
00_V
IN
SYS_
5V
P1V8
_VG
EN4 P2
V8_V
GEN
6
P2V8
_VG
EN6
P1V5
_VG
EN2
P1V8
_VG
EN4
P1V5
_VG
EN2
P1V8
_VG
EN4
P3V1
5_VD
DH
IGH
_SW
2P3
V15_
VDD
HIG
H_S
W2
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2 P1V5
_VG
EN2
LCD
_VSY
NC
(6,1
1)
LCD
_DAT
9(6
,13)
LCD
_DAT
2(6
,13)
LCD
_DAT
8(6
,13)
LCD
_EN
ABLE
(6,1
1)
LCD
_DAT
0(6
,13)
LCD
_DAT
1(6
,13)
LCD
_DAT
7(6
,13)
LCD
_DAT
5(6
,13)
LCD
_DAT
6(6
,13)
LCD
_DAT
3(6
,13)
LCD
_DAT
4(6
,13)
PWM
1(6
,11)
LCD
_DAT
12(6
,13)
LCD
_DAT
13(6
,13)
LCD
_DAT
14(6
,13)
LCD
_DAT
10(6
,13)
LCD
_DAT
11(6
,13)
LCD
_DAT
15(6
,13)
LCD
_DAT
17(6
,13)
LCD
_DAT
18(6
,13)
EPD
C_D
1(6
,11)
EPD
C_D
2(6
,11)
EPD
C_D
3(6
,11)
EPD
C_D
4(6
,11)
EPD
C_D
5(6
,11)
EPD
C_D
6(6
,11)
EPD
C_D
7(6
,11)
EPD
C_G
DSP
(6,1
1)EP
DC
_GD
OE
(6,1
1)
EPD
C_G
DC
LK(6
,11)
EPD
C_G
DR
L(6
,11)
EPD
C_S
DC
LK(6
,11)
EPD
C_S
DO
E(6
,11)
EPD
C_S
DLE
(6,1
1)
EPD
C_S
DSH
R(6
,11)
EPD
C_S
DC
E0(6
)EP
DC
_SD
CE1
(6)
EPD
C_P
WR
CO
M(6
,9)
EPD
C_P
WR
STAT
(6)
EPD
C_P
WR
CTR
L0(6
)EP
DC
_PW
RC
TRL1
(6)
EPD
C_P
WR
CTR
L2(6
)
EPD
C_S
DC
E3(6
,11)
LCD
_DAT
16(6
,13)
LCD
_DAT
21(6
,13)
LCD
_DAT
22(6
,13)
LCD
_DAT
23(6
,13)
LCD
_DAT
19(6
,13)
LCD
_DAT
20(6
,13)
EPD
C_B
DR
1(6
)EP
DC
_BD
R0
(6)
EPD
C_S
DC
E2(6
,11)
I2C
1_SC
L(4
,6)
I2C
1_SD
A(4
,6)
EPD
C_S
DC
LK(6
,11)
EPD
C_G
DR
L(6
,11)
SD2_
DAT
4(6
,8,1
1)SD
2_D
AT5
(6,8
,11)
I2C
2_SD
A(6
,10,
11)
I2C
2_SC
L(6
,10,
11)
KEY_
RO
W6
(6)
KEY_
CO
L6(6
)
KEY_
RO
W3
(6,1
1)
EPD
C_P
WR
WAK
EUP
(6)
KEY_
RO
W2
(6,1
1,12
)EP
DC
_PW
RIN
T(6
)
EPD
C_D
11(6
)
EPD
C_D
9(6
)
EPD
C_D
8(6
)
EPD
C_D
0(6
,11)
KEY_
RO
W0
(6,1
1,12
)KE
Y_R
OW
1(6
,11,
12)
EPD
C_V
CO
M0
(6)
EPD
C_V
CO
M1
(6)
EPD
C_D
10(6
)EP
DC
_D12
(6) EP
DC
_D13
(6)
EPD
C_D
14(6
)EP
DC
_D15
(6) EP
DC
_PW
RC
TRL3
(6,1
1)
LCD
_CLK
(6,1
1)
LCD
_RES
ET(6
)I2
C2_
SCL
(6,1
0,11
)I2
C2_
SDA
(6,1
0,11
)
ECSP
I2_M
ISO
(3,6
)EC
SPI2
_MO
SI(3
,6)
ECSP
I2_S
CLK
(6,8
,9)
SD2_
DAT
4(6
,8,1
1)
EPD
C_P
WR
CTR
L3(6
,11)
KEY_
RO
W5
(6)
ECSP
I2_S
S0(3
,6)
SD2_
DAT
5(6
,8,1
1)
I2C
2_SC
L(6
,10,
11)
I2C
2_SD
A(6
,10,
11)
SD2_
RST
(6,8
)
KEY_
RO
W2
(6,1
1,12
)
KEY_
RO
W1
(6,1
1,12
)
KEY_
RO
W0
(6,1
1,12
)
KEY_
RO
W3
(6,1
1)KE
Y_C
OL0
(6,1
1,12
)
KEY_
CO
L1(6
,11,
12)
KEY_
CO
L2(6
,11,
12)
KEY_
CO
L3(6
,8,1
1)
PWM
1(6
,11)
KEY_
CO
L0(6
,11,
12)
KEY_
CO
L2(6
,11,
12)
KEY_
CO
L3(6
,8,1
1)
KEY_
CO
L1(6
,11,
12)
LCD
_HSY
NC
(6,1
1)LC
D_C
LK(6
,11)
LCD
_EN
ABLE
(6,1
1)
LCD
_HSY
NC
(6,1
1)
LCD
_VSY
NC
(6,1
1)
EPD
C_D
1(6
,11)
EPD
C_D
0(6
,11)
EPD
C_G
DC
LK(6
,11)
EPD
C_G
DO
E(6
,11)
EPD
C_G
DSP
(6,1
1)
EPD
C_S
DC
E2(6
,11)
EPD
C_S
DC
E3(6
,11)
EPD
C_S
DLE
(6,1
1)EP
DC
_SD
OE
(6,1
1)
EPD
C_D
7(6
,11)
EPD
C_S
DC
LK(6
,11)
EPD
C_S
DSH
R(6
,11)
EPD
C_D
5(6
,11)
EPD
C_D
6(6
,11)
EPD
C_D
3(6
,11)
EPD
C_D
4(6
,11)
EPD
C_D
2(6
,11)
KEY_
RO
W4
(6,9
)
KEY_
RO
W7
(6,8
)
KEY_
CO
L4(6
,9)
KEY_
CO
L5(6
,9)
KEY_
CO
L7(6
,8)
POR
_B(4
,6,8
,13)
Dra
win
g Ti
tle:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
Vide
o
1116
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
Vide
o
1116
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
Vide
o
1116
___
___
X
J24
CO
NN
PLU
G 4
0
383430262218141062 403632282420161284
4142
4344
45
46
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
TP29
R25
10
0402
_CC
DN
P
R22
60
0402
_CC
L20
120O
HM
0603
_CC2
1
R26
00
0402
_CC
C17
64.
7uF
6.3V
0402
_CC
TP31
R24
10
0402
_CC
R24
40
0402
_CC
R23
80
0402
_CC
DN
P
R25
733
0402
_CC
TP30
R24
60
0402
_CC
DN
P
R23
20
0402
_CC
DN
P
L21
120O
HM
0603
_CC2
1
R24
50
0402
_CC
R25
30
0402
_CC
DN
P
R23
10
0402
_CC
TP33
R24
80
0402
_CC
R26
10
0402
_CC
R22
70
0402
_CC
R26
40
0402
_CC
R24
90
0402
_CC
DN
P
J13
QSH
-060
-01-
L-D
-A
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
SH
1S
H2
SH
3S
H4
SH
5S
H6
SH
7S
H8
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
8182
8384
8586
8788
8990
9192
9394
9596
9798
9910
010
110
210
310
410
510
610
710
810
911
011
111
211
311
411
511
611
711
811
912
0
R25
50
0402
_CC
DN
PR
247
004
02_C
C
R26
80
0402
_CC
DN
P
TP35
R26
70
0402
_CC
DN
P
TP39
C17
90.
1UF
16V
0402
_CC
L22
120O
HM
0603
_CC2
1
R23
70
0402
_CC
R22
50
0402
_CC
R23
60
0402
_CC
C17
81.
0UF
10V
TP37
R22
90
0402
_CC
R24
00
0402
_CC
DN
P
R23
00
0402
_CC
J12
QSH
-060
-01-
L-D
-A
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
SH
1S
H2
SH
3S
H4
SH
5S
H6
SH
7S
H8
6162
6364
6566
6768
6970
7172
7374
7576
7778
7980
8182
8384
8586
8788
8990
9192
9394
9596
9798
9910
010
110
210
310
410
510
610
710
810
911
011
111
211
311
411
511
611
711
811
912
0
R27
010
K04
02_C
CD
NP
TP40
C17
50.
1UF
16V
0402
_CC
R23
50
0402
_CC
DN
P
TP41
R24
30
0402
_CC
DN
PR
239
004
02_C
CD
NP
R24
20
0402
_CC
R25
20
0402
_CC
C17
70.
1UF
16V
0402
_CC
R89
1.0K 1%
DN
P
R22
80
0402
_CC
R25
00
0402
_CC
DN
P
R23
40
0402
_CC
R23
30
0402
_CC
DN
P
R25
90
0402
_CC
DN
P
R26
30
0402
_CC
DN
P
R26
50
0402
_CC
DN
P
R25
40
0402
_CC
R90
1.0K 1% DN
PR
272
004
02_C
C
R26
20
0402
_CC
R26
60
0402
_CC
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 14
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
3GCA
RD_O
N3G
CARD
_RST
Mini-PCIe HMC (3G Modem)
Button Matrix
Layo
ut:
Rou
te 9
0oh
m D
IFF
MMPF0100's SW2 capacitive load recommendation is
<500uF total. Do not populate C140, C191, C192 and C210
3GC
AR
D_P
WR
SIM
_IO
SIM
_CLK
SIM
_RE
SE
TS
IM_V
PP
SIM
_VC
C
SIM
_VP
PS
IM_I
O3G
CA
RD
_PW
RS
IM_C
LKS
IM_R
ES
ET
SIM
_VC
C
GN
DG
ND
GN
D
GN
D
P3V
15_V
DD
HIG
H_S
W2
AU
D_R
XFS
(6)
AU
D_R
XC
(6)
KE
Y_R
OW
0(6
,11)
KE
Y_R
OW
1(6
,11)
KE
Y_R
OW
2(6
,11)
KE
Y_C
OL0
(6,1
1)
KE
Y_C
OL1
(6,1
1)
KE
Y_C
OL2
(6,1
1)
PC
IE_U
SB
_Hos
t_D
_P(6
)P
CIE
_US
B_H
ost_
D_N
(6)
Dra
win
g Ti
tle:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
7452
PD
F: S
PF-
2745
2B
MC
IMX6
SLEV
K b
oard
B
Mon
day,
Mar
ch 3
0, 2
015
Wire
less
1216
___
___
XD
raw
ing
Title
:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
7452
PD
F: S
PF-
2745
2B
MC
IMX6
SLEV
K b
oard
B
Mon
day,
Mar
ch 3
0, 2
015
Wire
less
1216
___
___
XD
raw
ing
Title
:
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Pag
e Ti
tle:
ICA
P C
lass
ifica
tion:
FCP
:FI
UO
:P
UB
I:
SC
H-2
7452
PD
F: S
PF-
2745
2B
MC
IMX6
SLEV
K b
oard
B
Mon
day,
Mar
ch 3
0, 2
015
Wire
less
1216
___
___
X
C18
20.
1UF
16V
0402
_CC
SW
13
SP
ST
PB
13 4
2
TP44
SW
10
SP
ST
PB
13 4
2
TP42
C18
30.
1UF
16V
0402
_CC
R30
547
K
DN
P
0402
_CC
D18
LED
Red
AC
C21
010
0UF
10V
CC
1210
DN
PJ8 C
ON
2X
26 M
INI P
CI E
XP
RE
SS
WA
KE
#1
Res
erve
d13
Res
erve
d25
CLK
RE
Q#
7
GN
D1
9
RE
FCLK
-11
RE
FCLK
+13
GN
D2
15
Res
erve
d/U
IM_C
817
Res
erve
d/U
IM_C
419
GN
D3
21
PE
Rn0
23
PE
Rp0
25
GN
D4
27
GN
D5
29
PE
Tn0
31
PE
Tp0
33
GN
D6
35
Res
erve
d337
Res
erve
d439
Res
erve
d541
Res
erve
d643
Res
erve
d745
Res
erve
d847
Res
erve
d949
Res
erve
d10
51
3.3V
_12
GN
D7
4
1.5V
_16
UIM
_PW
R8
UIM
_DA
TA10
UIM
_CLK
12
UIM
_RE
SE
T14
UIM
_VP
P16
GN
D8
18
W_D
ISA
BLE
#20
PE
RS
T#22
+3.3
Vau
x24
GN
D9
26
1.5V
_228
SM
B_C
LK30
SM
B_D
ATA
32
GN
D10
34
US
B_D
-36
US
B_D
+38
GN
D11
40
LED
_WW
AN
#42
LED
_WLA
N#
44
LED
_WP
AN
#46
1.5V
_348
GN
D12
50
3.3V
_252
SW
8
SP
ST
PB
13 4
2
C18
40.
1UF
16V
0402
_CC
SW
9
SP
ST
PB
13 4
2
SW
11
SP
ST
PB
13 4
2
R30
933
004
02_C
C
SW
6
SP
ST
PB
13 4
2
C18
110
0UF
10V
CC
1210
C14
04.
7uF
6.3V
0402
_CC
DN
P
R30
647
K
DN
P
0402
_CC
J133
CO
N 6
SIM
CA
RD
VC
C1
RE
SE
T2
CLK
3
GN
D4
VP
P5
I/O6
SW
12
SP
ST
PB
13 4
2
TP45
J18
HD
R 1
X2
12
SW
7
SP
ST
PB
13 4
2
C19
110
0UF
10V
CC
1210
DN
P
C19
210
0UF
10V
CC
1210
DN
P
TP43
C18
010
0UF
10V
CC
1210
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 15
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Bus isolation
Boot Strap
Power Control
Use non metalic or non conducting standoff to avoid board
damage due to GND potential difference with chasis.
IMPORTANT NOTE :
GN
D T
EST
PO
INTS
Boot Strap
Note:
i.MX6SL reads values approximately
300uS to 1mS after reset released.
Buffers are active while unit is in
reset and 1ms-10ms after reset is
released.
Boot Strap Primary Switches
Boa
rd M
ount
ing
Hol
es fo
r 4-4
0 Sc
rew
s
BT_C
FG2
BT_C
FG3
BT_C
FG6
BT_C
FG7
BT_C
FG4
BT_C
FG5
BT_C
FG10
BT_C
FG11
BT_C
FG14
BT_C
FG15
BT_C
FG12
BT_C
FG13
BT_C
FG8
BT_C
FG9
BT_C
FG0
BT_C
FG1
BT_C
FG24
BT_C
FG25
BT_C
FG26
BT_C
FG27
BT_C
FG28
BT_C
FG29
BT_C
FG30
BT_C
FG31
outp
ut_p
ulse
BT_C
FG_E
N
BT_C
FG_E
N
GN
D
GN
D
GN
D
GN
D
GN
DG
ND
GN
D
VCC
_BT_
CFG
_OE
VCC
_BT_
CFG
_OE
VCC
_BT_
CFG
_OE
VCC
_BT_
CFG
_OE
VCC
_BT_
CFG
_OE
GN
D
VCC
_Boo
tStra
p
GN
D
VCC
_BT_
CFG
_OE
VCC
_BT_
CFG
_OE
GN
D
GN
D
VCC
_Boo
tStra
p
VCC
_BT_
CFG
_OE
VCC
_BT_
CFG
_OE
GN
DG
ND
GN
DG
ND
P3V1
5_VD
DH
IGH
_SW
2
LCD
_DAT
0(6
,11)
LCD
_DAT
1(6
,11)
LCD
_DAT
2(6
,11)
LCD
_DAT
3(6
,11)
LCD
_DAT
4(6
,11)
LCD
_DAT
5(6
,11)
LCD
_DAT
6(6
,11)
LCD
_DAT
7(6
,11)
LCD
_DAT
8(6
,11)
LCD
_DAT
9(6
,11)
LCD
_DAT
10(6
,11)
LCD
_DAT
11(6
,11)
LCD
_DAT
12(6
,11)
LCD
_DAT
13(6
,11)
LCD
_DAT
14(6
,11)
LCD
_DAT
15(6
,11)
LCD
_DAT
16(6
,11)
LCD
_DAT
17(6
,11)
LCD
_DAT
18(6
,11)
LCD
_DAT
19(6
,11)
LCD
_DAT
20(6
,11)
LCD
_DAT
21(6
,11)
LCD
_DAT
22(6
,11)
LCD
_DAT
23(6
,11)
POR
_B(4
,6,8
,11)
BOO
T_M
OD
E0(6
)BO
OT_
MO
DE1
(6)
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BI:
SCH
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49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
MIS
C
1316
___
___
XD
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ing
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:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
MIS
C
1316
___
___
XD
raw
ing
Title
:
Size
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umen
t Num
ber
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Dat
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eet
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Titl
e:
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catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
MIS
C
1316
___
___
X
TP66
R35
74.
7K04
02_C
C
H3
.635
" LO
NG
DN
P
TP72
R31
11.
0K
1%
SW3
SW D
IP-8
12345678
161514131211109
R35
44.
7K04
02_C
C
R33
14.
7K04
02_C
C
C18
70.
1UF
16V
0402
_CC
U21
74LV
C24
4APW
1A0
2
1A1
4
1A2
6
1A3
8
2A3
112A
213
2A1
152A
017
1OE
1
2OE
19
1Y0
18
1Y1
16
1Y2
14
1Y3
12
2Y3
92Y
27
2Y1
52Y
03
VC
C20
GN
D10
R31
820
K04
02_C
C
R33
520
K04
02_C
C
R35
54.
7K04
02_C
C
U24
74LV
C24
4APW
1A0
2
1A1
4
1A2
6
1A3
8
2A3
112A
213
2A1
152A
017
1OE
1
2OE
19
1Y0
18
1Y1
16
1Y2
14
1Y3
12
2Y3
92Y
27
2Y1
52Y
03
VC
C20
GN
D10
R31
01.
0K
1%
R32
74.
7K04
02_C
C
R36
14.
7K04
02_C
C
R41
006
03_C
C
R31
920
K04
02_C
C
R33
620
K04
02_C
C
R34
04.
7K04
02_C
C
R32
94.
7K04
02_C
C
R35
220
K04
02_C
C
R36
54.
7K04
02_C
C
R42
006
03_C
C
R35
94.
7K04
02_C
C
R32
020
K04
02_C
C
R34
120
K04
02_C
C
SW5
SW D
IP-8
12345678
161514131211109
R33
74.
7K04
02_C
C
TP71
R35
320
K04
02_C
C
U23
74LV
C24
4APW
1A0
2
1A1
4
1A2
6
1A3
8
2A3
112A
213
2A1
152A
017
1OE
1
2OE
19
1Y0
18
1Y1
16
1Y2
14
1Y3
12
2Y3
92Y
27
2Y1
52Y
03
VC
C20
GN
D10
R32
34.
7K04
02_C
CR
324
20K
0402
_CC
C18
50.
1UF
16V
0402
_CC
R33
34.
7K04
02_C
C
R33
920
K04
02_C
C
R72
10
0402
_CC
TP70
R36
74.
7K04
02_C
C
R33
84.
7K04
02_C
C
R35
820
K04
02_C
C
R34
320
K04
02_C
C
S1 SW_D
IP-2
/SM
1 24 3
R36
34.
7K04
02_C
C
R32
620
K04
02_C
C
C18
60.
1UF
16V
0402
_CC
R32
14.
7K04
02_C
C
R34
84.
7K04
02_C
C
R35
620
K04
02_C
C
R34
24.
7K04
02_C
C
H4
.635
" LO
NG
DN
P
R34
520
K04
02_C
C
R32
820
K04
02_C
C
SW4
SW D
IP-8
12345678
161514131211109
R34
44.
7K04
02_C
C
R36
020
K04
02_C
C
R44
0
0603
_CC
DN
P
R34
720
K04
02_C
C
R32
24.
7K04
02_C
C
TP65
R33
020
K04
02_C
C
R72
247
K04
02_C
C
VCC GND
2Y1Y1A 1G 2A 2GU
31
SN74
LVC
2G12
5
6 3
2 71 5
48
R34
64.
7K04
02_C
C
R36
220
K04
02_C
C
TP67
C21
81.
0UF
10V
R47
0
0603
_CC
H2
.635
" LO
NG
DN
P
R34
920
K04
02_C
C
R33
220
K04
02_C
C
R36
420
K04
02_C
C
R32
54.
7K04
02_C
C
TP68
H1
.635
" LO
NG
DN
P
R35
04.
7K04
02_C
C
TP69
R36
620
K04
02_C
C
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 16
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Layout note:
90ohm diff pairs
For driver installation, please refer to
http://www.ftdichip.com/Documents/InstallGuides.htm
JTAG_PWR
Debug UART2USB Converter
JTAG
Debug LED
led7
_2
led7
_3
J_D
BGAC
K
JTAG
_RTC
K
J_D
E_B
VTR
EF_J
TAG
led7
_1
rx23
2tx
232
debu
g_ua
rt_en
tx_l
edrx
_led
led8
led9
ftdi_
3v3o
ut
DEB
UG
_SH
L_G
ND
debu
g_us
b_5v
debu
g_us
b_d_
N
debu
g_us
b_d_
P
ftdi_
rese
t
debu
g_5v
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
P3V1
5_VD
DH
IGH
_SW
2
UAR
T1_T
XD(6
)
UAR
T1_R
XD(6
)
JTAG
_MO
D(6
)JTAG
_TR
STB
(6)
JTAG
_TD
I(6
)JT
AG_T
MS
(6)
JTAG
_TC
K(6
)
JTAG
_TD
O(6
)JT
AG_n
SRST
(6)
HSI
C_S
TRO
BE_G
PIO
(6)
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SCH
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49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
UART
& J
TAG
1416
___
___
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ing
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umen
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Titl
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ssifi
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P:FI
UO
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BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
UART
& J
TAG
1416
___
___
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ing
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SCH
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49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
UART
& J
TAG
1416
___
___
X
R39
910
K04
02_C
C
DN
P
D23
LED
Gre
en
A C
R37
510
K04
02_C
C
R39
010
K04
02_C
C
DN
P
R40
910
004
02_C
C1%
R39
810
K04
02_C
C
R38
91.
0K
1%J7 TS
T-11
0-05
-T-D
-RA
12
34
56
78
910
1112
1314
1516
1718
1920
R40
04.
7K04
02_C
C
C20
01.
0UF
10V
U27
SN74
LVC
2G12
6
1Y6
GN
D
4
2Y3
1A2
1OE
1V
CC8
2OE
7
2A5
R38
810
K04
02_C
C
DN
P
C20
60.
1UF
16V
0402
_CC
R38
610
K04
02_C
C
C19
94.
7uF
6.3V
0402
_CC
Q5
MM
BT39
04
23
1
R39
110
K04
02_C
C
DN
P
R39
710
K04
02_C
C
R39
610
K04
02_C
C
R39
510
K04
02_C
C
R39
210
004
02_C
C1%
L23
120O
HM
0603
_CC2
1
D22
LED
Gre
en
A C
5VD-
D+ID
G
MIC
RO
USB
AB
5J2
6
1
2
3
4
S2
5
S1
S3
S4
R37
81.
0K
1%
C20
90.
1UF
16V
0402
_CC
D21
LED
Red
A C
R38
710
K04
02_C
C
U28
FT23
2RQ
GND14
AGND24
RI#
3D
CD
#7
DS
R#
6D
TR#
31
3V3O
UT
16
VC
CIO
1
OS
CI
27R
ES
ET#
18
NC
623
OS
CO
28
CB
US
49
CB
US
311
CB
US
121
CB
US
022
CB
US
210
NC
529
NC
425
NC
313
NC
212
NC
15
US
BD
P14
US
BD
M15
VC
C19
GND420
GND217
TEST26
CTS
#8
RTS
#32
RX
D2
TXD
30
EP33
R38
110
K04
02_C
C
R39
433
004
02_C
C
R37
71.
0K
1%
TP75
TP76
C14
0.1U
F
16V
0402
_CC
C19
80.
1UF
16V
0402
_CC
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 17
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PHY ADDR:0x0
(default)
LAYO
UT
NO
TES:
1. T
he T
X a
nd R
X d
iff p
airs
sho
uld
be r
oute
d w
ith a
100o
hmdi
ffer
entia
l im
peda
nce
and
a 50
ohm
sin
gle
ende
d(c
hara
cter
istic
) im
peda
nce.
2. T
he t
race
leng
ths
with
in a
TX a
nd R
X di
ffer
entia
lpa
irsh
ould
be
mat
ched
.3.
The
dis
tanc
e be
twee
n ea
ch T
X a
nd R
X d
iffer
entia
lpa
ir s
houl
d be
50m
ils o
r m
ore.
GND_ENET is a small
isolated
GND plane which
should extend
under RJ45
connector
Power Control
High Level on
Ethernet
RX_
P
RX_
N
ENET
_LED
1
ENET
_LED
2
ENET
_VD
DC
R
TX_P
ENET
_RST
Mag
_led
2
TX_N
enet
_ctl_
sign
al
pow
er_r
ail_
enet
Mag
_led
1
ENET
_PH
YAD
0
ENET
_IN
T_B
ENET
_PW
R_E
N
FEC
3V15
GN
D
FEC
3V15
A_FE
C_3
V15
GN
D
A_FE
C_3
V15
GN
D
GN
D
GN
D
GN
DG
ND
_EN
ET
FEC
3V15
FEC
3V15
FEC
3V15
GN
D
GN
D
FEC
3V15
FEC
3V15
GN
D
FEC
3V15
GN
D
P3V1
5_VD
DH
IGH
_SW
2
FEC
_REF
_CLK
(6)
FEC
_MD
C(6
)FE
C_M
DIO
(6)
FEC
_CR
S_D
V(6
)FE
C_R
XD1
(6)
FEC
_RXD
0(6
)
FEC
_TX_
EN(6
)FE
C_T
XD1
(6)
FEC
_TXD
0(6
)
FEC
_TX_
CLK
(6)
Dra
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Titl
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ssifi
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P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
ENET
1516
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
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eet
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Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
ENET
1516
___
___
XD
raw
ing
Title
:
Size
Doc
umen
t Num
ber
Rev
Dat
e:Sh
eet
of
Page
Titl
e:
ICAP
Cla
ssifi
catio
n:FC
P:FI
UO
:PU
BI:
SCH
-285
49 P
DF:
SPF
-285
49A
MC
IMX6
SLEV
K-P
3 bo
ard
C
Mon
day,
Mar
ch 3
0, 2
015
ENET
1516
___
___
X
R40
70 04
02_C
C
R43
112
.1K
1%0402
_CC
R43
210
K04
02_C
C
C87
0.1U
F
16V
0402
_CC
R40
349
.906
03_C
C
Q6
IRLM
L640
1
1
32
C20
10.
1UF
16V
0402
_CC
R41
833
004
02_C
C
C20
40.
1UF
16V
0402
_CC
R40
649
.906
03_C
C
Q7
2N70
02
3
1
2
R40
247
K04
02_C
C
C20
310
uF
10V
R40
82.
2K04
02_C
C
R41
533
004
02_C
C
R40
449
.906
03_C
C
R42
410
K04
02_C
C
DN
P
TP51
C20
70.
1UF
16V
0402
_CC
C20
84.
7uF
6.3V
0402
_CC
L24
120O
HM
0603
_CC2
1
C20
50.
01U
F
16V
0402
_CC
R42
610
K04
02_C
C
R41
110
K04
02_C
C
TP50
R42
510
K04
02_C
C
J1
TX+
J2
TX-
J3
RX+
J4 J5 J6
RX-
J7 J8
J11
RJ4
5 8
TD+
1
TCT
2
TD-
3
RD
+4
RC
T5
RD
-6
NC
7
GN
D8
LED
1_C
11
LED
2_C
13
Chassis_GND19
LED
1_A
12
LED
2_A
14
Chassis_GND210
C20
20.
1UF
16V
0402
_CC
SH7
0
SH06
03
U8
LAN
8720
A
MD
IO12
MD
C13
LED
2/IN
TSE
L2
RX
D1/
MO
DE
17
RX
D0/
MO
DE
08
LED
1/R
EG
OFF
3
TXE
N16
TXD
017
TXD
118
CR
S_D
V/M
OD
E2
11
RS
T15
XTA
L1/C
LKIN
5
XTA
L24
VDD2A1
VDD1A19
RX
P23
RX
N22
TXN
20
TXP
21
VD
DC
R6
INT/
RE
FCLK
O14
RB
IAS
24
RX
ER
/PH
YA
D0
10
VDDIO9
VSS25
SH8
0
SH06
03
R40
549
.906
03_C
C
Schematic
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 18
anat
op.A
NATO
P_24
M_O
UT
anat
op.A
NATO
P_32
K_O
UT
anat
op.U
SBO
TG2_
IDan
atop
.USBO
TG1_
IDfe
c.REF
_OU
Tw
eim
.WEI
M_D
A_A
[0]
wei
m.W
EIM
_DA_A
[1]
wei
m.W
EIM
_DA_A
[2]
wei
m.W
EIM
_DA_A
[3]
wei
m.W
EIM
_DA_A
[4]
wei
m.W
EIM
_DA_A
[5]
wei
m.W
EIM
_DA_A
[6]
wei
m.W
EIM
_DA_A
[7]
wei
m.W
EIM
_DA_A
[8]
wei
m.W
EIM
_DA_A
[9]
wei
m.W
EIM
_DA_A
[10]
wei
m.W
EIM
_DA_A
[11]
wei
m.W
EIM
_DA_A
[12]
wei
m.W
EIM
_DA_A
[13]
wei
m.W
EIM
_DA_A
[14]
wei
m.W
EIM
_DA_A
[15]
csi.D
[0]
csi.D
[1]
csi.D
[2]
csi.D
[3]
csi.D
[4]
csi.D
[5]
csi.D
[6]
csi.D
[7]
wei
m.W
EIM
_A[1
6]w
eim
.WEI
M_A
[17]
wei
m.W
EIM
_A[1
8]w
eim
.WEI
M_A
[19]
wei
m.W
EIM
_A[2
0]w
eim
.WEI
M_A
[21]
wei
m.W
EIM
_A[2
2]w
eim
.WEI
M_A
[23]
csi.D
[8]
csi.D
[9]
csi.D
[10]
csi.D
[11]
wei
m.W
EIM
_CS[2
]w
eim
.WEI
M_L
BA
wei
m.W
EIM
_EB[0
]w
eim
.WEI
M_E
B[1
]cs
i.PIX
CLK
csi.H
SYN
Ccs
i.MCLK
csi.V
SYN
Cw
eim
.WEI
M_A
[24]
wei
m.W
EIM
_A[2
5]w
eim
.WEI
M_A
[26]
wei
m.W
EIM
_CRE
wei
m.W
EIM
_RW
wei
m.W
EIM
_OE
wei
m.W
EIM
_CS[0
]w
eim
.WEI
M_C
S[1
]w
eim
.WEI
M_B
CLK
wei
m.A
CLK
_FREE
RU
Nw
eim
.WEI
M_W
AIT
wei
m.W
EIM
_DTA
CK_B
wei
m.W
EIM
_RW
wei
m.W
EIM
_OE
wei
m.W
EIM
_CS[0
]w
eim
.WEI
M_C
S[1
]w
eim
.WEI
M_W
AIT
pwm
1.PW
MO
pwm
2.PW
MO
pwm
3.PW
MO
pwm
4.PW
MO
wdo
g2.W
DO
G_R
ST_
B_D
EBw
eim
.WEI
M_C
S[3
]w
eim
.WEI
M_D
[0]
wei
m.W
EIM
_D[1
]w
eim
.WEI
M_D
[2]
wei
m.W
EIM
_D[3
]w
eim
.WEI
M_D
[4]
wei
m.W
EIM
_D[5
]w
eim
.WEI
M_D
[6]
wei
m.W
EIM
_D[7
]w
eim
.WEI
M_D
[8]
wei
m.W
EIM
_D[9
]w
eim
.WEI
M_D
[10]
wei
m.W
EIM
_D[1
1]w
eim
.WEI
M_D
[12]
wei
m.W
EIM
_D[1
3]w
eim
.WEI
M_D
[14]
wei
m.W
EIM
_D[1
5]w
eim
.WEI
M_E
B[3
]w
eim
.WEI
M_E
B[2
]fe
c.M
DIO
fec.
TX_C
LKfe
c.RX_E
Rfe
c.RX_D
Vfe
c.RD
ATA
[1]
fec.
TDATA
[0]
fec.
MD
Cfe
c.CO
Lfe
c.RX_C
LKfe
c.RD
ATA
[0]
fec.
TX_E
Nfe
c.TD
ATA
[1]
fec.
REF
_OU
Tep
dc.V
CO
M[0
]ep
dc.V
CO
M[1
]ep
dc.B
DR[0
]ep
dc.B
DR[1
]cs
i.PIX
CLK
csi.H
SYN
Ccs
i.MCLK
csi.V
SYN
Cep
dc.S
DCE[
4]ep
dc.S
DCE[
5]ep
dc.S
DCE[
6]ep
dc.S
DCE[
7]ep
dc.S
DCE[
8]ep
dc.S
DCE[
9]ep
dc.S
DCLK
Nep
dc.S
DO
EDep
dc.S
DO
EZcc
m.P
MIC
_RD
Ysp
dif.
OU
T1cs
i.D[0
]cs
i.D[1
]cs
i.D[2
]cs
i.D[3
]cs
i.D[4
]cs
i.D[5
]cs
i.D[6
]cs
i.D[7
]cs
i.D[8
]cs
i.D[9
]cs
i.D[1
0]cs
i.D[1
1]cs
i.D[1
2]cs
i.D[1
3]cs
i.D[1
4]cs
i.D[1
5]ec
spi4
.SS0
ecsp
i4.S
CLK
ecsp
i4.M
OSI
ecsp
i4.M
ISO
ecsp
i4.S
S1
ecsp
i4.S
S2
usdh
c1.R
ST
usdh
c1.V
SEL
ECT
usdh
c1.W
Pus
dhc1
.CD
pwm
4.PW
MO
uart
5.RI
pwm
1.PW
MO
pwm
2.PW
MO
pwm
3.PW
MO
pwm
4.PW
MO
audm
ux.A
UD
IO_C
LK_O
UT
lcdi
f.D
AT[
0]lc
dif.
DAT[
1]lc
dif.
DAT[
2]lc
dif.
DAT[
3]lc
dif.
DAT[
4]lc
dif.
DAT[
5]lc
dif.
DAT[
6]lc
dif.
DAT[
7]lc
dif.
DAT[
8]lc
dif.
DAT[
9]lc
dif.
DAT[
10]
lcdi
f.D
AT[
11]
lcdi
f.D
AT[
12]
lcdi
f.D
AT[
13]
lcdi
f.D
AT[
14]
lcdi
f.D
AT[
15]
lcdi
f.D
AT[
24]
lcdi
f.D
AT[
25]
lcdi
f.D
AT[
26]
lcdi
f.D
AT[
27]
lcdi
f.D
AT[
28]
lcdi
f.D
AT[
29]
lcdi
f.D
AT[
30]
lcdi
f.D
AT[
31]
epdc
.PW
RCTR
L[0]
epdc
.PW
RCTR
L[1]
epdc
.PW
RCTR
L[2]
epdc
.PW
RCTR
L[3]
epdc
.PW
RCO
Mep
dc.P
WRIR
Qep
dc.P
WRSTA
Tep
dc.P
WRW
AKE
i2c2
.SCL
i2c2
.SD
Atc
on.X
DIO
Rep
dc.S
DCE[
4]pw
m3.
PWM
Opw
m4.
PWM
Opw
m1.
PWM
Opw
m2.
PWM
Otc
on.Y
CKR
tcon
.YO
ERtc
on.Y
DIO
UR
tcon
.YD
IOD
Rua
rt3.
RXD
_MU
Xua
rt3.
TXD
_MU
Xua
rt3.
RTS
uart
3.CTS
lcdi
f.D
AT[
16]
lcdi
f.D
AT[
17]
lcdi
f.D
AT[
18]
lcdi
f.D
AT[
19]
lcdi
f.D
AT[
20]
lcdi
f.D
AT[
21]
lcdi
f.D
AT[
22]
lcdi
f.D
AT[
23]
lcdi
f.W
R_R
WN
lcdi
f.RD
_Elc
dif.
CS
lcdi
f.RS
lcdi
f.BU
SY
anat
op.U
SBO
TG2_
IDan
atop
.USBO
TG1_
IDep
it2.E
PITO
uart
5.D
SR
csi.V
SYN
Ccs
i.HSYN
Ccs
i.PIX
CLK
csi.M
CLK
csi.D
[9]
csi.D
[8]
csi.D
[7]
csi.D
[6]
csi.D
[5]
csi.D
[4]
csi.D
[3]
csi.D
[2]
csi.D
[1]
csi.D
[0]
csi.D
[15]
csi.D
[14]
csi.D
[13]
csi.D
[12]
csi.D
[11]
csi.D
[10]
uart
3.RXD
_MU
Xua
rt3.
TXD
_MU
Xua
rt4.
RXD
_MU
Xua
rt4.
TXD
_MU
Xua
rt4.
RTS
uart
4.CTS
ecsp
i3.R
DY
uart
4.RXD
_MU
Xua
rt4.
TXD
_MU
Xec
spi3
.SS2
ecsp
i3.S
S3
spdi
f.IN
1sp
dif.
OU
T1ua
rt5.
RXD
_MU
Xua
rt5.
TXD
_MU
Xua
rt5.
RTS
uart
5.CTS
uart
3.RXD
_MU
Xua
rt3.
TXD
_MU
Xua
rt3.
RTS
uart
3.CTS
kpp.
CO
L[0]
kpp.
RO
W[0
]kp
p.CO
L[1]
kpp.
RO
W[1
]kp
p.CO
L[2]
kpp.
RO
W[2
]kp
p.CO
L[3]
kpp.
RO
W[3
]kp
p.CO
L[4]
kpp.
RO
W[4
]w
dog2
.WD
OG
_Bec
spi3
.SCLK
ecsp
i3.S
S0
ecsp
i3.M
OSI
ecsp
i3.M
ISO
fec.
CO
Lfe
c.RX_C
LKua
rt2.
RXD
_MU
Xua
rt2.
TXD
_MU
Xua
rt2.
RTS
uart
2.CTS
kpp.
CO
L[5]
kpp.
RO
W[5
]kp
p.CO
L[6]
kpp.
RO
W[6
]kp
p.CO
L[7]
kpp.
RO
W[7
]au
dmux
.AU
D6_
RXFS
audm
ux.A
UD
6_RXC
audm
ux.A
UD
6_RXD
audm
ux.A
UD
6_TX
Cau
dmux
.AU
D6_
TXFS
audm
ux.A
UD
6_TX
Dau
dmux
.AU
DIO
_CLK
_OU
Tan
atop
.USBO
TG1_
IDsp
dif.
IN1
spdi
f.O
UT1
wdo
g1.W
DO
G_B
wdo
g1.W
DO
G_R
ST_
B_D
EBi2
c1.S
CL
i2c1
.SD
Ai2
c3.S
CL
i2c3
.SD
Acc
m.C
LKO
i2c2
.SCL
i2c2
.SD
Aec
spi4
.MO
SI
ecsp
i4.M
ISO
ecsp
i4.S
S0
ecsp
i4.S
CLK
audm
ux.A
UD
6_RXFS
audm
ux.A
UD
6_RXC
audm
ux.A
UD
6_RXD
audm
ux.A
UD
6_TX
Cau
dmux
.AU
D6_
TXFS
audm
ux.A
UD
6_TX
Dua
rt4.
RXD
_MU
Xua
rt4.
TXD
_MU
Xua
rt4.
RTS
uart
4.CTS
ecsp
i4.M
OSI
ecsp
i4.M
ISO
ecsp
i4.S
S0
ecsp
i4.S
CLK
ecsp
i4.S
S1
ecsp
i4.S
S2
ecsp
i4.S
S3
ecsp
i4.R
DY
ecsp
i3.M
OSI
ecsp
i3.M
ISO
ecsp
i3.S
S0
ecsp
i3.S
CLK
uart
2.RXD
_MU
Xua
rt2.
TXD
_MU
Xua
rt2.
RTS
uart
2.CTS
ecsp
i2.M
OSI
ecsp
i2.M
ISO
ecsp
i2.S
S0
ecsp
i2.S
CLK
ecsp
i2.S
S1
wdo
g2.W
DO
G_B
i2c3
.SCL
i2c3
.SD
Aec
spi2
.SS2
ecsp
i2.S
S3
ecsp
i2.R
DY
pwm
4.PW
MO
audm
ux.A
UD
5_RXFS
audm
ux.A
UD
5_RXD
usdh
c4.C
LKus
dhc4
.CM
Dau
dmux
.AU
D5_
RXC
audm
ux.A
UD
5_TX
FSau
dmux
.AU
D5_
TXD
audm
ux.A
UD
5_TX
Cus
dhc4
.DAT0
usdh
c4.D
AT1
usdh
c4.D
AT2
usdh
c4.D
AT3
usdh
c4.D
AT4
usdh
c4.D
AT5
usdh
c4.D
AT6
usdh
c4.D
AT7
wei
m.W
EIM
_DTA
CK_B
ecsp
i1.M
OSI
ecsp
i1.M
ISO
ecsp
i1.S
S0
ecsp
i1.S
CLK
ecsp
i1.S
S1
ecsp
i1.S
S2
ecsp
i1.S
S3
ecsp
i1.R
DY
kpp.
CO
L[0]
kpp.
RO
W[0
]kp
p.CO
L[1]
kpp.
RO
W[1
]kp
p.CO
L[2]
kpp.
RO
W[2
]kp
p.CO
L[3]
kpp.
RO
W[3
]kp
p.CO
L[4]
kpp.
RO
W[4
]kp
p.CO
L[5]
kpp.
RO
W[5
]kp
p.CO
L[6]
kpp.
RO
W[6
]kp
p.CO
L[7]
kpp.
RO
W[7
]i2
c1.S
CL
i2c1
.SD
Aec
spi3
.MO
SI
ecsp
i3.M
ISO
pwm
3.PW
MO
ecsp
i3.S
CLK
pwm
4.PW
MO
pwm
1.PW
MO
pwm
2.PW
MO
uart
1.RTS
uart
1.CTS
audm
ux.A
UD
4_RXFS
audm
ux.A
UD
4_RXC
audm
ux.A
UD
4_TX
Dau
dmux
.AU
D4_
TXC
audm
ux.A
UD
4_TX
FSau
dmux
.AU
D4_
RXD
spdi
f.SPD
IF_E
XT_
CLK
sdm
a.SD
MA_E
XT_
EVEN
T[1]
sdm
a.SD
MA_E
XT_
EVEN
T[0]
ecsp
i1.S
S3
fec.
MD
IOfe
c.TX
_CLK
fec.
RX_E
Rfe
c.RX_D
Vfe
c.RD
ATA
[1]
fec.
TDATA
[0]
fec.
MD
Cfe
c.RD
ATA
[0]
fec.
TX_E
Nfe
c.TD
ATA
[1]
fec.
REF
_OU
Tau
dmux
.AU
D4_
RXFS
audm
ux.A
UD
4_RXC
audm
ux.A
UD
4_RXD
audm
ux.A
UD
4_TX
Cau
dmux
.AU
D4_
TXFS
audm
ux.A
UD
4_TX
Dus
dhc3
.DAT4
usdh
c3.D
AT5
usdh
c3.D
AT6
usdh
c3.D
AT7
audm
ux.A
UD
5_RXFS
audm
ux.A
UD
5_RXC
audm
ux.A
UD
5_RXD
audm
ux.A
UD
5_TX
Cau
dmux
.AU
D5_
TXFS
audm
ux.A
UD
5_TX
Dus
dhc4
.CLK
usdh
c4.C
MD
usdh
c4.D
AT0
usdh
c4.D
AT1
usdh
c4.D
AT2
usdh
c4.D
AT3
usdh
c4.D
AT4
usdh
c4.D
AT5
usdh
c4.D
AT6
usdh
c4.D
AT7
usdh
c4.R
ST
wdo
g1.W
DO
G_B
usb.
H_D
ATA
usb.
H_S
TRO
BE
anat
op.A
NATO
P_24
M_O
UT
anat
op.A
NATO
P_32
K_O
UT
pwm
1.PW
MO
kpp.
CO
L[0]
kpp.
RO
W[0
]kp
p.CO
L[1]
kpp.
RO
W[1
]kp
p.CO
L[2]
kpp.
RO
W[2
]kp
p.CO
L[3]
kpp.
RO
W[3
]kp
p.CO
L[4]
kpp.
RO
W[4
]kp
p.CO
L[5]
kpp.
RO
W[5
]kp
p.CO
L[6]
kpp.
RO
W[6
]kp
p.CO
L[7]
kpp.
RO
W[7
]ep
dc.S
DD
O[0
]ep
dc.S
DD
O[1
]ep
dc.S
DD
O[2
]ep
dc.S
DD
O[3
]ep
dc.S
DD
O[4
]ep
dc.S
DD
O[5
]ep
dc.S
DD
O[6
]ep
dc.S
DD
O[7
]ep
dc.S
DD
O[8
]ep
dc.S
DD
O[9
]ep
dc.S
DD
O[1
0]ep
dc.S
DD
O[1
1]ep
dc.S
DD
O[1
2]ep
dc.S
DD
O[1
3]ep
dc.S
DD
O[1
4]ep
dc.S
DD
O[1
5]ep
dc.S
DCLK
epdc
.SD
LEep
dc.S
DO
Eep
dc.S
DSH
Rep
dc.S
DCE[
0]ep
dc.S
DCE[
1]ep
dc.S
DCE[
2]ep
dc.S
DCE[
3]ep
dc.G
DCLK
epdc
.GD
OE
epdc
.GD
RL
epdc
.GD
SP
epdc
.VCO
M[0
]ep
dc.V
CO
M[1
]ep
dc.B
DR[0
]ep
dc.B
DR[1
]ep
dc.P
WRCTR
L[0]
epdc
.PW
RCTR
L[1]
epdc
.PW
RCTR
L[2]
epdc
.PW
RCTR
L[3]
epdc
.PW
RCO
Mep
dc.P
WRIR
Qep
dc.P
WRSTA
Tep
dc.P
WRW
AKE
lcdi
f.CLK
lcdi
f.EN
ABLE
lcdi
f.H
SYN
Clc
dif.
VSYN
Clc
dif.
RES
ETlc
dif.
DAT[
0]lc
dif.
DAT[
1]lc
dif.
DAT[
2]lc
dif.
DAT[
3]lc
dif.
DAT[
4]lc
dif.
DAT[
5]lc
dif.
DAT[
6]lc
dif.
DAT[
7]lc
dif.
DAT[
8]lc
dif.
DAT[
9]lc
dif.
DAT[
10]
lcdi
f.D
AT[
11]
lcdi
f.D
AT[
12]
lcdi
f.D
AT[
13]
lcdi
f.D
AT[
14]
lcdi
f.D
AT[
15]
lcdi
f.D
AT[
16]
lcdi
f.D
AT[
17]
lcdi
f.D
AT[
18]
lcdi
f.D
AT[
19]
lcdi
f.D
AT[
20]
lcdi
f.D
AT[
21]
lcdi
f.D
AT[
22]
lcdi
f.D
AT[
23]
audm
ux.A
UD
3_RXFS
audm
ux.A
UD
3_RXC
audm
ux.A
UD
3_RXD
audm
ux.A
UD
3_TX
Cau
dmux
.AU
D3_
TXFS
audm
ux.A
UD
3_TX
Dau
dmux
.AU
DIO
_CLK
_OU
Tua
rt1.
RXD
_MU
Xua
rt1.
TXD
_MU
Xi2
c1.S
CL
i2c1
.SD
Ai2
c2.S
CL
i2c2
.SD
Aec
spi1
.SCLK
ecsp
i1.M
OSI
ecsp
i1.M
ISO
ecsp
i1.S
S0
ecsp
i2.S
CLK
ecsp
i2.M
OSI
ecsp
i2.M
ISO
ecsp
i2.S
S0
usdh
c1.C
LKus
dhc1
.CM
Dus
dhc1
.DAT0
usdh
c1.D
AT1
usdh
c1.D
AT2
usdh
c1.D
AT3
usdh
c1.D
AT4
usdh
c1.D
AT5
usdh
c1.D
AT6
usdh
c1.D
AT7
usdh
c2.R
ST
usdh
c2.C
LKus
dhc2
.CM
Dus
dhc2
.DAT0
usdh
c2.D
AT1
usdh
c2.D
AT2
usdh
c2.D
AT3
usdh
c2.D
AT4
usdh
c2.D
AT5
usdh
c2.D
AT6
usdh
c2.D
AT7
usdh
c3.C
LKus
dhc3
.CM
Dus
dhc3
.DAT0
usdh
c3.D
AT1
usdh
c3.D
AT2
usdh
c3.D
AT3
fec.
MD
IOfe
c.TX
_CLK
fec.
RX_E
Rfe
c.RX_D
Vfe
c.RD
ATA
[1]
fec.
TDATA
[0]
fec.
MD
Cfe
c.RD
ATA
[0]
fec.
TX_E
Nfe
c.TD
ATA
[1]
fec.
REF
_OU
T
WD
OG
_BH
SIC
_DAT
HSIC
_STR
OBE
REF
_CLK
_24M
REF
_CLK
_32K
PWM
1KEY
_CO
L0KEY
_RO
W0
KEY
_CO
L1KEY
_RO
W1
KEY
_CO
L2KEY
_RO
W2
KEY
_CO
L3KEY
_RO
W3
KEY
_CO
L4KEY
_RO
W4
KEY
_CO
L5KEY
_RO
W5
KEY
_CO
L6KEY
_RO
W6
KEY
_CO
L7KEY
_RO
W7
EPD
C_D
0EP
DC_D
1EP
DC_D
2EP
DC_D
3EP
DC_D
4EP
DC_D
5EP
DC_D
6EP
DC_D
7EP
DC_D
8EP
DC_D
9EP
DC_D
10EP
DC_D
11EP
DC_D
12EP
DC_D
13EP
DC_D
14EP
DC_D
15EP
DC_S
DCLK
EPD
C_S
DLE
EPD
C_S
DO
EEP
DC_S
DSH
REP
DC_S
DCE0
EPD
C_S
DCE1
EPD
C_S
DCE2
EPD
C_S
DCE3
EPD
C_G
DCLK
EPD
C_G
DO
EEP
DC_G
DRL
EPD
C_G
DSP
EPD
C_V
CO
M0
EPD
C_V
CO
M1
EPD
C_B
DR0
EPD
C_B
DR1
EPD
C_P
WRCTR
L0EP
DC_P
WRCTR
L1EP
DC_P
WRCTR
L2EP
DC_P
WRCTR
L3EP
DC_P
WRCO
MEP
DC_P
WRIN
TEP
DC_P
WRSTA
TEP
DC_P
WRW
AKEU
PLC
D_C
LKLC
D_E
NABLE
LCD
_HSYN
CLC
D_V
SYN
CLC
D_R
ESET
LCD
_DAT0
LCD
_DAT1
LCD
_DAT2
LCD
_DAT3
LCD
_DAT4
LCD
_DAT5
LCD
_DAT6
LCD
_DAT7
LCD
_DAT8
LCD
_DAT9
LCD
_DAT1
0LC
D_D
AT1
1LC
D_D
AT1
2LC
D_D
AT1
3LC
D_D
AT1
4LC
D_D
AT1
5LC
D_D
AT1
6LC
D_D
AT1
7LC
D_D
AT1
8LC
D_D
AT1
9LC
D_D
AT2
0LC
D_D
AT2
1LC
D_D
AT2
2LC
D_D
AT2
3AU
D_R
XFS
AU
D_R
XC
AU
D_R
XD
AU
D_T
XC
AU
D_T
XFS
AU
D_T
XD
AU
D_M
CLK
UART1
_RXD
UART1
_TXD
I2C1_
SCL
I2C1_
SD
AI2
C2_
SCL
I2C2_
SD
AEC
SPI
1_SCLK
ECSPI
1_M
OSI
ECSPI
1_M
ISO
ECSPI
1_SS0
ECSPI
2_SCLK
ECSPI
2_M
OSI
ECSPI
2_M
ISO
ECSPI
2_SS0
SD
1_CLK
SD
1_CM
DSD
1_D
AT0
SD
1_D
AT1
SD
1_D
AT2
SD
1_D
AT3
SD
1_D
AT4
SD
1_D
AT5
SD
1_D
AT6
SD
1_D
AT7
SD
2_RST
SD
2_CLK
SD
2_CM
DSD
2_D
AT0
SD
2_D
AT1
SD
2_D
AT2
SD
2_D
AT3
SD
2_D
AT4
SD
2_D
AT5
SD
2_D
AT6
SD
2_D
AT7
SD
3_CLK
SD
3_CM
DSD
3_D
AT0
SD
3_D
AT1
SD
3_D
AT2
SD
3_D
AT3
FEC_M
DIO
FEC_T
X_C
LKFE
C_R
X_E
RFE
C_C
RS_D
VFE
C_R
XD
1FE
C_T
XD
0FE
C_M
DC
FEC_R
XD
0FE
C_T
X_E
NFE
C_T
XD
1FE
C_R
EF_C
LK
obse
rve_
mux
.OU
T[2]
mm
dc.M
MD
C_D
EBU
G[4
9]ob
serv
e_m
ux.O
UT[
3]ob
serv
e_m
ux.O
UT[
4]tp
smp.
HD
ATA
[0]
tpsm
p.H
DATA
[1]
tpsm
p.H
DATA
[2]
tpsm
p.H
DATA
[3]
tpsm
p.H
DATA
[4]
tpsm
p.H
DATA
[5]
tpsm
p.H
DATA
[6]
tpsm
p.H
DATA
[7]
tpsm
p.H
DATA
[8]
tpsm
p.H
DATA
[9]
tpsm
p.H
DATA
[10]
tpsm
p.H
DATA
[11]
tpsm
p.H
DATA
[12]
tpsm
p.H
DATA
[13]
tpsm
p.H
DATA
[14]
tpsm
p.H
DATA
[15]
obse
rve_
mux
.OU
T[0]
obse
rve_
mux
.OU
T[1]
tpsm
p.H
DATA
[28]
tpsm
p.H
DATA
[29]
tpsm
p.H
DATA
[30]
tpsm
p.H
DATA
[31]
mm
dc.M
MD
C_D
EBU
G[4
0]m
mdc
.MM
DC_D
EBU
G[3
2]m
mdc
.MM
DC_D
EBU
G[3
1]m
mdc
.MM
DC_D
EBU
G[3
0]m
mdc
.MM
DC_D
EBU
G[2
9]m
mdc
.MM
DC_D
EBU
G[2
8]m
mdc
.MM
DC_D
EBU
G[2
7]m
mdc
.MM
DC_D
EBU
G[2
6]m
mdc
.MM
DC_D
EBU
G[2
5]m
mdc
.MM
DC_D
EBU
G[2
4]m
mdc
.MM
DC_D
EBU
G[2
3]m
mdc
.MM
DC_D
EBU
G[2
2]m
mdc
.MM
DC_D
EBU
G[2
1]m
mdc
.MM
DC_D
EBU
G[2
0]m
mdc
.MM
DC_D
EBU
G[1
9]m
mdc
.MM
DC_D
EBU
G[1
8]m
mdc
.MM
DC_D
EBU
G[1
7]m
mdc
.MM
DC_D
EBU
G[1
6]m
mdc
.MM
DC_D
EBU
G[1
5]m
mdc
.MM
DC_D
EBU
G[1
4]m
mdc
.MM
DC_D
EBU
G[1
3]m
mdc
.MM
DC_D
EBU
G[1
2]m
mdc
.MM
DC_D
EBU
G[1
1]m
mdc
.MM
DC_D
EBU
G[1
0]m
mdc
.MM
DC_D
EBU
G[9
]m
mdc
.MM
DC_D
EBU
G[8
]m
mdc
.MM
DC_D
EBU
G[7
]m
mdc
.MM
DC_D
EBU
G[6
]m
mdc
.MM
DC_D
EBU
G[5
]m
mdc
.MM
DC_D
EBU
G[4
]m
mdc
.MM
DC_D
EBU
G[3
]m
mdc
.MM
DC_D
EBU
G[2
]m
mdc
.MM
DC_D
EBU
G[1
]m
mdc
.MM
DC_D
EBU
G[0
]tp
smp.
HTR
AN
S[0
]tp
smp.
HTR
AN
S[1
]tp
smp.
HD
ATA
[16]
tpsm
p.H
DATA
[17]
tpsm
p.H
DATA
_DIR
src.
BT_
CFG
[0]
src.
BT_
CFG
[1]
src.
BT_
CFG
[2]
src.
BT_
CFG
[3]
src.
BT_
CFG
[4]
src.
BT_
CFG
[5]
src.
BT_
CFG
[6]
src.
BT_
CFG
[7]
src.
BT_
CFG
[8]
src.
BT_
CFG
[9]
src.
BT_
CFG
[10]
src.
BT_
CFG
[11]
src.
BT_
CFG
[12]
src.
BT_
CFG
[13]
src.
BT_
CFG
[14]
src.
BT_
CFG
[15]
src.
BT_
CFG
[24]
src.
BT_
CFG
[25]
src.
BT_
CFG
[26]
src.
BT_
CFG
[27]
src.
BT_
CFG
[28]
src.
BT_
CFG
[29]
src.
BT_
CFG
[30]
src.
BT_
CFG
[31]
pl30
1_si
m_m
x6sl
_per
1.H
PRO
T[1]
pl30
1_si
m_m
x6sl
_per
1.H
REA
DYO
UT
pl30
1_si
m_m
x6sl
_per
1.H
RES
Ptp
smp.
HD
ATA
[24]
tpsm
p.H
DATA
[25]
tpsm
p.H
DATA
[26]
tpsm
p.H
DATA
[27]
tpsm
p.CLK
uart
5.D
CD
pl30
1_si
m_m
x6sl
_per
1.H
SIZ
E[0]
pl30
1_si
m_m
x6sl
_per
1.H
SIZ
E[1]
pl30
1_si
m_m
x6sl
_per
1.H
SIZ
E[2]
pl30
1_si
m_m
x6sl
_per
1.H
WRIT
Etp
smp.
HD
ATA
[18]
tpsm
p.H
DATA
[19]
tpsm
p.H
DATA
[20]
pl30
1_si
m_m
x6sl
_per
1.H
AD
DR[2
3]tp
smp.
HD
ATA
[21]
tpsm
p.H
DATA
[22]
tpsm
p.H
DATA
[23]
pl30
1_si
m_m
x6sl
_per
1.H
AD
DR[2
4]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
5]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
6]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
7]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
8]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
9]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[3
0]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[3
1]pl
301_
sim
_mx6
sl_p
er1.
HPR
OT[
3]pl
301_
sim
_mx6
sl_p
er1.
HPR
OT[
2]pl
301_
sim
_mx6
sl_p
er1.
HM
ASTL
OCK
pl30
1_si
m_m
x6sl
_per
1.H
BU
RST[
2]pl
301_
sim
_mx6
sl_p
er1.
HPR
OT[
1]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
1]pl
301_
sim
_mx6
sl_p
er1.
HPR
OT[
0]pl
301_
sim
_mx6
sl_p
er1.
HBU
RST[
1]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
2]pl
301_
sim
_mx6
sl_p
er1.
HBU
RST[
0]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
0]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
0]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
9]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
6]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
3]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
8]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
1]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
7]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
4]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
2]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
5]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[4
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[5
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[3
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[9
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[2
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[8
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[7
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[1
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[6
]pl
301_
sim
_mx6
sl_p
er1.
HAD
DR[0
]
usdh
c3.W
Pus
dhc3
.CD
epit1
.EPI
TO
usdh
c1.R
ST
usdh
c1.V
SEL
ECT
usb.
USBO
TG1_
PWR
usb.
USBO
TG1_
OC
usb.
USBO
TG2_
PWR
usb.
USBO
TG2_
OC
usdh
c3.R
ST
usdh
c3.V
SEL
ECT
usdh
c1.W
Pus
dhc1
.CD
anat
op.U
SBPH
Y1_T
STI
_TX_H
S_M
OD
Ean
atop
.USBPH
Y1_T
STI
_TX_L
S_M
OD
Ean
atop
.USBPH
Y1_T
STI
_TX_D
Nan
atop
.USBPH
Y1_T
STI
_TX_D
Pan
atop
.USBPH
Y1_T
STI
_TX_E
Nan
atop
.USBPH
Y1_T
STI
_TX_H
IZan
atop
.USBPH
Y2_T
STO
_RX_D
ISCO
N_D
ETan
atop
.USBPH
Y2_T
STO
_RX_F
S_R
XD
usdh
c4.R
ST
usdh
c4.V
SEL
ECT
usdh
c4.W
Pus
dhc4
.CD
ecsp
i3.S
S1
ecsp
i3.S
S2
ecsp
i3.S
S3
ecsp
i3.R
DY
anat
op.U
SBPH
Y2_T
STO
_RX_H
S_R
XD
anat
op.U
SBPH
Y2_T
STO
_RX_S
QU
ELCH
anat
op.U
SBPH
Y2_T
STO
_PLL
_CLK
20D
IVan
atop
.USBPH
Y1_T
STO
_RX_D
ISCO
N_D
ETan
atop
.USBPH
Y1_T
STO
_PLL
_CLK
20D
IVan
atop
.USBPH
Y1_T
STO
_RX_F
S_R
XD
anat
op.U
SBPH
Y1_T
STO
_RX_H
S_R
XD
anat
op.U
SBPH
Y1_T
STO
_RX_S
QU
ELCH
usdh
c2.R
ST
usdh
c2.V
SEL
ECT
usdh
c2.W
Pus
dhc2
.CD
epdc
.SD
CE[
5]ep
dc.S
DCE[
6]ep
dc.S
DCE[
7]ep
dc.S
DCE[
8]us
dhc4
.RST
usdh
c4.V
SEL
ECT
usdh
c4.W
Pus
dhc4
.CD
usdh
c3.R
ST
usdh
c3.V
SEL
ECT
usdh
c3.W
Pus
dhc3
.CD
src.
EARLY
_RST
ocot
p_ct
rl_w
rapp
er.F
USE_
LATC
HED
kitt
en.T
RCLK
kitt
en.T
RCTL
ccm
.PM
IC_R
DY
kitt
en.T
RACE[
0]ki
tten
.TRACE[
1]ki
tten
.TRACE[
2]ki
tten
.TRACE[
3]ki
tten
.TRACE[
4]ki
tten
.TRACE[
5]ki
tten
.TRACE[
6]ki
tten
.TRACE[
7]ki
tten
.TRACE[
8]ki
tten
.TRACE[
9]ki
tten
.TRACE[
10]
kitt
en.T
RACE[
11]
kitt
en.T
RACE[
12]
kitt
en.T
RACE[
13]
kitt
en.T
RACE[
14]
kitt
en.T
RACE[
15]
kitt
en.T
RACE[
16]
kitt
en.T
RACE[
17]
kitt
en.T
RACE[
18]
kitt
en.T
RACE[
19]
kitt
en.T
RACE[
20]
kitt
en.T
RACE[
21]
kitt
en.T
RACE[
22]
kitt
en.T
RACE[
23]
ecsp
i3.S
S0
ecsp
i3.S
S1
src.
INT_
BO
OT
src.
SYS
TEM
_RST
anat
op.A
NATO
P_TE
STI
[0]
anat
op.A
NATO
P_TE
STI
[1]
spdi
f.SPD
IF_E
XT_
CLK
anat
op.A
NATO
P_TE
STI
[2]
anat
op.A
NATO
P_TE
STI
[3]
ecsp
i1.S
S1
ecsp
i1.S
S2
ecsp
i1.R
DY
anat
op.A
NATO
P_TE
STO
[0]
usb.
USBO
TG2_
OC
ccm
.PLL
2_BYP
ccm
.PLL
3_BYP
usb.
USBO
TG2_
PWR
usb.
USBO
TG2_
OC
anat
op.A
NATO
P_TE
STO
[1]
usb.
USBO
TG1_
OC
usb.
USBO
TG1_
PWR
anat
op.A
NATO
P_TE
STO
[2]
anat
op.A
NATO
P_TE
STO
[3]
anat
op.A
NATO
P_TE
STO
[4]
anat
op.A
NATO
P_TE
STO
[5]
anat
op.A
NATO
P_TE
STO
[6]
anat
op.A
NATO
P_TE
STO
[7]
anat
op.A
NATO
P_TE
STO
[8]
anat
op.A
NATO
P_TE
STO
[9]
anat
op.A
NATO
P_TE
STO
[10]
anat
op.A
NATO
P_TE
STO
[11]
anat
op.A
NATO
P_TE
STO
[12]
anat
op.A
NATO
P_TE
STO
[13]
anat
op.A
NATO
P_TE
STO
[14]
anat
op.A
NATO
P_TE
STO
[15]
mm
dc.M
MD
C_D
EBU
G[3
9]m
mdc
.MM
DC_D
EBU
G[3
8]m
mdc
.MM
DC_D
EBU
G[3
7]m
mdc
.MM
DC_D
EBU
G[3
6]m
mdc
.MM
DC_D
EBU
G[3
5]m
mdc
.MM
DC_D
EBU
G[3
4]m
mdc
.MM
DC_D
EBU
G[3
3]us
b.U
SBO
TG1_
PWR
usb.
USBO
TG2_
PWR
sjc.
JTAG
_ACT
sjc.
DE_
Bus
b.U
SBO
TG2_
OC
usb.
USBO
TG1_
OC
kitt
en.T
RACE[
26]
kitt
en.T
RACE[
27]
kitt
en.T
RACE[
25]
kitt
en.T
RACE[
31]
fec.
CO
Lki
tten
.TRACE[
30]
kitt
en.T
RACE[
29]
kitt
en.T
RACE[
24]
kitt
en.T
RACE[
28]
fec.
RX_C
LKsp
dif.
SPD
IF_E
XT_
CLK
gpio
3.G
PIO
[18]
gpio
3.G
PIO
[19]
gpio
3.G
PIO
[20]
gpio
3.G
PIO
[21]
gpio
3.G
PIO
[22]
gpio
3.G
PIO
[23]
gpio
3.G
PIO
[24]
gpio
3.G
PIO
[25]
gpio
3.G
PIO
[26]
gpio
3.G
PIO
[27]
gpio
3.G
PIO
[28]
gpio
3.G
PIO
[29]
gpio
3.G
PIO
[30]
gpio
3.G
PIO
[31]
gpio
4.G
PIO
[0]
gpio
4.G
PIO
[1]
gpio
4.G
PIO
[2]
gpio
4.G
PIO
[3]
gpio
4.G
PIO
[4]
gpio
4.G
PIO
[5]
gpio
4.G
PIO
[6]
gpio
4.G
PIO
[7]
gpio
1.G
PIO
[7]
gpio
1.G
PIO
[8]
gpio
1.G
PIO
[9]
gpio
1.G
PIO
[10]
gpio
1.G
PIO
[11]
gpio
1.G
PIO
[12]
gpio
1.G
PIO
[13]
gpio
1.G
PIO
[14]
gpio
1.G
PIO
[15]
gpio
1.G
PIO
[16]
gpio
1.G
PIO
[17]
gpio
1.G
PIO
[18]
gpio
1.G
PIO
[19]
gpio
1.G
PIO
[20]
gpio
1.G
PIO
[21]
gpio
1.G
PIO
[22]
gpio
1.G
PIO
[23]
gpio
1.G
PIO
[24]
gpio
1.G
PIO
[25]
gpio
1.G
PIO
[26]
gpio
1.G
PIO
[27]
gpio
1.G
PIO
[28]
gpio
1.G
PIO
[29]
gpio
1.G
PIO
[30]
gpio
1.G
PIO
[31]
gpio
2.G
PIO
[0]
gpio
2.G
PIO
[1]
gpio
2.G
PIO
[2]
gpio
2.G
PIO
[3]
gpio
2.G
PIO
[4]
gpio
2.G
PIO
[5]
gpio
2.G
PIO
[6]
gpio
2.G
PIO
[7]
gpio
2.G
PIO
[8]
gpio
2.G
PIO
[9]
gpio
2.G
PIO
[10]
gpio
2.G
PIO
[11]
gpio
2.G
PIO
[12]
gpio
2.G
PIO
[13]
gpio
2.G
PIO
[14]
gpio
2.G
PIO
[15]
gpio
2.G
PIO
[16]
gpio
2.G
PIO
[17]
gpio
2.G
PIO
[18]
gpio
2.G
PIO
[19]
gpio
2.G
PIO
[20]
gpio
2.G
PIO
[21]
gpio
2.G
PIO
[22]
gpio
2.G
PIO
[23]
gpio
2.G
PIO
[24]
gpio
2.G
PIO
[25]
gpio
2.G
PIO
[26]
gpio
2.G
PIO
[27]
gpio
2.G
PIO
[28]
gpio
2.G
PIO
[29]
gpio
2.G
PIO
[30]
gpio
2.G
PIO
[31]
gpio
3.G
PIO
[0]
gpio
3.G
PIO
[1]
gpio
3.G
PIO
[2]
gpio
3.G
PIO
[3]
gpio
3.G
PIO
[4]
gpio
3.G
PIO
[5]
gpio
3.G
PIO
[6]
gpio
3.G
PIO
[7]
gpio
3.G
PIO
[8]
gpio
3.G
PIO
[9]
gpio
3.G
PIO
[10]
gpio
3.G
PIO
[11]
gpio
1.G
PIO
[0]
gpio
1.G
PIO
[1]
gpio
1.G
PIO
[2]
gpio
1.G
PIO
[3]
gpio
1.G
PIO
[4]
gpio
1.G
PIO
[5]
gpio
1.G
PIO
[6]
gpio
3.G
PIO
[16]
gpio
3.G
PIO
[17]
gpio
3.G
PIO
[12]
gpio
3.G
PIO
[13]
gpio
3.G
PIO
[14]
gpio
3.G
PIO
[15]
gpio
4.G
PIO
[8]
gpio
4.G
PIO
[9]
gpio
4.G
PIO
[10]
gpio
4.G
PIO
[11]
gpio
4.G
PIO
[12]
gpio
4.G
PIO
[13]
gpio
4.G
PIO
[14]
gpio
4.G
PIO
[15]
gpio
5.G
PIO
[15]
gpio
5.G
PIO
[14]
gpio
5.G
PIO
[11]
gpio
5.G
PIO
[8]
gpio
5.G
PIO
[13]
gpio
5.G
PIO
[6]
gpio
5.G
PIO
[12]
gpio
5.G
PIO
[9]
gpio
5.G
PIO
[7]
gpio
5.G
PIO
[10]
gpio
4.G
PIO
[27]
gpio
5.G
PIO
[5]
gpio
5.G
PIO
[4]
gpio
5.G
PIO
[1]
gpio
4.G
PIO
[30]
gpio
5.G
PIO
[3]
gpio
4.G
PIO
[28]
gpio
5.G
PIO
[2]
gpio
4.G
PIO
[31]
gpio
4.G
PIO
[29]
gpio
5.G
PIO
[0]
gpio
5.G
PIO
[18]
gpio
5.G
PIO
[21]
gpio
5.G
PIO
[19]
gpio
5.G
PIO
[20]
gpio
5.G
PIO
[16]
gpio
5.G
PIO
[17]
gpio
4.G
PIO
[20]
gpio
4.G
PIO
[21]
gpio
4.G
PIO
[19]
gpio
4.G
PIO
[25]
gpio
4.G
PIO
[18]
gpio
4.G
PIO
[24]
gpio
4.G
PIO
[23]
gpio
4.G
PIO
[17]
gpio
4.G
PIO
[22]
gpio
4.G
PIO
[16]
gpio
4.G
PIO
[26]
osc3
2k.3
2K_O
UT
ccm
.PM
IC_R
DY
usdh
c1.L
CTL
csi.M
CLK
usdh
c1.C
Dus
dhc1
.WP
usdh
c3.D
AT4
usdh
c3.D
AT5
usdh
c3.D
AT6
usdh
c3.D
AT7
usdh
c4.D
AT6
usdh
c4.D
AT7
usdh
c4.C
LKus
dhc4
.CM
Dus
dhc4
.DAT0
usdh
c4.D
AT1
usdh
c4.D
AT2
usdh
c4.D
AT3
usdh
c4.D
AT4
usdh
c4.D
AT5
tcon
.E_D
ATA
[0]
tcon
.E_D
ATA
[1]
tcon
.E_D
ATA
[2]
tcon
.E_D
ATA
[3]
tcon
.E_D
ATA
[4]
tcon
.E_D
ATA
[5]
tcon
.E_D
ATA
[6]
tcon
.E_D
ATA
[7]
tcon
.E_D
ATA
[8]
tcon
.E_D
ATA
[9]
tcon
.E_D
ATA
[10]
tcon
.E_D
ATA
[11]
tcon
.E_D
ATA
[12]
tcon
.E_D
ATA
[13]
tcon
.E_D
ATA
[14]
tcon
.E_D
ATA
[15]
tcon
.CL
tcon
.LD
tcon
.XD
IOL
tcon
.XD
IOR
tcon
.YCKR
tcon
.YO
ERtc
on.Y
DIO
UR
tcon
.YD
IOD
Rtc
on.Y
CKL
tcon
.YO
ELtc
on.Y
DIO
UL
tcon
.YD
IOD
Ltc
on.V
CO
M[0
]tc
on.V
CO
M[1
]tc
on.R
Ltc
on.U
Dtc
on.Y
CKL
tcon
.YO
ELtc
on.Y
DIO
UL
tcon
.YD
IOD
Lan
atop
.USBO
TG1_
IDan
atop
.USBO
TG2_
IDki
tten
.EVEN
TIki
tten
.EVEN
TOpw
m4.
PWM
Oua
rt2.
RXD
_MU
Xua
rt2.
TXD
_MU
Xua
rt2.
RTS
uart
2.CTS
uart
5.D
TRau
dmux
.AU
D4_
RXFS
audm
ux.A
UD
4_RXC
audm
ux.A
UD
4_RXD
audm
ux.A
UD
4_TX
Cau
dmux
.AU
D4_
TXFS
audm
ux.A
UD
4_TX
Dau
dmux
.AU
DIO
_CLK
_OU
Tec
spi2
.SCLK
ecsp
i2.M
OSI
ecsp
i2.M
ISO
ecsp
i2.S
S1
uart
5.RTS
uart
5.CTS
uart
5.RXD
_MU
Xua
rt5.
TXD
_MU
Xi2
c2.S
CL
i2c2
.SD
Agp
t.CAPI
N1
gpt.
CAPI
N2
gpt.
CM
POU
T1gp
t.CM
POU
T2gp
t.CM
POU
T3gp
t.CLK
INi2
c3.S
CL
i2c3
.SD
Aus
dhc1
.LCTL
usdh
c2.L
CTL
usdh
c3.L
CTL
usdh
c4.L
CTL
wdo
g2.W
DO
G_R
ST_
B_D
EBua
rt5.
RXD
_MU
Xua
rt5.
TXD
_MU
Xus
dhc3
.RST
usdh
c3.V
SEL
ECT
usdh
c3.W
Pus
dhc3
.CD
usdh
c2.R
ST
usdh
c2.V
SEL
ECT
usdh
c2.W
Pus
dhc2
.CD
usdh
c1.R
ST
usdh
c1.V
SEL
ECT
usdh
c1.W
Pus
dhc1
.CD
msh
c.SCLK
msh
c.BS
msh
c.D
ATA
[0]
msh
c.D
ATA
[1]
msh
c.D
ATA
[2]
msh
c.D
ATA
[3]
uart
4.RXD
_MU
Xua
rt4.
TXD
_MU
Xua
rt4.
RTS
uart
4.CTS
csi.M
CLK
osc3
2k.3
2K_O
UT
epit1
.EPI
TOua
rt5.
RTS
uart
5.CTS
uart
5.RXD
_MU
Xua
rt5.
TXD
_MU
Xsp
dif.
OU
T1sp
dif.
IN1
usdh
c2.W
Pus
dhc2
.CD
wdo
g1.W
DO
G_R
ST_
B_D
EBan
atop
.USBO
TG2_
IDan
atop
.USBO
TG1_
IDus
dhc1
.VSEL
ECT
epit1
.EPI
TOep
it2.E
PITO
gpt.
CAPI
N1
gpt.
CAPI
N2
gpt.
CM
POU
T1gp
t.CM
POU
T2gp
t.CM
POU
T3gp
t.CLK
INus
dhc3
.RST
usdh
c3.V
SEL
ECT
usdh
c3.W
Pus
dhc3
.CD
ccm
.PM
IC_R
DY
Revision history
Powering an i.MX 6SL based system using the PF3000 PMIC, Rev. 1.0NXP Semiconductors 19
5 Revision history
Revision Date Description of changes
1.04/2015 Initial release
7/2016 Updated to NXP document form and style
Information in this document is provided solely to enable system and software implementers to use NXP products. There
are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on
the information in this document. NXP reserves the right to make changes without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose,
nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be
provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including "typicals," must be validated for each customer application by the
customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells
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NXP, the NXP logo, Freescale, the Freescale logo, and SMARTMOS are trademarks of NXP B.V. All other product or
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© 2016 NXP B.V.
How to Reach Us:Home Page: NXP.com
Web Support: http://www.nxp.com/support
Document Number: AN5113Rev. 1.0
7/2016
