An ultra-low-voltage ultra-low-power CMOS active mixer

Amir Hossein Masnadi Shirazi • Shahriar Mirabbasi

Received: 31 March 2013 / Revised: 7 June 2013 / Accepted: 11 September 2013

� Springer Science+Business Media New York 2013

Abstract The scaling of CMOS technology has greatly

influenced the design of analog and radio-frequency cir-

cuits. In particular, as technology advances, due to the use

of lower supply voltage the available voltage headroom is

decreased. In this paper, after a brief overview of con-

ventional low-power CMOS active mixer structures, we

introduce an active mixer structure with sub-mW-level

power consumption that is capable of operating from a

supply voltage comparable or lower than the threshold

voltage of the transistor. In addition, the proposed archi-

tecture provides a performance and conversion gain (CG)

that compares favorably or exceeds those of the state-of-

the-art designs. As a proof-of-concept, a wide-band DC to

8.5 GHz down-conversion mixer is designed and fabricated

in a 90-nm CMOS process. Measurement results show that

the mixer achieves a CG as high as 18 dB while consuming

98 lW from a 0.3-V supply.

Keywords CMOS RF mixer � Ultra low power �Ultra low voltage � Wireless � Transceiver

1 Introduction

Mixers are among the important building blocks of many

communication systems and therefore a variety of mixer

structures have been proposed. Furthermore, since most

radio-frequency (RF) transceiver architectures use two or

more mixers, the power consumption of the mixer has a

considerable impact on the overall transceiver power

consumption. In addition, many transceivers use active

mixers since they provide a relatively high conversion gain

(CG). Conventional active mixer structures typically con-

sist of three stages, namely, the Gm stage (or the trans-

conductance stage), the switching stage, and the load stage.

These stages are usually stacked on top of each other and

thus operating from a low supply voltage is a challenging

task.

Figures 1 and 2 show the trend in supply voltage and

power consumption of the state-of-the-art active mixers

that are published over the last few years.1 As can be seen

from Fig. 1, in terms of supply voltage, the trend shows

approximately 85 mV per year reduction in the supply

voltage, however, the exponential trend line tends to level

off at around 0.8 V. From Fig. 2, the decrease in the power

consumption is around 0.8 mW per year, and the expo-

nential trend line flattens at around 1 mW. To further

reduce the supply voltage and power consumption, we will

first briefly discuss the relevant limitations of the conven-

tional active mixer structures and then propose solutions to

overcome these limitations.

Among the popular active mixer architectures, Gilbert-

type designs [1–3] are widely used due to their simplicity,

and reasonable CG, noise figure, and linearity. However,

Gilbert-type structures are not quite amenable to low-

voltage operation because of using stacked transistors

(refer to Fig. 3).

An alternative approach to lower the power consump-

tion is to operate the circuit in the subthreshold region [4].

Despite the ultra-low-power consumption of such circuits,

due to using stacked transistors the required supply voltage

A. H. M. Shirazi (&) � S. Mirabbasi

Department of Electrical and Computer Engineering, University

of British Columbia, Vancouver, BC, Canada

e-mail: amirms@ece.ubc.ca

1 The list of these publications is available at http://www.ece.ubc.ca/*amirms/mixer-trend.xlsx

123

Analog Integr Circ Sig Process

DOI 10.1007/s10470-013-0163-2

is still relatively high. Moreover, the linearity and noise

figure performance are compromised.

In this paper, we expand on our previous work [5] and

introduce a class of CMOS active mixer structures which

uses a multitude of techniques to achieve threshold-level

supply voltage and sub-mW-level power consumption

while maintaining a high performance. In the proposed

structure the dynamic power has a dominant role (as

opposed to conventional structures where the power is

mainly due to the static current). As a proof-of-concept, an

ultra-low-voltage ultra-low-power mixer that operates from

DC to 8.5-GHz is designed and fabricated in a 90-nm

CMOS process. The proposed mixer consumes 98 lW

from a 0.3-V supply while operating at 2.5 GHz. To

achieve low supply voltage and low power without com-

promising the performance the following techniques are

used: dynamic-threshold-voltage, inductive peaking, and

current-reusing (also known as current-bleeding). The

mixer achieves a CG of 18 dB with a typical LO power of

-7.5 dBm. The structure nominally operates in the sub-

threshold regime with a supply voltage of 0.3 V. The same

structure operates in the strong-inversion regime with a

supply voltage of 1 V.

The rest of the paper is organized as follows. First, we

present the proposed techniques that are used to reduce the

number of stacked transistors as well as techniques that are

used to improve the performance of the switching and Gm

stages. The circuit schematic of the proposed structure is

then presented. The performance of the proposed structure

is validated using a proof-of-concept prototype. Measure-

ment results and comparison to state-of-the-art designs are

also presented followed by some concluding remarks.

2 Proposed stack-reduction techniques

From the power consumption point of view, digital CMOS

systems are interesting structures. They have almost zero

DC power consumption and the main source of power

Fig. 3 Conventional double-balanced CMOS mixer with 4 stages of transistor and load resistor

0

1

2

3

4

1996 1998 2000 2002 2004 2006 2008 2010 2012 2014

Su

pp

lyV

olt

age

(V)

Year

Fig. 1 Supply voltage of reported active mixers (1997–2012). Supply

drops by approximately 85 mV per year

1

6

11

16

21

26

31

1996 1998 2000 2002 2004 2006 2008 2010 2012

Po

wer

Co

nsu

mp

tio

n (m

W)

Year

Fig. 2 Power consumption of reported active mixers (1997–2012).

Power consumption drops by around 0.8 mW per year, however, the

exponential trend line flattens out around 1 mW

Analog Integr Circ Sig Process

123

dissipation is the switching power (also known as dynamic

power). Often, when section of the circuit is not in use it is

turned off, and this can significantly reduce the power

consumption. Inspired by these two simple concepts and

the fact that we need switching in RF mixers, an alternative

low-power mixing methodology can be proposed as shown

in Fig. 4. Based on the LO value, each Gm stage turns on

for half of the LO period, pumps RF signal to the load

resistor and then turns off for the remaining half of the LO

period. As compared to the conventional active mixers in

which the Gm stage has a constant bias current, the pro-

posed technique does not require any DC bias in the Gm

stage and as will be shown the power consumption is

mainly dynamic in nature.

To find the CG of the proposed mixer, consider the

unbalanced mixer architecture shown in Fig. 4(a). The

transconductance of the Gm stage is dependent on the LO

value (state of the supply switches). When the Gm stage is

off, its transconductance is zero and while the Gm stage is

on, its transconductance starts to rise and reaches a maxi-

mum value. Figure 5 shows the transconductance of the Gm

stage as a function of time, namely, Gm(t).

To find the output voltage and the CG of the structure,

one can write:

VIF ¼ VRF � RL � Gm tð Þ¼ VRF � RL

� S0 þ S1 cos xLOtð Þ þ S2 cos 2xLOtð Þ þ � � �ð Þ ð1Þ

where Si factors are the Fourier coefficients of Gm(t). This

structure is a modified version of the structure proposed in

[6]. It can be shown that the CG of this structure can be

approximated as [7]:

CG ¼ S1:RL � sin cTsw

TLO

� �RLGm�max

p

� �ð2Þ

where Tsw is the rise (fall) time of the trapezoidal

approximation of Gm(t) and TLO is the period of the LO

signal (refer to Fig. 5). In terms of power consumption,

note that as compared to the conventional unbalanced-

mixer which uses a constant bias current over the period of

LO, here, we can save power during half of the LO cycle

(b)(a)

Fig. 4 Proposed low power

switching mixer. a Unbalanced

architecture. b Double-balanced

version

Fig. 5 Parabolic and

trapezoidal approximation of

transconductance of proposed

unbalanced-mixer versus time

Fig. 6 Implementation of switching stage with inverter

Analog Integr Circ Sig Process

123

when the Gm stage is turned off. Another benefit of this

type of mixer is that by proper choice of the switching

stage, the number of stacked transistors can be reduced. For

example, consider the case shown in Fig. 6 where the

switching stage is implemented using simple inverters.

Based on the value of the LO signal, the inverters are

toggling node X and Y to either VDD or GND and thus turn

the Gm stage on or off. As will be shown, one can reduce

the supply voltage of these inverters to as low as the

transistor threshold voltage while the inverters still provide

a full-swing operation.

Considering Fig. 6 and the fact that the Gm stage is

independent of the LO stage, the power consumption can

be written as

P ¼ PDynamic�Switch þ PStatic�Switch þ PDynamic�Gm

þ PStatic�Gmð3Þ

Taking into account that the DC power consumption in a

CMOS inverter is typically negligible and due to the small-

signal nature of the operation of the Gm stage (note that the

RF signal is a weak signal), the power consumption of this

stage is dominated by its static power, Eq. (3) can be

written as:

P ffi PDynamic�Switch þ PStatic�Gm

¼ a � fLO � C � V2DD þ IDC�Gm�Stage � VDD ð4Þ

where a or activity factor is the average number of

expected full transitions of the inverter output in each

cycle, fLO is the frequency of local oscillator, C is the load

capacitance of the inverter, IDC�Gm�Stage is the DC current

in the Gm stage, and VDD is the supply voltage. Equation 6

reveals that in contrast to a conventional mixer, a major

portion of the power consumption of the proposed class of

mixers is due to their dynamic power. Thus, in order to

reduce the power in a certain frequency, special attention

should be paid to the load capacitance as well as the supply

voltage.

3 Dynamic threshold MOS for ultra-low-voltage

inverter

For fast switching of the NMOS (or the PMOS) transistor

in an inverter, the input voltage should be high enough (or

low enough) to turn on the transistor. Furthermore, for an

inverter to operate from a low voltage supply and low input

swing, it is desired for the PMOS transistor to have a low

threshold voltage particularly when the input signal is low

and the PMOS is turned on. Similarly, it is desired for the

NMOS transistor to have a low threshold voltage, partic-

ularly when the input signal is high and the NMOS needs to

turn on. In other words, when PMOS transistor turns on and

the output signal starts rising to VDD, NMOS transistor

should be prepared to toggle back the output to GND and

vice versa. This preparation can be facilitated by dynamic

threshold adjustment of NMOS transistor. Such dynamic

threshold adjustment is a popular technique [8]. In dynamic

threshold approach the body effect of transistors is used for

adjusting their threshold voltage. The threshold voltage of a

typical NMOS or PMOS transistor can be expressed as:

Vth�NMOS ¼ Vth0 þ !ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2UF þ VSB

p�

ffiffiffiffiffiffiffiffiffi2UF

p� �ð5Þ

Vth�PMOS ¼ Vth0 � !ffiffiffiffiffiffiffiffiffi2UF

p�

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2UF � VBS

p� �ð6Þ

where Vth0 is the threshold voltage when the bulk-source

voltage is zero, 2UF is the surface potential,VSB is the

source-to-body voltage, and ! is the body-effect parame-

ter. For a 0.13-lm CMOS process, Fig. 7 shows the

threshold voltage of an NMOS device versus its VBS. The

point where VBS equals to the threshold voltage of the

device can be considered as the minimum supply voltage

which is required to change the state of an NMOS from off

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

VBS

VT

H

Fig. 7 Threshold voltage versus body-source voltage

0 50 100 1500

0.5

1

1.5

2

2.5

3

3.5

4

4.5x 10

-9

W/L

Ron

.Cou

t (se

c)

Fast Region

Supply Voltage Varies From 0.8 to 0.25 V

VDD

A

A

RON Cout

Cout

Fig. 8 RON 9 CP versus NMOS size and in different supply voltages

for a 0.13 process

Analog Integr Circ Sig Process

123

to on [8]. We denote this point as VDD-min. However, for

applications in which the input is a high-frequency signal,

we should take into account that to provide reasonable rise

and fall times at the output, the on-resistance of the device

should be low enough to charge or discharge the output

load in less than a half of the period of the signal. To find

the optimum size of the NMOS used in this low-voltage

inverter, we choose VDD-min as the supply voltage and tie

up the input of the inverter to the supply voltage. Then, by

sweeping WL

of the NMOS transistor and monitoring

Ron 9 Cout (where Ron is ON resistance of NMOS device

and Cout is the total capacitance seen at the output of the

inverter), the optimum size for the NMOS transistor can be

found as shown in Fig. 8.

Figure 9 various approaches to achieve dynamic-

threshold-voltage MOS (DTMOS) for an NMOS and

PMOS device of an inverter. As an example, in Fig. 9(a),

when node A toggles to VDD, the threshold voltage of the

NMOS transistor is lowered due to the body effect and

therefore it facilitates toggling of the output to ground (if

the input goes high). Note that it is assumed that a tech-

nology with triple-well option is available so that one can

have NMOS devices with local substrates. In effect, this

lowering of the threshold voltage improves the switching

transient of the circuit. With the same method for PMOS

transistors, for having a proper DTPMOS in an inverter the

body of the PMOS transistor can be connected to input of

the inverter as shown in Fig. 9(b).

Figure 10 compares the transient performance of a

standard CMOS inverter (graph B) with that of a DTMOS

inverter (graph A). At supply voltages of 0.5 and 0.8 V, the

outputs of the two inverters are shown in Fig. 10. As

expected, the dynamic-threshold-voltage adjustment is

effective in improving the rise and fall times as well as

extending the voltage swing of the output. As will be dis-

cussed, improving the switching transient and voltage

swing in the proposed mixer will improve the effective

transconductance of the Gm stage and thus will improve the

CG of the circuit.

4 Wideband switching

For wideband applications, it is desired to have inverters that

operate over a wide range of switching frequencies. Fur-

thermore, it is desired that the input power (LO power in this

context) does not increase and remains the same. However,

as switching frequency increases due to the low-pass

behaviour of the input, which is due to the input capacitance

of the inverter, the effective LO amplitude at the gate of the

VDD

LOCL

VDD

LOCL

A D

(a) (d)

C

VDD

LO

(c)

CL

VDD

LOCL

B

(b)

Fig. 9 a Inverter with dynamic-

threshold-voltage NMOS

(DTNMOS). b Inverter with

dynamic-threshold-voltage

PMOS (DTPMOS). c Inverter

with DTPMOS and DTNMOS.

d Conventional inverter

0 0.2 0.4 0.6 0.8 1 1.2 1.4x 10

-9

0

0.1

0.2

0.3

0.4

0.5

0.6Output Voltage of Inverter

Time (Sec)

Vol

tage

(V

)

A

B

0 0.2 0.4 0.6 0.8 1 1.2 1.4x 10

-9

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Time (Sec)

Vol

tage

(V

)

Output Voltage of Inverter

B

A

VDD = 0.5 V VDD = 0.8 VWith Dynamic Threshold VoltageWithout Dynamic Threshold Voltage

With Dynamic Threshold VoltageWithout Dynamic Threshold Voltage

(a) (b)

Fig. 10 Output voltage of the inverter with Wp = 200 lm, Wn = 100 lm, CL=1pF, 2.45 GHz (A) with dynamic threshold (DTMOS) inverter

(B) without dynamic threshold voltage

Analog Integr Circ Sig Process

123

input devices decreases. As a result, when the frequency is

increased, LO power should also be increased proportion-

ally. To extend the input bandwidth of the switching stage,

LO output voltage can be passively amplified by utilizing a

resonance circuit. Figure 11 shows the concept of resonance

amplification for the wideband inverter used in this work. To

find a proper value for the inductor, let us find the gate

voltage as a function of frequency:

IG ¼VLO

Rþ jxLþ 1jxC

) VG ¼VLO

Rþ jxLþ 1jxC

:1

jxC

¼ VLO

1� CLx2 þ jxRCð7Þ

jVGj ¼VLOj jffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

1� CLx2ð Þ2þ xRCð Þ2q ) jVGj

VLOj j ¼ GRðxÞ

¼ 1ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1� CLx2ð Þ2þ xRCð Þ2

q ð8Þ

GR

1

2pffiffiffiffiffiffiLCp

� �¼ GR�max ¼

1

xResRC) xRes ¼

1

GR�maxRC

ð9Þ

VDD

L

C

R VG

Zin

LO

VDD

(a)

C

R VG

Zin

LO

(b)

Fig. 11 a Conventional

inverter with a low-pass

response, b wideband inverter

10-1

100

101

0.01

0.1

1

10

100

Frequency (GHz)

Pas

sive

Gai

n Inverter with inductive peaking technique

Inverter without inductive peaking technique

Boosted Bandwidth

Fig. 12 Resonance passive-gainjVGjVLOj j

� �versus frequency

100 101 102 103 104108

109

1010

1011

1012

1013

Resonance Capacitance (fF)

Fre

q (H

z)

R = 50 ohm

C = 50 fFFreq = 10.5 GHz

C = 380 fFFreq = 5.8 GHz C = 851 fF

Freq = 3.9 GHz

C = 93 fFFreq = 10.1 GHz

C = 200 fFFreq = 7.9 GHz

Fig. 13 f ¼ 12pGR�maxRC

and f ¼1

2pffiffiffiffiffiffiLCp versus C and in fixed

L, R, and GR�max

Analog Integr Circ Sig Process

123

As shown in Fig. 12, the passive gain reaches its maximum

value at fRes ¼ 1ffiffiffiffiffiLCp . This maximum gain, namely GR�max,

would be infinity if R ¼ 0. However, in practical applications

R cannot be zero (or close to zero), otherwise, at resonance

frequency Zin ¼ 0 which impacts the LO generator (e.g.,

heavily loads the VCO). To find a practical value for GR�max,

let us draw f ¼ 12pGR�maxRC

and f ¼ 1

2pffiffiffiffiffiLCp simultaneously

versus C for a fixed values of L, GR�max, and R ¼ 50 X. The

intercept point of these graphs gives us the required C (C is the

input gate capacitance of the inverter which is directly related

to the size of the inverter) and frequency of resonance (or

maximum switching frequency). As can be seen from Fig. 13,

for frequencies less than approximately 10 GHz, it is possible

to achieve a passive gain of around 1–5 V/V while having a

practical value for on-chip L (\10 nH) and C (\1 pF) .

To choose a proper value for inductor, first, we optimize the

inverter sizing to achieve a full swing signal at their output

(refer to Sect. 3; Fig. 8). This will give us the input capacitance

of the inverter. Then, given the desired bandwidth of operation

and the input capacitance of the inverter the value of the

inductor can be calculated. In this work, the desired bandwidth

is 8.5 GHz and the input capacitance of the inverter is around

85 fF. These values will result to an inductor of 4 nH and the

resonance gain of 4.3 V/V at 8.5 GHz.

5 Gm-stage and the overall mixer architecture

Gm-stage structure should be chosen properly to maximize

the CG and linearity. Figure 14 shows 3 different possible

circuits for Gm stage.

Comparing these different solutions for the Gm stage, a

current reuse structure, shown in Fig. 14(d), can boost the

total transconductance from gmn or gmp to gmn ? gmp (that

is, from the transconductance of an NMOS or a PMOS, to

the summation of the transconductance of an NMOS and a

PMOS). In addition, this current reuse structure can operate

from a lower supply voltage while increasing the headroom

by using the current-bleeding technique [9], and improving

linearity by suppressing the second and third harmonics

using the complementary DS method [10–13]. Hence, in

comparison to the structures shown in Fig. 14(b, c), the

current-reusing structure has more advantages and thus it is

considered as for the Gm stage of the proposed mixer.

An important design consideration in this type of mixer

is to properly size the devices of the Gm stage. Having a

large transistor in this stage can increase the load capaci-

tance of the inverters which results in consuming higher

dynamic power. In addition, considering Fig. 15 as a

simplified model of the mixer and Fig. 16 as the generated

transconductance in the Gm stage versus time, gm;max should

be low enough such that 1gm;max

becomes much higher than

the RON of the inverters; otherwise, the voltage swing at the

inverter output will be compromised. As a reasonable

approximation, we choose RON to be 10 times lower than

maximum generated gm, that is:

RON �1

10� gm;max

:

Given the chosen architecture for the Gm stage, the

schematic diagram of the proposed double-balanced mixer

is shown in Fig. 17.

(b) (d)(a) (c)

Fig. 14 Different configurations in Gm-stage, a single balanced, b implementation with NMOS, c implementation with NMOS, dimplementation with current-reuse

Analog Integr Circ Sig Process

123

6 Conversion gain

Here, we present a detailed calculation of CG of the proposed

double-balanced mixer. Due to the variation of the source

voltage of the transistors in the Gm stage, the output current of

the Gm stage may have two components, drift (strong inversion)

and diffusion (sub-threshold). To be pessimistic and for ease of

calculation, we assume that gm in subthreshold is negligible.

If the VGS of transistors becomes higher than their threshold

voltage, then the current is mainly due to drift. To find gmn and

gmp, let us consider the typical waveform of the source voltage

of transistors (Node A or B in Fig. 17). A representative

waveform is shown in Fig. 18. In one LO period before t1 and

after t2 we can assume gmp is zero because VSG is less than

threshold voltage (ignoring the subthreshold effect), similarly

before t2 and after t3 gmn is zero VGS is less than threshold

voltage. Based on Fig. 18, VS(t) can be approximated with a

parabolic function. Thus, we can write:

gmn tð Þ ¼ Kn VBN � Vs tð Þ � Vthnð Þgmp tð Þ ¼ Kp Vs tð Þ � VBP � Vthp

� �(

Fig. 15 Simplified model of

inverters and their load during

turning ON the Gm stage

Fig. 16 Model of generated Gm

in NMOS or PMOS device

versus time

Fig. 17 The proposed double-balanced mixer

Analog Integr Circ Sig Process

123

and:

Vs tð Þ �VDD �

4 VBPþVthp�VDDð Þðt2�t1Þ2

t1þt22� t

� �2t1\t\t2

4 VBN�Vthnð Þt4�t3ð Þ2 t � t3þt4

2

� �2t3\t\t4

8<:

ð10Þ

Hence, over one period of LO signal, gmn and gmp can

be expressed as:

gmn tð Þ � Kn VBN � 4 VBN�Vthnð Þt4�t3ð Þ2 t � t3þt4

2

� �2�Vthn

� �t3\t\t4

0 else

(

Given the mixer architecture shown in Fig. 17 and

the Gm-stage structure used, the overall transconductance

for differential current-reuse structure, gm�CR tð Þ, and

the output voltage of the mixer can be approximated as:

gm�CR tð Þ ¼ gmn tð Þ þ gmp tð Þgm�total tð Þ ¼ gmn�CR1 tð Þ þ gmn�CR2 tð Þ þ gmp�CR1 tð Þ þ gmp�CR2 tð Þ

ð12ÞVout ¼ RL

2� gm�total tð Þ:VRF ð13Þ

Figure 19 shows gm�total versus time, by writing the

Fourier transform of gm�total tð Þ (which has a parabolic shape

in this approximation), the CG can be written in terms of LO

period (TLO), and rise/fall times of the inverter output (DToff).

a1 ¼1

TLO

ZTLO

0

gm�total tð Þ � cos2pTLO

t

� �� dt

¼gm0 TLO�DToff

� �pTLO

� a 1� cosp

TLO

TLO�DToff

� �� �� ��

þbsinp

TLO

TLO�DToff

� �� ��

¼gm0 TLO�DToff

� �pTLO

� f TLO;DToff

� �ð14Þ

CG � a1 � RL

2

¼ gm0 �RL

2p�

TLO � DToff

� �TLO

� f TLO;DToff

� �� �ð15Þ

Therefore, by improving DToff (rise/fall times of

the inverter output) the CG can be increased. As

discussed, using dynamic threshold technique further

improves DToff .

7 Power consumption

In this section, we analyse the power consumption of the

proposed mixer. As mentioned earlier, the dynamic power

consumption is a major portion of the total power of the

proposed mixer. To find the static power consumption of

the Gm stage, consider Fig. 20.

Referring to this figure, the power consumption of the

Gm stage can be written as

PGm�stage ¼ IP � VY þ IN � VX þ ðIN � IPÞ � VDD

¼ IP � VY þ ðIN � IPÞ � VDD

gmp tð Þ � Kp VDD �4 VBPþVthp�VDDð Þ

ðt2�t1Þ2t1þt2

2� t

� �2�VBP � Vthp

� �t1\t\t2

0 else

8<: ð11Þ

PMOS Strong Inversion Thresholdt3 t4

Strong Inversion Region for NMOS

Strong Inversion Region for PMOS

VBP+| Vthp|

VBN-VthnNMOS Strong Inversion Threshold

Weak Inversion Area

Weak Inversion

TIME

Voltage

VDD

t1 t2

Fig. 18 Simple model for

output voltage of inverters at

switching stage (Node A or B

in Fig. 17)

Fig. 19 Parabolic approximation for overall transconductance

Analog Integr Circ Sig Process

123

Considering that VX þ VY ¼ VDD, the equation can be

rewritten as:

PGm�stage ¼ IP � ðVDD � VXÞ þ ðIN � IPÞ � VDD

¼ IN � VDD � IP � VX ¼ IN � VDD

As shown in Fig. 21, IN has a square waveform with a

50 % duty cycle and thus the average power (i.e., DC

power) of the Gm-stage can be written as:

PDC�Gm�stage ¼IN�max

2� VDD ¼

KNWLN

VBN � Vth;n

� �2

2� VDD

where, KN ¼ lnCox is the process transconductance

parameter. Thus, for a single balanced mixer

configuration, the power consumption can be written

as:

P ¼ PDynamic�Switch þ PDC�Gm�stage

¼ a � fLO � C � V2DD þ

IN�max

2� VDD

¼ 2 � fLO � C � V2DD þ VDD �

KNWL

� �N

VBN � Vth;n

� �2� �

2

¼ VDD � 2 � fLO � C � VDD þKN

WLN

VBN � Vth;n

� �2

2

!

ð16Þ

Figure 21 shows the power consumption versus supply

voltage for the proposed double-balanced mixer.

Note that the bias voltages VBN and VBP (refer to

Fig. 17) have been adjusted for each supply voltage to

achieve the maximum CG for that supply volatge. As

can be seen in superthreshold region the rate of the

change of the curve increases due to the static power

whereas in the subthreshold region, the static power is

negligible and the dynamic power is the main

contributor.Fig. 20 Current and voltage shapes in Gm-stage

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

0.5

1

1.5

2

2.5

3

3.5

4x 10

-3

Supply Voltage (V)

Pow

er C

onsu

mpt

ion

(W)

Frequency from 7.5Ghz to 1.5 Ghz

SubthresholdDynamic-power is dominant

Less Than 1mW

SuperthresholdPower Consumption is both Dynamic and Static

Fig. 21 Simulation results of

the power consumption of the

proposed mixer implemented in

a 0.13-lm CMOS process.

Power is plotted versus supply

voltage for different frequencies

Analog Integr Circ Sig Process

123

8 Linearity of the Gm stage

As discussed earlier, the current reusing technique is used in

the Gm stage to achieve both higher transconductance and

higher gain. In addition to gain improvement, this block has

interesting properties in terms of linearity and can simulta-

neously improve second- and third-order distortions by

incorporating the modified derivative superposition (DS)

technique [12]. The DS method is a popular technique for

improving the linearity of various RF blocks including the

LNA, the mixer, and the power amplifier and has been around

since 1996 [14]. Here, we briefly explain the approach.

Consider a common-source NMOS stage which is

biased in saturation. In the context of small-signal analysis,

the output current of the NMOS device can be described as:

iOut ¼ gm1vGS;i þ gm2v2GS;i þ gm3v3

GS;i þ . . . ð17Þ

where Gm1, Gm2, and Gm3 are the first-, the second-, and the

third- order transconductance of the device and are defined as :

gm1 ¼oID

oVGS

; gm2 ¼1

2

o2ID

oV2GS

; gm3 ¼1

6

o3ID

oV3GS

ð18Þ

Considering (17), third-order input-referred intercept

point (IIP3) can be written as:

IIP3 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi4

3

gm1

gm3

s

ð19Þ

In the conventional DS method, the objective is to cancel

the third-order harmonic of the output signal of the transistor

by strategically combining the device with one or more

auxiliary devices (of the same type) which have different

biases [14]. The combined device then has a lower third-

order distortion. However, the main drawback of the

conventional DS method is that since gm2 of the devices

are added constructively, the technique typically results in a

large second-order distortion [12]. As an alternative solution

and to reduce gm3 in an NMOS device, an auxiliary PMOS

device (same as current-reuse structure) can be used which

generates complementary transconductance derivaties [12].

Figure 22 compares gm2 and gm3 of an NMOS and a PMOS

transistors. As can be seen, the PMOS and the NMOS

transistors have complementary characteristics for specific

gate biasing values. Thus, they can be used together for

simultaneous attenuation of both gm2 and gm3.

Figure 23 shows an intuitive time-domain explanation

for improved linearity in the current-reuse mixer. The

current-reuse structure similar to a class-AB push–pull

amplifier. When the input signal goes low, the PMOS

device enters its linear region and the NMOS becomes

more nonlinear, however their nonlinear terms of the two

devices are such that they minimize the second- and third-

order terms. When the input signal increases the nonlinear

terms of the PMOS device will reduce the overall nonlin-

earity of the combined NMOS and PMOS device.

Fig. 22 gm2 and gm3 of PMOS and NMOS devices

VRF

Cd

VDD

VRF

Cd Cd

Nonlinear Terms

Nonlinear Terms

Fig. 23 Complementary operation of PMOS and NMOS causes current reuse to achieve higher linearity

Analog Integr Circ Sig Process

123

9 Measurement results

Figure 24 shows the schematic of the implemented proof-

of-concept prototype mixer in a 90-nm process. (Note that

although the simulation results presented so far and those

presented in [5] are based on a 0.13-lm CMOS technology,

the proof-of-concept prototype is implemented in a 90-nm

CMOS process.) To facilitate measurement, two active

baluns have been designed at the input stage which use

different supply voltage terminals than those of the mixer

core. Finally, in the output stage two common-drain buffers

are designed to drive the 50-X load of the test equipment.

In the proof-of-concept prototype circuit (Fig. 24), the

voltage gain of the RF active balun at 1 GHz is set to cancel

the loss of the common-drain buffer at the IF frequency (set

to 50 MHz for all measurements); i.e., the voltage gain of the

combined balun and buffer is 1 V/V. Therefore, the overall

gain of the system for an RF signal of 1 GHz and the IF signal

of 50 MHz is equal to the CG of the mixer for the same RF

and IF frequencies. However, at higher RF frequencies

(beyond 1 GHz) the overall gain of the balun and the output

buffer will be less than 1 V/V and thus to have a fair com-

parison with the case when the RF signal is at 1 GHz, this

loss has to be taken into account in the CG measurements. In

addition, differential voltage gain of the LO balun is adjusted

to 1 V/V at 1 GHz. Thus, at frequencies higher than 1 GHz

the LO balun differential gain is less than 1 V/V and hence in

the LO power measurement this loss has to be taken into

account. It should be noted that based on the simulations for

the 90-nm CMOS circuit, the abovementioned loss in either

RF or LO path is less than 2.73 dBm.

To have a wideband circuit, the inductor LRES = 4 nH

is used in the LO stage to resonate with the input capacitance

of the inverters at 8.5 GHz. Table 1 shows the component

values of the mixer core. Figure 25 shows the chip

micrograph.

Fig. 24 Schematic of implemented mixer in a 90 nm process

Table 1 Mixer core component values

Component Value

RL (kX) 5

Wp, Gm-stage (lm) 24

Wn, Gm-stage (lm) 18

Cd (pF) 2

Wp, inverter (lm) 20

Wn, inverter (lm) 14

L, Gm-stage (nm) 100

L, inverter (nm) 200

Fig. 25 Layout and chip photograph of proposed mixer in a 90 nm

process

Analog Integr Circ Sig Process

123

As mentioned, in all CG measurements, the IF fre-

quency is set to 50 MHz. Figure 26 shows the CG of the

proposed mixer versus different supply voltages (the

nominal supply voltage for this 90-nm CMOS process is

1 V). In this figure, the frequency of operation is 2.5 GHz

and the differential LO power at the input of the inverters is

-5 dBm. Table 2 shows the bias configuration in the Gm

stage. As can be seen, it is possible to achieve a high CG

1 2 3 4 5 6 7 8 9 109

10

11

12

13

14

15

16

17

18

19

Frequency (GHz)

Con

vers

ion

Gai

n (d

B)

Measurement ResultsSimulation Results

VDD

= 350 mV

-8.5dB < PLO

<-6dB

Fig. 27 Measurement and simulation results—conversion gain ver-

sus frequency. IF is 50 MHz

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 15

10

15

20

25

30

Supply Voltage (V)

Con

vers

ion

Gai

n (d

B)

Frequency = 2.5 GHZ

PLO = - 5 dBm

For Voltages less than 0.45 V, VBN is equal to VDD and VBP is 0 V

For Voltages higher than 0.45 V, independent bias voltages is required for VBP and VBN

Fig. 26 Measurement results—conversion gain versus supply

voltage

Table 2 Mixer core bias condition in different supply voltages

VDD-2 VLO VBN VBP

0.2 0.1 0.2 0

0.35 0.1 0.35 0

0.45 0.2 0.45 0

0.55 0.2 0.5 0.1

0.65 0.3 0.5 0.2

0.8 0.4 0.4 0.4

0.9 0.45 0.45 0.45

1 0.5 0.5 0.6

-15 -10 -5 010

11

12

13

14

15

16

17

18

19

LO Power (dBm)

Con

vers

ion

Gai

n (d

B)

VDD = 350 mV

Freq = 2.5 GHz

Fig. 28 Conversion gain versus LO power

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

Supply Voltage (V)

Pow

er C

onsu

mpt

ion

(mW

)

Fig. 29 Measurement results—power consumption versus supply

voltage at 2.5 GHz

1 2 3 4 5 6 7 8 950

100

150

200

250

300

350

Frequency (GHz)

Pow

er C

onsu

mpt

ion

(uW

)

Measurement ResultsSimulation Results

VDD = 350mVPLO = -8 dBm

Fig. 30 Measurement and simulation results—power consumption

versus input frequency

Analog Integr Circ Sig Process

123

([10 dB) from a low supply voltage (*0.2 V). One

interesting feature about this mixer structure is that for

voltages less than 0.45 V, there is no need for any addi-

tional bias voltage in the Gm stage as in such cases VBN can

be set to VDD and VBP can be set to zero. This issue

facilitates the low-voltage design process.

Figure 27 shows the CG of the structure versus fre-

quency and compares that with simulation resutls. Here,

the mixer core supply voltage is 0.35 V and the diff-

rential LO power is between -6 and -8.5 dBm. As

expected, the CG drops rapidly after the resosance fre-

quency of 1

2pffiffiffiffiffiffiffiffiffiffiffiffiffiffiLRES �CG

p ¼ 8:5GHz which is mainly

attributed to the poor switching of the inverters at higher

frequencies.

Figure 28 shows the CG versus the differential LO

power at 2.5 GHz and 0.35 V supply. Figure 29 shows the

CG of the mixer core versus the supply voltage. The input

frequency is 2.5 GHz and the IF is 50 MHz. The values for

VBP and VBN are the same as those given in Table 2.

Similar to the simulation results, the power consumption is

a parabolic function of the supply voltage. As mentioned,

this is mainly due to the dominance of the dynamic power

of the inverters. Interestingly, for supply voltages less than

0.65 V the power consumption is below 1 mW and for

0.3 V supply, the mixer consumes as low as 98 lW and

provides a CG of 16.5 dB.

Figure 30 shows the power consumption versus fre-

quency for both measurement and simulation results. In

this case, the supply voltage is 0.35 V. VBN is equal to

Table 3 Measured IIP3 versus supply voltage

Supply

voltage (V)

IIP3 without

complementary DS (dBm)

IIP3 with

complementary DS

(dBm)

0.35 -4.4 NA

0.55 -2.3 6.3

0.65 -2.5 7.6

0.9 -0.3 8

Fig. 31 Tow tone

measurement, in this VDD is

0.55 V, VBP is 0 V, and PMOS

transistor operates in strong

inversion

Fig. 32 Tow tone

measurement, in this VDD is

0.55 V, VBP is 0.1 V, and

PMOS transistor operates in

weak inversion

Analog Integr Circ Sig Process

123

supply voltage and VBP is zero. Also, LO power is -8

dBm. As can be seen from the figure, the power con-

sumption is almost a linear function of the frequency.

Table 3 shows the measured IIP3 for different supply

voltages. As can be seen, the IIP3 improves at higher

supply voltages. This can be attributed to two significant

effects. First, IIP3 is directly proportional to the over-

drive voltage and hence a higher supply voltage provides

a higher linearity. Second, as mentioned earlier, in a Gm

stage, if the PMOS transistor operates in a complemen-

tary operating point with respect to the NMOS transistor

(the complementary operating point is achieved when the

PMOS is biased in the weak inversion) then it can sig-

nificantly suppress the third and second harmonics. Thus,

the supply voltage should be high enough to let us adjust

VBP and VBN to achieve the linearity sweet-spot. Fig-

ure 31 shows two-tone measurement of the mixer with a

0.55 V supply. In this figure, VBP is 0 V and the PMOS

operates in its strong inversion region. Figure 32 shows

the same measurement when VBP is 0.1 V. As can be

seen from the figure, when the PMOS operates in the

weak-inversion, the third-order harmonic can be signifi-

cantly suppressed. Tables 4 and 5 present the summary

of measurement results in 2.5 and 7.5 GHz.

To compare the overall performance of the proposed

mixer with that of the state-of-the-art designs, two different

figures of merit (FOMs) are used. The first FOM empha-

sizes on the supply voltage while the second one is a

standard FOM widely used for mixers [4]. Based on

Table 6, the performance of the proposed mixer compares

favorably with the state-of-the-art designs.

FOM1 ¼ 10 log10

CG�2NFþIIP3�10�PLOð Þ20

VDD

1:2V � PDC

� fRF

1GHz

!

FOM2 ¼ 10 log10

CG�2NFþIIP3�10�PLOð Þ20

PDC

� fRF

1GHz

!

Table 4 Performance of implemented 90 nm Mixer in 2.5 GHz and

IF of 50 MHz

Case 1:

sub-

threshold

Case 2:

sub-

threshold

Case 3:

weak

inversion

Case 4:

super-

threshold

Case 5:

super-

threshold

VDD(V) 0.35 0.45 0.5 0.8 1

VBN(V) 0.35 0.45 0.47 0.4 0.45

VBP(V) 0.00 0.00 0.00 0.4 0.6

PLO(dBm) -7 -6.2 -7.3 -7.5 -9

NF(dB) 10.4 10.2 11.2 10 8.45

CG(dB) 18.3 19.6 21.2 25.2 23.9

IIP3(dBm) -4.4 -3.3 3.4 7.4 8.1

PDC(mW) 0.11 0.279 0.37 1.84 5.1

Table 5 Performance of implemented 90 nm Mixer in 7.5 GHz and

IF of 50 MHz

Case 1:

sub-

threshold

Case 2:

sub-

threshold

Case 3:

weak

inversion

Case 4:

super-

threshold

Case 5:

super-

threshold

VDD(V) 0.35 0.45 0.5 0.8 1

VBN(V) 0.35 0.45 0.47 0.4 0.45

VBP(V) 0.00 0.00 0.00 0.4 0.6

PLO(dBm) -6.1 -6.2 -7 -7 -7.2

NF(dB) 9.2 9.1 10.2 12 9.2

CG(dB) 15.2 16.2 18 20.1 19.4

IIP3(dBm) -8.4 -4.4 1.2 5.25 6.1

PDC(mW) 0.265 0.4 0.5 2.1 6.2

Table 6 Performance summary and comparison among low power mixers

Parameters This work This work This work Ref. [6] Ref. [4] Ref. [15] Ref. [16]

LO-Gm architecture Separated Separated Separated Separated Stacked Folded Folded

LO-Gm separation method DTMOS inverter DTMOS inverter DTMOS inverter Conventional inverter N/A N/A N/A

Gm-stage Current reuse Current reuse Current reuse NMOS NMOS Current reuse NMOS

RF (GHz) DC-8.5 GHz DC-8.5 GHz DC-8.5 GHz 2.01 2.4 2.4 8.6

IF (MHz) 50 50 50 10 60 1 4350

PLO(dBm) -7.5 -7.5 -7.5 -4 -9 -2.0 -3.3

VDD(V) 0.3subthreshold 0.35 0.5 1 1 subthreshold 1.8 0.6

PDC(mW) 0.098@2.5 GHz 0.110@2.5 GHz 0.37@2.5 GHz 0.49 0.5 8.1 0.6

DSB NF (dB) 13.1 10.4 11.2 23.7 18.3 12.9 15.9

IIP3(dBm) -6@2.5 GHz -4.4@2.5 GHz 3.4@2.5 GHz 7 -9 1 -8

Conversion gain (dB) 16.5 18.3 21.2 9.8 15.7 15.7 6

CMOS technology (nm) 90 90 90 180 130 130 130

FOM1/FOM2 41/34.97 44.2/38.8 41.95/38.15 18.62/17.83 22.15/21.36 14.41/16.17 24.32/21.31

Analog Integr Circ Sig Process

123

10 Conclusion

An ultra-low-power ultra-low-voltage CMOS mixer is pre-

sented which can operate with sub-mW-level power con-

sumption and threshold-voltage-level supply voltage. The

number of stacked transistors have been reduced by using

switching transconductance technique; the gain and the lin-

earity of the circuit have been improved by current-reusing

technique; the required LO power and supply voltage have

been decreased by utilizing DTMOS devices; and inductive

peaking has been used to extend the bandwidth while

reducing the required LO power. In contrast to conventional

current-commutating mixers which consume static power,

dynamic power has a dominant role in the proposed mixer.

Acknowledgments This research is supported in part by the Natural

Sciences and Engineering Research Council (NSERC) of Canada.

CAD tools and access to technology are facilitated by CMC Micro-

systems. The authors would also like to thank Dr. Roberto Rosales

and Hooman Rashtian for their technical assistance, and Roozbeh

Mehrabadi for CAD tool support.

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Amir Hossein Masnadi Shir-azi Received the B.Sc. degree

(with honors) in Electrical

Engineering from Tehran Uni-

versity, Tehran, Iran, in 2011. In

January 2011 he joined

IED laboratory at university of

Tehran where he designed and

implemented wireless data log-

gers for solar cell power con-

verters. Since September 2011,

he has joined the Department of

Electrical and Computer Engi-

neering, University of British

Columbia, Vancouver, BC,

Canada where he is currently a Master student. In October 2012 he

joined Kapik Integration, Toronto, Canada, as an internship where he

worked on different blocks of large multi touch screens. His area of

research include analog, RF, and mm-wave integrated circuit and

system.

Shahriar Mirabbasi Received

the B.Sc. degree in Electrical

Engineering from Sharif Uni-

versity of Technology, Tehran,

Iran, in 1990, and the M.A.Sc.

and Ph.D. degrees in Electrical

and Computer Engineering from

the University of Toronto, Tor-

onto, ON, Canada, in 1997 and

2002, respectively. Since

August 2002, he has been with

the Department of Electrical and

Computer Engineering, Univer-

sity of British Columbia, Van-

couver, BC, Canada where he is

currently an Associate Professor. In 2008, he was a visiting Professor

at the Swiss Federal Institute of Technology (ETH) Zurich, and

subsequently in 2009 at the Laboratoire de l’Integration du Materiau

au Systeme (IMS Lab), Bordeaux, France. His current research

interests include analog, mixed-signal, RF, and mm-wave integrated

circuit and system design with particular emphasis on communica-

tion, sensor interface, and biomedical applications.

Analog Integr Circ Sig Process

123