ARTICLE IN PRESS

0026-2692/$ - se

doi:10.1016/j.m

�CorrespondE-mail addr

marques@fama

Microelectronics Journal 38 (2007) 1082–1094

www.elsevier.com/locate/mejo

An operational amplifier model for evaluating test strategies atbehavioural level

Eduardo Romeroa,b,�, Gabriela Perettia, Carlos Marquesb

aElectronics and Control Research Group, Facultad Regional Villa Marıa, Universidad Tecnologica Nacional, Avda Universidad 450,

5900 Villa Marıa, ArgentinabElectronics and Instrumentation Development Group, Facultad de Matematica, Astronomıa y Fısica, Universidad Nacional de Cordoba,

Medina Allende y Haya de Torre, 5000 Cordoba, Argentina

Received 18 May 2006; received in revised form 29 August 2007; accepted 30 August 2007

Available online 10 October 2007

Abstract

This paper proposes a new operational amplifier model for evaluating test strategies at behavioural level. Major modifications on a

previously reported model for improving its performance and for allowing reliable fault simulations are presented here. The new model

presents a set of very appealing characteristics for behavioural-level fault injection and simulation.

The matching between the behavioural-level model and a transistor-level one is evaluated for validating the model. We suggest the use

of the model early in the design process, when the schematic of the circuit is not available for the test engineer and only the specifications

are given. The model is also useful for evaluating different test alternatives for commercial operational amplifiers or standard cells

designed by others vendors. The paper addresses two application examples and shows the usefulness of the model for evaluating test

strategies when only the specifications of the circuit are available.

r 2007 Elsevier Ltd. All rights reserved.

Keywords: Behavioural analogue modelling; Operational amplifiers; Fault simulation; Testing

1. Introduction

The rapid development of integration technologies hasallowed the implementation of analogue and digitalfunctions in mixed-signal integrated circuits. Usually, theanalogue sections require a small area, but are hard to testdue to the frequently low observability of the internalnodes and the complex nature of the involved signals [1].This produces an increased impact on the overall cost ofthe circuits.

It is accepted by the test community that the test planmust be considered early in the design cycle for avoidingcostly and tedious modifications in later design stages.However, the traditional test evaluations based onstructural fault injection are difficult to perform as thecircuit schematic is usually not available early in the

e front matter r 2007 Elsevier Ltd. All rights reserved.

ejo.2007.08.006

ing author. Tel.: +54353 4537500; fax: +54 353 4535498.

esses: gisec@frvm.utn.edu.ar (E. Romero),

f.unc.edu.ar (C. Marques).

developing process. A similar situation arises (from the testviewpoint) in systems requiring off-the-shelf integratedcircuits or standard cells designed by third part vendors.For these cases, the implementation of alternative methodsfor evaluating and comparing different test strategiesbecomes necessary. A way for performing these evaluationsis to adopt a behavioural-level model for the Circuit underTest (CUT) and a fault model compatible with thisabstraction level.By other way, critical applications, such as spatial,

military or nuclear, could require in-field periodic testing.These tests are usually oriented to detect deviations in thespecifications beyond the acceptable limits imposed by theapplication. It is well known that circuit parameters exhibitdeviations during the operation under chemical, thermal ormechanical stress [2–4]. Ionizing radiation also causessevere changes in the circuit behaviour and a considerableresearch effort has been devoted to establish the deviationsin the specifications versus the severity of the exposition[5,6]. In these cases, the fault mechanisms at transistor level

ARTICLE IN PRESSE. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094 1083

are usually unknown or at least are very difficult toestablish, preventing traditional test evaluations. However,the variation in the specifications has been determined for anumber of commercial circuits. This information can beused with behavioural-level models for evaluating if a giventest strategy is able to detect deviations in the circuitspecifications that may cause a system failure.

In this work, we propose a new behavioural-leveloperational amplifier (OA) model for evaluating teststrategies early in the design process. The model presentedhere is also useful for the evaluation of test schemesaddressing applications based on off-the-shelf componentsor standard cells. Preliminary results of this research havebeen presented in [7].

The paper is organized in seven sections. In Section 2, wepresent a discussion on previous work related to theuse of OA behavioural models for fault simulations.In Section 3, we analyse the OA model being theconceptual starting point for the new one discussed inSection 4. The model validation adopting a previouslydesigned CMOS Folded Cascode OA is presented inSection 5. Two application examples illustrate the use ofthe model for evaluating test strategies in Section 6.Finally, Section 7 concludes the paper.

2. Previous work

Several authors propose the use of behavioural-levelmodels for the CUT and a fault model compatible with thisabstraction level for evaluating test strategies. Usually, theobserved effects of hard faults injected in the schematic aremathematically modelled and included in the behavioural-level model of the CUT. For implementing these proposals,the schematic of the OA has to be available for generatingboth the fault model and a convenient CUT model able tosupport the injection of behavioural faults [8–10]. Thisbecomes the main drawback of this approach because themethod is impossible to apply early in the design cycle orwhen off-the-shelf OAs are used. Additionally, thesemodels are frequently restricted to AC [11] or DCsimulations [12], or valid for a few closed-loop configura-tions [13]. This fact complicates the test generation andevaluation for cases requiring transient analysis or otherconfigurations.

The complexity of the OA models required for faultsimulations at behavioural level can be considerablyreduced if the fault effects are grouped. The author of[14] presents three groups of faults for OAs embedded insample-and-hold circuits: faults affecting input impe-dances, differential gain and output impedance. A differentapproach is proposed by Huang et al. in [15]. They use anOA model described at Laplace transfer-function level anda fault model based on the consideration that faults atstructural level will produce deviations in the transfer-function coefficients. The main limitation of the model is itsrestriction to small signal simulations.

Structural macromodels [16–18] could be used forinjecting faults at behavioural level by means of deviationsin the parameters of the model components. The maindrawbacks of this approach are that many importantcharacteristics of real OAs are neglected and that there isno straightforward relation between the specifications andmodel parameters. In [19], Maxim et al. present a modelthat overcomes the above-appointed drawbacks,but the discussion of this model is postponed to the nextsection.The authors of [20] propose the use of a simple two-stage

structural OA macromodel and a fault model for generat-ing input vectors for a given test scheme. For faultinjection, they suggest to introduce single deviations inthe OA specifications, previously to the model generation.However, the methodology presents the above-mentioneddrawbacks related to the use of macromodels. Addition-ally, the model has to be recalculated for each injected faultand it cannot be easily simplified if the test engineer needsto model only a subset of the OA characteristics.

3. Model analysis

In this section, we analyse the behavioural-level OAmodel proposed by Maxim et al. [19] because it is theconceptual starting point for the one suggested here. TheMaxim’s model is based upon the analogue behaviouralmodelling (ABM) library available in modern SPICEsimulators. A simplified version of this model is depictedin Fig. 1. In this figure, the block SUM adds the effects ofthe differential gain (ADIFF), the common-mode gain(ACOM), and the positive and negative power supplyrejection ratios (PSRR+ and PSRR�). The offset voltage(VOFF) is referred to the input.The blocks composed by HDIF-EDIF and HCOM-

ECOM model the effects of the common-mode anddifferential-mode input impedances. In the same way,HROUT and EROUT model the output impedance.Laplace blocks available in the ABM library allowmodelling these impedances in the frequency domain.The SRL block models the slew-rate limitation effects andESAT take into account the output saturation effects.Other characteristics included in the original model, suchas thermal effects and noise, are not shown here in order toobtain clear explanations.This model presents very appealing characteristics for

fault injection and simulation at behavioural level. Amongothers, the model is fully behavioural and includes somereal OAs characteristics neglected in other models. Byother way, it only needs the OA specifications, whichexhibit a straightforward relation with the model para-meters. The model topology also allows injecting devia-tions (faults) in a functional parameter (FP) without theneed of reformulating the whole model. Finally, themodularity of the model lets to simplify it in an easyway, if the test engineer is interested only in a subset ofcharacteristics.

ARTICLE IN PRESS

ADIFF

OUTIN

SRL INPUT SRL OPUTPUT ESAT

OUT+

OUT-

IN+

IN-

+

-

PSRR-

+

-

PSRR+

+

-

EDIFF

+

-

EDIFF

R+

d/dt

+SLEWMAX

-SLEWMAX

R-

INTEG

HCOM

VOFF

HDIFF

+

-

ECOM

SUM

IN1IN2

IN3IN4

OUT

ACOM

OUT+OUT-

IN+IN-

HROUT

+

-

EROUT

Vi+

Vi-

VDD

VSS

Vout

DIFF

SRL BLOCK

Fig. 1. Simplified version of Maxim’s OA model.

Time (sec)

0 50u 100u 150u 200u 250u 300u

Vin Vout

-4.0

0

4.0

Vo

lta

ge

(V

)

Fig. 2. Output response of the original OA model under saturation condition.

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–10941084

3.1. Detected problems and drawbacks

Despite the above-appointed appealing characteristicsfor fault injection and simulation, the model exhibits thefollowing problems.

3.1.1. DC behaviour

The normal operation of the block SRL eliminates theDC signals present at the input of this block because it hasa differentiator in the signal path (DIFF in Fig. 1).Consequently, the model does not reproduce the DCbehaviour of real OAs. The offset voltage is also notobservable at the output. For evidencing these problems,we configure the model as voltage follower obtaining an

offset voltage of 700 nV for grounded input (expectedvalue: 50mV). For the same configuration, an outputvoltage of 14 mV is obtained when the input is fixed to 1V(expected value: 1V).

3.1.2. Saturation effects

Under saturation conditions, the block ESAT limits theoutput signal and the differential voltage at the modelinput grows up rapidly. The block ADIFF amplifies thissignal, normally by a factor higher than 1000 for generalpurpose OAs. When this signal is limited at the saturationlimits, the output strongly departs from the behaviour ofreal OAs. In Fig. 2, we show the output of the model under

ARTICLE IN PRESS

Input voltage (v)

-300m -200m -100m 0 100m 200m 300m

Transistor Model

-2.0

0

2.0

(-256.522m, 1.7149)

(-260.000m, 2.2798)

Ou

tpu

t vo

lta

ge

(v)

Transistor

Model

Fig. 3. Output dynamic range for a real OA and for the original model.

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094 1085

saturation conditions. For this evaluation, the OA isconfigured as inverter with unity gain.

3.1.3. Output dynamic range

The output dynamic range of the model is considerablylower than the real OAs, particularly when high outputresistance OAs are being modelled. For these cases, whenthe saturation limits are reached the voltage drop in theoutput resistance causes this divergence. The problem isdepicted in Fig. 3. For this evaluation, the OA is configuredas inverter with gain equal to 10.

3.1.4. Input and output impedance networks

The differential- and common-mode input impedancesand the output impedance are modelled at Laplacetransfer-function level. This complicates the model andincrements the simulation time. Additionally, this model-ling style makes difficult the translation from specificationsto model parameters.

4. New behavioural model

In order to overcome the above-appointed problems, wepropose a set of major changes in the model. As a result, anew behavioural-level OA model, depicted in Fig. 4, isobtained.

RCOM1, RCOM2, CCOM1, CCOM2, RDIF andCDIF model the input differential- and common-modeimpedances. In this way, the complexity of the originalmodel is reduced. We also solve some convergenceproblems observed in our experiments with the originalmodel, related to the use of Laplace blocks.

The differential-mode signal is obtained from the inputvoltages by SUB1 and then is processed by ADIFF, whichrepresents the differential-mode frequency response of theOA. ADIFF is implemented using a Laplace block and (formost of the internally compensated OAs) it can beadequately modelled by the following transfer function:

ADIFFðsÞ ¼ADIFF0

½1þ s=ð2pf 1Þ�½1þ s=ð2pf 2Þ�(1)

In this expression, ADIFF0 is the DC differential gain, f1 isthe frequency of the dominant pole, f2 is the frequency of thesecond pole and s denotes the Laplace variable. The datarequired for implementing ADIFF are obtained from themanufacturer data sheet (for off-the-shelf integrated circuits),by simulations (if the structural-level model is available) orby means of experimental procedures if necessary. Theparameters are easily loaded in the model using the graphicalinterfaces available in modern SPICE simulators. Morecomplex frequency responses can be reproduced by addingzeroes and high-frequency poles to (1).In order to obtain the common-mode signal, the input

voltages are added by SUM1 and then are processed by theACOM block, which represents the common-mode fre-quency response. Since SUM1 performs only the additionof the two input voltages, the output signal of this block isdivided by two for obtaining the common-mode signal. Inour model, this operation is implemented by adjusting theDC gain of ACOM. The common-mode gain transfer-function ACOM(s) can be obtained from the followingrelation:

ACOMðsÞ ¼ADIFFðsÞ

CMRRðsÞ. (2)

In (2), CMRR(s) is the common-mode rejection ratiotransfer function, which can be obtained from the OA datasheet, frequently in the form of Bode plots. From theseplots, CMRR(s) can be synthesized in a very straightfor-ward way.Frequently, CMRR(s) can be adequately modelled as a

transfer function with a DC gain (CMRR0) and a pole (f3)located at higher frequency than the first pole of ADIFF(s):

CMRRðsÞ ¼CMRR0

½1þ s=ð2pf 3Þ�. (3)

As a consequence, ACOM(s) adopts the following form:

ACOMðsÞ ¼ACOMo½1þ ðs=2pf 3Þ�

½1þ s=ð2pf 1Þ�½1þ s=ð2pf 2Þ�. (4)

The effects of differential gain, common-mode gain,positive and negative power supply rejection ratios

ARTICLE IN PRESS

ABS

INPUT(+)

VDD

VSS

INPUT(-)

VOUT

VOFFSET

CCOM1

CCOM2

CDIF

RCOM1

RCOM2

RDIF

PSRR+

PSRR-

ADIFF

ACOM

TABLE

IFP

D/Dt

D/Dt

INTEG

INTEGLIMITERSLEWMAX

LIMITER

SRL1

AB

C

DSW

SUB1

SUB2

SUB3

SUM1

SUM2

SUM3

SUM4

SUM5

Fig. 4. New behavioural-level OA model.

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–10941086

(PSRR+ and PSRR�) are added at the input of the blockSRL1. PSRR+ and PSRR� are also represented in thefrequency domain by using Laplace blocks, employingtransfer functions synthesized from the Bode plots reportedin the vendor data sheet, obtained by simulations or byexperimentation.

We propose the use of the block SRL1 for modelling theslew-rate limitation effects. At point A, a DC plus ACsignal is observed. The branch composed by the blocksD/Dt (derivative action) and INTEG (integral action)allows obtaining at point B an AC-only signal. Theblock SUB3 performs the operation SIGNAL(A)�SIGNAL (B), obtaining at point D the DC compo-nent. The branch composed by the blocks D/Dt, SLEW-MAX (LIMITER) and INTEG models the slew-ratelimitation effects. An AC-only signal is obtained at pointC and SUM5 restores de DC level. The use of the SRL1block allows reproducing the DC behaviour of real OAs,overcoming the severe problems of the original model. Thiswill be clear in the next section, where we present the modelvalidation.

In order to reproduce the behaviour under saturationconditions, we propose to use the limiter observed at theoutput of the block SRL1. Nevertheless, the use of thissimple block causes the problem already pointed out in thispaper (Section 3.1). This drawback has been targeted in[21], but only with a partial solution based on the use of ahyperbolic function. We extensively experimented with thiskind of functions and with others presenting smoothcharacteristics. However, it was not possible to reproduce aright operation under saturation conditions, for all thefunctions and for our simulation platform (SPICE). Thisfact motivated the exploration of a more general solution.Our approach for solving this problem is based on the

reduction of the differential gain by means of an internalfeedback path (IFP). This feedback has to be active onlywhen saturation limits are reached. The non-linear functionproposed for implementing IFP is depicted in Fig. 5, wherethe input to the block (Vin) is taken from the output ofSUM5. This function is implemented by means of a tableand a multiplier, both available in the ABM library. IFPreduces the differential gain to one when the saturation

ARTICLE IN PRESS

0

Vout/vin

Vin(V)

1 1

Low Sat. High Sat.

Fig. 5. Non-linear function of IFP.

Table 1

Specifications of the modelled OA circuit

Specification Nominal value

Differential gain (dB) 80

First pole of differential gain (Hz) 884

Second pole of differential gain (MHz) 30

Common mode gain (dB) �38

First pole of common mode gain (Hz) 800

Second pole of common mode gain (MHz) 34

First zero of the common mode gain (kHz) 5.3

Differential input resistance (GO) 10

Common input resistance (GO) 10

Differential input capacitance (pF) 0.01

Common input capacitances (pF) 0.1

Output resistance (kO) 150

Slew rate (V/ms) 10

Offset voltage (input referred) (mV) 150

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094 1087

level is reached, and diminishes the effects of the systemdynamics under this condition.

The modules ABS and SW replace the output impedancenetwork of the original model. When the module of thesignal at the output limiter (operation performed by theABS module) exceeds the saturation limits, the output SWswitches on and connects in series its RON resistance; inother case, the series resistance is ROFF. Therefore, theoutput impedance in normal mode (no saturated) is ROFF.With this output network, we considerably improve theoutput dynamic range and overcome the problemsevidenced by the original model, particularly when highoutput impedance OAs are modelled.

5. Model validation

In order to evaluate the matching of the proposed modelwith a transistor-level one, a previously reported CMOSFolded Cascode OA [22] is adopted. The main specifica-tions of this circuit are shown in Table 1, and areloaded into the behavioural model developed in this work.The main motivations for selecting this OA are itsrelatively complex frequency response and its high outputresistance. These characteristics complicate the behaviouralmodelling.

For model validation, the responses of transistor andbehavioural-level models for different experiments areobtained. For all cases, we superimpose the results forcomparative purposes.The frequency responses of differential- and common-

mode gain are shown in Figs. 6 and 7, respectively. Thecommon-mode gain has been modelled with a transferfunction with one zero and two poles, for adequatelyreproducing the transistor-level circuit behaviour.The PSRR+ frequency response is depicted in Fig. 8.

The observed mismatch could be minimized but have beenregarded not relevant for our applications. It should bementioned at this point that the approximation to thebehaviour of a real OA could be improved incrementingthe poles and zeroes of the Laplace blocks modelling thebehaviours in the frequency domain, but this augments themodel complexity and consequently the simulation time.This could be a problem when fault injection andsimulation campaigns have to be done for complex circuits.Consequently, the test engineer must adopt a trade-offbetween the precision of the model responses and thecomputational cost of behavioural fault simulations.The large-signal response under slew-rate limitation

effects is evaluated using �0.7 to 0.7V step input(Fig. 9). It should be mentioned that the highest mismatchhas been obtained for this experiment, but it is consideredtolerable.The DC behaviour and the effect of the swing limiter are

evident in the DC sweep results depicted in Fig. 10. As canbe seen from the figure, the new model overcomes theproblems of reduced output dynamic range exhibited bythe original model (Fig. 3). The saturation effects for boththe transistor-level model and the behavioural one in aninverting configuration (unity gain) are shown in Fig. 11.The severe divergence between the original model andtransistor-level one under saturation conditions has beenalso reduced to a minimum extent.In order to demonstrate the DC response of the model

(Fig. 12), we configure the amplifier as unity gain inverterand excite it with a sinusoidal signal with a DC level of 1V.As can be seen from the simulation results, the new modelobtains the expected behaviour and overcomes the limita-tions of the original model.

6. Application examples

As it was mentioned in Section 1, the structural faultinjection cannot be implemented when the schematic of thecircuit is not available for the test engineer. This situationleads to the adoption of an OA model at an abstractionlevel different from the structural one, and a compatiblefault model.In the following examples, we adopt the OA model

presented in this paper and the functional fault modelling(FFM) concept proposed in [20] for performing theevaluations of the addressed test strategies. It should bepointed out that FFM has been reported to the scientific

ARTICLE IN PRESS

Frequency (Hz)

1.0 100 10K 1.0M 100M

Transistor Model

-50

0

50

100

Model

Transistor

Diffe

ren

tia

l g

ain

(d

B)

Fig. 6. Differential-mode gain frequency response.

Frequency (Hz)

100 10K 1.0M 100M10

Transistor Model

-80

-60

-40

-20

Transistor

Model

Com

mon-m

ode g

ain

(dB

)

1K 100K

Fig. 7. Common-mode gain frequency response.

Frequency (Hz)

1.000 100.00 10.00K 1.00M

Model

40

60

80

Model

Transistor

Transistor

PS

RR

+ (

dB

)

Fig. 8. Positive PSRR frequency response.

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–10941088

community in the recent past years, and the discussion onthe ability of this fault model for taking into account theeffects of structural faults is beyond the scope of this paper.The FFM approach defines a functional fault as adeviation in at least one specification of the OA, forinstance bandwidth, slew rate and common-mode gain. In

this sense, a faulty instance of an OA has one of itsspecifications beyond the acceptable limits. For the sake ofsimplicity, we denominate an OA specification as FP.In the following, we adopt two different approaches for

validating the test schemes presented as application examples.In the first one, we formulate an arbitrary fault list to be

ARTICLE IN PRESS

Time (sec)

0 0.2u 0.4u 0.6u 0.8u 1.0u

Model Transistor

-1.0

0

1.0Transistor

ModelOu

tpu

t vo

lta

ge

(V

)

Fig. 9. Step response.

Input voltage (V)

-1.0 -0.5 0 0.5 1.0

Transistor Model

-4.0

0

4.0

Model

Transistor

Outp

ut voltage (

V)

Fig. 10. DC sweep.

Time (sec)

0 0.4m 0.8m 1.2m 1.6m 2.0m

Model Input Transistor

-4.0

0

4.0Model

Transistor

Vo

lta

ge

(V

)

Fig. 11. Behaviour of the new model under saturation conditions.

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094 1089

injected in the OAmodel, following the procedure suggested in[20]. In this case, the goal is to demonstrate the use of themodel and to determine the hard-to-detect faults. In the secondone, we relate the deviations in the FPs with the applicationspecification. A deviation in a given FP is considered as a fault

if it produces a shift beyond tolerable limits in at least one ofthe application specifications. These two different procedureshave been adopted in order to give alternative approaches forgenerating the fault list. A third alternative to these approachesfor fault list generation is proposed in [23].

ARTICLE IN PRESS

Time (sec)

0 0.2m 0.4ms 0.6m 0.8m 1.0m

-2.0

0

2.0

output

input

Vo

lta

ge

(V

)

Fig. 12. Response of the new model configured as unity gain inverter.

N1

N2N4

N3

N5

Vout

+

-

R2

100k

R1

1k

C2

1n

C1

2n

Fig. 13. Band-pass filter (CUT).

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–10941090

6.1. Using the model for evaluating transient analysis

method (TRAM)

The model presented in this work is used to evaluate theability of TRAM for testing a biquadratic filter. Thismethod has been proposed in [24] and it is based on theassumption that a behavioural fault in the filter compo-nents will produce deviations in the transient response ofthe CUT. The test stimuli may be a step, ramp or parabola(regarding the order of the filter transfer functionnumerator), and the observed parameters are the peaktime and the overshoot of the filter output signal.

We assume that the ability of TRAM for detecting faultsin the passive components of the filter structure isevaluated by means of catastrophic and deviation faultmodels. The interest here is to determine if the test schemeis able to detect a set of proposed deviations in the FPs ofthe OA used in the filter. In this way, it is possible tocompare different testing alternatives, overcoming theproblems derived from the unavailability of the CUTschematic.

We chose for comparative purposes the negative feed-back biquadratic filter also proposed in [24]. This circuit(Fig. 13) is a band-pass filter tuned in 10.7 kHz whenR1 ¼ 1 kO, R2 ¼ 100 kO, C1 ¼ 2 nF and C2 ¼ 1 nF. For

this example, we assume that the OA to be designed later inthe development process has to fulfill the specificationsdepicted in Table 2. The assessment of the behaviouralfaults (deviations in the FPs) hard to detect by means ofTRAM is the main concern in this example.In order to perform this evaluation, we introduce

deviations in the model parameters and observe the outputsignal. A ramp (1000t) was selected as test stimuli to obtaina typical second order transient response. The functionalfaults to be injected in the OA are obtained from the datasummarized in Table 2. In this table, ‘‘x’’ denotes that thefaulty FP is obtained doing the product of the nominal FPby the indicated factor.The circuit transient responses for faults in the DC and

the first pole of the differential gain are shown in Figs. 14and 15, respectively, in order to illustrate some of thesimulation results obtained in our evaluation. In thesefigures, the fault-free response and the faulty ones aresuperimposed for comparative purposes. It is observed thatthe addressed deviations in the DC differential gain and inthe first pole of the differential gain are easily detectedusing TRAM. By other way, the faults injected in thesecond pole of the differential gain have to be declared asnon-detected because there are no differences between thefault-free and faulty responses.From the simulation results, we preliminary conclude

that TRAM presents severe problems for detectingdeviations in the parameters related to the common-modegain frequency response and to the input impedances.Deviations in the second pole of the differential gain arealso hard to detect. For all these injected deviations faults,there are almost no differences between the fault-free filterresponse and the faulty one.

6.2. Using the model for evaluating oscillation-based test

(OBT)

In the second application example, we address theproblem of evaluating an OBT scheme applied to the testof continuous-time nuclear pulse shapers. This kind of

ARTICLE IN PRESSE. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094 1091

systems is widely used in the nuclear industry, although theproblem of testing them has been recently addressed in [25].Our interest here is to show the use of the proposed modelfor evaluating test strategies applied to multiple OAscircuits. We assume, like in the previous example, that theefficiency for detecting catastrophic and deviations faults inthe passive components is determined using traditionalmethods.

We adopt as case study a system composed of adifferentiator, three integrators and a gain stage (Fig. 16).We use the OPA656 OA for implementing the shaper. Thestep response of the shaper should approximate a Gaussianshape [26] for optimizing its performance when used innuclear spectroscopy systems (a common application for

Table 2

Specifications of the OA used in the biquadratic filter and factors used for

obtaining the fault list

Functional parameter Nominal

value

Factor 1 Factor 2

Differential gain (dB) 114 � 0.5 � 0.25

First pole of differential gain

(Hz)

10 � 0.1 � 10

Second pole of differential gain

(MHz)

10 � 0.1 � 10

Common mode gain (dB) �6 � 10 � 100

First pole of common mode

gain (Hz)

10 � 0.1 � 10

Second pole of common mode

gain (MHz)

5 � 0.1 � 10

Differential input resistance

(GO)10 � 0.01 � 0.01

Common input resistance (GO) 10 � 0.01 � 0.01

Differential input capacitance

(pF)

0.01 � 10 � 100

Common input capacitances

(pF)

0.1 � 10 � 100

Output resistance (kO) 1 � 5 � 7.5

Slew rate (V/ms) 1 � 0.01 � 0.001

Tim

0 100u

Test-

mode o

utp

ut voltage (

V)

0

400m

800m

fault-fre

Fig. 14. Faults in the

this circuit). This approximation is better if the number ofintegrators in the circuit increases.For applying OBT, we convert the whole system into an

oscillator by adding a non-linear circuit in the feedbackloop (Fig. 17). We manipulate only the input and theoutput for switching the shaper from normal to test modein order to minimize the level of intrusion in the system.The advantages of the non-linear oscillators have beenwidely explained in previous work [23,27]. We follow aprocedure similar to the one suggested in [23] for designingthe oscillator.The OBT scheme could be evaluated by injecting

arbitrary deviation faults in the FPs as it was proposedin the previous example. Nevertheless, the negative feed-back paths around the OAs produce that relatively widedeviations in the FPs have a minor impact on the shaperperformance. We propose a specification-driven fault listgeneration from the circuit fault-free response. A singledeviation in the value of an FP (FFM concept) isconsidered as a fault if it shifts the shaper response beyondpre-established limits. We define a tolerance band of 5% atboth sides of the nominal response (Fig. 18), but this valuecould be changed depending on the resolution of theoverall spectroscopy system.For generating the fault list, we perturb the FPs using

the parametric analysis available in SPICE, and select as afault for the FP under study the value that shifts the shaperstep response outside of its specifications. For the sake ofsimplicity, we report in Table 3 the multiplying factors usedfor obtaining the faulty FPs. In this table, OA1 to OA5 arethe amplifiers observed in Fig. 16. A fault in a given FP isobtained multiplying its nominal value by the factorsdepicted in this table.As expected, wide deviations in the FPs are required for

causing the application go outside of its specification limits.For some FPs, only positive or negative deviations fromtheir nominal values are taken into account. For inputresistances, slew rate and second pole of differential gain,only decrements are considered as faults. Similarly, only

e (sec)

200u 300u 400u

e

differential gain.

ARTICLE IN PRESS

R1

R2

R4

R6

C1C2

+

-

OA4

R15

R5 R8

R12

R7

R9

C3

R10

R11

C4

INPUT

OUTPUT

R3

R14

+

-

OA1

R13

+

-

OA2+

-

OA3

+

- OA5

Fig. 16. Three-integrator shaper.

Time (sec)

100u 200u 300u 400u0

400m

800m

Te

st-

mo

de

ou

tpu

t vo

lta

ge

(V

)fault-free

Fig. 15. Faults in the first pole of the differential gain.

Shaper

Non linearelement

NL Input

NL input

NL output+Vref

-VrefNL output

Fig. 17. (a) Conceptual diagram of OBT implementation. (b) Character-

istic of non-linear block.

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–10941092

increments in the common-mode gain and in the inputcapacitances are considered as faults. Opposite deviationsin these FPs present no effects on the shaper performance.

In order to evaluate OBT, the faults to be injected in theOAs are obtained from the data depicted in Table 3. Weconsider a deviation fault in a given FP as detected whenthe amplitude and/or frequency of the oscillations departsmore than 5% from their fault-free values. The faultsimulation results show that OBT is able to detect faults inall the FPs, with the exception of common-mode inputresistance in OA3 and OA4. This suggests that OBT couldbe an attractive option for testing this kind of circuits.By other way, by adopting both the OA model and the

FFM concept it is possible to evaluate the test strategyregarding the OA behaviour. This evaluation is tradition-ally not carried out: it is assumed that the OAs are faultfree, and catastrophic and deviation faults are injected onlyin resistances, capacitors and switches.

ARTICLE IN PRESS

Time (sec)

1.0u 2.0u 3.0u 4.0u

0

0.4

0.8

1.2

nominal-5% nominal+5%nominal

Ste

p r

esponse (

sec)

Fig. 18. Nominal response and tolerance limits of the three-integrator shaper.

Table 3

Multiplication factors used for obtaining the fault list (shaper)

Functional parameter OA1 OA2 OA3 OA4 OA5

Differential gain 0.04 0.075 0.065 0.075 0.15

First pole of differential gain (positive deviation) 10 33.33 20 20 400

First pole of differential gain (negative deviation) 0.02 0.02857 0.02 0.022 0.05

Second pole of differential gain 0.143 0.05 0.033 0.05 0.025

Common mode gain 2400 2500 3000 3500 100

Slew rate 0.1 0.007 2.1e�3 1.15e�3 5e�3

Differential input resistance 0.0267 0.0266 0.025 0.04 0.06

Differential input capacitance 150 1900 1500 2000 100

Common input resistance 1.1e�4 1.1e�4 1e�3 1.1e�4 4e�4

Common input capacitance 600 1.4e4 12000 12000 500

Offset voltage (positive deviation) 87 58 36 58 73

Offset voltage (negative deviation) �90 �59 �40 �60 �73

E. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094 1093

7. Conclusions

In this work, we present a behavioural-level OA modeluseful for evaluating test strategies early in the design cycle,when the schematic of the circuit is usually not availablefor the test engineer. This new model allows consideringdifferent alternatives for testing prior schematic or layoutgeneration, avoiding tedious and costly modifications atthose levels.

Test strategies targeting commercial OAs or standardcells designed by third-part vendors could be also evaluateddue to only the specifications are needed for OA modelling.Additionally, it is possible to analyse and comparedifferent alternatives for testing, avoiding the use ofstructural fault models that require the CUT schematic.

The parameters required by the model presented in thispaper show a clear relation with the OA specifications,allowing a straightforward translation from functionalspecifications to model parameters. The model can beeasily simplified in order to use only the necessary blocksfor processing the test signals and to reduce the computa-tional effort needed for fault simulations in large systems.

The model is validated using a previously designedCMOS OA. The simulation results show that the modelpresents a good agreement with the transistor-level versionof the amplifier.In order to use the model for evaluating test strategies,

the concept of FFM is adopted. Fault simulations areeasily performed by means of parametric simulations in aSPICE simulator. The two application examples addressedin this work are intended to show the usefulness of themodel for evaluating test strategies for single and multipleOAs applications. In our fault simulation experiments, themodel showed an excellent stability without convergenceproblems.

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