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AN INTRODUCTION TO HYPERLYNX SI/PI TECHNOLOGY

BY STEVE KAUFER, MENTOR

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An Introduction to HyperLynx SI/PI Technology

OVERVIEW Digital designers are now required to make the leap from time domain to frequency domain, facing complexity similar to their RF/microwave brethren. They need to learn new methodologies like COM (channel operating margins), PAM4 (pulse amplitude modulation with 4 states), and HMC (hybrid memory cube & other 3D memory architectures). To tackle these challenges, HyperLynx® SI/PI integrates signal- and power-integrity analysis, 3D-electromagnetic solving, and fast DRC checking into a single unified environment. With such a complete set of analysis technologies, engineers can design any type of high-speed digital PCB. With a wide range of underlying simulation engines and featuring a GUI that supports both quick/interactive and exhaustive batch-mode analysis, HyperLynx sets the standard for deployment of high-speed capabilities in one easy-to-use environment.

ALL IN ONE ENVIRONMENT High-speed PCBs vary greatly in size, layer count, routing density, signaling speed, types of silicon used, power-delivery challenges, and other factors. Some designers resort to multiple analysis tools, for example trying a batch-mode SI (signal integrity) simulator for slower signals and a 3D-EM solver for very-high-speed SERDES channels. But even tools offered by a single EDA vendor typically require changing applications and user interfaces for different types of analysis (e.g., signal versus power versus 3D).

In contrast, HyperLynx offers all types of analysis in a single application, with one GUI. A user can literally be simulating a critical SERDES channel one minute, and analyzing a large power net’s decoupling the next minute, simply by selecting a menu item.

But such convenience is valuable only if underlying simulation engines and algorithms are strong. Significant R&D investments in interconnect modeling mean that HyperLynx now combines a super-fast computational geometry engine with advanced materials modeling (for wideband dielectrics, copper roughness, etc.) to produce highly accurate simulation netlists.

Crosstalk can be modeled in great detail; aggressor nets can be identified quickly in even the largest layout databases, based on geometric or electrical thresholds. For higher signaling speeds, a unique, dedicated engine and robust simulators efficiently handle S-parameter extractions and S-parameter models of virtually any size.

FEATURES AND BENEFITS:

■ Integrated technologies combine powerful, world-class EM solvers, simulators, and geometry processing engines that simplify methodologies for design, analysis, and signoff validation

■ Hybrid analysis flow and pattern recognition techniques reduce simulation time by orders of magnitude

■ Power-aware channel extraction and advanced decoupling analysis utilize a hybrid, full-wave solver to enhance power integrity analysis, including complex wide-band electromagnetic interactions between multiple power nets, traces, vias, and metal area fills

■ First commercially available solution for COM (channel operating margin) analysis specified in the 100 Gb/s Ethernet IEEE 802.3bj specification

■ PAM4 signaling supported within the HyperLynx channel analysis wizards allowing ‘what-if’ and post-layout analysis for research and trade-off analysis between traditional and emerging technologies

■ HTML-based reporting simplifies design documentation and speeds signoff

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An Introduction to HyperLynx SI/PI Technology

MEETING THE CHALLENGES OF NEW TECHNOLOGIES SERDES

SERDES technology has greatly increased the frequencies used in digital signaling—even a “mainstream” protocol like PCIe Gen3 runs at 8 Gb/s. HyperLynx has advanced electromagnetic (EM) solvers, including full-wave 3D, to handle this challenge. The figure to the right shows the effects of increasingly higher data rates and frequencies on a real SERDES channel.

3D EM simulation can be complex to understand and set up; accordingly, HyperLynx deeply integrates the 3D engine so that the user never has to learn the intricacies of a full-wave-solver environment. Structure geometries are passed, EM ports are formed, simulations are run, and S-parameter results are returned and incorporated into time-domain simulations, automatically.

To keep up with leading-edge SERDES simulation, HyperLynx includes the ability to simulate SERDES signaling based on PAM-4 modulation. A “hot” topic in the industry, PAM-4 uses four logic levels instead of NRZ modulation’s traditional two and is a big-enough technological shift that many designers are taking their time before committing to it. Using HyperLynx, engineers can experiment with PAM-4 in their existing and proposed systems, and contrast it directly with NRZ to see whether the switchover is worth risking. The figure below shows NRZ and PAM-4 eye diagrams for the same channel.

Lately, PCB power-delivery networks (PDNs) have come under a lot of stress. What formerly were “power planes” are now collections of highly compromised power “areas,” whose integrity must be simulated. HyperLynx has multiple engines — two 2.5D solvers, the industry’s fastest DC/IR-drop simulator, and a fast, quasi-static 3D solver — to enable a full set of power-integrity features, all of which are available in the same application as HyperLynx signal-integrity capabilities. The most recent engine is a powerful 2.5D solver that provides mixed-signal-and-power modeling for added accuracy in SI simulations when simultaneous switching-noise (SSN) complications are suspected. Much effort has also gone into accurately analyzing designs with non-ideal PDNs, including designs in which power is distributed primarily by traces rather than by large areas.

At top are the effects of increasingly high data rates on the eye closure of an actual SERDES channel. At bottom is a representation of how faster data rates/higher frequencies demand simulation modeling that is more and more detailed.

NRZ and PAM-4 eye diagrams for the same channel. The PAM-4 signal transmits the same data rate at half the baud rate.

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An Introduction to HyperLynx SI/PI Technology

From the user’s standpoint, power integrity (PI) simulation differs from SI in one very important way: the structures being modeled are much larger so analysis, therefore, takes much longer. Accordingly, all HyperLynx PI engines are constantly tuned for speed and contend strongly for best-in-industry performance. HyperLynx PI allows users to perform more-detailed and more-exhaustive simulation, similar to what they’ve become accustomed to doing for SI effects.

STREAMLINING BOARD-WIDE ANALYSIS

Simulating every detail of signal routing and power delivery on a PCB is powerful, but it can be overwhelming. Tuning raw simulation capabilities to the specific requirements of standard interfaces and protocols (e.g. DDRx memory and 100-Gb/s Ethernet SERDES) eases the burden and provides streamlined, summary pass/fail judgment on entire interfaces.

The HyperLynx DDRx batch-simulation wizard pioneered easy setup, automated whole-bus simulation, and consolidated results-reporting for memory interfaces, including DDR4 and LPDDR4 interfaces. HTML-based reporting creates design documentation and allows internal Web-based “publication” of results.

In the SERDES arena, protocols that support Channel Operating Margin (COM) check the “goodness” of links based on a specific, complex set of simulation steps that produce a single pass/fail number per channel. HyperLynx was also the first to offer robust commercial implementation of COM for 100GbE signaling, with all simulation details fully automated.

Another way to streamline the daunting task of simulating all signal and power effects on a large PCB is to proactively identify portions of a design that most need detailed analysis, and to reduce the time required for simulation by promoting aggressive re-use of expensive-to-create models (like 3D-based S parameters).

An example page in the HyperLynx DDRx Analysis Wizard. The Wizard “interviews” the user about a DDRx interface. Once the information is supplied, the Wizard runs thousands of simulations, makes all timing and SI measurements, records detailed waveforms, and presents pass/fail results for the entire interface.

HyperLynx HTML-based reporting simplifies creation of design documentation.

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An Introduction to HyperLynx SI/PI Technology

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HyperLynx does this by integrating the powerful HyperLynx DRC engine directly inside the HyperLynx SI/PI environment. The super-fast DRC engine (capable of scanning the entire board for routing and other geometric anomalies in seconds) can provide “simulation triage,” by accurately finding layout structures that violate design intent or best practice. For example, HyperLynx SI/PI deploys this engine to automatically find all differential via pairs that do not conform to pre-designed known-good “patterns.” It will also group all such vias into sets for which only one 3D-EM S-parameter extraction (automatically run) is needed per set, potentially saving many hours of simulation time per board. The same technology can also be used to find all of the via patterns (good or “bad”) that occur on a selected group of nets, automatically creating a minimum number of sets and sending each pattern off to the 3D-EM solver for extraction.

Finally, while HyperLynx continues to stay true to its heritage of ease-of-use and fast interactive analysis, it also excels in a very different type of usage: that of a pure batch-mode environment, driven by scripts, run on entire layouts at least once-per-day, with little/no user intervention and a completely suppressed GUI. Included with HyperLynx for this use are the ability to efficiently handle very large layouts (including extra-deep stackups, huge net counts, and entire multi-board systems); high-performance multi-processor and simulation engines and the ability to cache and re-use extracted models. HyperLynx offers two scripting interfaces: a simplified interface requiring no programming expertise and a richer, language-based environment that provides customized access to the powerful HyperLynx engines.

SUMMARY Long the most widely used high-speed tool in the industry; HyperLynx is now the most powerful and best-integrated high-speed tool as well. Engineers who still think of HyperLynx simply as providing `fast and easy SI’ should take a fresh look at how dramatically it has strengthened and matured over the years.

With many years of R&D investment and technology acquisition, HyperLynx offers a rich set of robust, high-performance, high-accuracy simulation capabilities in a single unified environment. HyperLynx can address all aspects of signal-integrity, power-integrity, SERDES, and 3D-electromagnetic analysis, and perform fast DRC/geometry scanning for simulation triage. The result is a toolset capable of a full range of capabilities from fast/interactive analysis, through complex mixed mode (signal/power/3D) simulation, and high-capacity, script-driven, daily-batch analysis.

Pioneering COM implementation allows simulation of 100GbE signaling.