An InteractiveComputer Graphics Languagefor the Design and Simulationof Digital SystemsShingfat S. Ching*andJames H. TraceyUniversity of Missouri-Rolla

4,0

Introduction

Many computer hardware description languages havebeen introduced to describe and model digital networksat the register transfer level.'-3 Most CHDL's, however,like common programming languages, are "text oriented"and employ textual statements in the specification of adigital system. The process of converting a word state-ment problem into a description written in a designlanguage is often tedious, especially when the design iscomplex. Many designers overcome this difficulty by"drawing" register layouts and control sequence or statediagrams for a design before hand-translating them intoa specification in an appropriate design language. Withthe reduction in the costs of on-line computing andgraphic terminals, this approach can be used early in thecomputer-aided-design cycle. This has in fact been accom-plished at the University of Missouri-Rolla, where agraphic language called FLOWWARE has been developedto allow digital networks to be specified pictorially.FLOWWARE is based upon the concept of employing

flowcharting techniques to describe the components andcontrol algorithm of a digital system.4'5 In a FLOWWAREdescription of a design, a flowchart specifies the controlsequence, while register layout diagrams represent thehardware organization. (The term FLOWWARE in thispaper is used interchangeably to mean the graphicallanguage and the implemented system.)Since its first implementation, FLOWWARE has been

further expanded to its current structure."8 Figure 1provides an overview of the complete FLOWWAREsystem and illustrates the interrelationship among thesystem modules as described in the paper. As imple-mented, FLOWWARE is an integration of an existingprogram called IDDAP (Interactive Digital Design Assist-

*Shingfat S. Ching, now with Digital Equipment Corporation,was affiliated with the University of Missouri-Rolla when workon this paper was done.

June 1977

ance Package) as written by Crall,9-10 a preprocessor tohandle graphics data inputs, and a graphics processor toproduce graphical outputs from simulation results. IDDAPuses a subset of Chu's CDL" and has an interactivesource statement translator as well as an interactivesimulator. Like most design automation systems, IDDAPaccepts a textual description of a design. The pre-processor in FLOWWARE, therefore, handles the trans-lation of graphic inputs received from a graphical terminalinto text data acceptable to IDDAP. Similarly, the

Figure 1. Structure of the FLOWWARE system.

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graphics processor controls the simulation operation andconverts the simulation results into graphical data to bedisplayed on the graphics terminal. This concept ofusing a preprocessor and graphics control processor canalso be applied to other "'text oriented" languages toallow implementation of FLOWWARE with other languages.

FLOWWARE elements

FLOWWARE uses two description phases to specifya digital system: an information flow phase (Phase I) anda control flow phase (Phase II). The information flowphase consists of the declaration of registers, memories,subregisters, clocks, terminals, controls, decoders, andother hardware components. Lines are drawn to inter-connect elements to show the data paths among regis-ters. A description in this phase essentially representsthe structural organization of a digital system. The controlflow phase specifies the control algorithm of a digitalnetwork by a control flowchart. Basic control structuresinclude the function block, decision block, decode block,start block, terminate block, etc. Register activities arewritten as simple IDDAP-type statements inside thefunction blocks.

Table 1 presents the elements used in the language.A FLOWWARE user can instruct the computer to drawan element by positioning a graphics cursor on theterminal screen at a desired location and then typing inan appropriate command. Most elements have some textualdescription associated with them. These textual state-ments may define the names of the components that theelements represent, or some control actions to be per-formed. FLOWWARE provides an editing facility toenable the user to add, change, or delete elements ortext. It also has a windowing capability to allow theuser to specify a design which requires several windowsor pages to be described.

Information flow phase elements. These elements areused to specify the components in the digital system tobe modeled. Figure 2 shows an information flow phasespecification of a serial parity bit generator for a 7-bitregister. The use of many of the Phase 1 elements isobvious from Table 1 and Figure 2, but some requirefurther explanation. In the case of the memory element,the user can define a memory with its word length aswell as the number of words in the unit. The memoryaddress register is also defined as part of the memoryelement.

INFO PHASEPAGE: 00000,00000

I SRC IEIZ- - -

L=R(7)I

ISWIZI

SIMULATEDISPLAY

STEPWAVE

GO BACKMOVE

SIZECLOCK

PHASEREDRAW

CLEAREXIT

Figure 2. An information flow phase description of the serial parity bit generator and the layout of the menu onthe graphics terminal.

CNT :]i

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The unary and binary operand function elementsenable the user to define a standard function to beperformed on the input operands. The exact function tobe performed is specified by pointing a control flow lineat the function name. Tables 2 and 3 specify thefunctions available with these elements.The terminal function element enables the user to

refer to a Boolean expression by a name. For example,if a "TERM = A*B" statement has been specified inside

Table 1. Elements and commands (a) Phase 1.

a terminal element, the user can subsequently use thename TERM to stand for A*B.The function element allows the user to define a set

of operations which can be referenced by the Phase 2description as subroutine calls. The operations are definedby statements from the original "text-oriented" language,or IDDAP in this case. The function element is activated,in Phase 2, by the statement "DO NAME" where NAMEis the name of the function block.

Table 1. Elements and commands (b) Phase 2.

Command Meaning

R DEFINE REGISTER

M DEFINE MEMORY

Computer Response

I

DEFINE INFORMATION FLOWCONNECTOR

Command Meaning

F DEFINE FUNCTION BLOCK

G DEFINE GO-TO LINE

C DEFINE CONTROL SIGNAL

L DEFINE CONTROL FLOWLINE

D DEFINE DECISION BLOCK

F DEFINE FUNCTION

DEFINE CONTROL El"1DEFINE CONTROL FLOWLINE

E DEFINE DECODER KZID-

E DEFINE DECODE BLOCK

0 DEFINE START BLOCK

1 DEFINE END BLOCK

2 DEFI N E TERM NATE BLOCK

START

END

TERMINATE |

B DEFINE BINARY OPERANDFUNCTION ELEMENT

U DEFINE UNARY OPERANDFUNCTION ELEMENT

K DEFINE CLOCK

S DEFINE SUBREGISTER

J DEFINETERMINAL

aO]~~~~~~~

LII"']

Table 2. Functions of unary operand function element.

MnemonicNOTCOM

LSRSLCRCCU

CD

MeaningLOGICAL NOTTWO'S COMPLEMENTLEFT SHIFT ONE POSITIONRIGHT SHIFT ONE POSITIONLEFT CIRCULATE ONE POSITION

RIGHT CIRCULATE ONE POSITIONCOUNT UPLONECOUNT DOWN ONE

Table 3. Functions of binary operand function element.

MnemonicADDSUBMULDIVREMOR

ANDXOR

MeaningADD OPERAND 1 TO OPERAND 2SUBTRACT OPERAND 2 FROM OPERAND 1MULTIPLY OPERAND 1 BY OPERAND 2DIVIDE OPERAND 1 BY OPERAND 2REMAINDER, OPERAND 1 MODULO OPERAND 2LOGICAL INCLUSIVE OR OF OPERAND 1 ANDOPERAND 2LOGICAL AND OF OPERAND 1 AND OPERAND 2LOGICAL EXCLUSIVE OR OF OPERAND 1 ANDOPERAND 2

June 1977

Computer Response

LIIIII

C

L

ADD [ SUBMUL DIVREM ORAND I XOR

NOT COMLS RSLC RCCU CD I

37

CNTL PHASEPAGE: 00000,00000

LSWL _ _-_

SIMULATE STEP GO BACK SIZE PHASE CLEARDISPLAY WAVE MOVE CLOCK REDRAW EXIT

Figure 3. A control flow phase description of the serial paritybit generator.

Control flow phase elements. The control flow phaseelements are used to describe the sequential behaviorof a digital system in terms of a flowchart. Figure 3illustrates a control flow phase description for the serialparity bit generator example.

Function block. The function block is used to describea particular function which may be one or more IDDAPstatements. When a function block becomes active duringsimulation, all data transfers and activities defined by theblock take place simultaneously.

Go-to line. The go-to line defines the direction of controlflow or the sequence in which operations are to be executed.The user can also create parallel paths on the flowchartby using the go-to line element.

Control signal and control flow line. In Phase 2, thecontrol signal acts as a switch which can open or blocka control flow path during simulation. Consider the controlsignal SW in Figure 3. If it has a logical value of 1,then the next function block on the control flow pathcan be executed. Otherwise, the simulation is blockedfrom continuing, and in this case it will be halted. Ifthere are other parallel paths which are active, simulationcan still be continued on other paths. The name specifiedin the control signal element can be a register or controlsignal from the Phase 1 description.

Decision block. The decision block is used to decidebetween two alternate paths.

38

Decode block. The decode block decodes the registerdefined within the block into one of 2n exit paths wheren is the length in bits of the register. The exit paths, whichare go-to lines themselves, have associated with them anumber which represents the decode of the block. Duringsimulation, the exit path to be taken for leaving this ele-ment is the path whose identification number is equal tothe decoded value. One exit path may be specified withouta number. This will be the exit path under a no-matchcondition.

Start, end, and terminate blocks. These three blockscontrol the simulation. The simulation normally begins atthe start block and ends at the terminate block. The endblock is used to specify the end of a path. When it isencountered, simulation of the corresponding branch isended, but the simulation of other active branchescontinues. The terminate block halts the simulation whenit is executed even if there are unexecuted parallel paths.

Design simulation

The next logical step to be taken after a descriptionhas been specified is the simulation of the design. Sincethe IDDAP simulator cannot display any simulationresult graphically, a graphics control processor has beenadded to provide facilities for the interpretation of usercommands during simulation, generation of graphic out-puts from simulation results, and control of the progressof simulation. It becomes active only after the translationof design data into internal form has completed, and isentirely under the control of commands issued by theuser.In coordination with the graphics processor, the basic

simulator of IDDAP has been extended to provideadditional capabilities. The modified simulator can performthree types of simulations: normal simulation, breakpointsimulation, and step-through mode simulation. The lasttwo types enable incremental simulation to be performed,and provide a finer degree of control for the simulation.A highlighting facility also exists to show the progressof a simulation graphically.Most often, the user would use the normal mode

simulation. Under this mode, the simulation begins fromthe start block and stops at the encountering of aterminate block. As each function block or decisionblock becomes active, a star symbol is drawn next to theactive element. This highlighting of active blocks'essentiallytraces through the path of simulation. By following thesequencing of the star symbols, the user can see howthe simulation of the design is being performed.The breakpoint mode simulation can be initiated when

the user has already installed some breakpoints in theflowchart description. FLOWWARE only allows break-points to be established at the function blocks in thecontrol flow phase description. A breakpoint simulationcommences from the start block or from the last break-point encountered. It ends at the next breakpoint on thepath of simulation, or at a terminate block. Active blocksare highlighted the same way as in ordinary simulation.The step-through simulation mode provides total control

over the progress of simulation. Each activation of thismode causes the simulator to simulate one function block.Active blocks are highlighted as before. After a functionblock is simulated, FLOWWARE suspends the simulationprocess, and the user may choose to view intermediateresults or to carry on with the simulation. By initiating

COMPUTER

a series of step-through mode simulations, the wholecontrol algorithm can be "stepped through."Simulation may be clocked or unclocked. In a clocked

mode simulation, update of registers is under the controlof a clock element or a register temporarily declaredas a clock. The actual update takes place only when thereis a clock pulse or when the temporary clock changesstate. In FLOWWARE, the user must specify all changesin clock states explicitly.

During simulation, the user can direct the operationof the graphics control processor by utilizing two types ofcontrol commands. Both types require the use of thegraphics cursor on the terminal. The Type 1 commands con-sist of those whose actions relate directly to the element inquestion. To enter a Type 1 command, one simply positionsthe graphics cursor within the area of the element andthen keys in a command character. Depending upon thecommand, additional information can be included by textinputs entered at the referenced point. The Type 2commands are those listed on a "menu" placed at thebottom of the terminal screen. The bottom of Figure 2shows the layout of the menu as it would appear onthe terminal. These commands normally do not associatedirectly with any element. A Type 2 command can beentered by positioning the graphics cursor at the commandand keying in a command character. The use of themenu enables the user to see at a glance most of thecommands available, thereby relieving him of memorywork.

In the discussion to follow, the input character for acommand is enclosed within parentheses.

Type 1 commands. The associated functions for Type 1commands are as follows:

(1) Set the value of an element (S).(2) Display the value of an element (D).(3) Display and modify the content of a memory loca-

tion (M).(4) Set up a master clock (C).(5) Enable waves-collecting option (E); specify that dur-

ing simulation, the values of the referenced element arecollected to generate waveform timing diagrams.

(6) Disable wave-collecting option for the referencedelement (R).

(7) Install a breakpoint (B); establish a point just beforethe referenced function block as a breakpoint.

(8) Remove the referenced function block from thebreakpoint list (K).

(9) Redraw the current display without listing the textdescription of the elements (W).

Type 2 control commands. The following 12 commandsare listed on the menu. Under each selection, the usermay also choose from among several options by enteringspecific command characters as inputs.

(1) SIMULATE: invokes the simulator. By default, thesimulation to be performed is in the normal mode. If a Bcommand character is entered, simulation will be in thebreakpoint mode.

(2) GO BACK: enables the user to go back to somebreakpoints which have been encountered previously inthe simulation. The simulation environment is also restoredto that of the new breakpoint.

(3) STEP: activates a step-through mode simulation.One function block will be simulated.

(4) SIZE: selects one of the few description displaymodes available. Each display mode gives a different

June1977

picture resolution. The user can have a choice of fullscale display, multiple window display, or split-screendisplay in which both a page from the Phase 1 and Phase 2descriptions are shown.

(5) DISPLAY: displays the logical values of all thecomponents currently being shown on the terminal.

(6) WAVE: draws on the terminal the timing diagramsgathered during simulation.

(7) CLOCK: enables or disables the action of the systemclock.

(8) PHASE: selects the description phase to be displayed.(9) MOVE: enables the selection of a new display window.(10) REDRAW: redraws to obtain a fresh copy of the

description.(11) CLEAR: resets FLOWWARE.(12) EXIT: exits from the graphics control processor.

From then onward, the user can choose to enter a newdescription or terminate the design session.

Use of FLOWWARE

FLOWWARE has been used successfully in the designand simulation of systems as complex as a modernminicomputer. However, such systems require manywindows of display-far too many to represent here.Therefore, the very small and simple example of a serialparity bit generator has been selected for illustrationhere. Figures 2 and 3 show the definition of this examplein the FLOWWARE language.The information flow phase description (Figure 2)

specifies that register R, the register for which the parityis to be generated, is connected to an operand functionmodule which can perform a circular right shift on inputs.This operand function module is controlled by the controlsignal SRC. The output from the function element isfed back to register R. A second operand functionmodule which performs the exclusive-or function generatesthe parity bit from the current values of registers T andPB. The output from this element-i.e., the new valueof the parity bit-is put back into PB. The control signalP controls whether or not this operation is to be taken.Similarly, the counter C is counted up by one every timethe control signal CNT becomes active. Bit 7 of registerR is also redefined as subregister L. The switchingregister SW is defined as 1 bit long.

The control flow phase description specifies how theparity bit can be generated using the components fromthe information flow phase description. Figure 3 showsthat simulation can begin only when the logical value ofSW is a 1. The first function block in the control flowpath clears both registers C and PB. The rest of theflowchart then forms a loop. At the top of the loop,the first function block causes the logical value of L-i.e.,the last bit of R-to be stored in register T. The nextblock then activates the control signals SRC, P, and CNTsimultaneously. This in turn causes the three operandfunction elements to perform their various duties. Upontesting the value of C, the decision block at the bottomof the loop decides whether to go back to the top of theloop or exit from the loop.As an illustration of the design, assume that register R

has a binary value of 1011010. This can be entered byissuing a SET command at R, and then keying in thevalue. Figure 4 shows the results of all the registers inbinary form after simulation. Notice that register T takeson the value of the most significant bit of R. The sameresults can also be viewed in other forms of representations.

39

INFO PHASEPAGE:00000,00000

00000000

00000001

SIMULATEDISPLAY

Figure 4. Values of the registers after simulation in binary form.

Due to page limitations, the highlighting facility, thebreakpoint and step-through simulation modes, and otherforms of display cannot be demonstrated here. Morecomprehensive information on the performance of thesystem is available elsewhere.6'7

Implementation of FLOWWARE

As mentioned earlier, FLOWWARE has been implemen-ted on the computer system at the University of Missouri-Rolla. At this particular installation, the computer systemhas an IBM/360 Model 50 computer connected via high-speed data link to a network of several Data GeneralNOVA 800 minis.12 As implemented, FLOWWAREconsists of two programs running simultaneously on thehost IBM/360 and a remote NOVA 800. The user entershis design from a Tektronix T4014 graphics terminalconnected to the remote NOVA. The NOVA program,written entirely in assembly language, performs elementdrawing, text editing, redrawing of descriptions, anddisplaying of simulation results. It also communicateswith the host computer. This organization allows alldrawings to be done locally and relieves the host computerfrom performing the time-consuming graphics activities.

The IBM/360 program, written in PL/1, translates thedesign data received from the NOVA computer into codesfor simulation. It also performs simulation on inputdesigns using the data generated by the translator program.

Conclusion

The FLOWWARE language has proven to be a viablealternative to conventional, "text-oriented" computerhardware description languages. As an implementedsystem, it provides both an easy means for specifyingdesigns, and an interactive graphic capability for the simu-lation process. The concept of using a modular preprocessorand graphics control processor can be used as a model tosupplement existing design automation systems.

Acknowledgments

This paper is an extension of work initiated by Dr.Wayne Omohundro while a student at the University ofMissouri-Rolla. Dr. Omohundro implemented an initialversion of FLOWWARE. The work reported here wassupported in part by NSF Grant ENG 72 0398 A01.

40

L71I

I .1 I

STEPWAVE

GO BACKMOVE

SIZECLOCK

PHASEREDRAW

0 CLEAREXIT

el. . . .,. .. -- - I-- -- - ..- .-..

COMPUTER

References ceedings ofpp. 93-98.

1. Computer, Special Issue on Hardware Description Lan-guages, Yaohan Chu (Guest Ed.), December 1974. 11. Y. Chu, "An

Communicai2. Proceedings, 1975 International Symposium on Computer

Hardware Description Languages and their Applications, 12. J. H. Trace.September 1975. Computer-A

Environmen3. M. R. Barbacci, "A Comparison of Register Transfer October 197.

Languages for Describing Computers and Digital Systems,"IEEE Transactions on Computers, February 1975, pp.

4. W. E. Omohundro, "FLOWWARE - A Flow ChartingMethod to Describe Digital Systems," PhD dissertation,University of Missouri-Rolla, 1973.

5. W. E. Omohundro, "FLOWWARE - A Flow ChartingProcedure to Describe Digital Networks," First AnnuaslSymposium on Computer Architecture, December 1973,pp. 91-97. 4>tSp 0

6. S. S. Ching, "EXFLOW - An Interactive Graphics Rolla, both in electPackage for the Design and Simulation of Digital Net-works," PhD dissertation, University of Missouri-Rolla,1976.

7. , "EXFLOW Users Manual," TechnicalReport, University of Missouri-Rolla, 1976.

8. , "EXFLOW Implementation Package,"Technical Report, University of Missouri-Rolla, 1976.

9. R. F. Crall, "IDDAP - Interactive Computer Assistancefor Creative Digital Design," PhD dissertation, Univer-sity of Missouri-Rolla, 1970.

10. _ _, and J. H. Tracey, "IDDAP - InteractiveComputer Assistance for Creative Digital Design," Pro- Tau Beta Pi, Eta I

-[ESILAUCHu SUPP")TCCOMUTIM IDICINISSnnnnrtfinitiae in I arItrla I hnrntnriPt' npw nlCsvstpl

the National Electronics Conference, 1970,

n ALGOL-Like Computer Design Language,"ions ofACM, Vol. 8, Oct. 1965, pp. 606-615.

y, H. J. Pottinger, and R. D. Rechtien, "Automated Laboratory System in a Universitynt," Proceedings of the IEEE, Vol. 63, No. 10,5, pp. 1486-1495.

Shingfat Stephen Ching is currently withDigital Equipment Corporation. From 1973to 1976, he was a graduate research assistantat the University of Missouri-Rolla. His cur-rent fields of interest include design auto-mation of digital systems, microprogramnming,and microcomputer systems.Ching received the BS degree from California

State University at Sacramento and thePhD degree from the Univesity of Missouri-

trical engineering.

James H. Tracey is a professor of electricalengineering at the University of Missouri-Rolla, where he currently does research andteaches in the areas of digital system design,computer networks, computer graphics, andswitching theory. Previously he was an assis-tant professor at Iowa State University ofScience and Technology, Ames, where he alsoreceived the BS, MS, and PhD degrees inelectrical engineering.

Dr. Tracey is a member of Phi Kappa Phi,Kappa Nu, Pi Mu Epsilon, and ACM.

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