Adaptive Estimation of Thermal Dynamics and Charge Imbalance in ...
An Integrated Thermal Estimation Framework for Industrial ...
Transcript of An Integrated Thermal Estimation Framework for Industrial ...
An Integrated Thermal Estimation Framework for Industrial Embedded Platforms
Andrea Calimera
Andrea Acquaviva
Alberto Macii
Enrico Macii
Massimo Poncino
Politecnico di Torino STMicroelectronics
Matteo Giaconia
Claudio Parrella
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Thermal Issues
DIFFICULTIES IN DISSIPATING HEAT
DIFFICULTIES IN
DISSIPATING HEAT
POWER
CONSUMPTION
POWER
CONSUMPTION
THERMAL ISSUES• High Operating Temperature• Large Temperature Gradient
CIRCUIT
PERFORMANCE
CIRCUIT
PERFORMANCERELIABILITY and
AGING
RELIABILITY and
AGING
Technology scaling
MORE GENERATED HEAT
MORE GENERATED
HEAT
Efficient application of these techniques requires fast thermal estimations at each stage of the design flow
Intrusive thermal-aware design techniques are required at each level of abstraction
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� Intrusive thermal-aware design techniques have become a
must in modern SoCs, at each level of abstraction
� application level (e.g., thermal aware task migration)
� system level (e.g., 3D ICs, packaging, heat spreading)
� architectural level (e.g., Measure & Control techniques - DVFS)
� temperature monitors
� knobs which implement control strategies
� Efficient application of these strategies requires fast estimation of thermal effects in the earlier stages of the SoC
design flows
� spatial&temporal gradients
� peak operating temperature and hotspotsA thermal estimation framework which integrates heterogeneous info - at design time - is missing in today’s flow
Thermal Aware Design
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� An ideal thermal estimator... just alchemy?
� Why it is so hard... an industrial test case
� Power/thermal estimation flow
� What you can do
� Single component analysis
� Component interaction analysis
� Conclusions
Outline
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THERMAL ESTIMATOR
THERMAL ESTIMATOR
PO
WE
R
ES
TIM
AT
OR
PO
WE
R
ES
TIM
AT
OR
fast & accurate
dynamic + leakage
Heterogeneous Thermal Estimator
SYSTEM CONFIGURATION
SYSTEM CONFIGURATION
SYSTEMSYSTEM
RTLRTL
GATEGATE
APPLICATIONAPPLICATION SoC
PHYSICALPHYSICAL
THERMAL MODELS
THERMAL
MODELS
WORKLOADWORKLOAD
thermal profile
thermal-aware
design
sensors&knobs
power domains
packaging&heat sinks
battery sizing
feedback
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ST Spear 1300 MPU: Mean Features
� Designed for cost-sensitive applications requiring significant
processing and connectivity capabilities at low power
consumption
� networking/home gateways (eth and WiFi interface)
� embedded media and imaging (camera interface, LCD/touch screen
controller, audio codecs)
� Architecture
� ARM A9 Cortex dual-core power-optimized 800MHz
� 512KB L2 Cache
� Serial Management Interface (SMI - IP)
� One-time programmable logic (anti-fuse)
� 300KB SRAM Memory
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300KB
High Speed
AC
P
UHC (2)
UOC
GMAC
MultiLayer Interconnect MatrixMultiLayer Interconnect Matrix
EX
PA
NS
ION
INT
ER
FA
CE
SPEAr1300
Low Speed
10
70
Basic
50
Application
C A B D
10/10020/50 35/80 30
10 20 35 5575 80
10 20 50 80
10/2050/5570/75
30/354060
KBD
I
81
100
I2S(2)
I2C
SSP
FSMC
UART
RAM
JPGC
1.3 Mgates1.3 Mgates
100
80
F
G
61
72
RAS
LCD
10/10020/7540/80
70
6060
ADC
80 10 20 30 35 40 55 50 60 70
75
Misc
GPIO(2)
RTC
GPT(4)
20
SMI
ROM
40
SATA/PCIe0
MCIF
C3
55
L2CC
FPU PTM i/f
Cortex A9
I-cache
32KB
D-cache
32KB
FPU PTM i/f
I-cache
32KB
D-cache
32KB
ABI
SCU GIC
A9SM
WD
/T
IME
R Cortex A9
WD
/T
IME
R
10100
60
50/55/80
70/75
30/35/40
20/110
16/32 (ECC)
SDRAM
Controller
DDR 2/3
H
L
K
J
M
N
CFG
30
7535
R
DMAC
L2 cache (512KB)
110
DMAC
110 30 35 40
55 50 70 75 80 110
SATA/PCIe
1
SATA/PCIe
2
I
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ST Spear 1300 MPU: Low-Power
� Advanced power savings features
� Multiple power mode: Normal,
Slow, Sleep mode
� CPU clock with software programmable frequency
� Multiple power domains
� Dual-core CPU
� configurable logic
� PCI controllers
� Memories
� I/O peripheral
� 2 levels of coarse-grain clock-
gating structures for each power
domain
� Power-aware physical synthesis using low-power libraries with dual
threshold voltage cell usage
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� A smart power estimator should be able to integrate mixed
information obtained using different techniques at different
steps of the design flow
physical infofloorplan
process
physical info
floorplanprocess
SRAM
info form data-sheet
�Area, Access time
�Leakage, Dynamic per cycle
SRAM
info form data-sheet
�Area, Access time
�Leakage, Dynamic per cycle
ARM-LP + Cache-L1
info form data-sheet
�Area, Frequency
�Leakage, Dynamic VS Power-Mode
ARM-LP + Cache-L1
info form data-sheet
�Area, Frequency
�Leakage, Dynamic VS Power-Mode
Heterogeneous Power Information
Synthesizable IP
gate-level power estimation
based on STD timing/power
library
Synthesizable IP
gate-level power estimation
based on STD timing/power
library
Cache-L2
info form data-sheet
�Area, Access time, Latency
�Leakage VS PowerMode
�Dynamic power per cycle
Cache-L2
info form data-sheet
�Area, Access time, Latency
�Leakage VS PowerMode
�Dynamic power per cycle
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Example of Power Information
� Global figures
� Per process (fast, nominal)
� Per temperature (75°C, 125°C)
� Leakage & dynamic power
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Power Information: Per Component
� Per component
information
� Hard macros (red)
� Synthesizable logic (yellow)
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Power/Thermal Estimation Flow
� An unique environment based on Matlab Simulink® which
integrates different power estimation techniques and interfaces with a thermal library
1. Activity Modulation Blocks (AMBs)
2. Power Management Blocks (PMBs)
3. Power Computation Blocks (PCBs)
4. Temperature Computation Blocks (TCBs)
ACTIVITY
MODULATION
ACTIVITY
MODULATIONPOWER
COMPUTATION
POWER COMPUTATION
1
3
FLOORPLAN-LIKE INFORMATION
FLOORPLAN-LIKE INFORMATION
THERMAL
LIBRARY
THERMAL
LIBRARY
THERMPERATURE
SENSORS EMULATION
THERMPERATURE
SENSORS EMULATION
4
4POWER/THERMAL
MANAGER
POWER/THERMAL
MANAGER 2
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Activity Modulation Blocks (AMBs)
� AMBs set the utilization profiles (statically or dynamically)
of the system components
� Implemented using Simulink Stateflow®
� design environment for state charts and flow diagram
� can interface with cycle accurate simulators (MPARM-Scope-SIMICS)
� For each component of the SoC
� the functionality is described as a finite state machine
� the activity is defined as states and transitions among theme triggered by self-generated or asynchronous external events
Component AMBs Output
IPs FSM Switching activity over time
Hard Macro Power-State Machine Power-state currently in use
Memory Memory access emulation of a trace # read/write operation cycles
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Power Management Blocks (PMBs)
� PMBs simulate the implementation of power and thermal
management policies
� Implemented using Matalb Simulink®
� Interact with AMBs, PCBs and TCBs
� take the activity information from AMBs and the thermal information coming from the thermal feedback
� decide when to enter a certain power state configuration
� the power configuration is used inside PCBs to compute actual power consumption
� e.g., if a component is idle (info from AMBs), it is turned into a power-gating state (by PMBs); this info will be used to calculate the effective power consumption (info to PCBs)
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Thermal Computation Blocks (TCBs)
� PCBs compute dynamic and leakage power consumption
� Implemented using different techniques depending on the type of components and the power characterizations available
COMPONENT AVAILABLE INFO DESCRIPTION
Core processor + L1 cache
Power state information
� It is the only info available for hard macros� Power consumption quantified for the given tech. and for various corner cases (WC, NOM, BC, temperature)� Static and available for each power mode
Memories (L2 cache, SRAM)
Energy per read/write cycle
� Total leakage and dynamic power per cycle for various corner cases and operating conditions (Voltage, Temp.)
Synthesizable IPs
Gate-level netlist + switching activity analysis + tech.libs
� Accurate power estimation using standard library characterization provided by silicon vendors� Statistical analysis is performed by imposing a probabilistic switching activity on the input ports of the IP
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Thermal Computation Blocks (TCBs)
� TCBs provide thermal estimation exploiting information about component area and position
� power consumption data are sampled at predefined time intervals (speed/accuracy)
and converted into power-density
� data are fitted into the thermal library and an
equivalent RC electrical model is generated
� emulated sensors provide temperature
(voltage measurement on the RC model)
sisi
si
si
si
si
si
si
si
Cu cucu cu cu
powe
r
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Industrial Thermal Characterization
� Thermal analysis report on fabricated chips:
� Global parameter about heat dissipation
efficiency
� Theta j-a (junction-
ambient)
How many degrees between ambient and spreader to dissipate 1W
Tamb = 300K
Theta=24°C
Tchip = 324K
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Single Component Analysis
� A component is selected using the component selection mask,
while the rest of the chip remains at a given initial temperature
� Used for two purposes
� simulate a realistic functional behavior for a specific use case or power management configuration
� evaluate the the self-heating that specific component independently from the surroundings
� Serial Management Interface (SMI)
� Power oriented dual-Vth synthesis
� STMicrolectronics 65nm STM tech.
� Power characterization under different PVT corners
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Exploiting the Thermal Feedback
� Dynamic and Leakage power
characterization under
different input activity
� Temperature-aware power characterization are used
in the PCBs
electro-thermal
coupling
electro-thermal
coupling
temperatureinsensitivity
temperatureinsensitivity
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Exploiting the Thermal Feedback
� Electro-thermal coupling effect for different heat spreading technologies
� [Θ] = K/W → temperature difference between the environment and the heat
spreader to dissipate 1W (thermal resistance)
� [ct] = um → thickness of the spreader Simulation over time
Maximum temperature analysis
Feedback for the package sizing
Simulation over time
Maximum temperature analysis
Feedback for the package sizing
Θ reducesthickness increases
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SMI Leakage increase due to other
components in some configuration
SMI Leakage increase due to other
components in some configuration
Component Interaction Analysis
� Analyze the impact of a component on the others in order to
evaluate system level power/thermal management policies
effect of PGeffect of PG
CL is ON, but
C1/C2 are PG
CL is ON, but
C1/C2 are PG
3 power domains: Cores1/2, Configurable Logic, SMI
Configuration 4 5 6
Leakage increase 36% 23% 12%
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Dealing with Lack of Thermal Information
� Ab-Initio Thermal Modelling VS Learning Models
� Ab-initio
� Equations based on parameters (thermal conductivity of silicon and spreader)
� Requires characterization of both silicon and spreader
� Changes if the spreader changes
� Learning Models
� Use boot-time or run-time routines for thermal characterization
� Workload –> Power -> Temperature
� Requires temperature sensors
� Challenges
� Where to place sensors?
� Which identification routines?
� Off-line VS runtime?
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Thermal-Aware Resource Management
Resource Manager
RM interface
Boot-time thermal
characterizationThermal
control policy
Thermal model
Temperature
sensors
Performan
ce
counters
� Auto characterization of thermal
behavior exploits stress-test
routines and temperature sensor
readings
� The thermal
characterization is then used to
drive a thermal control policy
� The overall objective is to:
� Override RM decisions to
prevent temperature-induced
shut-down
� Introduce reliability awareness
in RM decisions
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Thermal-Aware Resource Management
� GOAL
� proactive management of chip temperature to limit hotspots and
gradients, to avoid performance hit due to temperature-induced
shutdown and increase overall system reliability
� FEATURES
� the thermal behavior auto-characterization capability avoids the need of
detailed thermal characterization
� exploit on-chip temperature sensors
� interface with RM developed by UNIBO
� INPUT OF RM:
� temperature sensors, performance counters (HW), core utilization
information
� OUTPUT OF RM:
� panic temperature alarm, hotspots and thermal gradient information to
drive RM decisions about voltage/frequency scaling and task allocation
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Power consumption induced
by the stress-test routineTemperature sensors readings
Example with 4 cores and 2 temperature sensors
These traces are used to perform a thermal model identification
Example of Thermal Identification (I)
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Comparison between the real
temperature (black) and the
estimated temperature (blue)
Sensor 1
Example with 4 cores and 2 temperature sensors
Sensor 2
� PREDICTION RESULTS:
Example of Thermal Identification (II)
� The identified model is then used to:
� Make prediction about the temperature behavior for a given workload
characteristic
� Develop the control policy (TBD)T(°K)
Time (sec)
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Conclusions
� Temperature matters... several figures of merit are affected
(Performance, Power, Reliability)
� Thermal aware design has become a must
� Estimating temperature in the earlier design stages is of
paramount importance
� Integrated power/thermal estimators are now required
� Heterogeneous power information (from system to physical level)
� Link power and physical information to tech dependent thermal libraries
� Thermal feedback to drive thermal-aware design strategies
� Thermal identification is possible to avoid extensive
characterization and flexibility
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