An Integrated Programmable Wide-range PLL for …...and Andishe Moshirvaziri, Shuze Zhao, Vishal...

An Integrated Programmable Wide-range PLL forSwitching Synchronization in Isolated DC-DC Converters

by

Miad Fard

A thesis submitted in conformity with the requirementsfor the degree of Master of Applied Science

Graduate Department of Electrical and Computer EngineeringUniversity of Toronto

© Copyright 2016 by Miad Fard

Abstract

An Integrated Programmable Wide-range PLL for Switching Synchronization in

Isolated DC-DC Converters

Miad Fard

Master of Applied Science

Graduate Department of Electrical and Computer Engineering

University of Toronto

2016

In this thesis, two Phase-Locked-Loop (PLL) based synchronization schemes are intro-

duced and applied to a bi-directional Dual-Active-Bridge (DAB) dc-dc converter with

an input voltage up to 80 V switching in the range of 250 kHz to 1 MHz. The two

schemes synchronize gating signals across an isolated boundary without the need for an

isolator per transistor. The Power Transformer Sensing (PTS) method utilizes the DAB

power transformer to indirectly sense switching on the secondary side of the boundary,

while the Digital Isolator Sensing (DIS) method utilizes a miniature transformer for syn-

chronization and communication at up to 100 MHz. The PLL is implemented on-chip,

and is used to control an external DAB power-stage. This work will lead to lower cost,

high-frequency isolated dc-dc converters needed for a wide variety of emerging low power

applications where isolator cost is relatively high and there is a demand for the reduction

of parts.

ii

Acknowledgements

I’d like to begin by expressing my sincerest gratitude to my supervisor, Professor Olivier

Trescases, who has been an inspiration and a driving force in my development as an

engineer for the past 5 years. His support and vision served as a guiding light throughout

the duration of my master studies. His patience, and the freedom he gave me to express

creativity in my work was of tremendous importance to my growth. I am more mature

and more confident as an engineer because of his motivation, and he will continue to be

a great source of inspiration in my life.

I would like to thank my dear friend, colleague, and mentor, Shahab Poshtkouhi, with

whom we established the basis upon which I developed my research. With his guidance

we were able to tape out the chip that is presented in this thesis. The integrated power-

stage that he developed for the chip, is only mentioned and not covered in this thesis as

it is outside the scope of my contributions. Some of the figures and content produced

for the APEC 2016 digest submission, based on our joint research, is represented in this

thesis. I wish Shahab great success in his PhD studies and future life.

I would also like to thank Mehrad Mashayekhi, Richard Medal, Yue Wen, Mazhar

and Andishe Moshirvaziri, Shuze Zhao, Vishal Palaniappan, King Wai (David) Li, Ryan

Fernandes, and S. M. Ahsanuzzaman for their friendship and support.

I would like to acknowledge Ray Orr and Ben Bacque from Solantro Semiconductors

for their continued support and guidance during the course of this project. It has been a

valuable experience collaborating with and learning from them. Ike Choi and Magnachip

for their support during the design process of the designed IC. Without it we could not

have made the shuttle.

My family has always pointed me in the right direction and has given me a template of

how much hard work goes into being successful. I would like to thank my parents Simin

Kabiri and Hassan Fard for their love and support throughout my education and for

motivating me to excel in everything I do. I would also like to thank my brothers Emad

and Ali Fard for being the perfect role models. They have given me the competitive drive

that has always gotten me through adversity. Finally, I would like to thank my lovely

girlfriend Krisel Quiambao for being patient and supportive during the sleepness nights

when I was taping out my chip.

Last but not the least, I offer a sincere token of appreciation to those who have helped

and supported me by any means during this period. It has been a great pleasure sharing

this time of my life with all of you.

iii

Contents

1 Introduction 1

1.1 Isolated Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Synchronization in Isolated Converters . . . . . . . . . . . . . . . 1

1.1.2 Basic Operation of Dual-Active-Bridge . . . . . . . . . . . . . . . 3

1.2 Thesis Motivations and Objectives . . . . . . . . . . . . . . . . . . . . . 4

2 System Architecture 9

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Synchronization Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Power Transformer Sensing (PTS) . . . . . . . . . . . . . . . . . . 9

2.2.2 Digital Isolator Sensing (DIS) . . . . . . . . . . . . . . . . . . . . 11

2.3 Phase-Locked-Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.1 Delay-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.2 Phase Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 Charge-Pump and Loop-Filter . . . . . . . . . . . . . . . . . . . . 16

2.4 Chapter Summary and Conclusions . . . . . . . . . . . . . . . . . . . . . 17

3 Integrated Circuit Implementation and Simulation 19

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Serial Peripheral Interface Communication and Memory Banks . . . . . . 19

3.3 Digital Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.1 Input Reference Clock Distribution . . . . . . . . . . . . . . . . . 23

3.3.2 Reference Clock in DIS Mode . . . . . . . . . . . . . . . . . . . . 23

3.3.3 Fine Phase Shift Tuning . . . . . . . . . . . . . . . . . . . . . . . 24

3.3.4 PWM Generation and Coarse Phase Shift Tuning . . . . . . . . . 25

3.4 Phase-Locked-Loop Design and Considerations . . . . . . . . . . . . . . . 26

3.4.1 Delay-Line and Delay Elements . . . . . . . . . . . . . . . . . . . 26

3.4.2 Programmable Current Bank and Charge-Pump . . . . . . . . . . 28

iv

3.4.3 Programmable Loop-Filter . . . . . . . . . . . . . . . . . . . . . . 29


4 Implementation and Experimental Results 36

4.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1.1 Integrated Circuit Die and Packaging . . . . . . . . . . . . . . . . 36

4.1.2 PCB Implementation with Graphical User Interface . . . . . . . . 38

4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2.1 Communication Confirmation . . . . . . . . . . . . . . . . . . . . 41

4.2.2 Locking to External Reference Clock . . . . . . . . . . . . . . . . 41

4.2.3 Phase Shift Experimentation . . . . . . . . . . . . . . . . . . . . . 45

4.2.4 GISO Transmission Across Isolation Boundary . . . . . . . . . . . 47

4.2.5 Synchronized DAB Converter Waveforms . . . . . . . . . . . . . . 50


5 Conclusions 53

5.1 Thesis Summary and Contributions . . . . . . . . . . . . . . . . . . . . . 53

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

v

List of Tables

3.1 Memory Bank registers. . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 Configurable PLL parameters. . . . . . . . . . . . . . . . . . . . . 31

3.3 Stability analysis configuration. . . . . . . . . . . . . . . . . . . . 34

4.1 PLL settings for locking to 1 MHz. . . . . . . . . . . . . . . . . 43

5.1 Comparison of Driving Schemes in Isolated Converters. . . . 54

vi

List of Figures

1.1 (a) Architecture of a conventional isolated two-stage bi-directional dc-ac

converter (one isolator per transistor). (b) Alternative architecture where

the secondary-side controller drives the secondary-side switches, which re-

quires a synchronization scheme. . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Architecture of isolated DAB dc-dc converter. . . . . . . . . . . . . . . . 3

2.1 Simplified architecture of the two proposed synchronization schemes (DIS

and PTS) implemented on a DAB dc-dc converter. . . . . . . . . . . . . 10

2.2 Start-up sequence for PTS mode. . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Four-layer PCB layout of GISO high-frequency transformer used in DIS

mode shown on a 1mm grid. . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 GISO packet including the preamble and data periods. The PLL is acti-

vated during the preamble period. . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Simplified PLL architecture including the Delay-Line, Phase Detect, Charge-

Pump, and Loop-Filter blocks. . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Delay-Line including the Bias Generator, and Delay Elements. . . . . . . 15

2.7 (a) Architecture of Phase Detect block utilizing two Flip Flops and a

NAND gate to detect phase difference between two clocks. (b) Waveforms

showing operation of Phase Detect on two clocks with different frequencies. 16

2.8 Charge-Pump and the Loop-Filter, which provide the bias voltage for the

Delay-Line to adjust output frequency. . . . . . . . . . . . . . . . . . . . 17

3.1 Functional diagram of a typical 8-bit SPI protocol. Serially, the bytes of

data [10011111] and [10110011] are written and read, respectively, on the

rising edge of the SPI clock once the chip select signal goes low. . . . . . 20

3.2 Verilog functional simulation showing three 16-bit SPI cycles to write new

data, send ”Read” command, and read contents of 12-bit execSEL Memory

Bank register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

vii

3.3 The Digital Core provides configuration bits for different functions of the

analog PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4 Functional simulation of the Digital Core parsing a GISO packet. . . . . 24

3.5 Simulated waveform of Delay-Line output through 32-to-1 MUX for all

values of 5-bit control bus. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.6 Simulated waveform of Delay-Line output versus time as Bias Voltage, Vc,

is swept to 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.7 Delay-Line output versus Bias Voltage, VC . A slope of 105 MHz/V is

achieved within the desired range of 80-120 MHz. . . . . . . . . . . . . . 28

3.8 Charge-Pump circuit and Current Bank which provides chip with pro-

grammable current sources. . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.9 Bode plot of the Loop-Filter’s open loop gain, showing the desired relative

locations of the unity gain bandwidth, the zero and the pole. . . . . . . . 31

3.10 The memory bank can be programmed to turn on and off switches to

configure the desired Loop-Filter configuration. . . . . . . . . . . . . . . 32

3.11 Stabilization analysis for (a) 250 kHz and (b) 100 MHz locking frequency. 33

3.12 Closed-loop PLL startup operation with 100 MHz reference clock. . . . . 34

4.1 Layout of the on-chip PLL with labeled blocks presented in thesis. . . . . 37

4.2 Chip micrograph of die packaged in a 60-pin QFN package. . . . . . . . . 38

4.3 Architecture of test setup including an FPGA board, a GUI link, and the

test board containing the chip. . . . . . . . . . . . . . . . . . . . . . . . . 39

4.4 (a) IC PCB populated with the designed QFN chip and passive compo-

nents. (b) Control PCB with two isolated planes each with a dock for IC

PCBs for testing and debugging inter-boundary communication. . . . . . 40

4.5 The GUI allows for easy access to IC Memory Bank registers on either

side of the isolated boundary. . . . . . . . . . . . . . . . . . . . . . . . . 41

4.6 Experimental result of testing the IC’s SPI communication protocol. Data

is written into a Memory Bank register, and data is read out to confirm

proper data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.7 The PLL clock, CLKSY NC , locking to an external 1 MHz reference clock,

CLKREF , with bias voltage, VC shown. (a) The startup process with the

bias voltage gradually ramping up and stabilizing to lock CLKSY NC to the

reference clock. (b) A zoomed in view of the waveforms at steady-state,

where CLKSY NC is locked to CLKREF with stable VC . . . . . . . . . . . 44

viii

4.8 Circuit used to map the phase-shift between the reference and output

signal of the PLL to a 0 to 3.3 V analog voltage. . . . . . . . . . . . . . . 46

4.9 Plotted experimental result of tuning the 12-bit phaseSEL register and

measuring the resultant phase difference. . . . . . . . . . . . . . . . . . . 46

4.10 GISO operation across two boundaries using two ICs transmitting data

across a high speed transformer. The 150 MHz input clock to the TX side

is shown, along with the low swing dual rail signal going to the transformer

on the TX side. The resultant regenerated clock is output from the RX side. 48

4.11 The PLL clock, CLKSY NC , locking to a high speed 50 MHz reference clock

through the GISO protocol. (a) The startup process with the bias voltage

gradually ramping up and stabilizing to lock CLKSY NC to the reference

clock. (b) A zoomed in view of the waveforms at steady-state to show a

single GISO packet and the pllHOLD pattern with stable VC . . . . . . . 49

4.12 Synchronized DAB converter waveforms in the PTS mode (ILDAB: 5A/div). 50

4.13 Synchronized DAB converter waveforms in DIS mode with continuous 50

MHz GISOin input clock (ILDAB: 5A/div). . . . . . . . . . . . . . . . . . 51

ix

Chapter 1

Introduction

1.1 Isolated Converters

High-efficiency isolated power converters have been widely studied for emerging applica-

tions such as Electric Vehicles (EV), smart battery chargers [1, 2], and Photovoltaic (PV)

Micro-Inverters (MIV) [3]. In particular, there is a growing demand for bi-directional

power-flow capability and four-quadrant operation in inverters. Multi-port MIVs with

integrated storage, which is typically realized with a battery [4, 5] or super-capacitor [3],

have been proposed for reactive power support and off-grid operation as well as active

power smoothing [3]. Bi-directional EV charger topologies with Vehicle-to-Grid (V2G)

capability can provide ac grid support using the on-board battery during peak load de-

mand [6, 7].

1.1.1 Synchronization in Isolated Converters

A bi-directional dc-dc converter, as shown in Fig. 1.1(a) [7], requires active devices on

both sides of the transformer. Certain unidirectional dc-dc topologies, such as the LLC

converter, may also be designed with active switches on both sides of the isolation for im-

proved efficiency [8]. As the switching frequency is scaled up for improved power density

1

Chapter 1. Introduction 2

+

Vbus

-

ac grid+

V1

-

IacDc-dc Stage Dc-ac Stage

Bi-Directional MIV

Architecture

Digital

Controller

Digital

Isolators

drive

communicationDigital

Controller

drive

(a)

+

Vbus

-

ac grid+

V1

-

IacDc-dc Stage Dc-ac Stage

Bi-Directional MIV

Architecture

Digital

ControllerSynchronization

/communication

Digital

Controller

drive

(b)

Figure 1.1: (a) Architecture of a conventional isolated two-stage bi-directional dc-ac con-verter (one isolator per transistor). (b) Alternative architecture where the secondary-sidecontroller drives the secondary-side switches, which requires a synchronization scheme.

in modern converters, driving multiple switches on both sides of the transformer with pre-

cise timing is a major challenge. Low-frequency communication is also required between

the dc-dc and dc-ac stages for tasks such as start-up, fault-handling and feedforward

control loops, hence the need for additional digital isolators.

Opto-isolators are commonly used, however they suffer from poor matching, rela-

tively long delays (typically ≥15 ns) and short life-time at high temperature [9, 10].

More recently, digital isolators and isolated gate-drivers based on miniaturized magnetic

components or capacitive coupling either on the PCB [11] or on-chip [12–16] have ad-

dressed some of these shortcomings, while offering a high level of integration. Digital

isolators and drivers typically modulate the PWM signal with a carrier in the range of


tens of MHz to several GHz in order to reduce the size of the isolation passive compo-

nents [15, 16]. Moreover, the driver cost scales with the number of active switches driven

from the opposite side of the isolation.

1.1.2 Basic Operation of Dual-Active-Bridge

The work presented in this thesis focuses on the soft-switching Dual Active Bridge (DAB)

converter, as shown in Fig. 1.2, due to its wide-spread use in the industry for PV and

battery charging applications, among others. Both bridges operate with a duty cycle, D,

of 50% and the steady-state power flow is given by:

PDAB =VPV VbusnωsLDAB

φ

(1− |φ|

π

), (1.1)

where VPV and Vbus are the input and output voltage, respectively; n is the transformer

turns ratio; LDAB is the DAB inductance, which is the sum of transformer’s leakage

inductance and the external inductance; φ is the phase-shift between the two bridges;

and ωs = 2πfs, where fs is the switching frequency.

LDAB 1:n Cbus

+

V1

-

+

Vbus

-

ILDAB

ID

Cin + VLDAB -

M1 M2

M3 M4

M5 M6

M8M7

I1

Primary Side Secondary Side

c1 c2

c3 c4

c5 c6

c7 c8

Figure 1.2: Architecture of isolated DAB dc-dc converter.


1.2 Thesis Motivations and Objectives

This work is part of a long-term project to monolithically integrate the power transistors,

gate-drivers, digital controller and the digital isolation capability in a BCD technology

for optimized cost and performance.

In this thesis two alternative synchronization schemes are demonstrated on-chip to

eliminate the need for using one isolator per transistor, specifically in the context of

small-sized, high-frequency DAB converters where parts count is critical:

1. The Power Transformer Sensing (PTS) method relies on extracting the switching

signal on the secondary side directly from the reflected voltage across the power

transformer. The driving waveforms are reconstructed accordingly on the primary

side based on a 250 kHz to 1 MHz frequency range to target a high frequency DAB

for miniaturization.

2. The Digital Isolator Sensing (DIS) method encodes switching information in the

data packets sent through a miniature high-frequency galvanically isolated transceiver

(GISO) operating at about 100 MHz in order to make the GISO transformer as

small as possible without trading off high losses.

In both schemes, the active devices on the secondary side of the dc-dc stage are driven

by the dc-ac stage controller, as shown in Fig. 1.1(b), and a Phase-Locked-Loop (PLL)

is used for clock recovery.

It is important to note that both synchronization schemes are not intended to be

implemented together in a final product, allowing for a greatly simplified PLL design.

The objective of this thesis is to design a test chip to realize a PLL that demonstrates

the functionality of the two aforementioned synchronization methods with the following

requirements:

Operation compatible with discrete soft-switching DAB converter to allow power

flow across an isolated boundary with an input voltage range of up to 80 V.


PLL able to lock to wide frequency range of 250 kHz to 100 MHz to accommodate

both synchronization methods.

Internal transmission and reception of GISO packet to communicate and synchro-

nize at high speeds across an isolated boundary. The PLL will go on hold and stay

locked during the data phase of the GISO packet.

Programmable IC to change settings through an SPI interface running at 25 MHz

to allow for future work in closed loop control.

The PLL must produce a frequency divided and phase-shifted PWM signal, based

on locked synchronization frequency, to be sent as gating signals to DAB power-

stage. During switching events the PLL will be blanked due to on-chip power

transistors.

The thesis is organized as follows. The architecture and high-level system diagrams

of the PLL and synchronization schemes are presented in Chapter 2. The simulation and

design considerations of the PLL are presented in Chapter 3. The hardware implemen-

tation and testing of the final chip is covered in Chapter 4. Finally, the conclusion and

future work are presented in Chapter 5.

References

[1] Y.-C. Wang, Y.-C. Wu, and T.-L. Lee, “Design and implementation of a bidirectional

isolated dual-active-bridge-based dc/dc converter with dual-phase-shift control for

electric vehicle battery,” in 2013 IEEE Energy Conversion Congress and Exposition

(ECCE), Sept 2013, pp. 5468–5475.

[2] D. Costinett, K. Hathaway, M. Rehman, M. Evzelman, R. Zane, Y. Levron, and

D. Maksimovic, “Active balancing system for electric vehicles with incorporated

low voltage bus,” in 2014 Twenty-Ninth Annual IEEE Applied Power Electronics

Conference and Exposition (APEC), March 2014, pp. 3230–3236.

[3] S. Poshtkouhi, M. Fard, H. Hussein, L. Dos Santos, O. Trescases, M. Varlan, and

T. Lipan, “A dual-active-bridge based bi-directional micro-inverter with integrated

short-term li-ion ultra-capacitor storage and active power smoothing for modular pv

systems,” in Applied Power Electronics Conference and Exposition (APEC), 2014

Twenty-Ninth Annual IEEE, March 2014, pp. 643–649.

[4] W. Hu, H. Wu, Y. Xing, and K. Sun, “A full-bridge three-port converter for renew-

able energy application,” in Applied Power Electronics Conference and Exposition

(APEC), 2014 Twenty-Ninth Annual IEEE, March 2014, pp. 57–62.

[5] Q. Mei, X. Zhen-lin, and W.-Y. Wu, “A novel multi-port dc-dc converter for hy-

brid renewable energy distributed generation systems connected to power grid,” in

6

REFERENCES 7

Industrial Technology, 2008. ICIT 2008. IEEE International Conference on, April

2008, pp. 1–5.

[6] C.-J. Shin and J.-Y. Lee, “An electrolytic capacitor-less bi-directional ev on-board

charger using harmonic modulation technique,” Power Electronics, IEEE Transac-

tions on, vol. 29, no. 10, pp. 5195–5203, Oct 2014.

[7] B. Koushki, A. Safaee, P. Jain, and A. Bakhshai, “Review and comparison of bi-

directional ac-dc converters with v2g capability for on-board ev and hev,” in Trans-

portation Electrification Conference and Expo (ITEC), 2014 IEEE, June 2014, pp.

1–6.

[8] S. Abe, T. Ninomiya, T. Zaitsu, J. Yamamoto, and S. Ueda, “Seamless operation

of bi-directional llc resonant converter for pv system,” in Applied Power Electronics

Conference and Exposition (APEC), 2014 Twenty-Ninth Annual IEEE, March 2014,

pp. 2011–2016.

[9] A. Thaduri, A. Verma, G. Vinod, and R. Gopalan, “Reliability prediction of op-

tocouplers for the safety of digital instrumentation,” in 2011 IEEE International

Conference on Quality and Reliability (ICQR), Sept 2011, pp. 491–495.

[10] P. Jacob, G. Nicoletti, and M. Rutsch, “Reliability failures in small optocoupling

and dc/dc converter devices,” in 2006. 13th International Symposium on the Physical

and Failure Analysis of Integrated Circuits, July 2006, pp. 167–170.

[11] S. Hui, S. C. Tang, and H.-H. Chung, “Optimal operation of coreless pcb

transformer-isolated gate drive circuits with wide switching frequency range,” IEEE

Transactions on Power Electronics, vol. 14, no. 3, pp. 506–514, May 1999.

[12] Y. Moghe, A. Terry, and D. Luzon, “Monolithic 2.5kv rms, 1.8v;3.3v dual-channel

640mbps digital isolator in 0.5 um sos,” in IEEE International SOI Conference

(SOI), Oct 2012, pp. 1–2.

REFERENCES 8

[13] T. V. Nguyen, J.-C. Crebier, and P.-O. Jeannin, “Design and investigation of an

isolated gate driver using cmos integrated circuit and hf transformer for interleaved

dc/dc converter,” IEEE Transactions on Industry Applications, vol. 49, no. 1, pp.

189–197, Jan 2013.

[14] S. Nagai, T. Fukuda, N. Otsuka, D. Ueda, N. Negoro, H. Sakai, T. Ueda, and

T. Tanaka, “A one-chip isolated gate driver with an electromagnetic resonant cou-

pler using a spdt switch,” in 2012 24th International Symposium on Power Semi-

conductor Devices and ICs (ISPSD), June 2012, pp. 73–76.

[15] K. Muhammad and D.-C. Lu, “Magnetically isolated gate driver with leakage in-

ductance immunity,” IEEE Transactions on Power Electronics, vol. 29, no. 4, pp.

1567–1572, April 2014.

[16] B. Chen, “icoupler products with isopower technology: Signal and power transfer

across isolation barrier using microtransformers,” Analog Devices Inc., 2006, avail-

able http://www.analog.com/static/imported-files/overviews/isoPower.pdf.

Chapter 2

System Architecture

2.1 Introduction

This thesis presents a custom IC developed in a high-voltage 0.18 µm BCD technology to

demonstrate the design and operation of the PLL and the two synchronization schemes

on a DAB converter. The system architecture is presented in this chapter.

2.2 Synchronization Methods

The high-level architecture of the design is shown in Fig. 2.1. Synchronization can be

achieved using either a high-frequency isolated communication channel (DIS mode, acti-

vated when mode = 1), or sensing through the power transformer (PTS mode, activated

when mode = 0).

2.2.1 Power Transformer Sensing (PTS)

Using the PTS scheme, synchronization is achieved by sensing the reflected voltage across

the power transformer, hence eliminating the need for any digital isolator. The PTS

scheme was first reported in [1] using discrete components, where it was also shown

9

Chapter 2. System Architecture 10

LDAB 1:n Cbus

+

V1

-

+

Vbus

-

ILDAB Vx1

Vx2

ID

Cin + VLDAB -

M1 M2

M3 M4

M5 M6

M8M7

I1

Primary Side Secondary Side

Digital

ControllerDecoder/Encoder

PLL

CLK

RE

F

clk

_syn

c

counter

Digital Contro ller

φ

V1 I1 Vbus+

-s0

s1

mode

HF Transformer

c1 c4c3 c2

c1 c2

c3 c4

c5 c6 c7 c8

c5 c6

c7 c8

PTS Mode

DIS Mode

PW

M

Shift

Register

Dead-time

and Logic

Figure 2.1: Simplified architecture of the two proposed synchronization schemes (DISand PTS) implemented on a DAB dc-dc converter.

that low-frequency uni-directional communication can be achieved through switching

frequency modulation. The reflected switching waveform on the secondary side is de-

tected using a comparator, and the resulting waveform, comp, is fed as CLKREF to the

PLL, as shown in Fig. 2.1. When locked, CLKSY NC is in phase with the secondary-side

switching and can thus be phase-shifted in order to generate four PWM signals, c1−4, to

drive the primary side. The start-up sequence is illustrated in Fig. 2.2. Once the sec-

ondary controller activates the secondary-side bridge, the switching action is detected on

the primary side and PLL is enabled. The charge-pump output voltage, VC , is regulated

in order to synchronize CLKSY NC to CLKREF . Once lock is achieved, the converter can

start-up by driving c1−4.


pll_en

Vc

c1-4

c5-8

comp

Secondary starts

switching

Lock achieved: Primary starts switching

Figure 2.2: Start-up sequence for PTS mode.

2.2.2 Digital Isolator Sensing (DIS)

The DIS method utilizes a single digital isolator to achieve two purposes: 1) to synchro-

nize both controllers on opposite sides of the isolation and 2) to transmit data between the

controllers, as needed for control and fault handling. A custom low-power, high-speed

galvanically isolated (GISO) interface was developed to demonstrate the DIS scheme.

High-frequency modulation, up to 100 MHz, is adopted to reduce the air-core trans-

former size, which can be implemented using PCB traces, as shown in Fig. 2.3. The

high-speed GISO transceiver is designed with 1.8 V devices and transmits a differential

low-amplitude signal (typically 50-250 mV) across an on-chip 20 Ω termination resistor,

with a common-mode voltage of 0.9 V. The critical GISO parameters, including the driver

signal-swing and the receiver hysteresis are digitally programmable via an SPI interface.

The design and optimization of the GISO transceiver for DIS mode is beyond the scope

of this thesis.

A typical GISO communication packet includes two main components, as shown in


Figure 2.3: Four-layer PCB layout of GISO high-frequency transformer used in DIS modeshown on a 1mm grid.

Fig. 2.4. The first period of the packet is a preamble and serves as the reference clock,

CLKREF , for the PLL. The PLL is enabled during the preamble period. The bits

following the preamble contain the data and can be recovered using a variety of well-

known methods, such as Manchester coding [2]. The PLL is put into a hold state, where

the phase detector is disabled, in between consecutive pre-amble periods. The Voltage-

Controlled-Oscillator (VCO) is therefore free-running during this time. It is necessary

to maintain regular communication in order to maintain an acceptable PLL drift. Fur-

thermore, the PLL is placed in the hold state for 3% of the switching period, Ts, during

power-transistor switching, in order to minimize the disturbance on the synchronizing

operation. The locked output of PLL, CLKSY NC , is used as the main system clock in

order to generate the phase-shifted PWM signal, CLKSW , to control the primary-side

bridge of the DAB converter. The phase-shift is achieved by using a combination of a


Delay-Line and a counter for fine and coarse delay adjustment, respectively. The phase-

shift resolution is k + m, where k and m are the number of delay elements and counter

bits respectively. This is similar to the segmented approach of using a delay-line and

counter in high-resolution digital pulse-width modulators. In this work k = 5 and m =

7 are adopted.

hold

Vc

CLKSYNC

GISOin

PWM

Preamble:

PLL Enabled

Data:

PLL Disabled

3% Ts

PLL

drift

Figure 2.4: GISO packet including the preamble and data periods. The PLL is activatedduring the preamble period.

2.3 Phase-Locked-Loop

To achieve synchronization across an isolated boundary, the system must lock to an

external clock source, which can be realized using a Phase-Locked-Loop (PLL). The

analog PLL, as shown in Fig. 2.5, is implemented to include a ring of 31 current-starved

inverters. All inverters are fed back the same bias voltage from a phase detect block which


compares the rising edges of an external CLKREF and the internal CLKSY NC (from the

Delay-Line). The phase detect block determines whether the bias voltage should increase

or decrease to adjust the Delay-Line frequency. This closed loop system is designed as a

control system to generate an output clock signal with the same phase and frequency of

an input reference clock.

Phase

Detect

UP

DOWN

REF

SYNC

Charge

Pump VCAP

UP

DOWN

Loop Filter

Delay Line

CLKREF

CLKSYNC

Figure 2.5: Simplified PLL architecture including the Delay-Line, Phase Detect, Charge-Pump, and Loop-Filter blocks.

2.3.1 Delay-Line

The Delay-Line presented in this work serves as a Voltage Controlled Oscillator (VCO)

in the PLL module. Fig. 2.6 shows the design of the Delay-Line, including the bias

generator, and two of the 31 delay elements (connected in a ring). The control voltage

VC is sent to the Bias Generator block, where two bias signals are created to control the

rising and falling edges of the adjacent delay element by biasing the current drawn by

a CMOS inverter. The two bias signals, biasLS and biasHS are sent to all 31 delay

elements, ultimately controlling the output frequency of the adjustable ring oscillator

by current starving the inverters to increase rise and fall time. In each delay element,

additional inverters are added to serve as buffers, and to control the delay range of each

element based on the desired frequency range of the Delay-Line. Design considerations


and simulation results of the PLL are discussed in Section 3.4.

VDD

biasHS

IN

biasLS

GND

Bias

Generator

Vc

biasHS

biasLS

Figure 2.6: Delay-Line including the Bias Generator, and Delay Elements.

2.3.2 Phase Detect

The Phase Detect block compares the rising edge of the external reference clock, CLKREF ,

to that of the internal clock derived by the Delay-Line, CLKSY NC . As shown in Fig. 2.7(a),

two Flip Flops are clocked by the rising edge of each clock source. The input of both Flip

Flops are connected to V DD, so that on each rising edge the Flip Flop output Q goes

high for each clock source. A NAND gate connected to each Flip Flop output resets both

Flip Flops upon two consecutive rising edges from each clock source. In this scheme, if the

CLKREF rising edge arrives first then the Phase Detect block’s UP signal goes high until

the CLKSY NC rising edge arrives. Alternatively, if the CLKSY NC rising edge arrives first

then the Phase Detect block’s DOWN signal goes high until the CLKREF rising edge

arrives. This operation of the Phase Detect is shown in Fig. 2.7(b). The Phase Detect

block essentially detects whether CLKSY NC is leading or lagging CLKREF , and by how

much. In the following subsection, the Charge-Pump and Loop-Filter is introduced to

finish off how the Phase Detect’s UP and DOWN signals affect the Delay-Line’s bias


voltage V c to tune its output frequency to eventually lock with CLKREF .

D Q

RST

D QRST

UP

DOWN

CLKREF

CLKSYNC

VDD

VDD

(a)

UP

DOWN

CLKREF

CLKSYNC

(b)

Figure 2.7: (a) Architecture of Phase Detect block utilizing two Flip Flops and a NANDgate to detect phase difference between two clocks. (b) Waveforms showing operation ofPhase Detect on two clocks with different frequencies.

2.3.3 Charge-Pump and Loop-Filter

The UP and DOWN signals derived in the Phase Detect stage are passed on to the

charge pump. As shown in Fig. 2.8, depending on whether UP or DOWN are high

out of the Phase Detect block, current is either be pumped in, or pumped out of the

Loop-Filter, respectively. This either increases or decreases the voltage across the filter,

and since this voltage is used to bias the Delay-Line, it has a direct impact on the output

frequency of the PLL output, CLKREF .

The Loop-Filter not only acts as a capacitor bank for the bias voltage of the Delay-

Line, it is also directly responsible for the stability of the PLL. Given that the PLL is

a closed loop control system, the performance of the PLL relies on the stability of the

system, dictated by the values chosen for C1, C2, and R1 of the Loop-Filter. The transfer

function and stability design of the PLL and Loop-Filter is discussed in Section 3.4.


R1

Loop Filter

C1

C2

VDD

UP

DOWN

Vc

Figure 2.8: Charge-Pump and the Loop-Filter, which provide the bias voltage for theDelay-Line to adjust output frequency.

2.4 Chapter Summary and Conclusions

The system-level architecture of the on-chip PLL, the transistor-level schematics of the

PLL components, and the control scheme are presented in this chapter. The two syn-

chronization schemes available on the chip are also presented. PTS mode utilizes an

internal comparator to generate a PWM signal on the primary side of the DAB from the

switching signal forced onto the power transformer from the secondary side. To allow

for miniaturization, the DAB converter switches at a high frequency within the range of

250 kHz to 1 MHz. In DIS mode, the synchronization between the two isolated sides of

the DAB occurs through a GISO protocol on the chip placed on each side of the isola-

tion boundary. One chip acts as the TX module to send encoded switching information

to the RX module on the opposite side through a high speed transformer. To reduce

transformer size, the data is transferred in the 50-100 MHz range.

References

[1] S. Poshtkouhi, A. Eski, and O. Trescases, “Pll based bridge synchronization as an

alternative to digital isolators for dual active bridge dc-dc converters,” in Applied

Power Electronics Conference and Exposition (APEC), 2015 IEEE, March 2015, pp.

9–14.

[2] G. Raghul, K. Sudhakar, and M. Devi, “Design and implementation of encoding

techniques for wireless applications,” in Circuit, Power and Computing Technologies

(ICCPCT), 2015 International Conference on, March 2015, pp. 1–7.

18

Chapter 3

Integrated Circuit Implementation

and Simulation

3.1 Introduction

This chapter presents the implementation of the IC including schematics and design

considerations. Where applicable, simulation results are shown, including circuit level

SPECTRE simulations, and functional timing simulations of Verilog code synthesized

into the design of the chip. The communication and memory protocols are introduced

first to demonstrate the high reconfigurability of the chip through a digital programming

interface.

3.2 Serial Peripheral Interface Communication and

Memory Banks

To communicate with the chip, a Serial Peripheral Interface (SPI) protocol is imple-

mented in Verilog and synthesized into the IC design. SPI communication follows a

master-slave architecture. Data is registered serially based on a universal clock shared

19

Chapter 3. Integrated Circuit Implementation and Simulation 20

among the Master device and all its subsequent slave devices, allowing for reading and

writing of data. An example of SPI communication is shown in Fig. 3.1.

MASTER SLAVE

SCK

MOSI

MISO

!CS

SCK

MOSI

MISO

!CS

1 0 0 1 1 1 1 1

1 0 1 1 0 0 1 1

SCK

(Clock from Master)

MOSI

(Data written to Slave)

MISO

(Data read from Slave)

!CS

(Active low Chip Select)

Write to Slave Read from Slave

Figure 3.1: Functional diagram of a typical 8-bit SPI protocol. Serially, the bytes of data[10011111] and [10110011] are written and read, respectively, on the rising edge of theSPI clock once the chip select signal goes low.

A summary of the programmable Memory Bank registers is shown in Table 3.1.A list

of relevant Memory Bank registers and their bit allocation is shown in Table 3.1. In this

table, phaseSEL controls the phase-shift added to the output PWM signal in two stages,

fine tuning and coarse tuning. This process is further explained in Section 3.3. fswSEL

is used to program the switching frequency of the PWM signal using digital counters, as

well as the number of cycles allocated to the startup phase, which is used to ramp up the

PLL. preambleSEL configures the expected GISO packet parameters including the size

of the GISO package, as well as the size of the preamble phase, in number of cycles. This

protocol is introduced in Section 2.2.2. pllF ilterSEL is used to program the adjustable

Loop-Filter parameters, including the Charge-Pump current, the Loop-Filter resistance

and capacitance, as well as enabling external filter components.

A 16-bit SPI protocol is developed for programming and reading the status of the IC.


Table 3.1: Memory Bank registers.Address Data (12 Bits)

Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

phaseSEL 0 0 0 0 Coarse Phase Shift Counter Fine Phase Shift MUX

fswSEL 0 0 0 1 No. of Cycles for Startup Switching Frequency Counter

preambleSEL 0 0 1 0 No. of Cycles per GISO Pckg No. of Cycles Preamble

pllFilterSEL 0 0 1 1 ICP extFiltEn Filter Res Filter Cap

readSPI 1 1 1 1 4-bit Register Address

The IC serves as a Slave device communicating with an external Master device responsible

for programming the IC. Once the IC’s respective chip select signal goes low, it can accept

16 bits of data serially shifted into an internal register on each rising edge of the SPI clock

provided by the Master device. Up to 16, 12-bit, Memory Banks can used internally to

program switches in order to configure different IC parameters. Each Memory Bank has

a 4-bit address.

After 16 cycles of data transmission, the chip select signal goes high. On the rising

edge of chip select, the 12 LSB of the 16-bit shift register are written into a 12-bit Memory

Bank in a parallel manner, based on the 4-bit address retrieved from the 4 MSB of the

16-bit shift register. Similarly, the content in each Memory Bank can be sent back to

the Master after a ’write’ command is initiated. This process is show via the functional

Verilog simulation in Fig. 3.2.

The SPI protocol includes the ability to read back the content of any of the Memory

Bank registers on the IC. This is done by sending a [1111] command code with the 4-bit

register address as the LSB of the 16-bit SPI message. On the next SPI call, the specified

register contents are read back one bit at a time on the rising edge of the SPI clock, as

shown in Fig. 3.2.

3.3 Digital Core

The analog PLL is integrated with a synthesized digital core, which includes frequency

dividers, clock multiplexers, phase-shift counters, GISO signal parsing and other com-


1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 1

After rising edge of Chip Select, SPI

data is written to appropriate

Memory Bank register1st

SPI write command with new value

addressed to execSEL register SPI Read command for address [1000]

1 0 0 0 1 0 1 0 0 1 1 0 1 0 0 1

execSEL register content read out

serially

1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1

Figure 3.2: Verilog functional simulation showing three 16-bit SPI cycles to write newdata, send ”Read” command, and read contents of 12-bit execSEL Memory Bank register.

bined logic circuits. This mixed-signal interaction of the PLL is shown in Fig. 3.3. The

subsections that follow explore some of the digital core modules.

clk_shift

CLKSYNC

Vc

0010110 00110REG: phaseSEL

Digital Core (Coarse Phase Shift

+ 7-bit Divider)

PWM

32-to-1 MUX (Fine Phase Shift)

DL_out

FineCoarse

Digital Core

(7-bit Divider)

Digital Core (Reference Clock

Distribution + GISO

Packet Parsing)CLKREF

GISO Clock

(DIS Mode)

CMP Clock

(PTS Mode)

1xxxxx 00110REG: fswSEL

CLKSYNC Divider1

Analog PLL (Phase Detector +

Charge Pump + Loop

Filter)

VcMode

Figure 3.3: The Digital Core provides configuration bits for different functions of theanalog PLL.


3.3.1 Input Reference Clock Distribution

Referring to Fig. 3.3, the incoming reference clock, CLKREF , into the PLL can range in

frequencies depending on what mode the chip is running in. In PTS mode, the incoming

frequency is equal to the switching frequency of the converter, which is targeted to be

between 250 kHz and 1 MHz to allow for miniaturization of the converter filter elements.

In contrast, in DIS mode, we expect high speed communication with frequencies up to

100 MHz. Given that the Delay-Line frequency is to have a nominal frequency of 100

MHz, the PLL must have a conditional counter to divide the PLL’s output clock to lock

to the wide range of input reference frequencies. A 7-bit counter, programmed through

fswSEL[6:0], can enable the PLL to adapt to the reference clock, depending on what

mode the chip is operating in.

3.3.2 Reference Clock in DIS Mode

Unlike the reference clock in PTS mode that is constantly switching at a uniform fre-

quency based on gating over the isolation boundary, the reference clock in DIS mode

comes in unsynchronized packets of preamble and data, as is described in Section 2.2.2.

The Digital Core handles this by using the frequency divided output of the Delay-Line,

CLKSY NC , which is divided to match the frequency of the GISO signal, as a clock

source to drive combinational logic circuits. The expected GISO Preamble length and

GISO Packet length can be programmed into the preambleSEL Memory Bank register,

as numbers of cycles with periods equal to that corresponding to the GISO/CLKSY NC

frequency.

While in the preamble phase, the Digital Core counts on the rising edge of the GISO

signal until the counter reaches the number of cycles programmed for the preamplelength.

Subsequent to the preamble phase, the GISO signal starts sending data requiring the

Digital Core to put the PLL on hold by opening both switches of the Charge-Pump.

Once on hold, no current is fed into the Loop-Filter capacitors for VC to remain at a


constant voltage. In practice, small deviations result from current leakage out of the

Loop-Filter capacitors, causing a drift on VC .

The Digital Core is designed to determine when the data phase of the GISO signal

is complete so that it can wait for the next GISO packet. This is done by switching the

source clock of the combinational logic block to CLKSY NC , which will be the same fre-

quency and phase as the GISO preamble once the PLL is locked. The counter increments

on the rising edge of CLKSY NC until it matches the number of cycles corresponding to

the GISO packet length.

There is an asynchronous pause before the next GISO packet arrives, and the PLL

must remain on hold during this period. The source clock is then switched back to the

GISO clock. Once another GISO packet is sent, starting with the preamble phase, the

PLL will continue to run again to lock the PLL clock to the GISO clock in case there is

any drift on the VC bias signal. This process is shown in Fig. 3.4.

Preamble Data Asynchronous Pause

PLL active during preamble

~ ~

PLL locked during data and pause phases until

next GISO packet

Figure 3.4: Functional simulation of the Digital Core parsing a GISO packet.

3.3.3 Fine Phase Shift Tuning

As is introduced in Section 1.1.2, the power flow of the DAB is a function of the phase-

shift between the gating signals of the isolated sides. Therefore, the chip not only needs

to synchronize across the isolation boundary, but it also needs to add a programmable

phase-shift to the generated PWM signal that is intended for the power-stage on its

respective side. This allows the power flow of the DAB to be programmed through the

SPI interface of the chip by the relationship shown in (1.1.2).


The ring oscillator design of the Delay-Line allows each of the 31 Delay Element taps

to be accessed. As shown in Fig. 3.3, a 32-to-1 multiplexer is designed to control the fine

phase-shift tuning of the PWM output using a 5-bit bus from the phaseSEL memory

bank register. One of 32 taps of the nominally 100 MHz Delay-Line is chosen to be sent to

the Digital Core where the PWM signal is generated by dividing the finely phase-shifted

signal from the Delay-Line, and adding coarse phase-shifting as desired, as is described in

the next subsection. A simulation of the fine phase-shift tuning using the 32-to-1 MUX

is presented in Fig. 3.5. The Delay-Line output is shown for all 32 delay options. The 32

Delay Element tabs allows fine tuning with T/32=312.5 ps increments, where T is the

Delay-Line period (nominally 10 ns).

3.3.4 PWM Generation and Coarse Phase Shift Tuning

The main purpose of the on-chip PLL is to synthesize a synchronized clock based on

gating signals from the opposite side of the isolation boundary and generate a PWM for

switching on its respective side. The PWM is generated from the finely phase-shifted

output of the Delay-Line, clk shift, and is realized in the Digital Core, where clk shift

is used as the clock source in a combinational logic circuit. A 7-bit counter, programmed

via phaseSEL[11:5], is used not only to divide the 100 MHz Delay-Line frequency to

the desired PWM frequency (ranging from 250 kHz to 1 MHz), but also to add a coarse

phase-shift to the PWM with respect to the external reference clock by adding step delays

equivalent to a single clk shift nominal period of 10 ns.

The combination of the course and fine phase-shifting scheme allows the PWM to be

shifted at 0.3125 ns and 10 ns increments, respectively, via the values in the phaseSEL

Memory Bank register, as shown in Fig. 3.3.


1E-08 1.5E-08 2E-08 2.5E-08 3E-08

Time [s]

phaseSEL[4:0]

[00000]

[11111]

5-bit Resolution

for Full 360° ShiftT/32

Figure 3.5: Simulated waveform of Delay-Line output through 32-to-1 MUX for all valuesof 5-bit control bus.

3.4 Phase-Locked-Loop Design and Considerations

The following section summarizes the design considerations taken when implementing

the PLL. The decisions made to meet design specifications dictated by the application

of the chip are presented and justified.

3.4.1 Delay-Line and Delay Elements

The PLL, which contains a Delay-Line comprised of 31 individual Delay Elements whose

delays are controlled by a single Bias Generator (See Fig. 2.6), is required by design to


lock to external clock frequencies between 250 kHz to 100 MHz. Through integration

with the synthesized 7-bit frequency divider in the PLL, which can divide the Delay-Line

output clock by up to 127 times, the Delay-Line itself can produce a smaller range of

frequencies based on a 0 to 1.8 V bias range. The Delay-Line is intended to have a

nominal frequency of 100 MHz, with a +/- 20% margin, or a range of 80 to 120 MHz as

the bias voltage is ramped up to 1.8 V. The Delay Element transistors were sized through

parametric simulations to realize this range of operation. The simulation results that are

presented in Fig. 3.6 show the output oscillation of the Delay-Line as Bias Voltage, VC ,

is ramped from 0 V to 1.8 V.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0E+00 1E-07 2E-07 3E-07 4E-07 5E-07

Vo

lta

ge

[V

]

Time [s]

Delay Line output Bias Voltage, Vc

143MHz 71MHz

Figure 3.6: Simulated waveform of Delay-Line output versus time as Bias Voltage, Vc,is swept to 1.8 V.

The relationship between the output frequency of the Delay-Line with respect to the

Bias Voltage, VC , is shown in Fig. 3.7. As shown in this plot, although the Delay-Line is

able to produce frequencies between 70 and 140 MHz, there exists a linear region between

VC=0.8 V and VC=1.2 V where the Delay-Line frequency achieves the desired range of

80 to 120 MHz at a rate of 105 MHz/V with respect to the Bias Voltage.


60

70

80

90

100

110

120

130

140

150

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Del

ay L

ine

Freq

uen

cy [M

Hz]

Bias Voltage, Vc [V]

Δ=105MHz/V

Figure 3.7: Delay-Line output versus Bias Voltage, VC . A slope of 105 MHz/V is achievedwithin the desired range of 80-120 MHz.

3.4.2 Programmable Current Bank and Charge-Pump

As presented in Chapter 2, the Charge-Pump block of the PLL is used to adjust the

bias voltage, VC , to lock the internal clock, CLKSY NC to an external reference clock,

CLKREF . The simplified circuit for the charge pump is shown in Fig. 2.8. A more detailed

schematic is shown in Fig. 3.8, including the current bank that provides mirrored current

to all blocks on the chip including a programmable current source for the Charge-Pump.

The Charge-Pump current source can be programmed to have four different values: 5

µA, 15 µA, 30 µA, 40 µA. The Charge-Pump current is a variable in the transfer function

of the PLL, and the ability to program it allows the PLL to be tuned in order to lock

to a wide range of frequencies as is discussed in Section 3.4.3. The pllHOLD signal

disables any current from charging into or discharging out of the Loop-Filter, keeping


VDD

UP

Vc

Loop

Filter

Down

pllHOLD

pllHOLD

VDDVDD VDD VDDVDDVDDVDD VDD

ICP

xI

Current to rest of IC

M=1 M=x M=y M=z

yI zII=50 μA

ICPICP

ICP

M=0.5 M=0.2 M=0.1

25 μA 10 μA 5 μA

Current Bank

pllFilter[11] pllFilter[10]

RBIAS

Figure 3.8: Charge-Pump circuit and Current Bank which provides chip with pro-grammable current sources.

the bias voltage, VC , constant. This puts the PLL on hold, and if by this time CLKSY NC

is locked to CLKREF then the PLL remains locked during hold time. This is observed

experimentally in Section 4.2.4.

3.4.3 Programmable Loop-Filter

To achieve a wide frequency range PLL that can operate from 250 kHz to 100 MHz using

on-chip compensation, the Loop-Filter needs to be programmable to allow for fine-tuning

when locking to an external clock. This wide range of accepted external frequencies,

requires a wide range of resistor and capacitor values available on the chip.

The impendence of the Loop-Filter, shown in Fig. 2.8, is given by:

Z(s) =s · C2 ·R1 + 1

s2 · C1 · C2 ·R1 + s · (C1 + C2). (3.1)


Therefore, the 2nd order PLL Open Loop Gain is obtained:

H(jω) =IpKo

2πjω2N· (1 + jωRC1)

(C1 + C2)(1 + jωR C1C2

C1+C2). (3.2)

In (3.2), Ip is the phase-detector/charge-pump current. As mentioned in Section 3.4.2,

the charge pump current is adjustable with options for 5, 15, 30, and 40 µA available on-

chip, making it one of the tuning parameters of the PLL in addition to the Loop-Filter

resistance and capacitance. Ko is the VCO tuning voltage constant, or the frequency

versus voltage tuning ratio. In Section 3.4.1, the simulation for the Delay-Line is pre-

sented, and the VCO tuning voltage constant can be extrapolated from the linear region

of the Frequency versus Bias Voltage plot (see Fig. 3.7) to be approximately 105 MHz/V.

Finally, N is the main divider ratio, or the clock divider ratio implemented on the Delay-

Line output clock, DLout, to produce CLKSY NC . The ratio N , which is a 7-bit bus

that divides the Delay-Line clock by up to a factor of 127 can also be used to tune the

PLL, eliminating the need for excessively large capacitors. The bode plot of the transfer

function is shown in Fig. 3.9.

From (3.2) the unit gain bandwidth, the zero, and the pole can be found:

ωc =Ip2π· KoN

R(3.3)

ωz =1

RC1

(3.4)

ωp =1

R C1C2

C1+C2

. (3.5)


log|H(jω)|

ϕ|H(jω)|

Figure 3.9: Bode plot of the Loop-Filter’s open loop gain, showing the desired relativelocations of the unity gain bandwidth, the zero and the pole.

In (3.5), C1 and C2 are in series and the value is determined by the smaller capacitor.

To simplify and reduce the number of bits needed to program the Loop-Filter, the second

capacitor is set to C2 = C1/10. Considering the required PLL range of 250 kHz to 100

MHz, the Loop-Filter is designed as shown in Fig. 3.10. A summary of the programmable

range of the Loop-Filter parameters is shown in Table 3.2.

Table 3.2: Configurable PLL parameters.Filter Parameter Range Allocated Bits

C1 0-124 pF 5

C2 0-12.4 pF 5

R1 4-124 kΩ 4

Ip 5-40 µA 2

N 1-127 7

As shown in Fig. 3.9, to ensure a high phase margin, the zero, ωz, is designed to be

smaller than the unity gain bandwidth, ωc, and the pole, ωp, is designed to be larger.

As shown in Table 3.2, there are many configurable variables to tune in order for the


C1

Vc

4pF

64kΩ

32kΩ

16kΩ

8kΩ

4kΩ

8pF 16pF 32pF 64pF

0.4pF 0.8pF 1.6pF 3.2pF 6.4pF

[0] [1] [2] [3] [4]

[0] [1] [2] [3] [4]

[8]

[7]

[6]

[5]

R

C2

pllFilter[8:0]

Figure 3.10: The memory bank can be programmed to turn on and off switches toconfigure the desired Loop-Filter configuration.

PLL to lock to the intended range of frequencies. The PLL parameters are able to be

configured for stability (Phase Margin greater than 45 degrees) in the full range of 250

kHz to 100 MHz as shown in Fig. 3.11. The configuration used in the stability analysis

is summarized in Table 3.3.

The PLL was simulated in closed-loop with the stability analysis configurations to

confirm operation. The bias voltage, VC , settles within 0.2 µs as the PLL locks to a 100

MHz reference clock, as shown in Fig. 3.12.


Frequency (Hz)

Ph

ase

(d

eg)

Magn

itu

de (

dB

)

PM = 55°

250 kHz

(a)

Frequency (Hz)

Ph

ase

(d

eg)

Magn

itu

de (

dB

)

100 MHz

PM = 48°

(b)

Figure 3.11: Stabilization analysis for (a) 250 kHz and (b) 100 MHz locking frequency.


Table 3.3: Stability analysis configuration.Filter Parameter 250 kHz 100 MHz

C1 127 pF 4 pF

C2 12.7 pF 0.4 pF

R1 100 kΩ 12 kΩ

Ip 5 µA 40 µA

N 40 1

Phase Margin 55 degrees 48 degrees

Startup (PLL not enabled) Settling time = 0.2 us

VC

CLKSYNC

CLKREF

startup

Figure 3.12: Closed-loop PLL startup operation with 100 MHz reference clock.



To accommodate both synchronization schemes, the PLL is designed to be tunable to a

wide range of input reference frequencies with the ability to lock to reference signals rang-

ing from 250 kHz to 100 MHz through a configurable Loop-Filter design. This is realized

through an SPI-compatible Memory Bank, which provides programming bits to all con-

figurable blocks. The setup used to program and test the IC through an FPGA-enabled

control board, and a Graphical User Interface (GUI) used to change PLL parameters

and lock to external reference frequencies are presented in Chapter 4. Fast locking and

stable loop design is achieved over the desired frequency range.

Chapter 4

Implementation and Experimental

Results

4.1 Hardware Implementation

The IC is implemented in Magnachip’s 80 V, 0.18 µm BCD process, which allows for

such applications as battery charging and small-scale photovoltaic converters given the

80 V capability. As mentioned in Section 1.2, the work that is presented in this thesis is

part of a larger project to realize an on-chip power-stage suitable for isolated converters,

synchronized by a wide frequency range PLL. The technology node allows for compact

on-chip 100 mΩ switches to be realized in a full bridge setup. Two chips can be placed

on opposite sides of isolated boundaries to create a DAB converter, as shown in Fig. 2.1.

This section presents the physical setup and procedures used to test the implemented

chip.

4.1.1 Integrated Circuit Die and Packaging

The die measures 4.5×2.5 mm2, and the layout of the critical blocks is shown in Fig. 4.1.

The die is packaged in a 60 pin QFN package as shown in Fig. 4.2. The chip is divided

36

Chapter 4. Implementation and Experimental Results 37

spatially into two sections. The left side contains work that is out of the scope of this

thesis, which includes the power-stage, made apparent by the four power transistors

stacked vertically on the left, Power drivers, level shifters and a comparator. The PLL,

Digital Core and GISO blocks on the right side pertain to the work presented in this

thesis.

Synthesized

Digital Core

Filter

Cap

Delay Line +

Charge PumpFilter

Resistance

4.5 mm

2.5 mm

GISO RX/TX

Figure 4.1: Layout of the on-chip PLL with labeled blocks presented in thesis.


Figure 4.2: Chip micrograph of die packaged in a 60-pin QFN package.

4.1.2 PCB Implementation with Graphical User Interface

A dual-PCB system was developed to provide power and communicate with the chip, as

well as access to internal and external signals to aid in debugging and troubleshooting.

To facilitate the evaluation of multiple ICs without re-soldering the fine-pitched chip,

two PCBs were designed to interface to eachother, as shown in Fig. 4.3. The PCB

that contains the chip acts as a socket by mapping all the pins of the chip onto female

header pins. This PCB also allows for heat sinks for thermal management and contains


footprints for bypass capacitors along with anything that needs to be in close proximity

to the chip. The populated IC PCB is shown in Fig. 4.4(a).

NileDelta Provides link between GUI and Control

Board

Programs IC PCB through SPI interface

External Power Module

(Switches, drivers, deadtime,

etc.)

External Power Module

(Switches, drivers, deadtime,

etc.)

ISOLATION BOUNDARY

FPGA Board Provides external PWM signals to

power stage

Synthesizes external high speed

reference clock fed into PLL

Control PCB

Figure 4.3: Architecture of test setup including an FPGA board, a GUI link, and thetest board containing the chip.

The second PCB is the Control PCB, shown in Fig. 4.4(a). It contains two isolated

planes each with male header pins in the same pattern to allow the IC PCB to dock.

The Control PCB also contains numerous LDOs to provide the different power supplies

required by the IC PCB, as well as a communication protocol established through a

USB connected to a computer running a LabVIEW interface. The LabVIEW interface,

shown in Fig. 4.5, is able to write into the Memory Bank registers of the chip, via a 20

MHz SPI interface to effectively program the chip’s multiple functionalities. In addition,

the GUI provides easy access to specific registers to easily tune the Loop-Filter; adjust

the Charge-Pump current; multiplex the digital debug signals; and change modes of

operation.


(a)

FPGA Board

2x Isolated

IC Boards

GUI Link via

NileDelta

External DAB Power Stage

(b)

Figure 4.4: (a) IC PCB populated with the designed QFN chip and passive components.(b) Control PCB with two isolated planes each with a dock for IC PCBs for testing anddebugging inter-boundary communication.

4.2 Experimental Results

The dual-PCB platform allows the different functions of the IC, such as SPI communi-

cation, PLL locking, phase-shifting, and GISO communication across an isolated plane

to be tested. The following sections present the experimental results from such tests to


Figure 4.5: The GUI allows for easy access to IC Memory Bank registers on either sideof the isolated boundary.

confirm the functionality of the chip.

4.2.1 Communication Confirmation

The user interface allows Memory Bank SPI commands to be sent to the chip via the

Control PCB. The SPI communication is tested similarly to the simulation setup that is

shown in Fig. 3.2. In this test, a write command is initiated on a Memory Bank register,

and a read command is subsequently sent to read out of the same register to see if the

bits were updated appropriately. The oscilloscope results of this test is shown in Fig. 4.6.

The SPI interface can communicate at speeds as high as 25 MHz.

4.2.2 Locking to External Reference Clock

Once communication with the IC is established and confirmed, the chip can be pro-

grammed, and subsequently the internal PLL parameters can be tuned. The following

subsection presents the results from testing the PLL operation of the chip, more specifi-

cally locking to an external reference clock.


[1000101001101001]

1st SPI write command with new value addressed

to execSEL register

SPI Read command for address [1000]

[1000101001101001]

execSEL register content read out serially

[1111000000001001]

Figure 4.6: Experimental result of testing the IC’s SPI communication protocol. Datais written into a Memory Bank register, and data is read out to confirm proper datatransfer.

In this test, a controlled external clock signal from a function generator is sent to

the CLKREF signal of the chip. While the PLL is running, the internal parameters of

the chip are configured through the GUI until a lock is achieved between the external

reference clock, and the internal PLL clock. In this test a 1 MHz clock is sent to the chip

and the PLL is tuned to the values shown in Table 4.1. The locked PLL waveforms are

presented in Fig. 4.7.


Table 4.1: PLL settings for locking to 1 MHz.PLL Parameter Value Register Bits

C1 28 pF pllFiltSEL[4:0] = [00111]

C2 2.8 pF pllFiltSEL[4:0] = [00111]

R1 4 kΩ pllFiltSEL[8:5] = [0000]

ICP 5 µA pllFiltSEL[11:10] = [00]

Frequency Divider 1/92 fswSEL[6:0] = [1011100]


Vc

CLKREF

CLKSYNC

700 mV

920 mV

(a)

CLKREF

Vc

CLKSYNC

(b)

Figure 4.7: The PLL clock, CLKSY NC , locking to an external 1 MHz reference clock,CLKREF , with bias voltage, VC shown. (a) The startup process with the bias voltagegradually ramping up and stabilizing to lock CLKSY NC to the reference clock. (b) Azoomed in view of the waveforms at steady-state, where CLKSY NC is locked to CLKREF

with stable VC .


4.2.3 Phase Shift Experimentation

Section 3.3.3 and Section 3.3.4 present the IC’s ability to tune the phase difference be-

tween the input reference clock, and the PWM output from the PLL. Through SPI com-

munication, the 12-bit phaseSEL Memory Bank register is written into for the coarse

and fine tuning of the phase-shift. The phase-shift is then mapped to an analog voltage

between 0 V and 3.3 V by sending both the reference and phase-shifted clocks through

an XNOR gate to produce a 0 to 3.3 V square wave with a duty cycle proportional to

the phase difference between the two signals. An averaged voltage scaling with the duty

cycle is achieved by filtering the square wave using a low pass RC filter. The result is an

analog voltage from 0 to 3.3 V linearly mapped to the absolute phase difference (leading

or lagging neglected) of the two signals between 0 and 180 degrees, given by:

VOUT =φ

π× 3.3V. (4.1)

In (4.2.3) VOUT is the output voltage of the filter, and φ is the phase difference in

radians. The circuit that realizes this method of phase-shift measurement is shown in

Fig. 4.8.

While incrementing the 12-bit coarse and fine phase tuning one bit at a time every 500

ms, the LabVIEW-enabled GUI is able to interface with a digital multimeter via GPIB

communication to read the analog phase-shift voltage. The GUI stores the analog phase

voltage corresponding to each of the 4096 possible tuning options. This collected data is

then plotted to show the phase measured versus the 12-bit code programmed into the IC,

allowing for the performance of the phase-shift module to be evaluated. Fig. 4.9 shows

the experimental results of this test run on a 1 MHz reference clock made to produce a

phase-shifted 1 MHz PWM signal. Only a region of the plot is shown since outside of


CLK1

CLK2

To DMM

R

C

VOUT

VXNOR

CLK1

CLK2

VXNOR

VOUT

Figure 4.8: Circuit used to map the phase-shift between the reference and output signalof the PLL to a 0 to 3.3 V analog voltage.

this range the characteristic is non-linear due to a synthesis error. The limited region

is sufficient as the phase-shift is linear around 45 degrees which maximizes power flow

through the DAB based on (1.1.2). For a switching frequency of 1 MHz, a resolution of

0.1 degrees is achieved.

Figure 4.9: Plotted experimental result of tuning the 12-bit phaseSEL register andmeasuring the resultant phase difference.


4.2.4 GISO Transmission Across Isolation Boundary

The GISO protocol is a proprietary technology developed by SolantroSemiconductorsInc.

and was implemented in this IC to fulfill high speed communication across an isolated

boundary, which is crucial for the PLL’s operation in DIS mode. Two separate chips must

be able to communicate with each other across a high frequency transformer, where one

chip transfers the GISO packet (TX side) and the other receives it (RX side). Fig. 4.10

shows the GISO protocol being pushed to its limits between two ICs communicating at

150 MHz. The receiver side accepts the high frequency input clock, outputs a complemen-

tary, dual rail, low-swing signal to the transformer, where it passes the isolation boundary

and is then received by the RX side where the high frequency clock is regenerated.

The signal regenerated by the RX side is accessible to the input reference clock of the

PLL, CLKREF . The PLL is then able to lock to this signal and output a PWM signal

to sync to that of the TX side. This complete process is presented in Fig. 4.11 where the

PLL is shown locking to 50 MHz GISO packets from across an isolated boundary. The

pllHOLD signal, shown in Fig. 4.11(b), is shown to go high when the GISO leaves the

preamble phase of each packet, putting the PLL on hold, as explained in Section 3.4.2.

It also goes high on the rising and falling of the resultant PWM (not shown). This is to

ensure that the PLL is not affected by the transients caused when the power switches

are activated/deactivated.


Figure 4.10: GISO operation across two boundaries using two ICs transmitting dataacross a high speed transformer. The 150 MHz input clock to the TX side is shown,along with the low swing dual rail signal going to the transformer on the TX side. Theresultant regenerated clock is output from the RX side.


GISOin

Vc

Pre-Charge

startup

700 mV

920 mV

(a)

DataPreamble

pllHOLD

Vc

(b)

Figure 4.11: The PLL clock, CLKSY NC , locking to a high speed 50 MHz reference clockthrough the GISO protocol. (a) The startup process with the bias voltage graduallyramping up and stabilizing to lock CLKSY NC to the reference clock. (b) A zoomed inview of the waveforms at steady-state to show a single GISO packet and the pllHOLDpattern with stable VC .


4.2.5 Synchronized DAB Converter Waveforms

The chip was tested with a discrete DAB converter with the following parameters, LDAB

= 6.9 µH, V1 = 30 V, Vbus = 90 V, n = 3.5, fs = 500 kHz. The steady-state operations

in both DIS and PTS modes are shown in Fig. 4.12 and Fig. 4.13, respectively. The

PLL consumes 27 mW when constantly activated in these modes. The actual power

consumption in DIS mode can be much lower based on the frequency of communication.

ILDAB

Vc

Vx1

td td

CLKSYNC

Figure 4.12: Synchronized DAB converter waveforms in the PTS mode (ILDAB: 5A/div).


Vx2

GISOin

Vc

ILDAB

CLKSYNC

Figure 4.13: Synchronized DAB converter waveforms in DIS mode with continuous 50MHz GISOin input clock (ILDAB: 5A/div).


The experimental results of the IC’s numerous modules such as SPI communication, PLL

locking, PWM generation and phase-shifting are presented in this chapter. The results

show that a PLL with a Delay-Line frequency range of 80-140 MHz is realized with an

ability to lock to reference clock signals in the range of 250 kHz to 100 MHz. The PLL

locks in 300 µs in PTS mode, and in 105 µs in DIS mode. For both synchronization

schemes, the chip is able to synchronize the two sides of an isolated DAB converter to

transfer power in open-loop mode through phase-shift modulation. Due to a synthesis

error, the phase-shift has a limited linear region, which is sufficient to operate with a


DAB converter with a maximum power flow at a 45 degree phase-shift. The power

consumption of the PLL is not a primary consideration because it is intended to function

with a 50 W power-stage.

Chapter 5

Conclusions

5.1 Thesis Summary and Contributions

The objective of this work is to demonstrate a wide frequency range PLL implemented

in an 80 V 0.18 µm process for synchronization of gating signals of a low-power, high-

frequency Dual Active Bridge dc-dc converter. In Chapter 2, two synchronization meth-

ods are presented that are implemented in the IC design: Power Transforming Sensing

and Digital Isolator Sensing.

Chapter 3 is devoted to simulation and design considerations of the IC design to realize

the proposed PLL and synchronization schemes. The implementation of programmable

chip parameters to enable a wide-range frequency operation to accommodate the range

of frequencies between the two synchronization schemes are presented.

The resultant chip and testing architecture is presented in Chapter 4. This chapter

covers the experimental results gained from testing the chip, confirming the simulations

and design expectations that the previous chapter presents. The PLL and synchro-

nization scheme are applied to a DAB converter where power is transferred between an

isolated boundary.

A qualitative comparison of the PTS and DIS schemes is provided in Table 5.1. In

53

Chapter 5. Conclusions 54

Table 5.1: Comparison of Driving Schemes in Isolated Converters.Scheme Conventional PTS DIS

Communication Capability No Yes Yes

(unidirectional)

Continuous Communication No Yes Optional

(required to avoid PLL drift)

PLL Operation None Low frequency High frequency

Absolute Phase Reference N/A Available through comp Communicated

Number of Digital Isolators 4 0 1

Required for Driving (DAB)

Power Consumption High Lowest Low

Power Converter Topology No limitation Limited by No limit

transformer leakage inductance

High Voltage Comparator None Yes No

general, both of these schemes are superior to the conventional approach of using one

digital isolator per transistor in addition to the data channel. The results reported in this

work will contribute to lower cost, highly reliable isolated dc-dc converters for emerging

bi-directional power applications. The contributions to this thesis include:

A programmable PLL with current-starved inverter ring oscillator designed to pro-

duce frequencies between 70 to 140 MHz. Configurable on-chip Loop-Filter resis-

tance and capacitance allow the PLL to lock to a wide range of reference frequencies

from 250 kHz to 100 MHz.

GISO communication across isolated boundary through HS transformer at frequen-

cies up to 150 MHz to synchronize gating signals and transfer data.

First demonstration of PTS and DIS synchronization schemes. Experimental vali-

dation of utilizing a high voltage comparator to synchronize to transformer switch-

ing voltage in the range of 250 kHz to 1 MHz from the opposite side of the boundary.

High speed 100 MHz communication through an HS transformer via GISO interface

with support for data transfer between isolated sides.

Demonstration of IC versatility to act as both master or slave in a dual-chip setup to

synchronize and generate PWM between both sides of an isolated DAB converter.

Chapter 5. Conclusions 55

Adjustable phase-shift with 0.1 degree resolution between gating signals of isolated

sides added to control power flow in both PTS and DIS modes.

5.2 Future Work

The following directions are suggested for further exploration:

Operation of DAB in closed-loop mode with automatic phase-shift control and

PLL parameter adjustment to optimize power transfer. Through a control system

realized on an external FPGA, the power transfer through the DAB can be mea-

sured, and the synchronized, phase-shifted PWM from the chip can be adjusted to

maximize power.

Demonstration of full-chip integrated power converter with internal power-stage.

As previously mentioned the work presented in this thesis is part of a larger project

to realize a fully integrated power converter that is able to synchronize across an

isolated boundary. The chip consists of the PLL and synchronization scheme pre-

sented in this thesis, as well as an on-chip power-stage with a full bridge consisting

of 80 V, 100 mΩ power switches, drivers, and dead-time control. The full chip is

able to convert power without the need of a discrete power-stage.

Refinement of programmable phase-shift to provide a truly linear 12-bit resolution

to optimize power flow, especially in closed-loop operation.

The designed PLL is able to lock to the preamble phase of the GISO packet, while

staying on hold during the data phase and unsynchronized rest periods. Utilization

of the GISO protocol’s high speed data transfer capabilities to communicate across

the isolated boundary can be further explored.

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