An FPGA Implementation of an OFDM – Based …newton.ee.auth.gr/WSPLC08/Abstracts/DN_3.pdf · An...

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An FPGA Implementation An FPGA Implementation of an OFDM of an OFDM Based Based Communication System for Communication System for PLC Channels PLC Channels Stavros I. Tsakiris Anastasios D. Salis Nikolaos K. Uzunoglu National Technical University of Athens National Technical University of Athens Microwave and Fiber Optics Laboratory Microwave and Fiber Optics Laboratory This work was performed within the framework of the project PENED 2003, funded by the European Union – European Social Fund and from the GSRT of the Hellenic Ministry of Development. PLC Workshop 2008

Transcript of An FPGA Implementation of an OFDM – Based …newton.ee.auth.gr/WSPLC08/Abstracts/DN_3.pdf · An...

Page 1: An FPGA Implementation of an OFDM – Based …newton.ee.auth.gr/WSPLC08/Abstracts/DN_3.pdf · An FPGA Implementation of an OFDM – Based Communication System for PLC Channels Stavros

An FPGA Implementation An FPGA Implementation of an OFDM of an OFDM –– Based Based

Communication System for Communication System for PLC ChannelsPLC Channels

Stavros I. Tsakiris Anastasios D. Salis

Nikolaos K. Uzunoglu

National Technical University of AthensNational Technical University of AthensMicrowave and Fiber Optics LaboratoryMicrowave and Fiber Optics Laboratory

This work was performed within the framework of the project PENED 2003, funded by the European Union – European Social Fund and from the GSRT of the Hellenic Ministry of Development.

PLC Workshop 2008

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The PLC ChannelThe PLC ChannelHigh frequency signal propagation in power line High frequency signal propagation in power line communicationcommunication channels is mainly influenced channels is mainly influenced by:by:

attenuation caused by cable losses, increasing with attenuation caused by cable losses, increasing with frequency and lengthfrequency and lengthmultipath propagation arising from branching and multipath propagation arising from branching and unmatched line endsunmatched line endsnarrowband interference from existing broadcasting narrowband interference from existing broadcasting servicesservices

For such an environment, For such an environment, Orthogonal Frequency Orthogonal Frequency Division Multiplexing (OFDM)Division Multiplexing (OFDM) is considered is considered the the most favourable modulation schememost favourable modulation scheme ..

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OFDM Basics IOFDM Basics I

In contrast to the single carrier modulation In contrast to the single carrier modulation bandwidth bandwidth BBscmscm, the OFDM spectrum , the OFDM spectrum BBmcmmcm is is segmented into a large number segmented into a large number NNscsc of closely of closely ––spaced orthogonal subcarriers, each occupying spaced orthogonal subcarriers, each occupying a much narrower bandwidth a much narrower bandwidth BBkk ..

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OFDM Basics IIOFDM Basics II

The input data stream is divided into The input data stream is divided into several symbol streams, each of which several symbol streams, each of which has a much lower symbol rate (in other has a much lower symbol rate (in other words a much higher symbol duration words a much higher symbol duration TTss).).Each substream modulates the Each substream modulates the corresponding subcarrier following a corresponding subcarrier following a conventional modulation scheme, such as conventional modulation scheme, such as QAM or PSK.QAM or PSK.

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OFDM and Discrete Fourier OFDM and Discrete Fourier Transform (DFT)Transform (DFT)

A sampled version of the transmitted OFDM A sampled version of the transmitted OFDM signal for a time interval as long as the symbol signal for a time interval as long as the symbol duration duration TTss can be produced by applying the can be produced by applying the NNscsc

–– pointpoint inverse DFT matrix to the symbol vector.inverse DFT matrix to the symbol vector.The symbol vector expresses the value of the The symbol vector expresses the value of the information symbol at every subcarrier for a information symbol at every subcarrier for a specific symbol duration.specific symbol duration.The transmitted symbol vector can be recovered The transmitted symbol vector can be recovered at the receiver by means of the forward DFT.at the receiver by means of the forward DFT.

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OFDM and Delay Spread IOFDM and Delay Spread I

A multipath channel (such as the PLC channel) A multipath channel (such as the PLC channel) can be characterized by an impulse response can be characterized by an impulse response with delay spread in the time domain, as with delay spread in the time domain, as depicted in the figure above.depicted in the figure above.

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OFDM and Delay Spread IIOFDM and Delay Spread IIWithout a guard interval between successive OFDM Without a guard interval between successive OFDM symbols, intersymbol interference (ISI) from the previous symbols, intersymbol interference (ISI) from the previous symbol gives a distortion to the current symbol.symbol gives a distortion to the current symbol.If we employ a guard interval, where no signal If we employ a guard interval, where no signal transmission takes place, with length larger than the time transmission takes place, with length larger than the time delay between the first and the last path, we can delay between the first and the last path, we can perfectly eliminate ISI, but a sudden change of waveform perfectly eliminate ISI, but a sudden change of waveform results in interresults in inter-- subcarrier interference.subcarrier interference.The solution is a guard interval insertion technique with The solution is a guard interval insertion technique with cyclic prefix extension, i.e. the last samples of an OFDM cyclic prefix extension, i.e. the last samples of an OFDM symbol are repeated at the beginning of the symbol symbol are repeated at the beginning of the symbol during the guard interval, instead of transmitting no during the guard interval, instead of transmitting no signal.signal.

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Advantages of OFDM in PLCAdvantages of OFDM in PLCIn conclusion:In conclusion:

The OFDM spectrum is divided into numerous narrow The OFDM spectrum is divided into numerous narrow subchannels:subchannels:

This provides robustness against interference.This provides robustness against interference.Attenuation and group delay are constant within each channel.Attenuation and group delay are constant within each channel.

Thus equalization is easy by adopting one Thus equalization is easy by adopting one –– tap tap –– techniques.techniques.

The use of a guard interval with cyclic prefix insertion The use of a guard interval with cyclic prefix insertion can combat multipath propagation effect.can combat multipath propagation effect.Frequency ranges excluded from use for PLC due to Frequency ranges excluded from use for PLC due to regulation or bad quality can be faded out by zeroing the regulation or bad quality can be faded out by zeroing the corresponding carriers.corresponding carriers.

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OFDM and Digital ImplementationOFDM and Digital Implementation

Classical OFDM is an analog modulation scheme Classical OFDM is an analog modulation scheme employingemploying analog subcarrier oscillators and filters.analog subcarrier oscillators and filters.The use of IDFT / DFT eliminates the need for analog The use of IDFT / DFT eliminates the need for analog oscillators and filters at the transceivers making possible oscillators and filters at the transceivers making possible an all digital implementation.an all digital implementation.Digital OFDM systems have traditionally been developed Digital OFDM systems have traditionally been developed using microprocessors enhanced with functions for realusing microprocessors enhanced with functions for real--time digital signal processing, called DSPs.time digital signal processing, called DSPs.In this work we propose an OFDM In this work we propose an OFDM –– based based communication system in the 1 communication system in the 1 –– 30 MHz frequency 30 MHz frequency zone.zone. The transmitter and the receiver are realized The transmitter and the receiver are realized digitally on Field Programmable Gate Array (FPGA) digitally on Field Programmable Gate Array (FPGA) chips.chips.

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FPGA BasicsFPGA BasicsAn FPGA is an array of programmable logic cells An FPGA is an array of programmable logic cells interconnected by a matrix of wires and interconnected by a matrix of wires and programmable switches.programmable switches.Each cell performs a simple logic function Each cell performs a simple logic function defined by a user’s design.defined by a user’s design.In FPGAs, an integrated synthesis and mapping In FPGAs, an integrated synthesis and mapping tool transforms the user’s design (either tool transforms the user’s design (either graphical or codegraphical or code--style) to a hardware design, style) to a hardware design, whereas a microprocessor’s program whereas a microprocessor’s program corresponds to machine language (software) corresponds to machine language (software) instructions.instructions.

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FPGAs vs. microprocessorsFPGAs vs. microprocessorsFPGAs, like generic FPGAs, like generic –– purpose microprocessors, provide purpose microprocessors, provide a low cost solution.a low cost solution.A processor’s performance, measured by the number of A processor’s performance, measured by the number of possible operations per cycle, falls seriously short, possible operations per cycle, falls seriously short, compared to an FPGA, as the sampling rate and the compared to an FPGA, as the sampling rate and the respective clock rate increases.respective clock rate increases.In contrast to a microprocessor, where the tasks are In contrast to a microprocessor, where the tasks are executed sequentially,executed sequentially, an FPGA is inherently a parallel an FPGA is inherently a parallel implementation targeted deviceimplementation targeted device thus offering much thus offering much higher digital signal processing rates.higher digital signal processing rates.Traditional FPGAs are usually combined with related Traditional FPGAs are usually combined with related peripherals to form a complete development kit.peripherals to form a complete development kit.

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Development Kit Overview IDevelopment Kit Overview I

The figure shows the XtremeDSP Development Kit of the Nallatech The figure shows the XtremeDSP Development Kit of the Nallatech Corporation where our system will be implemented.Corporation where our system will be implemented.Transmitter and receiver will each be constructed on a differentTransmitter and receiver will each be constructed on a differentdevelopment kit.development kit.

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Development Kit Overview IIDevelopment Kit Overview IIThe master clock of the kit is a 105 MHz oscillator.The master clock of the kit is a 105 MHz oscillator.The interface with the communication medium consists of two inpuThe interface with the communication medium consists of two input and two t and two output channels, all terminated with a 50output channels, all terminated with a 50Ω Ω load at MCX type connectors.load at MCX type connectors.At each input channel an ADC converts the analog input to digitaAt each input channel an ADC converts the analog input to digital, 14 l, 14 –– bit bit wide signal. wide signal.

The digital signal ends up at the user FPGA where the signal proThe digital signal ends up at the user FPGA where the signal processing that the cessing that the user desires takes place. user desires takes place. The ADC can accept a maximum input of 2V p The ADC can accept a maximum input of 2V p –– p and a maximum sample rate p and a maximum sample rate of 105 MSPs.of 105 MSPs.

At each output channel a DAC converts digital 14 At each output channel a DAC converts digital 14 –– bit wide signal to analog bit wide signal to analog output. output.

The digital signal comes from the user FPGA and is the result ofThe digital signal comes from the user FPGA and is the result of the desired the desired signal processing. signal processing. The DAC has a maximum update rate of 160 MSPs and a maximum outpThe DAC has a maximum update rate of 160 MSPs and a maximum output of 2V ut of 2V p p –– p.p.

The sampling period at the ADCs / DACs is determined by clock siThe sampling period at the ADCs / DACs is determined by clock signals gnals arriving from the timing FPGA.arriving from the timing FPGA.

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Development Kit Overview IIIDevelopment Kit Overview IIIThe user FPGA is a Virtex IV device of the Xilinx The user FPGA is a Virtex IV device of the Xilinx Corporation. Corporation.

The user FPGA implements the circuit designed by The user FPGA implements the circuit designed by the user.the user.Inputs of the user FPGA can be the input channels Inputs of the user FPGA can be the input channels and clock signal from the timing FPGA.and clock signal from the timing FPGA.Outputs of the FPGA can be the output channels of Outputs of the FPGA can be the output channels of the kit. the kit.

The timing FPGA is a Xilinx Virtex II device.The timing FPGA is a Xilinx Virtex II device.The timing FPGA can accept an appropriate circuit The timing FPGA can accept an appropriate circuit that uses the kit’s master clock to generate clock that uses the kit’s master clock to generate clock signals for the user FPGA, ADCs, DACs, etc.signals for the user FPGA, ADCs, DACs, etc.

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Transmitter Design ITransmitter Design I

The figure depicts the architecture of the circuit The figure depicts the architecture of the circuit that will be implemented by the user FPGA of that will be implemented by the user FPGA of the transmitter’s development kit.the transmitter’s development kit.

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Transmitter Design IITransmitter Design IIThe monitor module adjusts the input data rateThe monitor module adjusts the input data rate and writes input and writes input samples from the ADC to the input RAM.samples from the ADC to the input RAM.The monitor module also supervises the symbol mapper module and The monitor module also supervises the symbol mapper module and sends data samples from the input RAM to it when the symbol sends data samples from the input RAM to it when the symbol mapper module is ready to process.mapper module is ready to process.Finally, the monitor module controls the operation of the transmFinally, the monitor module controls the operation of the transmitter itter by suspending the generation of the OFDM signal or resuming whenby suspending the generation of the OFDM signal or resuming whendesired.desired.

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Transmitter Design IIITransmitter Design IIIThe symbol mapper module maps the input data to theThe symbol mapper module maps the input data to the symbol vector.symbol vector.

The module uses binary phase shift keying (BPSK) to modulate eveThe module uses binary phase shift keying (BPSK) to modulate every subcarrier.ry subcarrier.The IFFT module produces a sampled version of the transmitted OFThe IFFT module produces a sampled version of the transmitted OFDM DM signal.signal.The CP insertion module adds a cyclic prefix to every produced sThe CP insertion module adds a cyclic prefix to every produced symbol of ymbol of the OFDM signal in order to combat the multipath propagation effthe OFDM signal in order to combat the multipath propagation effect.ect.The BPF module applies digital filtering to the produced signal The BPF module applies digital filtering to the produced signal to suppress to suppress spectral components beyond the desired signal bandwidth.spectral components beyond the desired signal bandwidth.

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Transmitter Design IVTransmitter Design IVThe transmission of the OFDM signal is not a continuous process The transmission of the OFDM signal is not a continuous process as as several OFDM symbols are grouped and sent together in an OFDM several OFDM symbols are grouped and sent together in an OFDM frame.frame.In each frame of M OFDM symbols, the first two symbols are In each frame of M OFDM symbols, the first two symbols are intended for frame synchronization and channel estimation purposintended for frame synchronization and channel estimation purposes es at the receiver, while the rest are payload symbols.at the receiver, while the rest are payload symbols.

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Receiver Design IReceiver Design I

This figure shows the architecture of the circuit This figure shows the architecture of the circuit that will be implemented by the user FPGA of that will be implemented by the user FPGA of the receiver development kit.the receiver development kit.

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Receiver Design IIReceiver Design IIThe analog transmitted OFDM The analog transmitted OFDM signal is received through the first signal is received through the first analog channel.analog channel.The ADC converts the analog The ADC converts the analog signal to a 14 signal to a 14 –– bit wide digital bit wide digital signal.signal.The frame synchronization module The frame synchronization module seeks among the input samples seeks among the input samples for the beginning of a new frame.for the beginning of a new frame.

If a new frame has been If a new frame has been recognized, the first symbol is recognized, the first symbol is removed and the remaining removed and the remaining MM--11symbols of the frame are written symbols of the frame are written to the inputto the input RAM.RAM.

The CP removal module removes The CP removal module removes the cyclic prefix from every OFDM the cyclic prefix from every OFDM symbol.symbol.

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Receiver Design IIIReceiver Design IIIThe FFT module retrieves the The FFT module retrieves the transmitted symbol vector by transmitted symbol vector by applying the forward applying the forward NNscsc ––pointpoint fast Fourier transform to fast Fourier transform to the received signal.the received signal.The decision module uses the The decision module uses the channel estimation symbol of channel estimation symbol of the frame to extract an the frame to extract an approximation of the approximation of the transmitter’s input data stream transmitter’s input data stream out of the symbol vector for out of the symbol vector for every OFDM symbol.every OFDM symbol.

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Experimental Setup for a coaxial Experimental Setup for a coaxial cable mediumcable medium

The figure shows the experimental setup The figure shows the experimental setup employed for a coaxial cable medium.employed for a coaxial cable medium.The transmitter and the receiver circuits are The transmitter and the receiver circuits are implemented on two identical XtremeDSP implemented on two identical XtremeDSP development kits.development kits.A signal generator is connected to the first A signal generator is connected to the first input channel of the transmitter and input channel of the transmitter and constitutes the source of input data.constitutes the source of input data.The first output channel of the transmitter is The first output channel of the transmitter is connected through a coaxial cable to a T connected through a coaxial cable to a T splitter.splitter.Half of the signal’s energy travels through a Half of the signal’s energy travels through a coaxial cable to the first channel of an coaxial cable to the first channel of an oscilloscope.oscilloscope.The other half energy travels through a The other half energy travels through a coaxial cable to the input channel of the coaxial cable to the input channel of the receiver.receiver.The first output channel of the receiver is The first output channel of the receiver is connected through a coaxial cable with the connected through a coaxial cable with the second channel of the oscilloscope.second channel of the oscilloscope.

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System Implementation System Implementation CharacteristicsCharacteristics

The communication system faces the following characteristics:The communication system faces the following characteristics:The master clock of our transmitter and receiver circuit has a The master clock of our transmitter and receiver circuit has a frequency of 105 MHz.frequency of 105 MHz.The maximum data rate of the system is approximately 3Mbps.The maximum data rate of the system is approximately 3Mbps.Every frame consists of 4 OFDM symbolsEvery frame consists of 4 OFDM symbols where the two last where the two last symbols carry information data.symbols carry information data.The available bandwidth is divided to 16 subcarriers.The available bandwidth is divided to 16 subcarriers.The guard interval length is selected to the 1/5 of the symbol The guard interval length is selected to the 1/5 of the symbol duration duration TTss..The duration of every sample is 38 ns.The duration of every sample is 38 ns.The actual bandwidth of the transmitted signal will be in the rThe actual bandwidth of the transmitted signal will be in the region egion

4.1MHz 4.1MHz –– 22.14MHz.22.14MHz.The length of every frame is 3040 ns and a new frame is producedThe length of every frame is 3040 ns and a new frame is producedevery 3952 ns.every 3952 ns.

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Results Coaxial IResults Coaxial IThe figures present the The figures present the signal at the input and signal at the input and output of the receiver for output of the receiver for a generator’s signal of a generator’s signal of frequency 100 kHz and frequency 100 kHz and amplitude 500mV in long amplitude 500mV in long –– range and short range and short –– range range view respectively. view respectively. Channel 1 of the Channel 1 of the oscilloscope depicts the oscilloscope depicts the received OFDM signal, received OFDM signal, whereas channel 2 shows whereas channel 2 shows the retrieved sequence.the retrieved sequence.

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Results Coaxial IIResults Coaxial II

This figure shows the This figure shows the signal at the receiver signal at the receiver for a generator’s for a generator’s signal of frequency signal of frequency 1MHz and amplitude 1MHz and amplitude 500mV in short 500mV in short ––range view.range view.

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Results Coaxial IIIResults Coaxial IIIThese figures depict the These figures depict the signal at the receiver for a signal at the receiver for a generator’s signal of generator’s signal of frequency 100kHz, frequency 100kHz, amplitude 500mV and amplitude 500mV and duty cycle 50%, 70%, duty cycle 50%, 70%, 80% respectively.80% respectively.

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Coupling Unit for PLC mediumCoupling Unit for PLC mediumIn order to test the system over In order to test the system over the PLC channel, an appropriate the PLC channel, an appropriate coupling unit should be used coupling unit should be used between the development kit and between the development kit and the power line consisting of:the power line consisting of:

A wideband RF transformer (with A wideband RF transformer (with a 1 dB bandwidth in the region a 1 dB bandwidth in the region 7kHz 7kHz -- 80MHz, 400V interwinding 80MHz, 400V interwinding isolation) that either couples the isolation) that either couples the OFDM signal to the power line or OFDM signal to the power line or decouples the RF signal from the decouples the RF signal from the power line, keeping the power line power line, keeping the power line and the communication circuits and the communication circuits isolated.isolated.A capacitor that operates as a A capacitor that operates as a high pass filter that cuts off noise high pass filter that cuts off noise below 1MHz.below 1MHz.

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Experimental Setup for the PLC Experimental Setup for the PLC channelchannel

The figure depicts the experimental The figure depicts the experimental setup employed in order to test the setup employed in order to test the communication system over a PLC communication system over a PLC channel.channel.A signal generator is connected to the A signal generator is connected to the transmitter development kit and transmitter development kit and constitutes the source of input data.constitutes the source of input data.The transmitter development kit is The transmitter development kit is connected through a coaxial cable to connected through a coaxial cable to the coupling unit.the coupling unit.The transmitter coupling unit injects The transmitter coupling unit injects the OFDM signal into a home power the OFDM signal into a home power line network through an F type socket.line network through an F type socket.Through another socket of the home Through another socket of the home network, the receiver coupling unit network, the receiver coupling unit extracts the OFDM signal and passes extracts the OFDM signal and passes it to the receiver development kit.it to the receiver development kit.The receiver development kit retrieves The receiver development kit retrieves the generator’s signal , which is the generator’s signal , which is depicted by the oscilloscope.depicted by the oscilloscope.

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Topology of the power line home Topology of the power line home networknetwork

The transmitter and The transmitter and the receiver are the receiver are connected through a connected through a 5m long power line in 5m long power line in a small home network a small home network topology, where topology, where several PCs (namely several PCs (namely switching power switching power supplies) are also supplies) are also connected as shown connected as shown in the figure.in the figure.

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PLC Results IPLC Results I

This figure presents the received OFDM signal, This figure presents the received OFDM signal, namely the output of the receiver coupling unit.namely the output of the receiver coupling unit.

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PLC Results IIPLC Results II

The figure above shows the output of the receiver The figure above shows the output of the receiver development kit for a generator’s signal of frequency 128 development kit for a generator’s signal of frequency 128 kHz.kHz.

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PLC Results IIIPLC Results III

This figure depicts the output of the receiver for This figure depicts the output of the receiver for a generator’s signal of frequency 380 kHz.a generator’s signal of frequency 380 kHz.

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PLC Results IVPLC Results IVThis last figure presents the output of the This last figure presents the output of the receiver for an input signal of frequency 760 receiver for an input signal of frequency 760 kHz.kHz.

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Comments on the ResultsComments on the ResultsThe results are quite satisfactory.The results are quite satisfactory.Many errors are due to the failure of the receiver to Many errors are due to the failure of the receiver to identify all the arriving frames.identify all the arriving frames.

A good frame synchronization algorithm employed by the A good frame synchronization algorithm employed by the receiver could improve results.receiver could improve results.

The propagation through the communication channelThe propagation through the communication channel is is also responsible for many errors.also responsible for many errors.

A different mapping technique of the input data to the A different mapping technique of the input data to the subcarriers, the use of more subcarriers, or even the use of an subcarriers, the use of more subcarriers, or even the use of an error correction scheme could reduce fault data.error correction scheme could reduce fault data.

Of course, the system’s performance needs to be tested Of course, the system’s performance needs to be tested over more complex home network topologies.over more complex home network topologies.

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Thank you!Thank you!ee--mail: mail: [email protected]@gmail.com

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