Procedia Computer Science 54 ( 2015 ) 605 – 611

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1877-0509 © 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).Peer-review under responsibility of organizing committee of the Eleventh International Multi-Conference on Information Processing-2015 (IMCIP-2015)doi: 10.1016/j.procs.2015.06.070

ScienceDirect

Eleventh International Multi-Conference on Information Processing-2015 (IMCIP-2015)

An Efficient 256-Tap Parallel FIR Digital Filter ImplementationUsing Distributed Arithmetic Architecture

Amita Nandala,∗, T. Vigneswarnb, Ashwani K. Ranaa and Arvind Dhakac

aDepartment of ECE, NIT HamirpurbDepartment of ECE, VIT University, Chennai

cDeparment of CSE, NIT Hamripur

Abstract

This paper discusses FPGA implementation of Finite Impulse Response (FIR) filters using Distributed Arithmetic (DA) whichsubstitute multiply and accumulate operations with a series of Look-Up-Table (LUT) accesses. Parallel FIR digital filter can be usedeither for high speed or low-power applications. The distributed arithmetic provides a multiplication-free method for calculatinginner products of fixed-point data, based on table lookups of pre calculated partial products. The implementation results are providedto demonstrate a high-speed and low power proposed architecture. The proposed filter is implemented in very high speed integratedcircuit hardware description language (VHDL) and verified via simulation. The proposed method offers average reductions of60% in the number of LUT, 40% reduction in occupied slices and 50% reduction in the number gates for parallel FIR filterimplementation.© 2015 The Authors. Published by Elsevier B.V.Peer-review under responsibility of organizing committee of the Eleventh International Multi-Conference on InformationProcessing-2015 (IMCIP-2015).

Keywords: Distributed arithmetic; DSP; Finite impulse response; LUT; MAC and parallel filters.

1. Introduction

Due to the intensive use of Finite Impulse Response (FIR) filters in video and communication systems, highperformance in speed, area and power consumption is demanded. Basically, digital filters are used to modify thecharacteristic of signals in time and frequency domain and have been recognized as primary digital signal processingelement. In DSP, the design methods were mainly focused in multiplier-based architectures to implement theMultiply-And-Accumulate (MAC) blocks that constitute the central piece in FIR filters and several functions. Fastparallel filter structures have been discussed in detail in1–9. Finite Impulse Response (FIR) filters are importantbuilding blocks for various Digital Signal Processing (DSP) applications. Recently, because of the increasing demandfor video-signal processing and transmission, high-speed and high-order programmable FIR filters have frequentlybeen used to perform adaptive pulse shaping and signal equalization on the received data in real time, such as ghostcancellation10, 11 and channel equalization12. Hence, an efficient VLSI architecture for a high-speed programmableFIR filter is needed.

∗Corresponding author. Tel.: 09736494921.E-mail address: amita−nandal@yahoo.com

© 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).Peer-review under responsibility of organizing committee of the Eleventh International Multi-Conference on Information Processing-2015 (IMCIP-2015)

606 Amita Nandal et al. / Procedia Computer Science 54 ( 2015 ) 605 – 611

Fig. 1. Block diagram of conventional parallel FIR filtering.

In this work we are addressing optimizations in the multiplier block of FIR filters by changes in architectural levelimprovements using distributed arithmetic concept of digital filtering which improves device utilization.

Distributed Arithmetic (DA) is a high speed multiplication technique used for implementation of digital filters andsignal up conversions21, 22. The DA is bit serial word parallel approach where throughput rate does not depend on filterlength or data size.

This paper is organized as follows. Section 2 briefly describes background study. We present a distributed arithmeticbased filtering scheme in section 3. In section 4 we present our proposed FIR filter design flow. Section 5 shows thesynthesis results obtained by XILINX. Section 6 summarizes the conclusions and presents proposals for future work.

2. Background Study

2.1 Parallel FIR filters

A FIR filter can be mathematically expressed by the equation (1)13, 26.

y[n] =N−1∑

i=0

h[i ]x[n − i ] (1)

where X represents the input signal, H the filter coefficients, Y the output signal, Y [n] is the current output sample,and N is the number of taps of the filter. In the sequential implementation a set of Multiply-And-Accumulate (MAC)operations is performed for each sample of the input data signal, multiplying the N delayed input samples bycoefficients and summing up the results together to generate the output signal. In parallel implementations, we canhave two main architectures. The first one consists of unrolling of MAC loop where we have several delayed versionsof the input signal entering in a fully parallel multiplier block, followed by a summation block. The other one consistsof a multiplier block, which takes the same input signal and delivers each output to an input of a delayed summationblock. Fig. 1 shows the basic block diagram of conventional parallel FIR filtering.

Several techniques for optimizing the multiplier block of parallel FIR filters were proposed in the literature. Most ofthem consider the use the fixed-point representation and transposed form implementation, because it is easier to obtaincommon sub expressions to be shared along two or more multipliers in this form14, 15. Many consider the use of somekind of Signed Digit (SD) representation, mainly the Canonical Signed Digit (CSD) representation16, 17, which resultsin fewer non-zero digits in each coefficient, usually resulting in a smaller multiplier block. Previous research has beenshown reductions of more than 50%16 in the number of adders by using these techniques. The great advantage ofthese techniques is that the optimized filter has the same behavior of the original non-optimized one (i.e. same impulseresponse or transfer function). Another approach consists of representing each coefficient as a sum of power-of-twoterms and limiting the number of power-of-two terms in each coefficient17–20.

An FIR digital filter of degree N is described by the impulse response, hn, n = 0, 1, 2, . . . , N and its transferfunction is represented as follows:

H (z) =N∑

n=0

hnz−n (2)

607 Amita Nandal et al. / Procedia Computer Science 54 ( 2015 ) 605 – 611

Fig. 2. Concept of existing distributed arithmetic based filtering.

the traditional L-parallel FIR filter can be derived using polyphase decomposition3 as,

L−1∑

p=0

Yp(zL)z−p =

L−1∑

q=0

Xq(zL)z−qL−1∑

r=0

Hr(zL)z−r (3)

A two-parallel FIR filter can be expressed as

Y0 + z−1 H1 = (H0 + z−1 H1)(X0 + z−1 X1) (4)

= H0X0 + z−1(H0X1 + H1X0) + z−2 H1X1 (5)

Equation 4 and equation 5 implies that,

Y0 = H0X0 + z−2 H1X1 (6)

Y1 = H0X1 + H1X0 (7)

2.2 Distributed arithmetic based filtering scheme

Distributed Arithmetic was first brought up by Croisier23, and was extended to cover the signed data system. Then itwas introduced into FPGA design to save MAC blocks with the development of FPGA technology. High performanceFIR filter based on DA using LMS architecture is implemented in24, 25.

If h[n] is the filter coefficient and x[n] is the input sequence to be processed, the N-length FIR filter can be describedas final form of distributed arithmetic as,

y = −2B xB[n]h[n] +B−1∑

b=0

2bN−1∑

N=0

h[n]xb[n] (8)

Figure 2 shows the existing DA based filtering scheme27.

3. Proposed Work

The basic LUT-DA scheme on an FPGA would consist of three main components: the input registers, the 4-inputLUT unit and the shifter/accumulator unit. Additionally, it would require a control unit to manipulate the filteroperation, and an adder tree unit to perform addition on partial filter results. Applying this approach the 4-input LUTunit will not be directly accessed instead 2-input LUT is used based on multiplexer select. The concept of multiplexerbased DA filtering scheme is shown in Fig. 4.

The proposed DA based filter architecture is shown in Fig. 4 for 256-tap parallel FIR filter. This architecture usesthe concept of multiplexer based DA filtering scheme shown in Fig. 3. The particular 2-input LUT is selected whichrepresent all the possible sum combinations of filter coefficients. It implies about 50% reduction in the number ofLUT used with increased speed. There are two main aspects to be considered when designing a parallel filter, namelythe number of bits required for the signal and the required transfer function of the filter. The former one determinesthe word length of the entire data path. The later one is determined by two parameters, namely the number of taps,and the number of bits in each coefficient. The multipliers are the most expensive blocks in terms of area, delay,

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Fig. 3. Multiplexer based DA filtering scheme.

Fig. 4. Proposed parallel digital FIR filter architecture.

and power in a FIR filter when considering custom implementation. In fact, even for a dedicated implementation ofconstant-coefficient multipliers, the amount of hardware needed is very high as we have several multipliers in theentire filter. To evaluate the performance of the proposed scheme, 4-tap, 8-tap, 16-tap, 32-tap, 64-tap, 128-tap and256-tap parallel FIR filters are implemented using VHDL and synthesis is carried out in XILINX-ISE8.1i. The resultsare compared with the conventional parallel FIR filtering scheme and existing DA based implementation.

4. Results and Discussion

The simulation has been done using MODEL SIM 6.4 and XILINX Integrated Software Environment (ISE) isused for performing synthesis and implementation of designs using ‘Spartan-3’ device. The power analysis has been

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Fig. 5. Comparison of number of LUTs used. Fig. 6. Comparison of number of occupied slices.

Fig. 7. Comparison of number of gates used. Fig. 8. Comparison of delay.

done using XILINX XPOWER tool. The evaluation of device utilization using proposed DA architecture can becomprehended easily with the help of the results in graphs shown below.

Figure 5 reports the comparison of number of LUTs used among the various filter architectures designed usingexisting and proposed method. It is shown that proposed multiplexer based DA filter comprehends the existing DAbased parallel FIR filter. The number of LUTs are reduced by 66% using proposed method as compared to DAbased method for parallel FIR filter implementation. This reduction is 19% when compared with conventional filterimplementation.

Figure 6 plots the comparison of number of occupied slices among various parallel FIR filter architectures. It isshown that the proposed multiplexer based DA filter has 42% reduced number of slices as compared to existing DAbased filter architecture. This reduction is 20% when compared to conventional architecture.

Figure 7 reports the comparison of number of gates used among various filter architectures designed. It is shownthat the proposed multiplexer based DA filter has 55% reduced number of slices as compared to existing DA basedfilter architecture. This reduction is 14% when compared to conventional architecture.

Figure 8 reports the delay comparison among various filter architectures designed. It is shown that the proposedmultiplexer based DA filter is 10% faster as compared to existing DA based filter architecture. This improvement is5% when compared to conventional architecture.

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Fig. 9. Comparison of power consumption. Fig. 10. Comparison of Power Delay Product (PDP).

Figure 9 reports the power consumption comparison among various filter architectures designed. It is shown that theproposed multiplexer based DA filter has 55% reduced power consumption as compared to existing DA based filterarchitecture. This reduction is 27% when compared to conventional architecture.

The overall performance metric (i.e. power, delay product) for proposed design is also improved as shown in Fig. 10.

5. Conclusion

We have presented an efficient multiplexer based DA scheme which is used to implement parallel FIR filters. Thedevice utilization of the proposed architecture is relatively less since it uses split LUT technique. Proposed method isimplemented for 4-tap to 256-tap parallel FIR filters and can be even extended for more taps. A high speed and less areaimplementation is achieved. The test results indicate that the designed filter using proposed distributed arithmetic canwork stable with high speed and can save almost 50 percent hardware resources. For various digital signal processingapplications the various parameters and order of filter can be changed accordingly.

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