An Area-efficient Vlsi Architecture of a Reed-solomon

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Kwon and Shin: An A rea-Efficient VLSI Architecture of a Reed-Solomon DecoderEncoder for Digital VCRs 1019

AN AREA-EFFICIENT VLSI ARCHITECTURE OF A REED-SOLOMONDECODEWENCODER FOR DIGITAL VCRs

Sunghoon Kwon and Hyunchul ShinDept. of Electronics Engineering, Hanyang University, Korea

Abstract : A new flexible and area-efficient VLSIarchitecture of a Reed-Solomon product-codedecoder/encoder has been developed for digital VCRs.The new architecture of the decoder/encoder targeted toreduce the circuit size and decoding latency has thefollowing three features. First, high area-efficiency hasbeen achieved by sharing a functional block fo rencoding, modified syndrome computation, and erasurelocator polynomial evaluation. Second, circuit size anddecoding latency has been reduced by using a newarchitecture to implement the modified Euclidsalgorithm. Third, by doubling the internal clock speedfrom 18 MHz to 36 MHz), the decoding latency andhence the memory size can be reduced. Thedecodeden coder designed by using the proposed m ethoduses less number of gates, by about 30 , than the onebased on the conventional architectures.

I. IntroductionThe Reed-Solomon (RS) coding is one of the mostpowerful and standardized techniques for error anderasure correction. Owing to its excellent capabilityfor correcting burst errors, it has been widely usedfor digital communication systems and storagedevices such as digital VCRs and disk drives [11. Inparticular, for error correction coding (ECC), thedigtal VCRs employ RS product codes.RS codes over finite fields are maximum&stance separable. The properties and theoreticalanalysis of RS codes are well-known [2]. However,the design of a high-bit-rate RS decoder is notstraightforward. The complexity of a RSdecodedencoder circuit is dependent on the data rate,the code length, and the error correction capability.Therefore, the algorithm and the archtecture shouldbe customized for each specific application toachieve high efficiency.

RS decoding techniques can be classified intotwo categories (time-domain and frequency-domain).Time-domain techmques seem to outperform

frequency-domain techmques both in area and indelay [3]. Most of the published time-domaintechniques use one of the following algorithms toevaluate errorlerasure locator and evaluatorpolynomials.Berlekamp-Massey algorithm : [4](Modified) Euclids algorithm : [ 5 , 6, 71Matrix calculation : [8]A VLSI design of a pipeline RS decoder usingsystolic array was also presented in [ 5 ] . By the useof a multiplexing and recursive technique, themodified Euclids algorithm was implemented withsignificant reduction of cells. RS decoder in [7] candecode three types of codes (inner/outer/subcode)flexibly. One of the features of this design is to sharethe encoder and the syndrome computation block toreduce hardware size. In [9], it is shown that any RSdecoder which corrects both errors and erasures alsocan be used as an encoder for the RS code. Butpower consumption can be increased by driving all ofthe blocks of decoder circuit during encodmg.

To satisfy the decoding/encoding requirementsfor digital VCRs, we have developed a new flexibleand area-efficient RS product-code decodedencoderarchitecture. Our decodedencoder can decode andencode three types of audio and video signals overGF(256). The three main features of the proposeddecodedencoder are1. sharing a hardware functional block2. developing a new architecture3. doubling the intemal clock speedThe proposed RS decodedencoder has beenimplemented by using about 30% less number ofgates than the one based on conventionalarchitectures.In Section 11, we describe the overview of theproposed RS decodedencoder. The flexible

to evaluate three different functions,for the modified Euclids algorithm andto reduce the latency.

Contributed PaperManuscript received June 9, 1997 0098 3063/97 10.00 1997 IEEE


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1020 IEEE Tran sactions on Co nsume r Electronics, Vol. 43, No. 4, NOVEMBER 1997

decodedencoder architecture is presented in Section111. The experimental results are described in SectionIV. Finally, the conclusions are given in SectionV.11. New Features of the

ecoder EncoderThe new flexible RS decoder circuit based on themodified Euclid's algorithm can correct errors anderasures for product codes (two-dimensional arraycodes). The decoding is performed in two steps, inner(row) and outer (column) decoding [ lo] . The innerdecoder performs error correction and error detection.The inner code protects inhvidual cade, primarilyagainst random errors. The same code, RS (85, 77),is used for both the audio and video signals. If adecoder failure is declared by the inner decoder, thenthe entire symbols in the corresponding row areerased. The outer decoder works essentially as anerror and erasure corrector. Outer RS code protects acomplete video or audio sector, primarily againstburst errors spanning a few codes. If the outerdecoder can not correct the errors and erasures, adecoding failure occurs and an error concealment isapplied. Our decodedencoder is flexible in that it candecode the following three types of codes overGF(256) [111:

(85,77) audiohide0 inner code* (149,138) video outer code* (14,9) audio outer codeThe maximum number of errors which can be

corrected are 4, 5 , and 2, respectively, for the threecodes. For outer codes, the maximum number oferasures which can be corrected are 11 and 5respectively, for (149, 138) and (14, 9) codes. In theproposed architecture, (85, 77) and (14, 9) codes arealso encoded and decoded by using the same (149,138) code processing block. Suppose e errors and ferasures occur, then in general, the followingequation indicated by maximum correction capabilityshould be satisfied in (n, k) RS codes.

(1)where, n is the code length and k is informationlength. Furthermore, 2t = n - k and t is the errorcorrection capability.The proposed RS decodedencoder is shown inFig. 1. The circuit is pipelined and consists of sixfunctional blocks, which are syndrome computation,encoder and polynomial expansion computation,modified Euclid's algorithm processing, Chien search,error correction and verification, and FIFO memoryblocks.The general decoding algorithm is as follows.1. Compute a syndrome polynomial, S(x).

2. Compute the error locator polynomial, A(x)and modified syndrome polynomial, T x)

3. Perform a modified Euclid's algorithm.4. Evaluate erroderasure locator polynomial

2e + f n - k

and error/erasure evaluator polynomial (Ghiensearch algorithm).5 . Correct and verify the errors.

.E.$.mpu...............

ModifiedEudidsAlgOnthm....................................

Interior Regbns. . . . . . . . .....c

....................


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Kwon and Shin: An Area-Efficient VLSI Architecture of a Reed-Solomon DecoderEncoder for Digital VCRs 1021

The proposed decodedencoder architecture hasat least three major features which improve the area-efficiency significantly when compared toconventional architectures.1. Three different functions share a hardwarefunctional block. The encoder and polynomialexpansions of T x) and A(x) share a functionalblock by using MUXs as shown in Fig. 2 . Themodified syndrome polynomial, T x), and theerasure locator polynomial, A(x) , can be computedby using the same hardware by setting differentinitial values. Each function is performed in differenttime periods. For faster (simpler) erasure informationtransfer during this process, we use erasure addressesof 8 bits instead of erasure flags of 1 bit.2. Decoder size is reduced by using a new circuitarchitecture in which erroderasure locator anderroderasure evaluator polynomials are found. Thenew architecture implementing the modified Euclidsalgorithm is shown in Fig. 3.In this architecture, thecoefficients of each polynomial are grouped into two(upper and lower) parts and separately stored in Ri,Q;, L,, U, registers. The two parts are calculated inparallel. Owing to the parallel processing, decodinglatency is significantly reduced.

3 . The clock speed is doubled in intemal decoderblocks to reduce latency and memory size. The datarate in our specification is 18 Mbytesjsec at theprimary I/O and the base clock speed is 18 MHz.However, present VLSIs can easily accommodate a36 MHz clock. Therefore, ,the three blocks in theinterior regions marked by dotted box in Fig. 1 mayoperate at 36 MHz. (Other blocks operate at 18MHz) Th~sllows sharing of the Chien search block,shown in Fig. 4, by errorlerasure locator anderroderasure evaluator polynomials,These novel techniques have the obvious benefitsof reducing the decodedencoder size and thedecoding latency.111. RS DecodedEncoder ArchitecturesIn th s Section, we first explain the overall behaviorof the proposed decoderlencoder and then, describethe proposed architectures and their timing diagramsin detail.

3.1 Overall Behavior of the Decoder/EncoderEncoding for (n, k) RS codes is usuallyperformed by (n - k)-stage linear feedback shiftregisters [11. In our design, encoding is performed inthe Encoder and Polynomial Expansion block, toshare hardware.In Fig. 1, decoding is performed in two steps foraudlo and video signals, respectively. For audiosignals, (85, 77) inner decoding is followed by (14,

9) outer decodmg. Similarly, for video signals, (85,77) inner and (149, 138) outer decodings areperformed. In inner or outer decoding, errors can bedetected and corrected. However, erasures aredetected during the inner decoding and correctedduring the outer decoding. The proposed decoder/encoder consists of six blocks similar to generaldkcoding architecture.Let {rn. ] ,.., l , ro>be the received symbols of 8bits and letr x, = rn-lxn-l... + r,xl + ro

g x) = x- a o ) x - a )..( -

2 )The generator polynomial of a (n, k) code isrepresented by the following equation over GF(256).(3)where, a is a primitive element in GF(2.56).The behavior of each block of thedecodedencoder in Fig. 1 can be summarized asfollows.

1. The Syndrome Computation blockcalculates syndrome polynomial, S x) . Thecoefficients of polynomial S ( x ) are calculated as

n-k-1

1=0

where, s, = r a )2 . The Encoder and Polynomial Expansionblock calculates the erasure locator polynomial,A ( x ) , by using the erasure addresses of 8 bits. In

other approaches, the erasure locations are frequentlyrepresented by one-bit flags. However, we useerasure addresses of 8 bits instead of erasure flags.By using these addresses, A(x) can be calculated inadvance and passed to the next modified Euclidsalgorithm block. The modified syndrome polynomial,T x) s calculated by using the following equation.

T x ) = S x )A(x) modx2 ( 5 )


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1022 IEEE Transactions on Consumer Electronics, Vol. 43, No. 4, NOVEMBER 1997

Erasure

,,IitsL Encod ingo u t p u t @ : 8 bits multiplier over GF(256): 8 bits adder over GF(256)Coefficients of S X) are stored in registers to be u sed for the calculation of modified syndrome.Switch S is ON (OFF) if erasure value is non-zero 0).

Fig. 2. Encoder an d polynomial expans ion b lock .3 . The Modified Euclids Algorithm blockcomputes error/erasure locator polynomial, O(X) ,

and erroderasure evaluator polynomial, ~ ( x )byusing T x) nd A(x) as initial conditions. A newarchitecture for this block implementation has beendeveloped and will be described later in detail.

4. The Chien Searcp block evaluates o(a-)odd,(a-)nd m ( d ) or i = 0, ..., n-1. The rootsof these polynomials are used to computeerroderasure locations and values.

5 . The Error Correction and Verificationblock computes erroderasure value, ei romei = ~ ( a - )oodda ? ) or i = 0, ..., n-1 (6)

where o O d da- ) s the sum of odd-terms of ~ x )Then, a corrected symbol is obtained by addingthe error c i o the received erroneous symbol r, .6= q + ei for i = 0, ..., n-1 (7)

The is then used to verify the correctness ofthe corrected values, i.e., to check whetherS(x) = 0 or not. If S ( x )= 0 , is accepted.Othemise, the correction in the inner decoding is notsuccessful and thus the row address is saved for theouter decoding. For erasure decoding, the receiveddata stored in the FIFO memory block is used.6 The FIFO memory block is used to delaythe received data by 2n + 6 , where 2n is the delayrequired for the syndrome computation, Chien search,and verification and 6 is the processing time delayof other (the Encoder and Polynomial Expansionand the modified Euclids algorithm) blocks,

3.2 Hardw are Sharing for Encoding andPolynomial ExpansionFig. 2 shows the detailed architecture of theEncoder and Polynomial Expansion block. Sinceencoding and polynomial expansions of A(x) and

T x) can be computed by using the architectureshown in Fig. 2, the hardware is time-shared for thethree computations.Now we explain how encoding of a (149, 138)code is performed. Switch S is used to control signaltransfer. Initially, all the switches are ON andregisters, & - RIO,re reset to 0. Constants go - 10(the coefficients of the generator polynomial in eq.(3)) are selected by MUXs, i.e., MU& - MUXIO.Then, systematic encoding is performed. For the first138 clock cycle times, encoding input is selected byMUXll and MUXI*.For the rest 11 clock times, theresultant parities computed in registers are selected

A(x) is computed as follows. Assume that Ais the set of a-s where a- E A implies thatthe location of r is an erasure. The A(x) can bewritten as

(8)During inner decodmg, A x ) = 1, since there

are no erasures. In the case of a (149, 138) outercode, the maximum degree of A(x) is 2t = 11. RI1is only used to store the coefficient of the maximumdegree 11.

by MUXI1.

A(x) = n X - a-)a- EA


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Kwon and Shin: An Area-Efficient VLSI Architecture of a Reed-Solomon Decoder/Encoder for Digital VCRs 1023

Initially, R = 1 and all the R1 - RI1values are0. After the polynomial expansion, the i'th degreecoefficient of A(x) are stored in Ri register. Ifa- A , switch S is off and thus signals can not bepassed to registers.Similarly, the modified syndrome polynomialT x ) shown in equation (5) can be computed byusing the circuit. T x ) uses the coefficients ofS x), instead of the initial register values, i.e., 1. R- Rlo registers initially store the coefficients of

For (85, 77) and (14, 9) code processing, (R3 -S ( X )R11) and ( - R11) registers are used, respectively.3.3 An Efficient Architecture to Perform theMo dified Euclid s Algorithm

To determine erroderasure locator polynomial~ x ) nd erroderasure evaluator polynomial m(x) ,the modified Euclid's algorithm [5] is applied. Thealgorithm is summarized in the following procedure.1. Initial value setting2. Recursive computation and stop condition

The initial values of the Euclid's algorithm arecheckingR, (x) = x~~ Q, (x) = T(x) (9)L o x) = 0, U, (x) = A(x) (10)Then, recursive computation is performed as

follows until the stop condition, i.e., deg(Li x)) >deg(R,(x)) , is satisfied. If the stop condition issatisfied,then m ( x > = R i ( x ) and o ( x ) = L i ( x ) .

xl'i'[oiaiQi(x)+FibiRi(x)] (11)(12)

x'z i ' [oia iUi(x)Fib iL i (x ) ] (13)(14)

R1 1x) = ColbiRi(x) + iaiQi ~11-Qi+l (x) = o i Q i (x) +ZiRi (x)

ui+lx) = q u i x) +OiLi x)Li+,(x)= [o i b i L i (x )+CiaiUi(x) ] -

where, (ai,b i ) is the leadmg coefficients of@ i (x), Q i (XI)

= deg(Ri XI)- deg(Qi (x))if Zi 0 oi= 1, else oi 0 (15)(16)Fig. 3, a), (b), (c) and (d) shows the proposednew archtecture. In this architecture, we computeupper coefficients and lower coefficients of thepolynomials in parallel. Since multiplication and

addition is performed for ea& coefficient ofpolynomials, the coefficients can be computed inparallel. In addition, double-speed clock is used inthis block. Since r 6 5 / 14/ 2 / 2 =1, (14, 9) outercode requires only 1 cell. As a result, the number ofcells is reduced from 3 to 1 when compared to astraightforward implementation of [SI.

We now describe briefly the hardware operationfor the modified Euclid's algorithm. Fig. 3 (a) and(b) show the recursive computation blocks ofR i(x) Q i x) and Li(x) U i x) . Initially, thecoefficients of these polynomials are set in Ri QiLi and U i registers, divided into the upper andlower coefficient groups, respectively. Qi(x) andU,(x) register value transfer control block iscomposed of MUXs. In Fig. 3 (c), and stopcondition is calculated. According to I Qi(x)and U,(x) register value transfer control blockshifts the coefficients or swaps polynomials,{ R i ( x 1, i (x) 1 and { Li(x) Ui x) . Owing tothe polynomial computations in (1 1)- 16),polynomial swapping is needed if Zi < 0 .Fig. 3(d)shows the arithmetic blocks used in (a) and (b). Inparticular, arithmetic unit (3) is used to computeinitial condition for the next &en Search block.This computation is necessary, for n 2 - 1 in

As an example, we describe decoding of a (149,138) code by using the circuit in Fig. 3 (a). Note thatthe maximum number of coefficient of Ri ( x >polynomial is 12. Therefore, the upper degreecoefficients of Ri ( x are stored in & - R11registers in block 3, marked by dotted box. Similarly,the lower degree coefficients are stored in Ro - RSregisters of block 1 and block 2. Then, the modifiedEuclid's algorithm is performed, recursively. At thistime, MUXl and MUX3 select R and R5,respectively. And, MUX2 selects the output of thearithmetic unit (1) of block 3.In the case of a 85, 77) code, RS, RIO nd R11registers are initially set to 0. The (14, 9) code isprocessed by using blocks 1 and 2. Similarly, the 6coefficients of the (14, 9) code are divided into twoparts and stored in (& - k nd in (R3- Rs)registers in blocks 1 and 2, respectively.

GF(z ).


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1024 IEEE Transactions on Consumer Electronics, Vol. 43, No. 4, NOVEMBER 1997

(a ) Ri x ) , Q i x ) computat ion b lock.

(b) L i x ) , Ui x ) computat ion b lock..............................................d e g ( R ; ( x ) ) d e g ( Q ; ( x ) )

(c) D egree com putat ion b lock...

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Arith. unit 3).a, ,b ,) leading coeff. o f R , ( x ) , Q , x )(d) Arithmetic units.

F ig . 3. Mo dif ied Eucl id s a lgor i thm processing b lock.The modified Euclid's algorithm is processed byusing the proposed architecture in parallel. Owing tothis parallel processing, the decoding latency can be

significantly reduced and as a consequence, thenumber of cells and the FIFO memory sizes arereduced.3.4 Chien Search Implementation Block

In general, o(a- ),,,(a- ) and ~ ( a - )

are computed in two blocks of the same architecture.We have developed a new archtecture capable

of sharing the hardware blocks. The architecture issimple, as shown in Fig. 4.Hardware sharing ispossible by using double-speed clock of 36 M H Z . Inthis block, the roots of erroderasure locatorpolynomials, and erroderasure evaluator polynomialsare computed alternately. During even clocks,o(a- ) nd oodd(a- )re computed, whileduring odd clocks, w ( a - ' ) is computed. The output


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1025won and Shin: An Area-Efficient VLSI Architecture of a Reed-Solomon DecoderEncoder for Digital VCRs

8r1 0 ( a - i )odd

Summation by XO R treeFig. 4 . Chien search Implementation b l o c k .

is adjusted to the original clock speed which is 18M H Z

3.5 RS Decoder/Encoder Timing D iagramFig. 5 shows the timing diagram for (n, k) RS

decodedencoder. In particular, the latency of theEuclids algorithm block is { (r(2t + 1)/ 21 + 1) 2t+ (2t + 1) }/2. In this latency, r t + 1 / 21 +1)*2tclock cycle times are needed to complete the modifiedEuclids algorithm. It takes (2t+l) clock cycle timesto compute initial values used in Chien search block.Of course, by using the double-speed clock, decodinglatency is reduced by half.

w

The error correction and verification is initiallyperformed for (n+3) clock cycle times. As a result,overall decodmg latency is given byDecoding latency = n + {2t +((r(2t + 1) / 21+ 1) 2t + (2t + 1)) }/2 + n + 3.

IV. Experimental ResultsWe have implemented the proposed RSdecodedencoder using VHDL. During the hardwaresynthesis, circuit delays have been considered byrestricting the longest path delays of thedecodedencoder.Table 1 shows the implementation resultsbased on several design methods, i.e., [ 5 ] , [7], anindustry design, and our proposed method. A gatecorresponds to a 2 input NAND gate. The number oftotal gates is from the synthesized results excludingthe FIFO memories. The new proposed architecturehas been implemented by using about 35,000 gates,which is about 30 smaller than the other designresults. The FIFO memory sizes have been reducedsince the latency has been reduced.In the industry result, Berlekamp-Masseyalgorithm has been used. In others, the modifiedEuclids algorithm has been used. Note that in [7],design specification (code length, error correctioncapability, etc.) is different from others and therefore,direct comparison is not possible.We have verified the correctness of thedesigned decodedencoder by using extensivesimulatiomith randomly generated data and errors.


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1026 IEEE Transactions on Consu mer E lectronics, Vol. 43, No. 4, NOVEMBER 1997

Modified Euclid's algorithm*

(Notes): '- ' n 171 means unknown, i.e., the results have not been published.

V. ConclusionsIn this paper, we have proposed a new flexible andarea-efficient VLSI architecture of a Reed-Solomonproduct code decodedencoder for digital VCRs . Theproposed architecture has three major features. First,area-efficiency has been significantly improved bysharing a functional block. Second, a newarchtecture implementing the modified Euclid'salgorithm has been developed to reduce the circuitsize and latency. Third, by doubling the internalclock speed, the decoding latency and hence thememory size have been reduced. The correctness ofthe proposed decoder/encoder has been verified bythe extensive simulation.

References[I] S. B. Wicker and V. K. Bhargava, Reed-SolomonCodes and Their Applications , New York, IEEEPress, 1994.[2] S. B. Wicker Error Control Systems for DigitalCommunication and Storage , Prentice Hall, 1995.[3] Y. Jeong and W. Burleson, High-Level Estimationof High-Performance Architectures for Reed-Solomon Decoding, ISCAS, vol. 1, pp. 720-723,May, 1995.[4] J. M. Hsu and C. L. Wang, An Area-Efficient VLSIArchitecture for Decoding of Reed-Solomon Codes,ICASSP, vol. 6, pp. 3291-3294, May 1996.[ 5 ] H. M. Shao and I. S. Reed, On the VLSI Design of

a Pipeline Reed-Solomon Decoder Using SystolicArrays, IEEE Trans. on Computers, vol. 37, no. 10,pp. 1273-1280, Oct. 1988.

[6] H. M. Shao, W. Hills, T. K. Truong, I. S. Hsu, bothof Pasadena, L. J. Deutsch, Sepulveda, all of Calif.,Architecture for Time or Transform DomainDecoding of Reed-Solomon Codes, U. S. Patent4,868,828, Sep. 19, 1989.[7] G. Y. Lee, B. H. Kwuan, S. W. Lee, J. W. Jung, S. H.Nam, Y. S. Chun, D. I. Han, K. S. Park, Y. D. Choi,D. I. Cho, and J. K. Lee, A VLSI Design of RSCODEC for Digital Data Recorder, ASIC DesignWorkshop, pp. 115-124, 1996.

[8] T. Iwaki, T. Tanaka, E. Yamada, T. Okuda, and T.Sasada, Architecture of A High Speed Reed-Solomon Decoder, IEEE Trans. on ConsumerElectronics, vol. 40, no. 1, pp. 75-81, Feb. 1994.[9] C. C. Hsu, I. S. Reed, and T. K. Truong, Use of theRS Decoder as an RS Encoder for Two-way DigitalCommunications and Storage Systems, IEEE Trans.on Circuits and Systems for Video Technology, vol.4. no. 1, pp. 91-92, Feb. 1994.[lo] S. H. Kim and S. W. Kim, An Error-ControlCoding Scheme for Multispeed Play of Digital VCR ,IEEE Trans. on Circuits and Systems for VideoTechnology, vol. 5 . no. 3. pp. 243-247, June 1995[1 ] Specifications of Digital VCR for Consumer-Use ,SD; Standard Definition, NTSC, PAL, SECOM,HD-Digital VCR Conference, DRAFT IEC

document, Confidential, June 1994.

BiographiesSunghoon Kwon received the B.S. degree andthe M.S. degree in electronics engineering fromHan-Yang University, in 1991 and 1993,respectively. He is working toward the Ph.D. degree


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Kwon and Shin: An Area-Efficient VLSI Architecture of a Reed-Solomon DecoderEncoder for Digital VCRs

in electronics engineering at Han-Yang University.synthesis of VLSIsHis research interests include system design and

Hyunchul Shin (S78-M80-SM96) receivedthe B.S. degree in electronics engineering fromSeoul National University, the M.S. degree inelectrical engineering from the Korea AdvancedInstitute of Science and Technology in 1978 and1980, respectively, and the Ph.D. degree in electricalengineering and computer sciences from theUniversity of California, Berkeley, in 1987.From 1980 to 1983, he was with the Departmentof Electronics Engineering, Kun-Oh Institute ofTechnology, Korea. In 1983, he received aFullbright Scholarship. From 1987 to 1989, he wasa Member of the Technical Staff at AT&T BellLaboratories, Murray Hill, NJ. Since 1989, he hasbeen with the Department of Electronics Engineering,Han-Yang University, Korea. His research interestsinclude design and synthesis of integrated circuitsand systems.

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An Area-efficient Vlsi Architecture of a Reed-solomon

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