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1. Introduction The purpose of this report is to document the design, construction and testing of a 50W high quality audio power amplifier. This amplifier was developed at The University of Sheffield over a period of seven weeks during the second semester of the 2002/2003 academic year. The idea behind a power amplifier is to take a signal produced by a microphone or some form of player (e.g. a CD/record player) and amplify it to such a power that it can be reproduced through a loud speaker. Often there is a pre-amplifier placed before the power amplifier which controls the volume and other signal parameters such as bass and treble. Pre-amplifier design will not be considered here. The vast majority of power amplifiers have the same high level layout consisting of a differential amplifier stage, followed by a voltage amplification stage (VAS), followed by a third stage providing the required current gain. The current gain stage is often two devices working in a Push Pull arrangement. Negative feedback connects the output to the input differential stage to provide a stable circuit. (See Figure 1)

Figure 1 General Power Amplifier Circuit Three classes of the topology in figure 1 exist and relate to the different biasing (DC quiescent operating point) of the output current gain stage. Class A circuits are biased so that both output devices are on for the whole input cycle. This requires a large bias current and large heat sinks to dissipate the heat generated in the output devices. Class A circuits are therefore relatively inefficient. Maximum efficiency is reached at full volume when one of the output devices comes close to turning off. However class A circuits have low distortions due to the output devices never turning off. Class B circuits are biased so that the output devices are never on together and never off together. [1] (I.e. the instant one device turns off the other turns on.) This results in much better efficiency than class A but distortion occurs at the point of conduction changeover between the two devices. At an extreme, crossover distortion results (where there is a delay between one device turning on after the other has turned off.) This distortion would sound very unpleasant to a listener.

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It is possible to have a circuit biased so that it operates in class A for small signals and then switches over to class B operation for larger signals. This is called class AB operation. It is somewhat of a compromise between the high quiescent power dissipations and high linearity of class A operation and lower quiescent power dissipations and lower linearity of class B operation. Class C circuits are very efficient but are generally only used in radio frequency (RF) applications. The output devices conduct for less than 50% of the input cycle. [2] This results in severe cross over distortion and therefore class C circuits do not have a use in audio circuits. A slight variation on figure 1 is a class G amplifier. [3] This makes use of the fact that musical signals spend most of their time at low levels and occasionally jump up to higher levels. Therefore to keep power dissipations low in the output devices they are powered from a low voltage most of the time with the ability to switch to a higher voltage when the input signal is large. A totally different way of amplification which is not based on figure 1 is a class D amplifier. This uses the input signal to pulse width modulate (PWM) a high frequency, high power signal. This PWM signal is then low pass filtered to remove the high frequency component leaving only a larger version of the input signal. Class D amplifiers are potentially very efficient because the output devices are either fully on or fully off in which case little power is dissipated within them. This report will consider the design of a class AB power amplifier with bipolar junction transistors (BJTs) as the output devices. It was designed to meet the following specification given to us at the start of the project. Output power Up to 50W into an 8Ω resistive load with a sinusoidal

drive. (This was increased from 20W in hope of a better chance of annoying the neighbours.)

Input signal level 0dBV from a source with an internal impedance of 1kΩ for full output.

Output resistance <0.1Ω Frequency response -1dB points of 20Hz and 20kHz. Stability Unconditionally stable for inductive and resistive loads,

and for magnitudes of capacitive loads likely to be caused by speaker cables.

Dynamic Range (DR) >100dB

=

voltage noise and hum m.s maxvoltage signalm.s maxDR log20

Short circuit protection To prevent against accidental shorting of the output

terminals. Linearity Total harmonic distortion < 0.1% at 10W. Extra functionality was included that was not in the specification given to us. This was DC offset protection and Anti-Thud protection which will be discussed later in this report.

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The rest of the report is organised such that an overview of the circuit topology is given next, followed by a detailed design explanation. SPICE circuit simulation is then considered before a section on the physical construction of the amplifier is included. The results obtained through testing are then discussed before the report is concluded. 2. Circuit Topology 2.1 High Level Topology Figure 2 shows the amplifier circuit in a high level block diagram form.

Figure 2 High Level Block Diagram 2.2 Band-Pass Filter The band-pass filter prevents any unwanted frequencies from entering the amplifier. It is therefore designed to have -1dB points at 20Hz and 20kHz which is the frequency response required in the specification. It is simply a first order high-pass filter in series with a first order low-pass filter. See figure 3

Figure 3 Band Pass Filter

2.3 Differential Amplifier The output from the band-pass filter is fed into the differential amplifier stage (also known as a long tailed pair). See figure 4

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Figure 4 Simple Differential Amplifier The differential amplifier stage has two inputs at the transistor base connections shown in figure 4. It operates such that differential signals (those which do not appear the same at both inputs) are amplified and common mode signals (those which do appear the same at both inputs) are attenuated. R1 in figure 4 sets a roughly constant current and under steady state conditions this is shared equally between both transistors, Q1 and Q2. R2 converts the current flowing in the left hand arm of the differential amplifier into a voltage to drive the voltage amplification stage (VAS). A differential signal has the effect of unbalancing the two arms so current would now be shared unequally between the two halves. This would cause a change in voltage across R2. For a common mode signal the voltage across R2 will remain constant as the two halves remain balanced (R1 has defined a constant current which continues to be split equally between both halves.) An example of a common mode signal could be noise present on both inputs to the differential amplifier. The differential amplifier therefore helps to keep noise out of the power amplifier. The ability of a circuit to reject common mode signals is quantified by its common mode rejection ratio (CMRR). Others have shown [4] that the larger the emitter resistance is (R1 in figure 4) the larger the CMRR is. However making R1 too large means only a small bias current will flow. This means the transistors will be operating on a less linear part of its base-emitter voltage / collector current characteristic. (See figure 5)

Figure 5 Transistor Transconductance Characteristic

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However, replacing R1 in figure 4 with a current source means that any collector current can be set while the effective impedance of the current source is high giving a large value for the CMRR. The current source will also help to improve the power supply rejection ratio (PSRR). The PSRR is a measure of a circuits ability to operate normally should the power supply vary. It is possible to have a mains frequency hum on top of the supply voltage. The current source would continue to supply a roughly uniform current in this case. Improvements in linearity of the differential amplifier can be made by adding emitter degeneration resistors in both arms. [5] This effectively swamps the variation of internal emitter resistance of the transistors as the collector current varies. I.e. include a linear resistor so that the non linear variation of the transistors internal resistance becomes less significant. This leads to an improved differential amplifier shown in figure 6.

Figure 6 Improved Differential Amplifier

2.4 Voltage Amplification Stage (VAS) This is based around a common emitter amplifier operating in the class A region. This is where most of the voltage gain occurs and it must be capable of the full output voltage swing. Figure 7 shows a simplified diagram. R1 models the collector load and C1 is the dominant pole compensation capacitor. This is used to help stabilise the circuit and prevent it oscillating. The gain of any multistage amplifier begins to roll off at -20dB/decade at some frequency [6] i.e. the circuit acts as a first order low-pass filter. At a higher frequency a second pole will be reached and the gain will roll off at -40dB/decade and then a third pole for -60dB/decade and so on. Each pole creates a 90º phase shift. In order to prevent positive feedback the gain of the amplifier must be less than unity before a 180º inversion has occurred. Positive feedback causes instability and would effectively make an oscillator. Adding C1 as in figure 7 has the effect of taking the first pole, reducing the frequency at which it occurs and therefore making it dominate the amplifiers frequency response. This helps ensure that the gain falls below unity before a phase shift of 180º occurs.

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The voltage gain of the VAS is proportional to the effective value of the collector resistance (R1 in figure 7.) This relationship is derived in appendix 1. To produce a high gain R1 must be made large but, again as in the differential amplifier case, making it too large leads to nonlinearities with the transistor operating on a very nonlinear part of its I-V characteristic. A current source is therefore used in place of R1 to allow the current to be precisely set and to have a high effective collector resistance at the same time.

Figure 7 VAS Stage

Also in the collector arm of the VAS circuit is the biasing arrangement which puts the output devices into slight conduction under DC conditions. This reduces crossover distortion and depending on the voltage dropped across the biasing arrangement, it takes the circuit from a class C (crossover distortion) to a class B (one output device turns on as the other turns off) to a class AB (both devices on for small signals). Figure 8 shows the VAS with the current source and biasing arrangement included.

Figure 8 VAS with Current Source as Collector Load R1 in figure 8 allow the quiescent voltage between the two output devices to be trimmed. The diodes help to keep the circuit thermally stable (this will be discussed later)

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2.5 Output Devices This stage provides the current gain required to drive the speaker load and is shown in figure 9. Q1 and Q2 perform the positive half signal cycles and Q3 and Q4 perform the negative half cycles. Q2 and Q4 are power devices designed to dissipate relatively large powers within themselves (if properly heat-sinked). Q1 and Q3 are smaller signal driver transistors. The arrangement of the two output sections are known as a compound pairs or the Sziklai connection.[7] It is an improvement over the usual darlington pair arrangement as there is only one base emitter voltage drop in the direct signal path whereas with a darlington pair there are two. Each base emitter drop has a temperature coefficient of around -2.5mV/ºC. As the devices warm up due to quiescent current flow the base emitter voltage drops allowing more collector current to flow heating the device further thus reducing the base emitter voltage further and so still more collector current flows and so on. This is called thermal runaway. Placing two base emitter drops in the signal path (as in the darlington arrangement) means the combination has an overall temperature coefficient of around -5 mV/ºC, thus increasing the chances of thermal runaway. The output signal can also get closer to the supply voltage with only one base emitter voltage drop. Diodes D1 and D2 in figure 9 help to thermally stabilise the circuit. If D1and D2 are arranged on the circuit board so that they are in they are in thermal contact with Q1 and Q3 then as the arrangement warms up the bias voltage will drop at the same rate as the base emitter voltages drop, keeping the collector current of Q1 and Q3 roughly constant. Resistors R2 and R5 in figure 9 help to speed up the turn off time of Q2 and Q4. [8] They also prevent the collector leakage current of Q1 and Q3 from turning Q2 and Q4 on. Resistors R3 and R4 provide a cushion to drop any extra voltage created in the bias circuit that is not dropped across the base emitter junctions of Q1 and Q3.[9] They provide some local negative feedback so that when quiescent current increase in the output stage more voltage is dropped across them reducing the collector current of Q1 and Q3 and hence helping to improve thermal stability.

Figure 9 Output Stage

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2.6 Negative Feedback (NFB) Putting all the above sections together effectively makes a high power Op-Amp with, hopefully, a high voltage gain and good linearity. Negative feedback is used to define the gain accurately provide stability for the circuit. It takes the output voltage from across the load and feeds a proportion of it back to the differential amplifier stage. The gain is reduced to unity at DC such that DC offsets at the differential amplifier are not amplified. This is done by adding a capacitor into the resistive feedback divider. Shown in figure 10.

Figure 10 NFB connected between output and differential amplifier

The feedback divider consists of R1, R6 and C1 shown in figure 10. This will be discussed further in the design section. All the fundamental parts of the circuit have now been discussed and all the parts are shown together in a circuit diagram in figure 11. Still to be discussed is the protection circuitry employed. 2.7 Short Circuit Protection If the output of the amplifier is shorted to ground in some way, while the amplifier is turned on and an input signal is present, then large currents will flow and all the output voltage will appear across the output transistors. Therefore power dissipated within the output transistors will be very high causing the output devices to fail in the order of microseconds. These transistors and possibly other devices in the circuit would then have to be replaced before the amplifier could be operated again. A simple current limiting circuit is therefore included to prevent too much current flowing (and hence power dissipation within the device) should the output be shorted to ground. The implementation for this is shown in figure 12.

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Figure 12 Short Circuit Protection Circuitry

From figure 12, R1 and R7 form a potential divider measuring the voltage across the output resistor R3. When too much current flows (short circuit condition) sufficient voltage appears across the output resistor R3 to turn transistor Q5 on via the potential divider formed by R1 and R7. This shunts current away from the base of Q1 turning off Q2 and hopefully preventing Q2 from being destroyed. The arrangement based around Q5 serves for positive signal half cycles and that around Q6 serves the negative half cycles. 2.8 DC Offset Protection This prevents damage to the speaker load should the output somehow sit at the supply voltage. Possible damage could be speaker coil burn out or permanent displacement of the speaker cone when too much current flows for too longer duration. A DC offset could occur if, for some reason, the feedback loop became open circuit. Under this case any slight DC offset at the differential amplifier would be amplified by the open loop gain (designed to be very large) thus causing the output to jump to one of the supply voltages. Protection is provided in the form of a slow blow fuse connected in series with the speaker load which will blow should too much current flow into the speaker due to a DC offset. The blown fuse disconnects the speaker from the circuit preventing damage to it. A slow blow fuse is specified so that it will not blow under normal operation when large peak currents are demanded. 2.9 Anti Thud Protection When power is applied to the circuit it takes time to stabilise. This is due to various time constants within the circuit such as that formed in the feedback loop. The output at turn on is likely to jump in voltage taking time to settle back to 0V. This causes a thud to be produced by the speaker load which is unpleasant to the ear and possibly damaging to the speaker. The speaker is there foreleft disconnected, via a relay, for a period of time until the circuit has stabilised. The implementation is shown in figure 13.

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Figure 13 Anti Thud and DC Offset Protection Circuitry

From figure 13 R2 and D1 derive 12V from the main amplifier positive supply voltage. The 12V is used to power a relay coil which when energised connects the speaker to the amplifier output. However the relay coil takes time to energise after the power is applied due to the time delay formed by R3 and C2. This produces the required turn on delay to prevent a turn on thud. F1 in figure 13 is the slow blow fuse required for DC offset protection. 3. Design Section This section of the report will discuss the method of component choice for the circuit topology described in the previous section. In this section all components are referenced to figure 11 3.1 Power Supply and Output Stage For 50W RMS sinusoidal drive into an 8Ω resistive load the peak voltage required:

Lp PRV 2= which comes from LR

VP2

= and RMSp VV 2=

where P is the RMS power and LR is the load resistance. So pV = 28.3 V Therefore in order to achieve 50W into 8Ω then the power supply rails must be at least +/- 28.3V. However, there will be some voltage drop across the output transistors and output resistors such that the full power supply voltage will not all appear across the load. This means a greater supply voltage is required. Making it too large increases power dissipation within the output devices making the circuit less efficient. A supply of +/- 30V was therefore chosen. The peak current required from the supply is given by:

L

pRPI 2=

12

So pI = 3.53 A and therefore RMSI = 1.12 A The maximum power dissipated within one of the output devices is given by:

L

CCDMAX

RVP 2

2

π= Where CCV is the supply voltage.

Giving DMAXP = 11.4 W (This relationship is derived in appendix 2) Output transistors (Q5 and Q7 in figure 11) were therefore chosen to cope with a maximum collector current of at least 3.5A, a maximum collector emitter voltage of at least 30V and a maximum internal power dissipation of at least 11.4W. Q5 was chosen as an MJ15023 and Q7 chosen as an MJ15022. Both these transistors have maximum collector currents of 8A, collector emitter voltages of 250V and power dissipations of 250W (If properly heat-sunk). These transistors therefore give large safety margins over the absolute minimum requirements calculated above. This conservative design will help make sure the circuit operates reliably. These output transistors require heatsinks to prevent the semiconductor junction from overheating. The data sheet specifies a maximum junction temperature of 200 ºC and a junction to case thermal resistance of 0.7 ºC/W. Therefore at a maximum power dissipation of 11.4 W, calculated above, the transistor case will be 8.2 ºC (0.7 x 11.4) cooler than the junction. Another condition is the maximum temperature of the heatsink. If this has the possibility of coming into contact with a person then the temperature of the heatsink should be limited to around 80 ºC to prevent injury. Therefore if the transistor case is thermally bonded to the heatsink such that a low thermal resistance is created (normally around 0.4 ºC/W if heat conductive paste is used) then the limiting condition will be the maximum heatsink temperature. The situation is modelled in figure 14.

Rjc = junction to case thermal resistance Rcs = case to heatsink thermal resistance Rsa = heatsink to ambient thermal resistance

Figure 14 Model of Amplifiers Thermal Characteristics

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Assuming the ambient temperature is 25 ºC then the thermal resistance of the heatsink (Rsa in figure 14) should be a maximum of: (80 25) / 11.7 = 4.7 ºC/W It should be noted that this is for one transistor. If both transistors are to be mounted on the same heatsink then the maximum thermal resistance should be half of this value. Two heatsinks of thermal resistance 3.3 ºC/W were therefore chosen. These were purchased predrilled to take the transistor case (TO3) and had spare holes so they could be mounted on the circuit board. The choice of the output resistors (R14 and R15 in figure 11) depends on both electrical and thermal properties. If they are too small then thermal runaway becomes more likely, if they are too large energy is wasted and the maximum voltage that can appear across the load is reduced. Others have shown [10] that in order to prevent thermal runaway:

JACCE VR θα≥ where ER is the value of an output resistor, α is the temperature coefficient of the base emitter voltage (typically 2.5mV/ºC, CCV is the supply voltage and JAθ is the junction to ambient thermal resistance.

With CCV = 30V and JAθ = 4.4 ºC/W gives a minimum ER of 0.33Ω. A value of 0.43Ω was chosen. This value was not available from the supplier (RS) therefore 0.50Ω resistors were used instead. A maximum current of 3.5A flows through the output resistors therefore the maximum power dissipated within them will be: RIP MAXMAX

2= 13.6=MAXP W 15 W, 0.5 Ω resistors were therefore used for the output resistors (R14 and R15). For the driver transistors (Q4 and Q6 in figure 11) ZTX653 and ZTX753 were chosen. These transistors have to provide enough current to drive the output transistors Q5 and Q7. The current gain of the output transistors is typically 40 and for a peak output current of 3.5A the collector current required in the driver transistors is therefore: (3.5 / 40) = 87.5mA The maximum collector to emitter voltage that can occur equals the supply voltage

CCV (30V). The ZTX753/653 are capable of 500mA collector current and 100V collector to emitter voltage and are therefore suitable for use as the driver transistors. For the resistors R13 and R12 a value of 200 Ω has been used. If this value is too large then the output transistors may turn on due to the collector leakage current of the

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driver transistors Q4 and Q6. If this value is too small the output transistors may never turn on. So for the first condition:

BELEAKAGE VRI ≤ where LEAKAGEI is the collector leakage current of Q4 and Q6, R is the resistance of R12 and R13 and BEV is the base emitter turn on voltage of the output transistors.

From data sheets [11] the maximum value of LEAKAGEI is quoted as 10µA and BEV is typically 0.6V. Therefore:

≤R 60 kΩ

For the second condition, roughly 0.7V must be developed across R12 and R13 when in normal operation in order to turn the output devices on. This is not easy to calculate but a few hundred ohms are recommended by others [7]. The value was set at 200Ω and appeared to work under simulation. 3.2 VAS Stage and Biasing The quiescent collector current for the VAS transistor (Q2 in figure 11) must be chosen so that it is always operating in the class A region. The quiescent collector current should therefore be between 1.5 to 5 times the maximum current required by the driver transistors Q4 and Q6.[8] The combined current gain for the compound pair is typically 8000 (40 x 200). So for a peak current of 3.5A in the output the peak base current into the driver transistors is 0.44mA (3.5 / 8000). Therefore choosing a VAS quiescent collector current of three times this value gives 1.3mA. The VAS quiescent collector current is produced by the current source based around Q3 in figure 11. It operates such that roughly one diode voltage drop appears across R10. This voltage is roughly constant for varying loads and a varying power supply, hence a constant current is produced. The value of R10 required is therefore:

REQUIRED

BE

IVR =10 =

0013.07.0 = 533 Ω

The nearest preferred value being 510Ω Diodes D5 and D6 are chosen as small signal 1N4148 as only a small current is required to set up a voltage reference at the base of Q3. Resistor R11 is chosen to put the diodes D5 and D6 into conduction and also so that the current flowing through R11 is much larger than the current flowing into the base of Q3. With a value of 4.3kΩ for R11, the current through D5 and D6 is:

11

)2(R

VVI BECCDIODE

−= = 4300

)4.1(30 − = 6.7mA

The base current required by Q3 is:

15

2000013.0==

FE

CB

hII = 6.5µA

The current through R11 is therefore roughly 1000 times larger than the base current of Q3. The VAS transistor (Q2) is chosen such that a full signal swing (60V) does not exceed the maximum collector emitter voltage. Also a small signal transistor with a large current gain ( FEh ) is preferable as FEh is proportional to voltage gain in the VAS stage (See appendix 1 for relationship). A ZTX 653, with a maximum collector emitter voltage of 100V and a typical FEh of 200, is therefore chosen. The dominant pole compensation capacitor (C3) is chosen as 100pF. If it is too large the slew rate of the amplifier is limited and distortion results when driving fast signals. If it is too small then it does not reduce the pole frequency sufficiently and there is danger of instability due to positive feedback around the feedback loop. Under simulation 100pF seemed to perform its task in providing stability and did not appear to cause any slewing effects at high frequency. In the bias circuit D3 and D4 are chosen as small signal types (1N4148) to match the base emitter junctions of the driver transistors Q4 and Q6. The variable resistor R9 is chosen so that the quiescent current can be varied in the output stage. Assuming that D3 and D4 exactly match the base emitter junctions of Q4 and Q6 then any voltage appearing across R9 will directly appear across both output resistors. For a maximum output quiescent current of 65mA, to put the circuit well into class AB operation, then the voltage that must be developed across R9 is: 5.02065.0)2(9 ××=×= OUTPUTQUIESCENTR RIV = 0.065V therefore R9:

0013.0065.09

9 ==VAS

R

IVR = 50Ω

where VASI is the current flowing in the VAS collector. R9 was therefore chosen as a 50Ω multi-turn preset potentiometer. A Multi-turn was chosen to ease setting the quiescent output current accurately. Capacitor C4 is present to couple the signal across the biasing arrangement such that both Q4 and Q6 see the same signal. A value of 10µF was an arbitrary choice which performed the required task under simulation. 3.3 Differential Amplifier Stage As with the design of the VAS stage the first step is to choose the quiescent current that is to flow through both halves of this circuit. If it is chosen too small then the differential stage may struggle to supply the required current to the VAS transistor

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Q2. If it is too large then the input impedance of the differential amplifier will be too low, loading the input filter down. The quiescent current required in the VAS collector is 1.3mA (Calculated above). The base current required by the VAS stage is therefore:

2000013.0==

FE

CB

hII = 6.5µA

To keep transistor Q8 operating in class A mode then the quiescent current should be between 1.5 to 5 time the above value.[8] However a quiescent current of 1.2mA was chosen to improve linearity and allow the addition of the two emitter degeneration resistors (R5 and R6 chosen as 16Ω each) [5]. Also, increasing the quiescent current through this stage helps provide the current required by the dominant pole compensation capacitor (C3) at high frequencies. Therefore high frequency linearity is improved. [12] The design of the current source for this stage follows the same lines as for the VAS stage. Diodes D1, D2 and resistor R8 provide the same voltage reference and therefore take the same values as before. 1.2mA is required in both arms so a 2.4mA current is required from the current source. Therefore,

0024.0

7.07 ==

REQUIRED

BE

IVR = 290Ω

The preferred value of 300Ω was therefore used for R7. The value of R4 was chosen so that roughly 0.7V would be dropped across it under quiescent conditions in order to put the VAS transistor (Q2) into conduction. Therefore:

0012.0

7.04 ==

QUIESCENT

BE

IVR = 583Ω

The preferred value of 560Ω was therefore used. Transistors Q8 and Q9 where chosen as small signal BC212 types. Most small signal transistor would be adequate for this job providing they had a maximum collector emitter voltage of more than around 35V. The BC212s has a maximum collector emitter voltage of 50V. 3.4 Negative Feedback Connecting the differential amplifier to the VAS stage and then to the output devices effectively produces a high power operational amplifier with a high open loop gain. (Most of this gain occurs in the VAS stage and providing this has a high collector resistance the gain can be thought of as being very large. The constant current source has a very high impedance.) The circuit can therefore be modelled as an op-amp shown in figure 15.

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Figure 15 Op - Amp Model

Assuming that the gain of the op-amp stage is infinite the circuit in figure 15 has a pole-zero transfer function given as: (This is derived in appendix 3)

0

0

011

ωω

ωω

ωω j

jk

j

kvv h

l

i

o

++

+=

Where lk is the low frequency gain. hk is the higher frequency gain. ω is the angular frequency. 0ω is the angular frequency at which the high frequency gain drops by -3dB. From the circuit in figure 15: lk = 1, i.e. the gain is reduced to unity at DC.

2

21

RRRkh

+=

CR2

01=ω

0ω is chosen such that it is less than 20Hz, other wise it will interfere with the

frequency response set by the input filter. hk should be set so that the maximum input voltage produce the maximum output voltage available. The specification states that 1Vrms should produce the maximum output which is about 20Vrms (allowing for drops across the output transistors and resistors). hk should therefore be around 20. However a design error was made here such that a 1V peak value produces the maximum output and therefore the gain was set to 28. I.e. R1 was chosen as 27kΩ (R17 in figure 11) and R2 chosen as 1kΩ (R18 in figure 11). The value of C (C5 in figure 11) used was 100µF such that the pole ( 0ω ) occurs at 1.6Hz. This is far enough below 20Hz not to affect the low frequency response of the amplifier.

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3.5 Input Filter This is where the frequency response of the amplifier is limited. The specification states -1dB points at 20Hz and 20kHz. This is achieved by a high pass filter (C1 and R2 in figure 11) in series with a low pass filter (R3 and C2). The signal source internal impedance of 1kΩ (R1 in figure 11) must be taken into account when calculating component values for the filters. Connecting a first order high pass filter in series with a first order low pass filter produces a second order band pass filter. However the poles of these two filters are sufficiently far apart for one not to affect the other. This means they can be treated as separate first order circuits simplifying the design considerably. It is also assumed that the input impedance of the differential amplifier is large so as not to affect the filters. The high pass filter requires a -1dB point at 20Hz which corresponds to a -3dB point at around 10Hz. The transfer function for the high pass filter is: (Derived in appendix 4)

( )( )211

211

21

2

1 RRCjRRCj

RRR

vv

i

o

+++

+=

ωω

Therefore if R2 is much larger than R1 (1kΩ source impedance) the gain will be close to unity above the pole frequency. The pole 0ω , occurs at:

( )2110

1RRC +

=ω and therefore, ( )2110

21

RRCf

+=

π

Another condition in the choice of R2 is that R2 + R3 ≈ R17 in figure 11. This is to keep the bases of Q8 and Q9 at the same quiescent potential to avoid any DC offset occurring. Therefore making R2 = 20kΩ, the source resistance, R1 being 1kΩ and the pole frequency 0f being 10Hz, C1 must be around 760nF. Under simulation this value was tweaked to 820nF before 1µF was actually used in the real circuit due to available components. The low pass circuit requires a -1dB point at 20kHz. The transfer function for this circuit is:

321

1RCjv

vi

o

ω+= , therefore:

( )2

3221

1

RCvv

i

o

ω+= , Rearranging this gives:

ω

112

32

−

= iov

vRC or

fv

vRC i

o

π2

112

32

−

=

19

At -1dB i

ov

v = 0.891 and so for a frequency of 20kHz 6

32 1005. −×= 4RC If R3 = 8.2kΩ to balance the DC offset then C3 = 500pF. A preferred value of 470pF was therefore chosen. 3.6 Short Circuit Protection The first stage in designing this circuit is to decide on a power dissipation limit for the output transistors. The manufacturer publishes a Safe Operating Area (SOA) curve on their datasheet [13] shown in figure 16.

Figure 16 SOA Curve for MJ15023

To avoid damage to the output devices they must be operated below the thick black line shown in figure 16. The scheme chosen was a simple current limit shown in figure 12 but implementations are possible which follow the thick black line more closely. Under a short circuit situation nearly all the output voltage appears across the output transistors, so 30V will appear across the collector emitter junction of the output transistors. From figure 16 the maximum collector current allowed at 30V is 8A. Therefore the protection circuit must limit at 8A. It is undesirable for the protection circuitry to operate under normal conditions as lots of distortion would occur. The maximum collector current under normal operation is 3.5A and so hopefully the protection circuitry will not operate under normal conditions. Referring to figure 12 the voltage dropped across an output resistor (R3) when maximum current flows is: 33 RIV MAXR = where MAXI = 8A and 3R = 0.5Ω. Therefore: =3RV 4V This 4V is then divided by resistors R1 and R7 such that 0.7V appears across R7 to turn transistor Q5 on. Therefore:

20

71

747.0RRR

+×=

Rearranging this gives: 17 212.0 RR ×= Also the series resistance of R1 and R7 needs to be much greater than the resistance of the output resistor R3 so that R1 and R7 do not alter the effective output resistance. A value of 100Ω was chosen for R1 and 24Ω was chosen for R7. This circuit is duplicated for protection on positive and negative parts of the signal cycle. Therefore R6 was 100Ω and R8, 24Ω. Transistors Q5 and Q6 were again chosen as the ZTX653 and ZTX753 as the choice here was not critical. Diodes D1 and D2 where chosen as small signal 1N4148 as only small currents will flow (the base current of the driver transistor ≈ 0.5mA). The short circuit protection circuitry with component values included is shown in figure 17. (The protection circuitry was not included in figure 11 due to limitations designed into the evaluation edition of the circuit simulation software used.)

Figure 17 Short Circuit Protection Circuitry Containing Component Values 3.7 DC Offset Protection If the output was to somehow sit at one of the supply voltages then the steady DC current flowing would be:

LOAD

CCDCOFFSET

RVI =

21

where CCV is the supply voltage (30V) and LOADR is the DC resistance of the speaker load. This is often around 6Ω for an 8Ω impedance speaker [14] (8Ω is the impedance at a given frequency, often 1kHz). Therefore:

630=DCOFFSETI = 5A

A 3.15A slow blow fuse was therefore included in series with the speaker load. Hopefully if a 5A DC current was to flow in the output then this fuse would blow before damage occurred to the speaker and also hopefully it will not blow under short current spikes of up to 3.5A in normal operation. 3.8 Anti Thud Protection Referring to figure 13, it is first necessary to decide on a value of R2 in order to put zener diode D1 into its active region. The maximum value that R2 can be is given by:

ZENERLOAD

OUTIN

IIVVR

+−=2

where INV is the supply voltage (30V), OUTV is the zener voltage (12V), LOADI is the current required by the relay coils (≈ 35mA) and ZENERI is the minimum current required by the zener diode to put it into its active region (5mA). Therefore the maximum value of R2 is:

=+−=

005.0035.01230

2R 450Ω

R2 was therefore chosen as 390Ω. The relay load is never disconnected from the zener and so the power dissipation within it is simply: =×=×= 005.012ZENEROUTZENER IVP 60mW A standard 12V 500mW zener is therefore sufficient. Capacitor C1 in figure 13 is a smoothing/decoupling capacitor and is a 100µF electrolytic type. Resistors R2 and C2 in figure 13 provide the time delay to prevent the turn on thud. R2 should be smaller than the resistance of the relay coil so that most of the 12V appears across the relay coil once a steady state has been reached. The relay has a coil resistance of around 350Ω and so R2 was chosen as 100Ω. (This may seem a little large but the relay still seems to operate). The capacitor C2 is chosen as a 220µF to give a time constant of 22mS. There will therefore be a delay in the order of a few 10s of milliseconds between power supply switch on and the connection of the load speaker to the output. This will hopefully be sufficient to prevent any turn on thud.

22

The relay chosen was a standard 12V double pole double throw type such that another channel (for stereo operation) could also be switched into circuit at the same time. Figure 18 shows the component values for the anti thud protection circuitry. Fuse F1 is the slow blow type included for DC off set protection.

Figure 18 Anti Thud and DC Offset Protection Circuitry Including Component

Values

4. Circuit Simulation The amplifier circuit (excluding the protection circuitry) was entered into a SPICE circuit simulation package called Circuit Maker that was developed by Protel Technologies. This was a student version downloaded for free from the Internet. It had a number of restrictions including a maximum number of components allowed, however it was sufficient to simulate the main parts of the amplifier. SPICE simulation is not perfect but gives an idea as to whether the designed circuit will work or not. First to be tested was the DC offset at the output. 4.2mV was measured which is good. Anything under 50mV appears to be acceptable. [15] Next a sinusoidal input signal was applied to see if the output was a larger version of the input and by the right amount. At 1V peak a 26.5V peak sinusoid was produced at the output, shown in figure 19. Therefore the voltage gain is around 26.5 as opposed to the calculated value of 28. This is possibly due to the open loop gain of the circuit not being large enough so that the operational amplifier assumption can be applied without error. Clipping occurs after the output goes above 27V peak. This corresponds to a maximum power output of 45W. This is 5W less than specified and is down to voltage drops across the output transistors and resistors. In order to get the extra 5W it would be necessary to increase the supply rail voltage. The frequency magnitude response of the circuit as measured by the circuit simulators bode plotter is shown in figure 20. X-cursor (d) in figure 20 is at -1dB from the peak value (X-cursor c). -1dB corresponds to frequencies of 19Hz and 20kHz which is very close to the expected values.

23

The phase response is shown in figure 21. A 180º phase inversion occurs at 1.4Mhz and comparing this to the magnitude response shown in figure 22 it can be seen that the gain has dropped to almost -20dB. This is well below a gain of unity and therefore the circuit is stable. (A circuit becomes unstable when positive feedback occurs. i.e. signals with a frequency high enough, to have a phase difference of 180º or greater, are amplified) Modelling speaker cable as having a capacitance of 15pF/m to ground and having a maximum cable length of 15m gives a total capacitance to ground of 900pF. With this capacitance in series with the load, a -180º phase inversion occurs at 1.22Mhz where the gain of the circuit -17dB and so the circuit is still stable. Modelling the speaker as a 6Ω resistance in series with a 0.32mH inductor (2Ω at 1kHz) gives a -180º phase shift at a gain of -11.5dB and therefore the circuit still remains stable. The simulated circuit can therefore be considered to be stable for all expected loads. Total harmonic distortion measured at an output power of 44W, measured up to 24kHz with a fundamental frequency of 1kHz was given as 0.123%. The spectrum is shown in figure 23 and is produced using the softwares fourier analysis tool. At 10W total harmonic distortion goes down to 0.032% which is well below the 0.1% set down in the specification. 5. Construction The circuit was built up on pin board with the components on one side and most of the interconnections on the reverse. The output transistors were mounted on heat sinks with insulating mica washers preventing the TO3 cases from electrifying the heat sinks. Thermally conducting paste was used to reduce the thermal resistance of the transistor case to heat sink junction. The heat sinks were mounted vertically either side of the board with the aid of two small aluminium angle brackets. Mounting the heat sink with the fins vertical helps the air to flow through the fins via convection, hence reducing the heat sink to ambient thermal resistance. Connections from the circuit board to the output transistor were kept as short as possible to prevent these radiating into the smaller signal stages of the amplifier. Also the input and output were at opposite ends of the board to prevent crosstalk and feedback effects. One major star point was used where the grounds of the small current sections connected to the grounds of the larger current sections. If large ground currents are run along the grounds of small signal sections then it is possible (due to the finite resistance of the ground conductor) that the small signal section will become corrupted by the information carried by the large signal current. The star point prevents this by connecting all ground currents at the same place before connecting to the supply.

24

25

26

27

28

29

6. Testing 6.1 DC Conditions Once the circuit had been built up power was applied and its operation was tested. A few mistakes were in made in construction which meant it did not work first time. There was a few poor solder joints, capacitors placed the wrong way around and a capacitor of the wrong value. After these faults were corrected the DC conditions were measured with a multimeter. The DC offset at the output was initially fairly large ≈ 60mV which meant the input differential amplifier was out of balance. The DC offset was reduced to -24.5mV by connecting an extra 2.2kΩ resistor in parallel with R4 in figure 11. This reduced the effective resistance at the bottom of the differential amplifier helping improve the balance. The quiescent current in the output stage was measured by measuring the voltage across one of the output resistors (e.g. R14 in figure 11). The quiescent current was 130mA with the preset potentiometer set to its minimum resistance. This was much higher than anticipated meaning that the biasing diodes (D4 and D3) had much larger voltage drops than the base emitter junctions of the driver transistors (Q4 and Q6). Either larger signal diodes should replace the small signal 1N4148 types thus providing a smaller bias voltage for the same current or only one small signal diode should be used in the bias arm. The current flowing into the differential amplifier was measured by measuring the voltage across R7 in figure 11. This was 2.8mA which was about right (2.4mA expected). 1.3mA flowed down the left hand side and 1.5mA flowed down the right hand side of the differential amplifier. This accounts for the DC offset at the output. To remove this DC offset altogether a preset potentiometer could be placed at the top of the differential amplifier replacing the emitter degeneration resistors, R5 and R6. Potential could then be manually varied either side of the differential amplifier to trim the DC offset at the output to zero. This would have to be done after the circuit had been switched on for a while because the DC offset varies as the circuit warms up. The quiescent current flowing into the collector of the VAS transistor (Q2) was measured by measuring the voltage across R10. This gave 1.24mA which is close to the 1.3mA expected. The DC voltage across the base emitter junction of Q2 was only 0.55V which seems a little low. 0.6 to 0.7 V was expected. This indicates that the VAS transistor (Q2) is only just turned on and therefore operating in a relatively non linear part of its transconductance characteristic. Either a smaller signal transistor should be used or the quiescent current into the VAS collector should be increased. 6.2 AC Conditions When an input signal was first applied the output was observed with an oscilloscope. High frequency instability was noticed with the peaks of the output signal blurring. This was rectified by including two 100µF decoupling capacitors across the supply rails.

30

With no load applied a sinusoidal signal was applied to the input with a signal generator. The frequency was fixed at 1kHz and the amplitude varied. The output voltage was measured with an oscilloscope and the results are graphed in figure 24. The voltage gain of the circuit is around 26 and this remains constant for all the input amplitudes (shown by the straight line in figure 24). At an input voltage of 2.16V peak to peak the output waveform just starts to clip at an output value of 55.7V peak to peak. The maximum power output for an undistorted sinusoidal waveform is therefore 47.6W which is only 2.3W from the 50W specified. Again it would be necessary to increase the supply voltage slightly to get the extra 2.3W but this extra power would probably not be noticed by a listener. The human ear has an exponential response to sound such that there is a law of diminishing returns as the output power is increased. The output resistance of the amplifier was measured by inputting a sinusoidal signal of frequency 1kHz and first measuring the open circuit output voltage (no load). This was 43.98V peak to peak. Connecting an 8Ω load reduced this to 43.70V peak to peak. Therefore the output resistance of the amplifier is:

=−×=−×= 87.43

898.43LOAD

ONLOAD

LOADTOPENCIRCUIOUT R

VRVR 0.05Ω

This is better than the 0.1Ω specified. The frequency response of the amplifier was measured using a spectrum analyser. This sweeps through a range of frequencies and measures the output and input signal to produce a plot of circuit gain against frequency. A plot produced by the spectrum analyser is shown in figure 25. The frequency range scanned was between 10Hz and 50kHz which was sufficient to show that the -1dB points occur at around 20Hz and 20kHz as specified. In order to check stability the phase response of the amplifier should have been measured with the spectrum analyser. The circuit would be said to be stable if the gain had dropped below unity when a phase shift of -180º had occurred. However this test was not carried out and therefore it is not possible to definitely say the circuit is stable. However no evidence was found (after the supply decoupling capacitors had been added) that the circuit was in fact unstable. There was a fairly big safety margin of -11dB when capacitive speaker cable and inductive speakers were simulated on the computer. Therefore there is a very good chance that the actual circuit will be stable for all likely loads. Total Harmonic Distortion (THD) was measured using the Fast Fourier Transform (FFT) function on an oscilloscope. This displays the fundamental frequency and a number of harmonics as peaks on the oscilloscope screen. The y axis corresponds to signal strength in dBV and the x axis as frequency. A 1kHz signal was applied with a magnitude of 18.2dBV (8.1V rms or 8.25W power output) and the harmonic amplitudes were measured up to 20kHz. Total harmonic distortion can then be calculated from:

31

32

33

100....0

24

23

22

21 ×++++=

vvvvvTHD %

where 1v is the first harmonic rms value 2v is the second harmonic rms value, etc 0v is the fundamental rms value. This gave a THD of 0.18% at 8.25W which is not too bad. However this does not meet the 0.10% set down in the specification. Strangely when this test is repeated at 30W output power the THD goes down to 0.15%. This distortion may have come from the circuit but it is also possible that some was produced in the signal generator and it is also possible that the power leads were causing distortions too. The noise performance of the amplifier was also measured using the FFT function on an oscilloscope. A 1V peak, 1kHz signal was connected to the input and the difference from the top of the output signal to the top of the noise voltage (noise floor) was measured. This gave a difference or dynamic range of 98dB which is only 2dB short of the 100dB set down in the specification. The last test to be performed was to connect a load speaker onto the output and a CD player onto the input (via a preamplifier) and listen to the sound quality. It seemed to sound good and could operate loud enough for it to be unpleasant sitting near the speaker. The low frequencies were compromised at high signal levels as the current limit on the power supply would tend to kick in. A better power supply with a higher current capacity was therefore required. However it was still very pleasing to listen to. 7. Conclusion The overall result of this project is the production of a working class AB, 45W power amplifier. During the design process the author has learnt about power amplifiers and linear circuits in general. The author used a SPICE circuit package to simulate a circuit once designed and then constructed the circuit on pin board. The author learnt to take care over the physical layout which is very important in such a circuit. The finished circuit was then tested and the author is very pleased with the result.

34

8. References [1] R.C.Tozer; Printed notes on Power Amplifiers for EEE204 [2] D.Self; Audio Power Amplifier Design Handbook; Pg 35; Newnes; 2002. [3] D.Self; Audio Power Amplifier Design Handbook; Pg 36; Newnes; 2002. [4] Horowitz & Hill; The Art of Electronics; Pg 99; Cambridge University

Press; 1989 [5] D.Self; Audio Power Amplifier Design Handbook; Pg 82; Newnes; 2002. [6] Horowitz & Hill; The Art of Electronics; Pg 243; Cambridge University

Press; 1989 [7] Horowitz & Hill; The Art of Electronics; Pg 95; Cambridge University

Press; 1989 [8] Rod Elliot; Elliot Sound Products Audio Amplifier Design Guidelines

http://sound.westhost.com/amp_design.htm [9] Horowitz & Hill; The Art of Electronics; Pg 93; Cambridge University

Press; 1989 [10] R.C.Tozer; Printed notes on Thermal stability of output stage bias [11] Data sheet for ZTX 753; Author Unknown; July 1994 [12] D.Self; Audio Power Amplifier Design Handbook; Pg 74; Newnes; 2002. [13] Data sheet for MJ15023; ON Semiconductor; March 2001 [14] R.C.Tozer; Printed notes on Generic power amplifier circuit [15] D.Self; Audio Power Amplifier Design Handbook; Pg 89; Newnes; 2002.

35

Appendices Appendix 1 Derivation of voltage gain for the VAS stage.

Simplified VAS stage Equivalent Circuit

bebi

cbo

riVRiV

=−= β

Therefore voltage gain: be

c

i

o

rR

VV β−=

Appendix 2 Derivation of maximum power dissipated in one output transistor. (Method taken from R.C. Tozers lecture notes for EEE204) Assumes sinusoidal input Power in = Power out

LDS PPP += where SP is the power delivered by the supply, DP is the power dissipated in the output devices and LP is the useful power dissipated in the load.

So, 2

2 2LP

DPCC RIPIV +=

π

Where CCV is the supply voltage.

L

PD

L

PCC

RVP

RVV

22 2

+=π

36

L

P

L

PCCD

RV

RVVP

22 2

−=π

(1)

differentiating DP w.r.t PV gives

L

P

L

CC

P

D

RV

RV

dVdP −=

π2

For DP to be a maximum P

D

dVdP = 0. Therefore,

πCC

PVV 2= for maximum power dissipation. Substituting back into (1),

L

CCDMAX

RVP 2

22π

= for both output transistors

L

CCDMAX

RVP 2

2

π= for one output transistor.

Appendix 3 Derivation of the pole-zero response of the feedback network.

Figure 15 If the op-amp is considered to have an infinite input impedance then the voltage gain for this non inverting arrangement is

2

21

zzz

vv

i

o += where 11 Rz = and CjRz ω122 +=

this gives

CjCRj

CjCRjR

vv

i

o

ωω

ωω

2

21

1

1

+

++=

37

rearranging to give: 2

21

1)(1

CRjRRCj

vv

i

o

ωω+

++= (1)

Standard form for a pole zero

+

+=

0

1

1

1

ωω

ωω

j

jk

vv

i

o (2)

So from equation (1) 1=k

)(

121

1RRC +

=ω

2

01

CR=ω

Therefore 01 ωω ≤ Equation (2) can be rewritten in the form a low pass equation added to a high pass equation.

0

1

011 ω

ωω

ω

ωω j

jk

jk

vv ll

i

o

++

+=

0

0

1

0

011 ω

ωω

ω

ωω

ωω j

jk

jk

vv

ll

i

o

++

+=

0

0

011

1

ωωω

ω

ωω j

jk

jk

vv

hli

o

++

+=

So from (1) lk = 1

2

21

1

0

RRRkh

+==ωω

2

01

CR=ω

Appendix 4 Derivation of high pass filter transfer function. Assumes that the low pass filter in series with this high pass filter does not affect the high pass filter characteristics. Referring to figure 11

38

1

21

2

1CjRR

Rvv

i

o

ω++=

( )211

21

1 RRCjRCj

vv

i

o

++=

ωω (1)

Rearranging to get (1) into a standard form gives:

( )( )211

211

21

2

1 RRCjRRCj

RRR

vv

i

o

+++

+=

ωω

With higher frequency gain = 21

2

RRR+

And pole frequency, ( )2110

1RRC +

=ω and so ( )2110

21

RRCf

+=

π