Ambit BuildGates Synthesis User Guidemrs8n/soc/SynthesisTutorials/esug.pdf · Ambit BuildGates...

Ambit BuildGates Synthesis User Guide

Product Version 4.0.8May 2001

1997-2001 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

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discontinued immediately upon written notice from Cadence.

Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformation of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customerin accordance with, a written agreement between Cadence and its customer. Except as may be explicitly setforth in such agreement, Cadence does not make, and expressly disclaims, any representations or warrantiesas to the completeness, accuracy or usefulness of the information contained in this document. Cadence doesnot warrant that use of such information will not infringe any third party rights, nor does Cadence assume anyliability for damages or costs of any kind that may result from use of such information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth inFAR52.227-14 and DFAR252.227-7013 et seq. or its successor.


Contents

Preface ............................................................................................................................ 9

About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Other Information Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Text Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10About the Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Using Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Using Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1Introduction to Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . 13

Separately Licensed Software Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Low Power Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Physically Knowledgeable Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Datapath Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AC_Shell / DC_Shell Equivalencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Invoking Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Getting Help for Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Exiting Ambit BuildGates Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Files Used in Ambit BuildGates Synthesis Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Key Bindings and Mouse Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3Using the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Main Menu Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39File Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Edit Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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View Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Commands Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Reports Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Window Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Help Menu Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

The Main Tool Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73The Browsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

The Module Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74The Variable Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Work Area Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80HDL and Tcl Editors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Constraints Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86The Schematic Viewer and Symbol Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Distributed Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93The ac_shell Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94The Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4Flow Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Typical Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Read the Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Read the Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Build a Generic Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104Set Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Optimize the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Generate Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Save Final Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5Viewing the Schematic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

How to Use the Schematic Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Mouse Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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Objects in the Schematic Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Accessing Context-Sensitive Pop-Up Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Highlighting Path Between Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Viewing Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

The Schematic Tool Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128The Module Title Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Searching for an Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Grouping Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Dissolving Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Creating a Unique Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Displaying Logic Cones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Extracting Logic Cones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Displaying Port Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139Printing a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

6Setting Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Units in Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

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7Optimizing Before Place-and-Route. . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Running do_optimize Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Top-Down Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Bottom-Up Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Deriving Constraints from Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Time Budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Preserving Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Uniquifying Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Collapsing Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Incremental Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154Applying Timing Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

8Optimizing with Logic Transforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Introduction to Transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Logic Optimization Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Optimizing Generic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Mapping and Unmapping of Generic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Constraint-Driven Optimizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Summary Listing of Transform Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9Optimizing After Place-and-Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Backannotating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

A Script Showing the Backannotation of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . 164Reading SDF Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

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Optimizing to Correct Late and Early Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

10Report Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Report Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Timing Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170Area Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Sample Area Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172Library Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173Hierarchy Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Sample Hierarchy Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Design Rule Violations Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Sample Design Rule Violations Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177VHDL Library Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Sample VHDL Library Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179End Point Slack and Path Histogram Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180Fanin and Fanout Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Sample Fanin Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182Finite State Machine Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Sample FSM Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185Customizing Report Column Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

AUsing Tcl within ac_shell and pks_shell . . . . . . . . . . . . . . . . . . . . . . 189

The Tcl Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190Tcl Variables and Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194find Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194get_names Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Abbreviating Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Searching for Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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Accessing Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Returning Unix Command Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

BQuick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

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Preface

This preface contains the following sections:

■ About This Manual on page 9

■ Other Information Sources on page 9

■ Syntax Conventions on page 10

■ About the Graphical User Interface on page 11

About This Manual

This manual describes the Ambit® BuildGates® synthesis software. BuildGates synthesis canbe run both in command line mode and in graphical user interface (GUI) mode. See GettingStarted on page 27 for an explanation on how to use both modes.

Other Information Sources

For more information about Ambit BuildGates synthesis and other related products, you canconsult the sources listed here.

■ Command Reference for Ambit BuildGates Synthesis and Cadence PKS

■ Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS

■ Test Synthesis for Ambit BuildGates Synthesis and Cadence PKS

■ HDL Modeling for Ambit BuildGates Synthesis

■ Distributed Processing of Ambit BuildGates Synthesis

■ Synthesis Place-and-Route (SP&R) Flow Guide

■ Constraint Translator for Ambit BuildGates Synthesis and Cadence PKS

Depending on the product licenses your site has purchased, you could also have thesedocuments.

■ PKS User Guide

May 2001 9 Product Version 4.0.8

Ambit BuildGates Synthesis User GuidePreface

■ Datapath Option of Ambit BuildGates Synthesis and Cadence PKS

■ Low Power Option of Ambit BuildGates Synthesis and Cadence PKS

BuildGates synthesis is often used with other Cadence® tools during various design flows.The following documents provide information about these tools and flows. Availability of thesedocuments depends on the product licenses your site has purchased.

■ Cadence Timing Library Format Reference

■ Cadence Pearl Timing Analyzer User Guide

■ Cadence General Constraint Format Reference

The following books are helpful references.

■ IEEE 1364 Verilog HDL LRM

■ TCL Reference, Tcl and the Tk Toolkit, John K. Ousterhout, Addison-WesleyPublishing Company

Syntax Conventions

This section provides the Text Command Syntax used in this document.

Text Command Syntax

The list below describes the syntax conventions used for the Ambit BuildGates synthesis textinterface commands.

Important

Command names and arguments are case sensitive. User-defined information iscase sensitive for Verilog designs and, depending on the value specified for theglobal variable hdl_vhdl_case , may be case sensitive as well.

literal Nonitalic words indicate keywords that you must enter literally.These keywords represent command or option names.

argument Words in italics indicate user-defined arguments or informationfor which you must substitute a name or a value.

| Vertical bars (OR-bars) separate possible choices for a singleargument.



[ ] Brackets denote optional arguments. When used with OR-bars,they enclose a list of choices from which you can choose one.

{ } Braces are used to indicate that a choice is required from the listof arguments separated by OR-bars. You must choose one fromthe list.

{ argument1 | argument2 | argument3 }

{ } Bold braces are used in Tcl commands to indicate that thebraces must be typed in literally.

... Three dots (...) indicate that you can repeat the previousargument. If the three dots are used with brackets (that is,[argument ]...) , you can specify zero or more arguments. Ifthe three dots are used without brackets (argument ...) , youmust specify at least one argument, but can specify more.

# The pound sign precedes comments in command files.

About the Graphical User Interface

This section describes the conventions used for the BuildGates synthesis graphical userinterface (GUI) commands and describes how to use the menus and forms in the BuildGatessynthesis software.

Using Menus

The GUI commands are located on menus at the top of the window. They can take one ofthree forms.

CommandName A command name with no dots or arrow executes immediately.

CommandName… A command name with three dots displays a form for choosingoptions.

CommandName -> A command name with a right arrow displays an additional menuwith more commands. Multiple layers of menus and commandsare presented in what are called command sequences, forexample: File – Import – LEF. In this example, you go to the Filemenu, then the Import submenu, and, finally, the LEF command.



Using Forms

… A menu button that contains only three dots provides browsingcapability. When you select the browse button, a list of choicesappears.

Ok The Ok button executes the command and closes the form.

Cancel The Cancel button cancels the command and closes the form.

Defaults The Defaults button displays default values for options on theform.

Apply The Apply button executes the command but does not close theform.

Help The Help button provides information about the command.



1Introduction to Ambit BuildGatesSynthesis

This chapter provides a description of the Ambit® BuildGates® synthesis software, includingbrief descriptions of the three software options that are offered. This chapter also provides acomparison table of dc_shell and ac_shell command equivalents.

Capable of running in both command line mode and in graphical user interface (GUI) mode,the BuildGates synthesis tool delivers dramatic performance and productivity benefits overconventional synthesis tools. The key features of the Ambit BuildGates synthesis tool aredescribed in the following paragraphs.

At the heart of the Ambit BuildGates synthesis tool is a signoff-quality, fast, full-chip timingengine that enables high-capacity and high-performance chip-level synthesis. Fast andflexible, BuildGates synthesis supports a wide variety of design styles such as multiple clocks,including both edge triggered and level sensitive with cycle stealing.

BuildGates synthesis has a high capacity database that allows synthesis of more of thedesign at once. Its fast runtime assures rapid turnaround, making chip-level synthesispractical. In addition, high-capacity enables productivity gains by eliminating the need forexcessive resources and time required for elaborate bottom-up script development.

BuildGates synthesis also offers automatic time budgeting, integration with physical designtools, VHDL and Verilog support, support of both reads and writes of netlist EDIF 2.0, Tclcommand line interface for shell level control, transforms for performing focusedoptimizations, schematic and textual report capabilities, and integrated DFT analysis andscan insertion.

Separately Licensed Software Products

Cadence® low power synthesis, Cadence physically knowledgeable synthesis (PKS), andCadence datapath synthesis option are companion products to the basic Ambit BuildGatessynthesis software and require separate licenses. For details on these products, please


Ambit BuildGates Synthesis User GuideIntroduction to Ambit BuildGates Synthesis

contact your Cadence marketing representative. If you are a licensed user, the appropriatesoftware and documentation are included in your installation package.

Low Power Synthesis

The low power module provides both power analysis and power optimization capabilities.Power analysis estimates the power consuming modules in your design at the gate-levelthrough each phase of the design cycle until you have met your power specifications. Thepower optimizer synthesizes a minimum power netlist that meets your specified timingconstraints, optimizing design power consumption at the register-transfer level (RTL).

Licensed users can refer to the Low Power Option of Ambit BuildGates Synthesis andCadence PKS for details.

Physically Knowledgeable Synthesis

Cadence physically knowledgeable synthesis (PKS) performs placement-driven timing byadding a physical model of the netlist to the timing and interconnect models that currentlyexist in the Ambit BuildGates synthesis tool. The physical model allows for timing estimationsto take place during the optimization process, virtually eliminating the need for third-partyplacement tools.

Placement information is read into PKS using a PDEF file, which includes the x,y locationof every cell. PKS uses highly accurate Steiner routes to estimate interconnect, resulting incloser correlation between the timing in BuildGates synthesis and the timing that results afterrunning a place-and-route tool.

Licensed users can refer to the PKS User Guide for details.

Datapath Synthesis

The Cadence datapath synthesis option product performs complex arithmetic operations thatmanipulate data in the RTL (in Verilog or VHDL format) to aid in the development ofsophisticated, high-performance ASICs. Arithmetic components such as adders, subtractors,multipliers, comparators, and shifters are used to define the mathematical properties of thedesign.

Licensed users can refer to the Datapath Option of Ambit BuildGates Synthesis andCadence PKS for details.



AC_Shell / DC_Shell Equivalencies

The table below shows the dc_shell commands and their ac_shell equivalents.

Table 1-1 AC_Shell and DC_Shell Command Equivalencies (Sheet 1 of 11)

dc_shell ac_shell

alias alias

all_clocks find -ports -clocks

all_connected get_info

all_designs find -module *

all_inputs find -ports -input

all_inputs_not_clock find -ports -no_clocks

all_outputs find -ports -output

allocate_budget do_time_budget

all_registers find -instance -registers

analyze read_verilog, read_vhdl

balance_buffer Not needed

balance_registers No equivalent

break break

catch (Tcl command) catch (Tcl command)

cd cd

change_link do_rebind

change_names do_change_names

characterize do_derive_context

check_design check_netlist or check_timing

check_timing check_timing

compare_design No equivalent

compare_fsm No equivalent

compile do_optimize



compile -incremental do_xform_optimize_slack

compile_fix_multiple_port_net

do_xform_fix_multiport_nets

set_global fix_multiport_nets

compile -map_effort high do_optimize -effort high

compile -only_design_rules do_xform_fix_design_rule_violations

connect_net Contact your Cadence AE for set of equivalents.

continue continue

copy_design do_copy_module

create_bus Contact your Cadence AE for set of equivalents.

create_cell Contact your Cadence AE for set of equivalents.

create_clock set_clock

create_clock clksourcelist set_clock_root

create_design Contact your Cadence AE for set of equivalents.

create_net Contact your Cadence AE for set of equivalents.

create_port Contact your Cadence AE for set of equivalents.

current_design set_top_timing_module

set_current_module

current_instance set_current_instance

define_design_lib set_vhdl_library

define_name_rules set_global dcn_{ bus | inst | module| net | port |}

derive_clocks Tcl script

derive_timing_constraints No equivalent

disconnect_net delete_object

drive_of get_cell_drive

echo puts


dc_shell ac_shell



elaborate do_build_generic

exit exit

extract Verilog source code pragmas

filter get_info

find find

find (cell, name) find -instance

find (lib_cell, name) find -cellref

find (library, name) find -techlib

find (net, name) find -net

find (pin, name) find -pin

find (port, name) find -port

for for

foreach foreach

get_attribute get_info

get_cells find -instance

get_lib_cells find -cellref

get_libs find -techlib

get_nets find -net

get_pins find -pin

get_ports find -port

get_unix_variable $env(name)

group create_hierarchy or do_extract

group_path Not needed

group_variable Not needed

help help


dc_shell ac_shell



history history

if if

include source

link do_link

do_build_generic

list list

list_designs get_names […]

list_instances get_names [find -techlib]

list_libs No equivalent

load_of get_cell_pin_load

minimize_fsm Verilog source code pragmas

propagate_constraints No equivalent

pwd pwd

quit quit

read_db read_adb

read_edif read_edif

read -f db read_adb

read -f vhdl read_vhdl

read_verilog read_verilog

do_build_generic

read_lib read_alf

read_sdf read_sdf

read_timing read_sdf

read_vhdl read_vhdl

reduce_fsm Verilog source code pragmas

regexp (Built-in Tcl command) regexp (Built-in Tcl command)


dc_shell ac_shell



remove_attribute remove_assertions

remove_bus delete_object [find -bus name]

remove_cache Not needed

remove_cell delete_object [find -cell name]

remove_clock remove_assertions

remove_constraint remove_assertions

remove_design do_remove_design

remove_input_delay remove_assertions

remove_net delete_object [find -net name]

remove_output_delay remove_assertions

remove_pads delete_object [find -instance name]

remove_port delete_object [find -port name]

remove_unconnected_ports No equivalent

remove_variable No equivalent

rename_design do_change_name

reoptimize_design do_xform_optimize_slack

replace_synthetic No equivalent

report_area report_area

report_annotated_check report_annotations

report_attribute get_info

report_bus No equivalent

report_cache Not needed

report_cell report_area -cell

report_clock report_clocks

report_compile_options No equivalent


dc_shell ac_shell



report_constraint report_timing or

report_design_rule_violations

report_delay_calculation report_cell_instance_timing

report_design No equivalent

report_fsm report_fsm

report_hierarchy report_hierarchy

report_lib report_library

report_multicycles No equivalent

report_name_rules get_global dcn_{ bus | inst | module| net | port |}

report_names No equivalent

report_net report_net

report_path_group Not needed

report_port report_ports

report_reference report_area

report_resource_estimates No equivalent

report_resources No equivalent

report_routability No equivalent

report_synlib No equivalent

report_timing report_timing

report_timing_requirements No equivalent

report_transitive_fanin report_fanin

report_transitive_fanout report_fanout

report_wire_load report_area -summary

reset_compare_design_script No equivalent

reset_design No equivalent


dc_shell ac_shell



reset_path No equivalent

set_annotated_check read_sdf

set_annotated_delay read_sdf

set_attribute set_attribute

set_balance_registers No equivalent

set_boundary_optimization set_port_property (for constant propagationonly)

set_case_analysis set_constant_for_timing

set_clock_gating_check set_global clock_gating_to_be_checked

set_clock_latency set_clock_insertion_delay

set_clock_skew set_clock_insertion_delay

set_clock_uncertainty

set_clock_skew -ideal |propagated

set_clock_propagation -ideal |propagated

set_clock_transition set_slew_time -clock clockname-pos | neg

set_clock_uncertainty set_clock_uncertainty

set_compare_design_script No equivalent

set_critical_range do_optimize -critical_ratio or

do_optimize -critical_offset

set_disable_timing set_disable_timing or

set_disable_cell_timing

set_dont_touch instance set_dont_modify [find -instinstance ]

set_dont_touch module set_dont_modify [find -modulemodule ]

set_dont_touch net set_dont_modify [ find -net net ]


dc_shell ac_shell



set_dont_touch set_cell_property dont_modify true

set_dont_touch_network set_dont_modify -network -hier

set_dont_use set_cell_property dont_utilize true

set_drive set_drive_resistance

set_driving_cell set_drive_cell

set_equal No equivalent

set_false_path set_false_path

set_fanout_load set_fanout_load

set_fix_hold do_timing_correction -fix_hold or

do_xform_fix_hold

set_flatten do_optimize -flatten on

set_fsm_encoding Verilog source code pragmas, VHDL attributesand pragmas

set_fsm_encoding_style Verilog source code pragmas, VHDL attributesand pragmas

set_fsm_minimize Verilog source code pragmas, VHDL attributesand pragmas

set_fsm_order Verilog source code pragmas, VHDL attributesand pragmas

set_fsm_preserve_state Verilog source code pragmas, VHDL attributesand pragmas

set_fsm_state_vector Verilog source code pragmas, VHDL attributesand pragmas

set_impl_priority No equivalent

set_implementation set_global acl_default_arch

set_input_delay set_input_delay

set_input_transition set_slew_time

set_load set_port_capacitance


dc_shell ac_shell



set_load -pin_load set_port_capacitance

set_load -fanout_number set_num_external_sinks

set_local_link_library Not needed

set_logic_one set_logic1

set_logic_zero set_logic0

set_map_only No equivalent

set_max_area No equivalent

set_max_capacitance set_global capacitance_limit

set_port_capacitance_limit

set_max_delay set_path_delay -late

set_max_fanout set_global fanout_load_limit

set_fanout_load_limit

set_max_time_borrow No equivalent

set_max_transition set_global slew_time_limit

set_slew_time_limit

set_min_capacitance No equivalent

set_min_delay set_path_delay -early

set_min_fanout No equivalent

set_min_porosity No equivalent

set_min_transition No equivalent

set_minimize_tree_delay No equivalent

set_model_drive Not needed

set_model_load Not needed

set_model_map_effort Not needed

set_model_scale Not needed

set_multicycle_path N -setup set_cycle_addition N-1 -late


dc_shell ac_shell



set_multicycle_path N -hold set_cycle_addition N -early

set_operating_conditions set_operating_conditions

set_opposite No equivalent

set_output_delay set_external_delay

set_port_fanout_number set_num_external_sinks

set_prefer Not needed

set_propagated_clock set_clock_propagation propagated

set_register_type Not needed

set_resistance set_wire_resistance

set_resource_allocation No equivalent

set_resource_implementation No equivalent

set_share_cse No equivalent

set_structure no do_xform_propagate_constants

do_xform_map -hierarchical

do_optimize

set_timing_disable_internal_inout_cell_paths

set_global bidi_io_arc

set_timing_ranges Not needed

set_true_delay_case_analysis No equivalent

set_unconnected set_unconnected

set_ungroup do_dissolve_hierarchy

set_unix_variable No equivalent

set_wire_load set_wire_load

set_wire_load_mode set_wire_load_mode

set_wire_load_model set_wire_load wireload

set_wire_load -port_list set_port_wire_load


dc_shell ac_shell



set_wire_load_selection_

group

set_wire_load_selection_table

simplify_constants do_xform_propagate_constants

sh exec

syntax_check No equivalent

target_library = set_global target_technology techlib

translate No equivalent

unalias unalias

ungroup do_dissolve_hierarchy

uniquify do_uniquely_instantiate

update_lib read_library_update

update_script Not needed

update_timing Not needed

while while

write -f verilog write_verilog

write -f db write_adb

write_compare_design_script No equivalent

write_lib libcompile libname.lib libname.alf(Unix command)

write_script write_assertions

write_constraints write_constraints

write_timing write_sdf

write -f vhdl write_vhdl


dc_shell ac_shell



2Getting Started

Invoking Ambit BuildGates Synthesis

The Ambit BuildGates synthesis software is installed in the following directory:

install_dir/ambit/BuildGates/version/bin/

where install_dir is the directory in which Ambit BuildGates synthesis software islocally installed and version is the software release version.

Use the full path when invoking Ambit BuildGates synthesis software, either via an alias or byadding the above directory to your shell path variable. To invoke the command line version,type the following at the Unix prompt and press Return.

install_dir/ambit/BuildGates/version/bin/ac_shell

To invoke the GUI version, type the following at the Unix prompt and press Return.

install_dir/ambit/BuildGates/version/bin/ac_shell -gui

The main screen is displayed and the default (or user-specified default) options are loaded.The main screen is explained fully in Using the GUI on page 37. By default, the onlinedocumentation delivery help is enabled whenever ac_shell is invoked with the -gui option;for more detail, refer to the -cdsdocd option in Table 2-1 below.

The command line options for invoking the Ambit BuildGates synthesis software are listed inTable 2-1 and described in more detail in the Command Reference for Ambit BuildGatesSynthesis and Cadence PKS, ac_shell command. Unless otherwise specified, the optionsare valid for both command line and GUI mode. Multiple options can be used in a singlecommand.

Table 2-1 Ambit BuildGates Synthesis Command Line Options

Option Description

-64 Start ac_shell in a 64 bit session. Default is 32 bit.


Ambit BuildGates Synthesis User GuideGetting Started

-cdsdocd {on | off} Enable or disable the browser-based documentationdelivery system for ac_shell help . When set to on ,the full documentation set is available from the Helpbutton in the GUI. When set to off , only the syntax isdisplayed at the command line.

When ac_shell is invoked with the -gui option, thedefault is on such that the online, browser-baseddocumentation is enabled.

When ac_shell is invoked without the -gui option,the default is off and only syntax help is available atthe command-line.

-cmdfile filename.cmd Record in a file, all executed commands in thesession. The default file name is ac_shell.cmd .

-colormap filename Run Ambit BuildGates synthesis software using thespecified file. Valid only in GUI mode.

-continue Do not exit after an error in Tcl script file.

-datapath Run the Ambit BuildGates synthesis application withthe Datapath option. A separate license must bepurchased for the Datapath option.

-display machine_name:0 Set the configuration to display Ambit BuildGatessynthesis software to the specified machine. Validonly in GUI mode.

[-f] filename.tcl Run Ambit BuildGates synthesis software using thespecified Tcl file. You can specify the filename.tclwithout typing the optional -f .

-fullscreen Use the entire screen to display the application. Validonly in GUI mode.

Table 2-1 Ambit BuildGates Synthesis Command Line Options, continued

Option Description



-geometry width Xheight xoff yoff

Set the initial size and position of the GUI main screenwindow. Where width and height are in pixels.And xoff and yoff are the number of pixels fromthe corner; a negative value is measured from thebottom or right corners, and a positive value ismeasured from the top or left corners. No spaces areallowed between the values.

For example: -geometry 800x400+10-30 meanscreate a window 800 by 400 pixels with its left edgeoffset 10 pixels from the left edge of the screen and itsbottom edge offset 30 pixels from the bottom of thescreen

Valid only in GUI mode.

-gui Run Ambit BuildGates synthesis software using theGUI interface.

-help Print the ac_shell option help text. Does not run thesoftware.

-large Increase the data limit to approximately 3.7 GB,depending on the platform and configuration.

-limit Print the current datasize limit and memory allocationlimit for the machine on which the software will run.Does not run the software.

-logfile filename.log Record in a file, all executed commands andac_shell console messages in the session. Thedefault file name is ac_shell.log .

-no_init Disable sourcing of ~/.ambit/.acshrc and$ambit_path/.acshrc .

-no_pks Run Ambit BuildGates synthesis using a standardlicense; if this fails, run with PKS license. Only valid ifa separate license has been purchased for PKS

-no_pks_1st Run Ambit BuildGates synthesis software using astandard license. Only valid if a separate license hasbeen purchased for PKS.


Option Description



-pks Run the Ambit BuildGates synthesis application withthe physically knowledgeable synthesis option. Aseparate license must be purchased for PKS.

-power Run the Ambit BuildGates synthesis application withthe low power option. A separate license must bepurchased for the low power option.

-queue Wait for a license if none are available.

-set variable= value Initialize a Tcl variable to the specified value.

-version Print the software version. Does not run the software.

-which Display on the command line or console the full pathname of the Ambit BuildGates synthesis executable.


Option Description



Getting Help for Ambit BuildGates Synthesis

Help is available in two different modes: command-line syntax help and online,browser-based documentation delivery. By default, the command-line syntax help is availablein both command-line and GUI mode.

The browser-based help is available only when ac_shell is invoked with the -gui option.This online help provides the full Ambit BuildGates synthesis documentation set and isaccessed via the Help button on main menu line in the GUI, as shown in Figure 3-1 onpage 37. The functions of the Help button are defined in Table 3-25 on page 71. You candisable the browser-based help with the the -cdsdocd option, as defined in Table 2-1.

To use the command-line syntax help, type the following on the ac_shell console line:

ac_shell[1]> help command_name

If you are uncertain as to the name of the command you are seeking, enter a partial commandname. For example, the following will display applicable commands.

ac_shell[2]> help do_opt

Outputs:

Info: Applicable commands are:

do_optimize

do_xform_tcorr_eco

do_xform_timing_correction

ac_shell[3]>



Exiting Ambit BuildGates Synthesis

To quit the command line version of Ambit BuildGates synthesis software, type exit at theac_shell prompt and press Return.

ac_shell[n]>exit

To quit the GUI version of Ambit BuildGates synthesis software, do one of the following:

■ Select Main Menu – File – Exit; click Ok when the exit confirmation dialog is displayed.

■ Press the Control-x key sequence; click Ok when the exit confirmation dialog isdisplayed.

■ In the ac_shell console, type exit and press Return when the exit confirmationdialog is displayed.

■ In the ac_shell console, type exit 0 and press Return to exit without invoking aconfirmation dialog.



Files Used in Ambit BuildGates Synthesis Software

The default file extensions used in Ambit BuildGates synthesis software are shown in thetable below.

Key Bindings and Mouse Operations

Table 2-3 lists the key sequences and mouse operations that can be used in the HDL/Tcleditors and ac_shell console. The Page_Up, Page_Down, Prior, and Next keys refer tothe keys to the left of the numeric keypad; the PgUp and PgDn keys on the numeric keypaddo not operate in the editors or ac_shell console.

Table 2-2 Default File Extensions

File Name Extensions Description

.vhd,.vhdl VHDL

.v, .vh, .h, .vpp Verilog

.txt text files

.alf Ambit library format (technology library)

.tcl Tcl source files

.html HTML files for on-line documentation

.adb Ambit database files

tcl_menu.cmds User-created commands on the Tcl menu

ambit.state Stores state information, user preferences, windowpositions, and so on.

Table 2-3 Key Sequences and Mouse Operations

Key/MouseDescription

Editor Console

Left Arrow, Control-b Move back one character.

Right Arrow, Control-f Move forward one character.

Up Arrow, Control-p Move insertion cursor up oneline.

Display previous history event.



Down Arrow, Control-n Move insertion cursor downone line.

Display next history event.

Prior, Page_Up Scroll up one page.

Next, Page_Down Scroll down one page.

Home, Control-a Move insertion cursor to the beginning of the line.

End, Control-e Move the insertion cursor to the end of the line

Tab Standard tab function. Command completion (on firstword) or file completion (onany other word).

Control-Tab No function. File completion.

Shift-Tab No function. Command completion.

Control-i Insert tab.

Return Insert a carriage return (blankline).

Issue a command.

Delete Delete highlighted character(s) or delete character in front ofthe insertion cursor.

BackSpace, Control-h Delete highlighted character(s) or delete character to the leftof the insertion cursor.

Control-d Delete the character to the right of the insertion cursor.

Control-k Delete from the insertion cursor to the end of the line.

Control-l No function. Clear console buffer, withoutlosing current command lineinput.

Control-m Toggle between the standard split-screen and thewhole-screen display to minimize or maximize the window inwhich the cursor resides.

Control-o Open a new file. Open a new line in the input.

Control-t Reverse the order of the characters to the right and to the leftof the insertion cursor.

Table 2-3 Key Sequences and Mouse Operations, continued


Editor Console



Control-u No function. Clear the command line.

Meta-d Delete the word to the right of the insertion cursor.

Meta-BackSpace Delete the word to the left of the insertion cursor

Click middle mouse button,Insert

Paste the highlighted text where the cursor is located.

Copy, Control-c Copy functions as in console.Control-c: no function.

Copy the highlighted text tothe clipboard.

Cut, Control-x Cut functions as in consoleand Control-x exits AmbitBuildGates synthesissoftware.

Copy the highlighted text tothe clipboard and delete thetext.

Paste, Control-v Paste functions as in console.Control-v: no function.

Paste the contents of theclipboard onto the commandline.

Table 2-3 Key Sequences and Mouse Operations, continued


Editor Console



3Using the GUI

This chapter describes the principle screens, windows, and menus of the Ambit BuildGatessynthesis graphical user interface (GUI). The main screen is the first screen you see whenyou start the tool in the GUI mode (refer to Invoking Ambit BuildGates Synthesis on page 27for startup options). The functions of main screen are called out in Figure 3-1 anddiagrammed in Figure 3-2.

Figure 3-1 Ambit BuildGates Synthesis Main Screen

Tool Bar

Browsers

console

Status bar

Work Area

ac_shell

Tools

Work Area

Main Menu

Updatemode

Main


Ambit BuildGates Synthesis User GuideUsing the GUI

Important

PKS and the low power option are additions to the BuildGates synthesis product. Ifyou have the licenses for these products, the tabs are displayed on the work areatool bar and the functionality is available in your application. Power and PKS aredocumented in the Low Power Option of Ambit BuildGates Synthesis andCadence PKS and PKS User Guide, respectively.

Figure 3-2 Main Screen Function Flow

The main menu, browsers, and work area tools functions contain options and commands thathave ac_shell command line equivilalents. For a cross-reference between thesecommands and ac_shell command line commands, refer to Appendix B, “QuickReference”.

Important

This chapter is intended as a navigational tool for BuildGates synthesis, not acomplete reference guide; menu options are listed but not defined in detail. Refer tothe Command Reference for Ambit BuildGates Synthesis and Cadence PKSfor details on each command and its options.

Work Area

Main Menu

Tool Bar

Browsers

UpdateMode

Status Bar

Main Screen

Toolsac_shellConsole

Main



Main Menu Functions

The main menu functions are diagrammed below.

Each of these functions has a menu associated with it and is explained in the followingsections.

For a cross-reference between the main menu commands and ac_shell command linecommands, refer to Appendix B, “Quick Reference”.

Reports

File

Edit

View

Window

Help

Main Menu

Commands

Main Screen



File Menu Options

The file menu functions are diagrammed below and Table 3-1 defines the options.

Table 3-1 File Menu Options

Option Definition

New Clear the current database information so that a new designdatabase can be loaded. After selecting New, use View–Opento specify the new database file.

Open Open a database file and load the design data for synthesis.Figure 3-3 provides a sample Open File dialog box. (Samefunction as the Open icon on the Tool Bar; see “The Main ToolBar” on page 73.)

Specify the type of file with the buttons on the right, and specifythe file location in the dialog box on the left.

Save Save the database to an ADB, Verilog, or VHDL file. (Samefunction as the Save icon on the Tool Bar; see “The Main ToolBar” on page 73.)

Save Preferences Save the preferences changed on the General Preferences andSchematic Preferences option windows; see “GeneralPreferences Options” on page 45 and “Schematic PreferencesOptions” on page 52, respectively.

Save

New

Open

Save

Printer

Exit

Main Menu

Save

Main Screen

Preferences

Console Log

Setup

File



Figure 3-3 Sample Open Database File Screen

Save Console Log Save to a file the contents of the ac_shell console.

Printer Setup Enter the printer command.

The default printer is defined by the Unix printer environmentvariable.

Exit Close the BuildGates synthesis application.

Table 3-1 File Menu Options, continued

Option Definition



Edit Menu Options

Figure 3-4 diagrams the edit menu functions and Table 3-2 defines the options.

Figure 3-4 Edit Menu Function Flow

Table 3-2 Edit Menu Options

Option Definition

Cut Cut and copy to the clipboard the text highlighted on the ac_shellconsole. (Same function as the Cut icon on the Tool Bar; see “TheMain Tool Bar” on page 73.)

Copy Copy to the clipboard the text highlighted on the ac_shell console.(Same function as the Copy icon on the Tool Bar; see “The Main ToolBar” on page 73.)

Paste Paste the text stored in the clipboard into the ac_shell console.(Same function as the Paste icon on the Tool Bar; see “The Main ToolBar” on page 73.)

Clear Clear the content of the ac_shell console. (Same function as theClear icon on the Tool Bar; see “The Main Tool Bar” on page 73.)

User Command Define a command and add it as an option to an existing menu.Figure 3-5 provides a sample User Command window.

■ Enter the menu name to which the command is added.

■ Enter the command name (label) to be displayed on the menu.

■ Enter the command syntax.

Cut

Main Menu

Main Screen

Copy PasteUser

CommandClear

Edit



Figure 3-5 User Command Window



View Menu Options

Figure 3-6 diagrams the view menu functions and Table 3-3 defines the options.

Figure 3-6 View Menu Function Flow

Table 3-3 View Menu Options

Option Definition

Toolbar Hide Click the box to toggle between showing and hiding the toolbar.

Refresh View Redisplay the window/view displayed on the monitor screen.

GeneralPreferences

Specify the GUI display general preferences. These options aredefined in “General Preferences Options” on page 45.

SchematicPreferences

Specify the schematic viewer preferences. These options are definedin “Schematic Preferences Options” on page 52.

ConsoleMessageMonitor

Display a dialog box to monitor the error and warning messages thatare printed in the ac_shell console. This monitor provides a wayto view and save messages from a centralized window rather thanfrom the multi-purpose console. The vBGates(cmm_ids) filtervariable must be set in order to display and filter. Any or all of thefollowing display options can be enabled:

■ All errors

■ All warnings

■ Filter list

■ Time stamp

Toolbar Hide

Main Menu

Main Screen

View

Refresh ViewSchematic

PreferencesGeneral

PreferencesConsole

Msg Monitor



General Preferences Options

Figure 3-7 diagrams the general preferences menu options and the following sections definethe options. Use the Save Preferences option defined in Table 3-1 to save changes to thepreferences before leaving the session. To see the effects of the preference changes to themodule browser or schematic viewer, you must refresh the screen using View–RefreshView.

Figure 3-7 General Preferences Function Flow

General Preferences:General Options

Table 3-4 defines the General Preferences:General options.

Fonts Distributed

Main Menu

Main Screen

View

Files

Colors

Browser

General Preferences

General



Table 3-4 General Preferences:General Options

Option Description

ConsoleWindow

■ To set the position of the ac_shell console window, choose anyone of the following:

❑ Console on top

❑ Console on bottom

❑ Hide Console

❑ Hide Work area

■ Wrap lines – Click to enable line-wrap in the report tables. Wrapwidth is set to the total number of characters that can fit on oneconsole line. If not enabled, the width is 512 characters.

BrowserWindow

To set the position of the browser window, choose any one of thefollowing:

■ Browser on left

■ Browser on right

■ Hide browser

■ Hide editor



General Preferences:Files Options

Table 3-5 defines the General Preferences:Files options.

General Options ■ Echo menu command – display on the ac_shell command lineany command executed by a menu command.

■ Sticky tooltip – the icon label persists while the mouse is positionedover the icon.

■ Save ADB hierarchy – save the hierarchy specified by the designdatabase.

■ Confirm file overwrite – display a confirmation dialog beforeoverwriting a file.

■ Save geometry – save GUI window geometry. The GUI windowsize and preferences configuration are saved and displayed uponstartup of next session.

■ Backing store – enable the X Windows backing store feature, whichstores a copy of the image in a buffer and uses that buffer to refreshthe image if it gets obscured.

■ Focus follows mouse – make active the window that contains themouse. If disable this feature, the implementation will not takeeffect until the next session startup.

Table 3-5 General Preferences:Files Options

Option Description

File Extensions Enter the default extension for the files to be listed in the form of*.extension

Default Directory Enter the full path for desired default ALF directory.

Table 3-4 General Preferences:General Options, continued

Option Description



General Preferences:Colors Options

Figure 3-8 shows the colors options screen and Table 3-6 defines the GeneralPreferences:Colors options. Color preferences are stored in the file ~/.ambit/ambit.state .

Figure 3-8 General Preferences:Colors Options Screen

Table 3-6 General Preferences:Colors Options

Option Description

Color Items For each item on the list, a color can be specified. Double-click on theitem to highlight it. Then adjust the three color selection bars bydragging the index markers on the bars. Click Apply to implement thecolor selection.

Color Selection Each color selection bar has a range from zero to 255. Click the indexmarker on a bar and drag the marker to the desired color and number.The rectangular box below the three bars displays the color indicatedby the selected index.



General Preferences:Fonts Options

Table 3-7 defines the General Preferences:Fonts options. Font preferences are stored in thefile ~/.ambit/ambit.state .

Table 3-7 General Preferences:Fonts Options

Option Description

Font Items For each item on the list, a font can be specified. Double-click on theitem to highlight it. Then specify the font selection parameters, definedbelow. Click Apply to implement the font selection.

Font Selection For each item on the Font Items list, a font type, size, and weight canbe specified.

Click on the top Font Selection tab to display the list of available fonttypes; highlight the desired type. Select either normal or bold weight.Click on the bottom Font Selection tab to display the list of availablefont sizes; highlight the desired size. The rectangle at the bottom of theFont Selection box will display the word “sample” in the selected type,weight, and size.

Click Apply to implement the font selection.



General Preferences:Browser Options

Table 3-8 defines the General Preferences:Browser options.

Table 3-8 General Preferences:Browser Options

Option Description

Browser Mode If View–General Preferences–Browser–Browser Options–NoAuto Open is enabled, these browser mode settings are ignored.

■ To set the default modes used by the browser, choose one of thefollowing.

❑ Auto browser update – automatically updates the browsermodule list when a change is made to the design hierarchy.

❑ Manual browser update – does not automatically update thebrowser module list when a change is made to the designhierarchy. To rebuild the module list, you must use: ModuleBrowser–Rebuild Tree.

■ To set the default modes used by the HDL editor, choose one of thefollowing:

❑ Main HDL window – always open the HDL in the main editorwindow.

❑ New HDL window – always open the HDL in a new editorwindow.

■ To set the default modes used by the schematic viewer, chooseone of the following:

❑ Main schematic window – always open the schematic in themain schematic window.

❑ New schematic window – always open the schematic in a newschematic window.



Browser Options ■ To set the default browser opening option, choose any one of thefollowing:

❑ No auto open – When an entry on the module browser isdouble-clicked, neither the HDL editor or the schematic viewerwill open. If this option is enabled, the View–GeneralPreferences–Browser–Browser Mode settings areignored.

❑ Auto HDL open – double-clicking on a module browser entrywill open the corresponding code in the HDL editor.

❑ Auto schematic open – double-clicking on a module browserentry will open the corresponding schematic in the schematicviewer.

■ Show module name – display the module name in each browserentry.

■ Module depth – either use the up and down spinner arrows to pickthe current display depth or type in the depth. A plus sign to the leftof the module name indicates there are additional levels that arenot displayed; a minus sign indicates there are no more levels todisplay.Default is 3 levels of display.

Table 3-8 General Preferences:Browser Options, continued

Option Description



General Preferences:Distributed Options

Figure 3-9 shows the General Preferences:Distributed screen. All distributed processingfunctions are documented in the Distributed Processing of Ambit BuildGates Synthesis.

Figure 3-9 General Preferences:Distributed Screen

Schematic Preferences Options

Figure 3-10 diagrams the schematic preferences menu functions and the following sectionsdefine the options. Use the Save Preferences option defined in Table 3-1 to save changes tothe preferences before leaving the session. To see the effects of the preference changes, youmust refresh the screen using View–Refresh View.



Refer to Viewing the Schematic Design on page 115 for details on the use of the viewer anddetails on tasks.

Figure 3-10 Schematic Preferences Function Flow

Schematic Preferences:General Options

Table 3-9 defines the Schematic Preferences:General options.

Table 3-9 Schematic Preferences:General Options

Option Description

Display Modes Click any or none of the following options to enable.

■ Display scan chain

■ Display cell name (enabled by default)

■ Bus mode (enabled by default)

Cursor Query Click any one option to enable.

■ Status bar mode – when the cursor is positioned on an object,display its name on the status bar (default)

■ Balloon mode – when the cursor is on an object, display its namein a balloon window next to the object

■ Off – disable both status bar and balloon mode

General Highlighting Printing

Main Menu

Main Screen

View

Paging

Schematic Preferences



Schematic Preferences:Highlighting Options

Table 3-10 defines the Schematic Preferences:Highlighting options.

Symbol Libraries Enter the default generic symbol library and technology symbol library.If either the read_symbol or read_symbol_update command isentered on the console to specify a symbol library, these default pathsare ignored.

■ Default generic symbol library – enter the path of the genericlibrary.

■ Default technology symbol library – enter the path of thetechnology library. For additional information, refer to TheSchematic Viewer and Symbol Files on page 90.

Table 3-10 Schematic Preferences:Highlighting Options

Option Description

Coloring Modes ■ Click any or none of the following options to enable color-highlighting choices. All three are enabled by default.

❑ Gray mode

❑ Multiple highlights

❑ Stop at sequential element

■ Click either option to specify highlighting based on module level orpath. Colors are set in View–General Preferences–Colors–Color Items.

❑ Color by level (default)

❑ Color by path

■ Stop at level – specify the highlighting level at which to stop. range:0 to 500, default: 20

Table 3-9 Schematic Preferences:General Options, continued

Option Description



Path Properties ■ Click any or none of the following options to enable labeling on thehighlighted path.

❑ Level number – label the level with “L = ”

❑ Slack – label the slack time path with “S = ”

❑ Arrival – label the arrival time path with “A = ”

❑ Required – label the required time path with “R = ”

❑ Width – specify the decimal place accuracy of the times.range: 0 to 20, default: 2

Cone Properties ■ Click any or none of the following options to enable labeling on thehighlighted cone path.

❑ Level number – label the level with “L = ”

❑ Slack – label the slack time path with “S = ”

❑ Arrival – label the arrival time path with “A = ”

❑ Required – label the required time path with “R = ”

■ Width – specify the decimal place accuracy of the times. range: 0to 20, default: 2

Table 3-10 Schematic Preferences:Highlighting Options, continued

Option Description



Schematic Preferences:Paging Options

Table 3-11 defines the Schematic Preferences:Paging options.

Table 3-11 Schematic Preferences:Paging Options

Option Description

Page Size Click the option to specify page size for displaying the schematic onthe monitor. Default size is “C.” The size options are: None, A, B, C, D,A1, A2, A3, A4.

If “None” is selected, the schematic is placed on a single page and thepage column on the module title bar will contain a 1. If an option otherthan “None” is selected and the schematic fits on more than one pageof the selected size, then the page column on the module title bar willcontain “unspl” (unsplit) to indicate additional pages.

The pages are autogenerated whenever you double-click on anoffpage connector that leads to another page.

Time Limit Click any one of the following options to specify the time limit to waitbefore abandoning the attempt to generate the specified page size anddisplay on the monitor a lower-resolution schematic. If generation ofthe schematic takes longer than the specified time limit, generation willstop, a warning message is displayed on the status bar, and a partialschematic is displayed.

■ Small – 20 seconds

■ Medium – 40 seconds (default)

■ Large – 60 seconds

Fit Page Click one of the following options to enable.

■ Yes – do fit to page

■ No – do not fit to page (default)



Schematic Preferences:Printing Options

Table 3-12 defines the Schematic Preferences:Printing Options.

Table 3-12 Schematic Preferences:Printing Options

Option Description

Page Size Click the option to specify page size for printing the schematic. Defaultsize is “A.” The size options are: A, B, C, D, A1, A2, A3, A4.

Job size Click one of the following options to specify which schematic pages toprint.

■ Current page (default)

■ All pages

Coloring Click one of the following options to specify the color properties of theprinting of the schematic.

■ Monochrome (default)

■ Color

■ Inverted color – background color is inverted (typically used whenbackground is black)

Scaling Click one of the following options to specify the view to print to a file orto the printer.

■ Full page (default)

■ Current view

Orientation Click one of the following options to specify printing orientation of theschematic.

■ Auto (default) – optimal orientation is determined and used.

■ Landscape

■ Portrait



Commands Menu Options

The commands menu functions are diagrammed below and Table 3-13 defines the options.

Table 3-13 Commands Menu Options

Option Definition

Set OperatingParameters

Specify the voltage, process, and temperature constraints of thedesign.

Voltage – range: 0 to 10, default: 5

Process – for multi-process library, specify the desired process.range: 0 to 10, default: 1

Temperature – specify in Fahrenheit. range: 0o to 200o, default: 25o

Set TargetTechnology

Specify the target technology as either:

■ ambit_xatl

■ atl

Load DCL Rules Load the DCL constraints. For more information refer to Read theLibraries in this book, and Timing Analysis for Ambit BuildGatesSynthesis and Cadence PKS “Using Timing Libraries” chapter.

Unload DCL Rules Unload the DCL constraints.

Main Menu

Main Screen

Set OperatingOptimize

Set Target

Load

Build

Parameters

Technology

DCL Rules

UnloadDCL Rules

CheckTiming

Generic

Commands

CheckNetlist

CheckTest Rules



Check Netlist Checks structural connectivity of the netlist, including: recursively-defined modules, combinational feedback, undriven nets and pins,multiply-driven nets and pins, and undriven ports. Applies to genericand mapped modules.

Check Timing Performs a variety of consistency and completeness checks on thedesign’s timing constraints, including: arrival time and required time(external delay) for each clock in a multiple clock system and clockversus data connectivity such as gated clock analysis. Typicallyused after applying all constraints but before optimizing or reportgenerating.

Applies to generic and mapped modules.

Check Test Rules Checks for DFT rule violations, such as gated clocks, derivedclocks, and uncontrollable asynchronous signals such as resets.This command operates at the level of the top-DFT module,regardless of the current module.

Build Generic Build the generic netlist.

Click any or none of the following options to set the parameters usedin the generic build.

■ Group all processes – create new level of hierarchy based onlogic of all processes.

■ Group named processes – create new level of hierarchy basedon logic of named processes.

■ Group all subprocesses – create new level of hierarchy based onlogic of all subprocesses.

■ Extract FSM – extract FSM for registers marked with state vectordirective.

Table 3-13 Commands Menu Options, continued

Option Definition



Optimize ■ To set the logic optimization effort level, choose any one of thefollowing.

❑ Low – quickly performs simple mapping steps to meet basicrequirements.

❑ Medium (default) – searches for alternate mappings andstructures to meet all constraints.

❑ High – performs detailed algorithms for top optimization.■ Set the flatten mode, choose any one of the following.

❑ On – flatten the logic equations into a sum of products formbefore applying optimization.

❑ Auto – perform limited, non-time-consuming flatteningoperations.

❑ Off (default)

■ Set the priority as one of the following.

❑ Area

❑ Time (default)■ Click any or none of the following options to use during

optimization.

❑ No partition

❑ No design rules

❑ No area reclaim

❑ Minimize area

❑ Time budget

❑ Incremental

❑ Force

❑ Checkpoint

■ Specify scan file name.

Table 3-13 Commands Menu Options, continued

Option Definition



Reports Menu Options

Table 3-14 defines the operations of the icons displayed in the upper right corner of eachreport screen. For additional detail and sample reports, refer to the chapter ReportGeneration on page 169.

Figure 3-11 diagrams the reports menu functions and the following sections define theoptions.

Figure 3-11 Reports Menu Function Flow

Timing Report

The timing report provides information concerning the various paths in the design. Table 3-15defines the timing report options. Timing reports are covered in detail in the Timing Analysis

Table 3-14 Report Icons

Icon Option Description

Generate the report and display it in the report window.

Save the report to a file.

Print the report.

Close the report window.

Main Menu

Main Screen

Library

End Point

Design

Timing

Area

Hierarchy Rules

VHDLLibrary

Histogram

PathHistogram

Reports



for Ambit BuildGates Synthesis and Cadence PKS, Generating and UnderstandingTiming Reports chapter.

Table 3-15 Timing Report Options

Option Description

all This option enables the following timing report options.

■ Late mode hold/setup

■ Rise transition

■ Fall transition

■ Summary of both rise and fall transitions

■ Worst path to each endpoint

Mode Click either option to enable.

■ Early

■ Late (default)

Transition Click any or none of the following options to enable.

■ Rise transition

■ Fall transition

■ Summary (default)

Path Click either option to enable.

■ Max paths

■ Worst paths (default)

Number of Paths Specify number of paths on which to report. range: 0 to 999,999,999default: 1

From Pins Specify the starting pin in the path.

Through Pins Specify the through pins in the path.

To Pins Specify the ending pins in the path.



Area Report

The area report generates a report on the area of the netlist. Table 3-16 defines the areareport options.

Library Report

The library report generates a report concerning the technology library used in the design.Table 3-17 defines the library report options.

Hierarchy Report

The hierarchy report generates a report on the structural hierarchy as it exists at variousstages of the synthesis process. Table 3-18 defines the hierarchy report option.

Table 3-16 Area Report Options

Option Description

Cells Report on cell area.

Summary Provide summary report.

Hierarchical Report on structural hierarchy as it exists at various stages in thesynthesis process.

Table 3-17 Library Report Options

Option Description

Cells Report information about all cells in the library.

Wireload model Report information on all wireload models in the library.

Operatingconditions

Report information on all operating conditions in the library.



Design Rules Report

The design rules report generates a report on design rule violations. Table 3-19 defines thedesign rules options.

VHDL Library Report

The VHDL library report generates a report on the mappings between all defined VHDLlibraries and the directories to which they are mapped. Table 3-20 defines the VHDL libraryoption.

Table 3-18 Hierarchy Report Option

Option Description

Instances Report the instance name of the module instantiation in the output.

Table 3-19 Design Rules Report Options

Option Description

Verbose Report all design rules for every net and port in the design even ifviolations do not exist.

Hierarchy Report the violations for the hierarchal ports.

Ignore clock Do not report the clock net violations.

Current moduleonly

Report only the violations in the current module.

Table 3-20 VHDL Library Report Option

Option Description

Verbose Report the contents of the VHDL library.



End Point Slack Histogram Report

The end point histogram report generates a report on the statistical distribution of the timingslack at each point in the design. Figure 3-12 shows a sample histogram and Table 3-15defines the end point histogram options.

Negative slack values indicate a divergence between the timing constraints and the desiredtiming result.

Figure 3-12 End Point Slack Histogram Report

The x axis indicates the median slack in nanoseconds; the range is computed automatically.The y axis indicates the number of points in the computation; the range is computedautomatically. When you position the cursor over a bar, the total number of points and theminimum and maximum slack time for that bar are displayed.

When you double-click on a bar, a report is displayed. For each pin, the report indicates thefollowing information: status, slack time, arrival time, and required time. For each instance,the report indicates the following information: arc, delay, arrival time, required time and slew.

num

ber

of p

oint

s in

pat

h

end point slack range (in nanoseconds)

double-click on a bar to displaya report on pins and instances

processing status



Path Histogram Report

The path histogram report generates a report on the statistical distribution of the timing pathat each point in the design; this histogram helps locate paths that violate timing constraints.Figure 3-13 shows a sample histogram and Table 3-22 defines the end point histogramoptions.

Negative slack values indicate a divergence between the timing constraints and the desiredtiming result.

Table 3-21 End Point Slack Histogram Report Options

Option/Icon Description

Compute Histogram – generate and display the histogram (seeFigure 3-12 for a sample histogram).

Write Data to a File – a dialog is displayed requesting name andlocation to save the report file.

Print Histogram.

Close Window – close the histogram window.

all Select the ideal clock for which to generate the report. Selecting allgenerates a report that includes all of the ideal clocks.

Maximum count Specify the maximum number of points in the computation,default: 100

Mode Click either mode option to enable.

■ Early

■ Late

Rise Report on rise transition.

Fall Report on fall transition.



Figure 3-13 Path Histogram Report

The x axis indicates the median path slack in nanoseconds; the range is computedautomatically. The y axis indicates the number of points in the computation; the range iscomputed automatically. When you position the cursor over a bar, the total number of pointsand the minimum and maximum path slack time for that bar are displayed.

When you double-click on a bar, a report is displayed. For each pin, the report indicates thefollowing information: status, slack time, arrival time, and required time. For each instance,the report indicates the following information: arc, delay, arrival time, required time and slew.

Table 3-22 Path Histogram Report Options


Compute Histogram – generate and display the histogram.

Write Data to a File – a dialog is displayed requesting name andlocation to save the report file.

Print Histogram.

Close Window – close the histogram window.

num

ber

of p

oint

s in

pat

h

timing path slack range (in nanoseconds)

double-click on a bar to displaya report on pins and instances

processing status



all Select the ideal clock for which to generate the report. Selecting allgenerates a report that includes all of the ideal clocks.

Maximum Count Specify the maximum number of points in the computation,default: 100

Mode Click either option to enable.

■ Early

■ Late

Transition Click either option to enable.

■ Rise

■ Fall

Table 3-22 Path Histogram Report Options, continued




Window Menu Options

Figure 3-14 diagrams the window menu functions. Table 3-23 defines the options/iconsdisplayed with the HDL and Tcl editors when a new window is open. Table 3-24 defines theoptions/icons displayed with schematic editor when a new window is open. Refer to “Viewingthe Schematic Design” on page 115 for instructions on using the schematic editor.

Figure 3-14 Window Menu Function Flow

Table 3-23 HDL and Tcl Editor Functions


Verilog/VHDL Specify the design language. Default: Verilog

Create a new HDL/Tcl script.

Open an existing HDL/Tcl file.

Save the HDL/Tcl file.

Save the current contents of the HDL/Tcl editor in a file.

Save and parse.

Search and replace.

Close the HDL/Tcl editor window.

Main Menu

Main Screen

Window

New Tcl Editor New Schematic EditorNew HDL Editor



Table 3-24 Schematic Editor Functions


Normal/Gray Specify the design shading. Default: normal

Clear the highlighting.

Highlight the selected design.

Unselect the highlighted design.

Zoom in on design.

Zoom out on design.

Move up on the schematic hierarchy.

Move down on the schematic hierarchy.

Return to the last displayed schematic view. A stack of 10 designs aremaintained so that you can backtrack through the view history.

Return to the previously displayed schematic view. It allows you to goforward through views that you previously backtracked.

View whole module.

Search for a specific instance, net, port, bus, or module in theschematic or a list of all instances, nets, ports, bus, or modules in theschematic. For an explanation of the search task, refer to “Searchingfor an Object” on page 131.

Prevent changes to the schematic database. To unfreeze thedatabase, click Freeze again; the setting toggles between an on andoff state. Operations that are not available during the database freezeare indicated by the schematic tool bar icons; grayed-out icons indicatethe operation is not available.

Group highlighted instances.

Dissolve highlighted instances.

Uniquify instances.

Save schematic.



Help Menu Options

The help menu functions are diagrammed below and Table 3-25 defines the help options.

Print schematic.

Close the schematic window.

Module Specify which schematic module to display.

Page Click and drag the slider to view the different pages.

Table 3-25 Help Options

Option Description

Reference Provides a list and link to the Ambit BuildGates synthesis referencedocumentation.

Known Problemsand Solutions

Provides a link to the Ambit BuildGates synthesis Known Problemsand Solutions document.

Product Notes Provides a link to the Ambit BuildGates synthesis Product Notesdocument.

Table 3-24 Schematic Editor Functions, continued


Main Menu

Main Screen

Help

Product Notes AboutReference

Known Problemsand Solutions

User Guides

Specify DocumentServer



User Guides Provides a list and link to the Ambit BuildGates synthesis user guidedocumentation. Product manuals that require a software license thatyou have not purchased will be grayed-out on the list and will not beaccessible.

Specify DocumentServer

Allows you to connect to an alternate, currently-running documentserver, instead of the default local server.

About Provides Ambit BuildGates synthesis version and releaseinformation.

Table 3-25 Help Options, continued

Option Description



The Main Tool Bar

The main tool bar is an iconised menu that allows quick access to some of the morefrequently used Ambit BuildGates synthesis functions and commands. To display thedescription associated with an icon, click the right mouse button on the icon on the main toolbar.

The icons on the tool bar provide shortcuts to functions and commands that are available fromthe pulldowns on the main menu (except for the Stop icon). Figure 3-15 displays each iconand indicates its main menu command equivalent. Refer to Main Menu Functions on page 39for full descriptions.

The Stop function terminates the execution of the current command. To preserve the integrityof the database, the stopping process allows the command to safely and logically terminateits execution before ending. Therefore, the stop could take a moment to come to an orderlyend.

Figure 3-15 Tool Bar Functions and Commands

Open File

Main Menu: File

Set Operating Parameters

Main Menu: Commands

Clear the Console

Main Menu: Edit

Paste Console Text

Main Menu: Edit

Copy Console Text

Main Menu: Edit

Save File

Main Menu: File

Cut Console Text

Main Menu: Edit

Report Hierarchy

Main Menu: Reports

End Point Slack Histogram

Main Menu: Reports

Optimize

Main Menu: Commands

Stop Command

Path Slack Histogram

Main Menu: Reports

Build Generic

Main Menu: Commands



The Browsers

BuildGates synthesis provides the following browsers.

■ The Module Browser

■ The Variable Browser

To display the module browser or variable browser listing such that it occupies the whole mainscreen window instead of only a portion of the window, place the cursor in the browser portionand press the Control-m keys. Repeatedly pressing Control-m toggles between the standardsplit-screen and the whole-screen display.

The module and variable browsers contain commands that have ac_shell command lineequivilalents. For a cross-reference between these commands and ac_shell command linecommands, refer to Appendix B, “Quick Reference”.

The Module Browser

The module browser is a hierarchical module and instance browser, which displays topmodules and hierarchical instances of the modules. It is similar to using thereport_hierarchy -instance command in ac_shell .

To open a design file and view the hierarchy of a module, click the Open File icon on the maintool bar. A window similar to the one shown in Figure 3-16 is displayed.

Figure 3-16 Sample Open Design File Window



1. Click the desired file type button on the middle column of the window.

2. Select or type in the desired file on the left side of the window. For example, selectclock_test.tcl.

3. Click Ok to display the module browser window; a sample window is shown below.

As called-out in the sample window above, the module browser has three levels of hierarchy:instance name, module name, and module state. Instance name is the name of the instance,which must be instance unique. Module name is the name of the module in the design andcan be called any number of times from more than one instance. The module state indicatorshows the state of that particular module. The available module states are: blackbox (b),generic (g), optimized (o), mapped (m), and don’t modify (x). Table 3-26 defines the color andsymbol associations of the module states.

The modules can be expanded and collapsed by clicking on + and - indicators. The modulebrowser displays multiple trees, single trees, or branches of a tree. The number of expandedlevels displayed depends on the default value set in “display depth” in the browser optionsscreen (refer to Table 3-8 on page 50). Viewing a branch displays the “selected” module asthe top of a single tree. Branch viewing is used for large designs with many levels of hierarchy.

instance

module

module

name

name

state



Note: If the state of the module browser gets confused or it is not updated, double click onthe desired module to redraw the contents of the browser with the current information or usethe Module Browser–Rebuild Tree command.

Module Browser Pop-Up Menu

The module browser has a context sensitive pop-up menu, which is activated in thebackground of the display area.

To activate the browser pop-up menu:

1. Click and hold the right mouse button to activate in the context sensitive background areain the browser window.

2. Move the mouse arrow to the desired option on the pop-up menu.

Table 3-26 Module Type with Symbol and Color Association

Color/Icon Module Type

Generic module (g)

Optimized module (o)

Mapped module (m)

Blackbox module (b)

Don't modify module (x)

Red text

Top timing module

Blue text

Current timing module

Red text

Top and current timing module



3. Release the right mouse button to select the option.

The browser pop-up menu options are described below.

Module Browser Quick Commands

Table 3-27 Module Browser Pop-Up Menu

Menu Option Description

Rebuild Tree Redraw the module hierarchy tree. This option is used onlywhen the Browser Module update is in manual mode.

(View–General Preferences–Browser–Browser Mode–Manual Browser Update).

Set Current Module Set the selected module to the current module.

Set Top Timing Module Set the selected module to the top timing module.

Open HDLWindow [Main/New]

Open and view the HDL in the main window or a new window.The file can be edited.

Open Schematic[MainWindow/NewWindow]

For the selected module, view the schematic in the mainwindow or a new window.

Set Don’t Modify Setting this option prevents the instances, modules, or portsfrom being modified.

Reset Don’t Modify Reset the Set Don’t Modify option.

Mouse Button Action

Left Click + or - indicator to expand or reduce the tree for the module.

Left Double click on a module name to open the HDL file or view theschematic, depending on the options setting inView–General Preferences–Browser–Browser Mode.



The Variable Browser

The variable browser (shown in Figure 3-17) displays a hierarchical list of all the globalvariables in the Ambit BuildGates synthesis product.

Figure 3-17 The Variable Browser

The global attributes are divided into the following three categories.

■ set_globalSet the ac_shell attributes on global matters using the set_global command.The attributes are divided into categories by function, as defined in Figure 3-18 .

Click left mouse button to display the settings. To set the value of a variable, select thevariable, enter the value in the variable value field, and click the Set button. To clear orreset to the default the value of a variable, select the variable and click the Clear orDefault button, respectively. Click the right or middle mouse button to display in theconsole the help syntax for the selected variable.

Variables whose values have been changed from the default value are displayed in redtext.



■ tcl scalarDisplay the read-only tcl global variables.

■ tcl arrayDisplay the read-only tcl global arrays. Use the + and - indicators to open and display thecontent of an array.

Figure 3-18 Displaying Variable Values

variable value

AmbitWare - datapath

scan insertion

distributed processing

and testing

HDL modeling

miscellaneousphysically knowledgeablesynthesis

electronic design interchangepower

timing analysis

format

user interface

field

optimization

do_change_name -rules options



Work Area Tools

The Ambit BuildGates synthesis tool provides the following design tools, which are describedin detail in the following sections.

■ The HDL Editor

■ The Tcl Editor

■ Constraints tool

■ The Schematic Viewer

■ Distributed processing

The HDL editor and constraints tool contain commands that have ac_shell command lineequivlalents. For a cross-reference between these commands and ac_shell command linecommands, refer to Appendix B, “Quick Reference”.

HDL and Tcl Editors

To display an editor or viewer such that it occupies the whole main screen window instead ofonly a portion of the window, place the cursor in the editor portion and press the Control-mkeys. Repeatedly pressing Control-m toggles between the standard split-screen and thewhole-screen display.

Note: Opening an HDL or Tcl file with the editor does not load/read the design file. However,the “Save and Parse” option button for both HDL and Tcl does load the file; see the followingsections. Also, refer to “File Menu Options” on page 40 for instructions on loading a file.

The HDL Editor

The HDL Editor (shown in Figure 3-19) displays and edits Verilog and VHDL files. The textdisplayed in the HDL editor is color-coded by type: normal, operator, comparator, number,and so on. You can specify custom colors in View–General Preferences–Colors–ColorItems.



Figure 3-19 The HDL Editor

The HDL file’s path and name are displayed on the dialog box above the HDL text. This fieldcan be used to specify the path and name of another file to display and/or edit. Click the scroll-down arrow to the right of the file name field to display the pull down menu showing the historyof all the files previously opened. To re-open a previously opened file, click the left mousebutton on a file in the history list.

The line number and column number fields display the current line and column numbers ofthe insertion cursor. These fields can be edited to position the cursor at a specific location inthe file. To do so: click left mouse button in the field, overwrite the current value, and pressthe Return key. Lines start at 1 and columns start at 0.

The HDL button bar provides the following file operations.

Button Description

Verilog/VHDL

Toggle between Verilog or VHDL to indicate the type of source code file todisplay and open.

New HDLScript

Open a blank edit page to write new HDL code.

HDL filename

column

HDL buttonbar

line num

num/sample/database/cpu.v



Open HDLFile

Open an HDL file.

If HDL is the default editor, then double clicking a module in the modulebrowser will open the associated HDL file in the editor. Refer to “ViewMenu Options” on page 44 for setting the editor/viewer default.

Save HDLFile

Save the current file using the current, displayed file name. To close a filewithout saving changes, click New HDL Script.

Save asHDL File

Save the current file to a new location and name.

Save +Parse

Save the current file using the current file name and automatically call theappropriate HDL parser.

Search andReplace

Display the Search dialog. “Searching in the Editors” on page 84 for moreinformation.

Button Description



The Tcl Editor

The Tcl Editor (shown in Figure 3-20) displays and edits Tcl files.

Figure 3-20 The Tcl Editor

The Tcl file’s path and name are displayed on the dialog box above the Tcl text. This field canbe used to specify the path and name of another file to display and/or edit. Click the scroll-down arrow to the right of the file name field to display the pull down menu showing the historyof all the files previously opened. To re-open a previously opened file, click left mouse buttonon a file in the history list.

The line number and column number fields display the current line and column numbers ofthe insertion cursor. These fields can be edited to position the cursor at a specific location inthe file. To do so: click left mouse button in the field, overwrite the current value, and pressthe Return key. Lines start at 1 and columns start at 0.

Tcl filename

Tcl buttonbar

/sample/database/cpu.tcl column

line num

num



The Tcl button bar provides the following file operations.

Searching in the Editors

The search mechanism and interface, shown in Figure 3-21, is the same for both the HDLand Tcl editors.

Figure 3-21 Searching Within the Editors

To Search for a String

1. Open the HDL or Tcl file as described in the above sections.

Button Description

New TclScript

Open a blank edit page to write new Tcl code.

Open TclFile

Open an Tcl file.

Save TclFile

Save the current file using the current, displayed file name. To close a filewithout saving changes, click New Tcl Script.

Save as TclFile

Save the current file to a new location and name

Save +Parse

Save the current file using the current file name and automatically sourcethe file.

Search andReplace

Display the search dialog. Refer to Searching in the Editors for moreinformation.



2. Click the Search and Replace icon to display the window shown in Figure 3-21.

3. Enter the search string in the Text to Search field.

4. If replacement is desired, enter the replacement text in the Text to Search field.

5. If desired, select the following options:

❑ Search up/Search down — to specify direction of search. Search down is thedefault.

❑ Match case — to match upper/lower case sensitivity in search string.

❑ Replace all — to replace all instances of the search string with the specifiedreplacement string. Press the Replace button to automatically replace all instanceswithout prompting.

6. Click Find to search for the string. Continue to click Find until the desired occurrence isdisplayed and highlighted.

7. If text replacement is desired, click Replace to replace the search string with the stringspecified.



Constraints Tool

The constraints screen (a sample is shown in Figure 3-22) displays the current timingconstraints and allows you to change data in the input fields. The constraints screen consistsof three panels: ideal clock panel, port clock panel, and port constraints panel. The panelscontain both editable input fields and uneditable data fields. The port clock panel has sevencolumns and is too wide to fully display in the figure below, therefore this panel is defined inthe cutout at the bottom of the figure. On the actual screen, left click the scroll arrow underthe panel to access all columns.

Figure 3-22 Sample Constraints Screen

inputfields

inputfields

inputfields

data

datafields

fields

datafields

Polarity:Lead/Trail

New IdealSave TimingAssertions

Clock Delete AllConstraints

Ideal Clock Panel Port Clock Panel

Port

(see cutout below)

Clock Port Panel Cutout

ConstraintsPanel

ck

ck ck

pos

neg

ck

none

0.000000



Note: If you begin typing in an input field and change your mind, press ESC to abort theprocess.

Clicking the right mouse button in any of the three panels displays a pop-up menu withadditional functions. The following tables define the pop-up functions.

Table 3-28 Ideal Clock Panel Pop-Up Menu

Option Description

Refresh Clock Table Update all three constraint panels with newly entered input.

New Ideal Clock Create a new ideal clock. A dialog is displayed for entry ofthe clock name and period.

Table 3-29 Port Clock Panel Pop-Up Menu

Option Description

New Port Clock ... Create a port clock. A dialog is displayed for entry of thefollowing information: ideal clock associated with the newport clock, name of port clock, positive or negative edge,and optionally, early or late rise and early or late fall.

Remove Clock Assertions Remove all assertions associated with the selected portclock (this cannot be undone).

Table 3-30 Port Constraints Panel Pop-Up Menu

Option Description

Show Default Clock Display the data for the default ideal clock; this is indicatedby the “@” symbol in the clock column of port constraintspanel.

Toggle Polarity Toggle between Lead and Trail in the polarity column ofthe port constraints panel.



Figure 3-23 Sample Port Timing Constraints Report

After updating constraints, you can optimize the design by selecting Main Menu –Commands – Optimize, or generate a timing report by selecting Main Menu – Reports–Timing Report.

The values in the columns of all three panels are color-coded: red text indicates a “none” ormissing entry, blue text indicates a zero value, and black text indicates values that youspecified.

When the constraints tab is selected, the first constraint screen displayed contains the datafor the default ideal clock, which is indicated by the “@” symbol in the clock column of portconstraints panel. To display the port constraints data for an ideal clock listed on the idealclock panel, left click the ideal clock name to update the port constraints panel.

To display the constraints screen such that it occupies the whole main screen window insteadof only a portion of the window, place the cursor anywhere in the constraints screen and press

Create Positive Edge Clock Create a positive edge clock for the selected port.

You cannot have both a positive and negative edge clock.

Create Negative Edge Clock Create a negative edge clock for the selected port.

You cannot have both a positive and negative edge clock.

Report Port Assertions Display a report on the assertions associated with theselected port. For each ideal clock, the report includes:input/output type, assertion status, early/late rise time, andearly/late fall time. See Figure 3-23 for a sample porttiming constraints report.

Remove Port Assertions Remove all assertions associated with the selected port. Adialog box will ask for confirmation of the deletion.

Table 3-30 Port Constraints Panel Pop-Up Menu, continued

Option Description



the Control-m keys. Repeatedly pressing Control-m toggles between the standard split-screen and the whole-screen display.

For additional information on the methodology of setting constraints, refer to Setting TimingConstraints in the Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS.

Important

To save all constraint and other changes made to your design, select Main Menu –File – Save and specify a file name before exiting Ambit BuildGates synthesis.

Changing Values in Input Fields

1. Click left mouse button in any panel input field that you want to change.

2. Type the new value (you do not need to erase the current value).

3. Press the Return key.

4. Click right mouse button anywhere in the port clock panel to display the pop-up menu foradding a port clock. See Adding a New Port Clock below for procedure.

5. Click right mouse button anywhere in the port constraints panel to display the pop-upmenu for additional functions. See Changing Port Constraints below for procedure.

6. To save your changes, click left mouse button on the Save Timing Assertions icon onthe constraints screen.

Adding an Ideal Clock

1. Click left mouse button on New Ideal Clock icon on the constraints screen.

2. In the dialog box that is displayed, enter the new clock name and period.Click Ok.

3. The new clock is added to the ideal clock panel.

4. To display and update the port constraints for the new clock, click left mouse button onthe new ideal clock.

5. Set the constraints for the new ideal clock as described above in Changing Values inInput Fields.



Deleting Timing Constraints

1. Click left mouse button on Delete All Constraints icon on the constraints screen.

2. In the warning dialog that is displayed, click Ok to delete the constraints.

Adding a New Port Clock

1. Click right mouse button anywhere in the port clock panel to display a dialog for addinga new port clock; move cursor to New Port Clock. Release the mouse button.A dialog is displayed for data entry.

2. Click left mouse button on the down arrow on the Ideal Clock field to select the idealclock.

3. Click left mouse button on the down arrow on the Port Clock field to select the port clock.

4. Click left mouse button on either positive or negative edge.

5. If desired, click left mouse button to select early or late rise, or, early or late fall.

6. Left click Ok.

Changing Port Constraints

1. Click right mouse button anywhere in the port constraints panel to display the pop-upmenu; move cursor to the desired command. Release the mouse button.

2. Refer to Table 3-30 for descriptions of the port constraints panel pop-up menucommands; make changes as desired.

3. To save the changes, select Refresh Clock Table in the ideal clock panel pop-up menu;see Table 3-28.

The Schematic Viewer and Symbol Files

For a complete description of the schematic viewer and typical tasks instructions, please referto the Viewing the Schematic Design chapter.

The schematic viewer accepts .sym format files. If you have an .slib , .edif , or .edfformat file from a third part library vendor, you must convert it to a .sym format. To effectivelyuse the schematic viewer, you must specify the correct symbol file which corresponds to the



technology library from the library vendor. The following section defines the conversion stepsthat coordinate the symbol file to the technology library.

Converting Symbol Files to . sym Format

Cadence provides the necessary utilities to convert .slib, .edif, and .edf format filesto .sym format. The utilities edifconv and slibconv are located in the following directory:

install_dir /BuildGates/ version /symutils/ operating_sys

If you have a symbol library named after the technology in the current working directly thatwill be searched first.

The schematic viewer will search the directory structure for the . sym file in the followingorder:

■ If the symbol library is named after the technology library, the current working directoryis searched first.

■ The install directory is searched next.

■ The symbol library path set in the GUI (View–Schematic Preferences–General–Symbol Libraries on page 54) is searched last.

The conversion utilities are run from the UNIX shell, not from within ac_shell .

To convert a .edif or .edf file, issue the edifconv command at the Unix prompt. Thedefault output file name is output.sym. For example:

edifconv library_file_name

Or, the edifconv utility allows you to specify an output file name:

edifconv library_file_name -outfile library.sym

For example:

edifconv componentA2.edif -outfile componentA2.sym

To convert a .slib file, issue the slibconv command at the Unix prompt. The defaultoutput file name is output.sym , and the utility does not allow you to specify your own outputfile name. For example:

slibconv library_file_name.slib

Specifying Technology Symbols

To use the schematic symbols in the .sym format, you must specify the file name containingthe schematic symbols for the cells in the library. The following steps explain the process.



1. From the main toolbar, select View–Schematic Preferences–General. The followingdialogue box is displayed.

2. In the field labeled "Default technology," specify the complete path to the .sym filecontaining the schematic symbols.

3. Click Apply. Click Ok.

The schematic symbols are now selected for your technology library.

Distributed Processing

The Ambit BuildGates synthesis distributed synthesis tool enables you to use a network ofheterogeneous computers as a single processing system. Parallel optimization of logicmodules and reduced compute time enable synthesis runtimes that are two to four timesfaster than without distributed synthesis.

The distributed synthesis tool selects hosts based on current load conditions and resourcerequirements of other applications running on the host machine. Remote jobs behave in thesame manner as jobs run locally.

The tool is supported on both the Sun and HP platforms (including a heterogeneous mix ofSun and HP machines).



For complete information on using Cadence distributed synthesis tool, refer to DistributedProcessing of Ambit BuildGates Synthesis.

Update Mode

The value in the update mode field (see Figure 3-1 on page 37) displays either the wordautomatic or manual and reflects the setting in View–General Preferences–Browser–Browser Mode. If manual browser mode is enabled, the browser module list is notautomatically updated the when a change is made to the design hierarchy; to see thechanged hierarchy, you must rebuild the module list using Module Browser–Rebuild Tree.



The ac_shell Console

As an interface to Ambit BuildGates synthesis, the ac_shell console provides directcommand line access to the tool. The console accepts basic text input and output andsupports all of the functionality of ac_shell , command line completion, file completion, anda logging mechanism. See Figure 3-1 on page 37 for the location of the ac_shell consoleon the main screen.

To display the ac_shell console such that it occupies the whole main screen windowinstead of only a portion of the window, place the cursor in the console and press the Control-m keys. Repeatedly pressing Control-m toggles between the standard split-screen and thewhole-screen display.

All informational, warning, and error messages are output to the ac_shell console. Thedefault colors are listed in the table below but can be reassigned if desired; refer to View–General Preferences–Colors–Color Items.

Message Type DefaultColor Syntax

standard input/output black

error messages red ==> ERROR: <message>

warning messages yellow --> WARNING: <message>

informational message fromac_shell

burgundy Info: <message>



The Status Bar

The status bar, shown ibelow, is located at the bottom of the main screen and consists of fourfields: the busy box, the message field, the last command field, and the current technologyfield.

The busy box indicates when the Ambit BuildGates synthesis tool is working on a task: redindicates busy and green indicates availability. The tool is busy whenever an HDL or Tcl fileis loading, when a command is entered at the command line, and when most menucommands are selected. Additional tasks cannot be requested when the tool is busy. To halta process while preserving the integrity of the database, click the Stop button on the tool barto interrupt at the at the next stable place in the operation.

By default, the message field displays informational messages, including the object names inthe schematic viewer as the cursor passes over an object in a schematic. This status bardisplay mode can be turned off via View–Schematic Preferences–General–CursorQuery.

The last command field displays the last command executed through the ac_shell consoleor by selecting menu options.

The current technology field displays the name of the technology library being used for thedesign.

busy box message field last command current technology



4Flow Procedures

This chapter provides a high level tutorial of the tasks in a typical synthesis flow. The tasksare presented with both the command line instructions and the GUI procedures.

Refer to Key Bindings and Mouse Operations on page 33 for assistance in navigating the GUIeditors and ac_shell console, and Syntax Conventions on page 10 in the Preface forcommand line syntax.

Typical Synthesis Flow

The typical high level flow in BuildGates synthesis is shown in Figure 4-1 and consists of thefollowing tasks.

■ Read Libraries

■ Read Design Data

■ Build Generic Design

■ Set Timing Constraints

■ Optimize Design

■ Generate Reports

■ Save Final Netlist

The actual order of these tasks can vary and overlap. For example, you may want to generatereports both before and after optimizing the design. The following sections expand andexplain each of the tasks in the flow.


Ambit BuildGates Synthesis User GuideFlow Procedures

Figure 4-1 Typical Synthesis Flow

Read Libraries

Optimize Design

Generate Reports

Save Final Netlist

Read Design Data

Set Timing Constraints

Chip Planning

Synthesis Complete

Build Generic Design



Read the Libraries

Typically when running the Ambit BuildGates synthesis software, the first step is to load thetiming and power libraries needed in the chip design. Cadence supports the followinglibraries.

■ Cadence Timing Library Format 4.3 — TLF4.3

■ IEEE 1481 Delay Calculation Language — DCL (a form of Delay and Power CalculationSystem — DCPS)

■ Open Library API — OLA v1.0.2

■ Synopsys Liberty, .lib , format

■ Synopsys Stamp Models

■ Graybox modeling

This section provides an overview of the libraries; libraries are explained in detail in theTiming Analysis for Ambit BuildGates Synthesis and Cadence PKS, Using Timing Librarieschapter.

The DCL compiler, ndcl , compiles DCL into a binary Delay and Power Calculation Module(DPCM). The DPCM is an executable shared library that is linked to the BuildGates synthesisdatabase at runtime. The DCL compiler is available through Cadence for library developmentpurposes.

To use DCL libraries, a .alf (Advanced Library Format) library is loaded using theread_alf command, then a DCL library (or more accurately a DPCM) is loaded with theload_dcl_rule command followed by a read_library_update command. When theDPCM library is loaded after an .alf, all timing information is derived from the DPCMspecified by the read_library_update file, and all cell function is derived from the .alf.If the DPCM contains cell properties (like area) and pin properties (like capacitance andwireloads), the DPCM takes precedence over the .alf and will override any similarinformation provided by the .alf . If the DPCM does not contain this information, the cell andpin properties and wireloads from the .alf will be used. To map to multiple libraries, onelibrary is loaded using the read_alf command and additional libraries are merged using theread_library_update command.

To enable communication between BuildGates synthesis and the DPCM, the following Unixenvironment variables must be set: DCMRULEPATH, DCMTABLEPATH, andLD_LIBRARY_PATH for Solaris (or the equivalent for other platforms). Refer toload_dcl_rule in the Command Reference for Ambit BuildGates Synthesis andCadence PKS and/or the Using IEEE 1481 Delay and Power Calculation System (DCL)



Libraries section in the Timing Analysis for Ambit BuildGates Synthesis and CadencePKS.

The OLA specification is an extension of the Delay and Power Calculation System and isloaded in the same manner as the DCL: with the load_dcl_rule command afterread_alf . Some of the key extensions to OLA over DPCS are the addition of cell functioninformation and properties equivalents to dont_use and dont_touch which can be usedfor synthesis.

The .lib format is the ASCII synthesis timing and power library format originally defined bySynopsys™ and now licensed by Synopsys through the TAP-in™ program. Cadence is aTAP-in licensee. The Cadence library compiler, libcompile , supports the .lib format andproduces a binary .alf file. Typically, .lib refers to the constructs in the .lib standard orto the actual library source; while .alf refers to the compiled library that is loaded into AmbitBuildGates synthesis.

Run the libcompile command from the Unix prompt (not from ac_shell ) to compile a.lib file as follows:

libcompile xy_cells.lib xy_cells.alf

For exact libcompile syntax, refer to the Timing Analysis for Ambit BuildGates Synthesisand Cadence PKS.

The Stamp modeling language is a Synopsys proprietary language developed specifically todescribe the timing models of large custom blocks, such as RAMs and microprocessor coresthat have not been synthesized into gate-level netlists.

Graybox modeling is a practical solution for incorporating standard functions in the form ofcommercially available cores. These reusable IP (Intellectual Property) cores are pre-designed and pre-verified functional building blocks that enable a major productivity gain forASIC and IC design. In addition, Graybox modeling is also used in design situations in whichthe chip designer does not want to pass the netlist to the synthesis tool due to IP reasons.For these IP blocks, no re-synthesis or optimization is performed but timing validity must beensured. Graybox modeling is supported in the .lib format. Run the libcompilecommand with the -ipformat option from the Unix prompt to compile a .lib file withgraybox modeling:

libcompile -ipformat xy_cells.lib xy_cells.alf

Note: The Ambit Synthesis Technology Library (ATL) and Extended ATL (XATL) are internallibraries called upon by the do_build_generic command to transform a design read in byread_vhdl or read_verilog into a hierarchical, gate-level netlist consisting of technology-independent logic gates.



To report the functionality of each cell in the ATL and Ambit_XATL libraries, use the followingcommands:

report_library -library atl

report_library -library ambit_xatl

The following paragraphs list the GUI and command line steps to read a library, update thislibrary with additional information from the update file, and load the DCL rules.

Read Library — GUI Procedure

1. Select File – Open – Ambit Library.

2. Browse for or type in the path and file name and click Ok.

3. On the ac_shell console type read_library_update libfile.alf and pressReturn.

4. Select Commands – Load DCL Rules.

Read Library — Command Line Procedure

Note, the Unix environment variables DCMRULEPATH, DCMTABLEPATH, andLD_LIBRARY_PATH (see Read the Libraries on page 99) must be loaded prior to thesesteps.

1. Type read_alf libfile.alf and press Return.

2. Type read_library_update libfile.alf and press Return.

3. Type load_dcl_rule and press Return.



Read the Design Data

Listed below are the data formats that Ambit® BuildGates® synthesis accepts as basic designsources. After a generic netlist is generated, Standard Delay Format (SDF) data can also beloaded to include physical design constraints.

■ VHDL data

■ Verilog data

■ Electronic Design Interchange Format — EDIF data

■ Ambit Data Base — ADB data

VHDL and Verilog are the typical RTL hardware languages used to design chips; refer to theHDL Modeling for Ambit BuildGates Synthesis for information. EDIF is primarily used toexchange gate-level designs between EDA tools; refer to the EDIF Interface chapter in theHDL Modeling for Ambit BuildGates Synthesis for information.

ADB data is generated when the do_build_generic command is executed and defines ahierarchical, gate-level netlist which consists of technology-independent ATL (AmbitTechnology Library) and XATL (extended ATL) logic components. The binary .adb file canbe saved for reuse with the write_adb command. The ADB file can be used as the sourcefor re-synthesis and analysis.

Tip

If the software terminates abnormally, an ADB recovery file is created in the /TMPfile. To use a directory other than the default /TMP, use the environment variableAMBIT_TMP_DIR. For example: setenv AMBIT_TMP_DIR ./adb_dir .

The following paragraphs list the GUI and command line steps to read a Verilog file.

Read Design Data — GUI Procedure

1. Select File – Open – Verilog.

2. Browse for or type in the path and file name and click Ok.

Read Design Data — Command Line Procedure

➤ Type read_verilog filename.v and press Return.



To load a VHDL, EDIF, or ADB file, use the commands read_vhdl , read_edif , andread_adb , respectively. For syntax detail for each of these commands, refer to theCommand Reference for Ambit BuildGates Synthesis and Cadence PKS.



Build a Generic Netlist

Below is a flow chart of a typical build task.

The following paragraphs list the GUI and command line steps to build a generic netlist.

Build Generic Netlist — GUI Procedure

1. Select Commands – Build Generic.

The Build Generic options form appears.

2. Select one or more options; click Ok.

3. Save the database (in this example, save as a .adb ); select File – Save – Ambitdatabase.

4. Browse for or type in the path, then type in file name and click Ok.

Read Design Data

Set Constraints

Build Generic Netlist



Build Generic Netlist — Command Line Procedure

1. Type do_build_generic and press Return.

2. To save the complete hierarchical database design as a .adb file, typewrite_verilog -hierarchical filename.adb and press Return.

3. To specify the top timing module, type set_top_timing_module module_id andpress Return.

4. To specify the current module, type set_current_module module_id and pressReturn.



Set Constraints

For complete information on the methodology of setting constraints, refer to Setting TimingConstraints in the Timing Analysis for Ambit BuildGates Synthesis and CadencePKS.

Below is a flow chart of a typical setting constraints task.

The following paragraphs list the GUI and command line steps to set basic timing constraints.

Set Constraints — GUI Procedure

1. To specify the top timing module, select Modules – with right mouse button, highlight thedesired module – release mouse on Set Top Timing Module option. The top timingmodule is displayed in red letters.

2. To specify the current timing module, select Modules – with right mouse button, highlightthe desired module – release mouse on Set Current Module option. The currentmodule is displayed in blue letters.

3. To set ideal clock, select Constraints – press/hold right mouse button in Ideal ClockPanel (see “Constraints Tool” on page 86) – release mouse on New Ideal Clock option.

4. On the Ideal Clock form that is displayed, type the clock name and period; click Ok.By default, the leading edge is set to 0 and the trailing edge is set at the mid-point of theperiod such that a symmetric clock is generated.

Define Ideal Clocks

Build Generic Netlist

Set Top/Current

Optimize

Level Module



Set Constraints — Command Line Procedure

1. To specify the top timing module, type:set_top_timing_module filename and press Return.

2. To specify the current timing module, type:set_current_module module_name and press Return.

3. To create an ideal clock with a period of 20, type:set_clock i_clk_name -period 20 and press Return.

By default, the leading edge is set to 0 and the trailing edge is set at the mid-point of theperiod such that a symmetric clock is generated.



Optimize the Design

Optimization can be performed either with the do_optimize command or with individualdo_xform_ transform commands. For a list of transforms and which do_xform_ commandsare equivalent to the do_optimize command, refer to Optimizing with Logic Transforms onpage 155. For information on optimization before and after place-and-route, refer to:Optimizing Before Place-and-Route on page 143 and Optimizing After Place-and-Route onpage 163.

The target technology library must be set with the set_globa l target_technologytarget_libs command prior to running the do_optimize or do_xform_ commands.

The following paragraphs list the GUI and command line steps to specify the targettechnology library and write the assertions. The set_global step is typically run prior tobeginning synthesis when all global parameters are set for the whole design. Also, thewrite_assertions command is used to save the design assertions in a .tcl file and isan optional step.

Specify Target Technology Library and Write the Assertions — GUI Procedure

1. Select Commands – Set Target Technology.

The Set Technology form appears with a list of available libraries.

2. Select the target technology and click Ok.

3. Assertions must be written from the ac_shell console in the GUI; typewrite_assertions filename.tcl and press Return.

Specify Target Technology Library and Write the Assertions — Command LineProcedure

1. Type set_global -target_technology target_lib and press Return.



2. Type write_assertions filename.tcl and press Return.

The following paragraphs list the GUI and command line steps to optimize your design.

Optimize Design — GUI Procedure

1. Select Commands – Optimize.

The Optimize form appears.

2. Select optimize options and click Ok.

Optimize Design Using do_optimize — Command Line Procedure

In the example syntax below, optimization is performed with a high effort level, in auto flattenmode, and with time budgeting performed. Refer to the Command Reference for AmbitBuildGates Synthesis and Cadence PKS for the full list of do_optimize options.

➤ Type do_optimize -effort high -flatten auto -time_budget and pressReturn.

Optimize Design Using do_xform_ — Command Line Procedure

Below are the steps to optimize a design with the do_xform_ commands that are equivalentto running the do_optimize command with its default options. Running transforms allowsyou to customize the optimization process. For example, the do_xform_map command



maps a design to a specific technology library; omitting this command leaves the netlist as apurely generic one. Also, using do_xform_ commands instead of the do_optimizecommand allows you to perform other commands during the optimization process, such asgenerating reports or saving the design in various formats.

1. To propagate constants at the logic levels (0 or 1) throughout the design and crossinghierarchical boundaries, type do_xform_propagate_constants and press Ok.

2. To remove redundancies from the netlist, type do_xform_remove_redundancy andpress Ok.

3. To apply boolean and algebraic algorithms and technology-independent transforms toachieve logic optimization and logic structuring, type do_xform_structure and pressOk.

Note: The do_xform_optimize_generic command runs the transforms:do_xform_propagate_constants,do_xform_remove_redundancy, anddo_xform_structure .

4. To map the generic netlist to the target technology library specified in the set_globalcommand and apply to all hierarchical levels of the design, typedo_xform_map -hier and press Ok.

5. Type do_xform_timing_correction and press Ok to execute the followingcommands.

❑ do_xform_buffer — Insert buffers at the non-critical fanouts of the critical nets toreduce the load driven by the critical net and improve the effective timing on thecritical path.

❑ do_xform_clone — Divide a net into two nets by duplicating the instance drivingthe original net to improve timing on critical path.

❑ do_xform_fix_design_rule_violations — Correct design rule violators.

❑ do_xform_reclaim_area — Replace cells with smaller area cells that have thesame functionality and removes unnecessary buffers or clones. Applies to anytransforms that reduce area, without worsening the worst negative slack.

❑ do_xform_resize — If the library contains a choice of cells with the samefunctionality but different drives, replaces a cell with an equivalent cell of differentdrive if the new cell contributes toward meeting the goal of the transform.

6. To restructure and remap the critical path to meet the timing constraints, typedo_xform_restructure and press Ok.

Note: The do_xform_optimize_slack command runs the transforms:do_xform_timing_correction and do_xform_restructure .



Generate Reports

BuildGates synthesis provides the following report categories.

■ Timing

■ Area

■ Library

■ Hierarchy

■ Design Rules

■ VHDL Library

■ End Point Histogram

■ Path Histogram

Each of these categories has options which allow the customization of the report. For detailson options and syntax, refer to the report_ commands in the Command Reference forAmbit BuildGates Synthesis and Cadence PKS. For report strategies and additionalexamples, refer to chapter Report Generation on page 169 of this book.

Below is an example of generating a timing report; the procedure for other reports is similar.Reports are saved in ASCII format and can be viewed with an ASCII editor.



Generate Report — GUI Procedure

1. Select Reports – Timing.

The Report Timing form appears; the options part of the form is shown below.

2. Click the options and type the information that specifies the desired timing report andclick the Generate Report icon on the Report Timing options form. The report isdisplayed in the text window to the left of the options form.

3. To save the report to a file, click on the Write Report to a File icon on the Report Timingoptions form and specify a file name and path.

Generate Report — Command Line Procedure

In the example syntax below, options are specified to display the worst late path to eachviolating endpoint that has a slack less than -1.0 and to write the report to a file namedcpu_rep1.rpt .

➤ To generate a timing report, type:report_timing -max_slack -1.0 > cpu_rep1.rptand press Return.



Save Final Netlist

After optimization is compete and the report results are satisfactory, the final netlists need tobe saved. You may write over the netlist files generated in the setting constraints task or savewith new file names. In the example below, the final netlists are saved in .v and .adbformats.

Below are the GUI and command line steps to save the technology-dependent and optimizednetlists.

Save Netlist — GUI Procedure

1. Save the database as a .v file; select File – Save – Verilog. Browse for or type in thepath, then type in file name and click Ok.

2. Save the database as an .adb file; select File – Save – Ambit database. Browse foror type in the path, then type in file name and click Ok.

Save Netlist — Command Line Procedure

1. Save the database including its module hierarchy as a .v file; typewrite_verilog -hierarchical filename.v and press Return.

2. Save the database including its module hierarchy as a.adb .adb file; typewrite_adb -hierarchical filename.abd and press Return.



5Viewing the Schematic Design

The schematic viewer, shown in Figure 5-1, allows you to view a module netlist as aschematic diagram. You can view modules both before and after optimization. The schematicviewer displays only one module at a time in the viewer. To display more than one module youmust select the New Window option from the module browser (see Table 3-27 on page 77).You can have multiple windows open at a time with views to many different modules.

You can pan and zoom, display fanin and fanout cones, and display critical paths and timingvalues. You can group instances to make a new module, dissolve instances, or change thereference point of an instance.

The schematic viewer accepts .sym format files. If you have .slib or .edif format filesfrom a third part library vendor, you must convert them to .sym format. For instruction onconversion, refer to The Schematic Viewer and Symbol Files on page 90.

Figure 5-1 The Schematic Viewer

Module

ViewerDisplay

Title Bar

Tool BarSchematic


Ambit BuildGates Synthesis User GuideViewing the Schematic Design

How to Use the Schematic Viewer

You can navigate the schematic viewer with mouse operations, keyboard shortcuts, and byselecting menu options. The schematic viewer must be the active window for the options tobe available. To make a window active, click the left mouse inside the window.

Keyboard Shortcuts

The keyboard shortcuts are listed in Table 5-1.

Table 5-1 Keyboard Shortcuts

KeyboardOption

MouseEquivalent Description

CTRL-m inviewerwindow

none Display the viewer such that it occupies the whole mainscreen window instead of only a portion of the window.Repeatedly pressing Control-m toggles between thestandard split-screen and the whole-screen display.

1 none Normal view mode, Scale of 1.

i click and dragleft mousebutton (SE)

Zoom in to increase magnification. The zoom factor isdecreased as you drag the mouse.

o click and dragleft mousebutton (NE)

Zoom out to decrease magnification. When using themouse the zoom factor is incremented as you drag themouse.

f click and dragleft mousebutton (SW)

Reduce or increase the design size to fit the window.

F none Display the full design page. This includes the pageframe.

r none Redraw the screen.

l none Return to the last view. A stack of 10 designs aremaintained so that you can backtrack through the viewhistory.

p none This is the reverse of the backtrack option. It allows youto go forward through views that you previouslybacktracked.



U click and dragleft mousebutton (NW)

Navigate up the hierarchy to the parent module anddisplay the parent module in a window.

Right arrow none Scrolls right to the view the design. Scrolling is limitedby the page size.

Left arrow none Scrolls left to the view of the design. Scrolling is limitedby the page size.

Up arrow none Scroll up inside the window. Scrolling is limited by thepage size.

Down arrow none Scroll down inside the window. Scrolling is limited bythe page size.

Page Up none In multipage schematics, display the previous page.

Page Down none In multipage schematics, display the next page.

Table 5-1 Keyboard Shortcuts

KeyboardOption

MouseEquivalent Description



Mouse Operations

Table 5-2 describes the specific behavior of the mouse in the schematic viewer.

Table 5-2 Mouse Operations

Mouse Description

Double click leftbutton

Operates only on a hierarchical instance to display the upper levelmodule. Selecting a non-hierarchical instance produces a warning.

Hold and drag leftbutton

Perform 4 functions: ascend a level in your design (U), zoom out (o),zoom in (i), and fit the design to the screen (f).

The further the distance that the mouse is dragged up, down, left orright in the window, the greater the effect of the zoom. The zoomfactor is incremented as you drag.

Using A as a starting point the diagram shows the effect of the mouseoperations.

Click and dragmiddle button

Move schematic in any direction.

Click right button When cursor is in the background of schematic, displays theCommands pop-up menu. When cursor is placed on an object (bus,port, instance, net, pin, or bus port), displays the associated pop-upmenu. Refer to “Accessing Context-Sensitive Pop-Up Menus” onpage 120 for details.

U o

if

Zoom out

Zoom in

Ascend a Level

Fullfit

[Schematic Viewer]

N

S

W EA



Objects in the Schematic Database

The schematic viewer displays your netlist using the six basic objects described in Table 5-3.Each of these objects has a context-sensitive pull-down menu accessed with the right mousebutton, which is defined in the following section. The last two items in Table 5-3, the on-pageand off-page connectors, are used only to move between pages in the viewer. You can doubleclick on a connector to follow to the end of the connector on the next page.

To change the object default colors or fonts, refer to View–General Preferences–ColorItems and View–General Preferences–Font Items, respectively. For additionalpreference selections, refer also to View–Schematic Preferences.

Table 5-3 Object Descriptions

Object Description Default Color

Instance Blue

Net Yellow

Port Blue; connected toyellow net

Bus Brown

Bus Port Blue; connected tobrown bus

Pin name

Pin name

Pin name

Pin Name

Module Name

InstanceName

Port Name

Net

Bus

Output Port

Input Port



Accessing Context-Sensitive Pop-Up Menus

The schematic viewer uses seven basic context-sensitive pop-up menus. The Commandspop-up menu is displayed by clicking the right mouse button in the background area of theschematic viewer. The other six pop-up menus are displayed by clicking the right mousebutton on any of the basic objects described in Table 5-3.

The seven pop-up menus are defined in the following tables.

Pin Blue; connected toyellow net

On-pageConnector

BlueHighlighted on thenewly displayed page.

Off-pageConnector

BlueHighlighted on thenewly displayed page.

Table 5-4 Commands Pop-Up Menu

Menu Item Action

Extract Fanin Cone Extract a fanin cone for use in another module. Displays an extractbar between the module bar and the schematic. For a description ofthe task, refer to “Extracting Logic Cones” on page 137.

Extract Fanout Cone Extract a fanout cone for use in another module. Displays an extractbar between the module bar and the schematic. For a description ofthe task, refer to “Extracting Logic Cones” on page 137.

Pin to Pin Path ... Displays the pin-to-pin panel between the module bar and theschematic (see Figure 5-2 for a sample panel). Specify the to-from,from-to, or between pins for the desired object.

Table 5-3 Object Descriptions, continued

Object Description Default Color

Input Pin Output Pin

Net Item

Net Name

Net Name



Generate all Pages Force the generation of the page for the displayed module. If theschematic is multipage and shows unsplit (unspl) in the module titlebar, the pages are regenerated and scaled to fit on multiple pages.

This command performs the same function as View–SchematicPreferences–Paging–Page Size, except the paging is performedonly once and does not affect the schematic preferences or pagingon other modules.

Regenerate CurrentPage

Regenerate and center the current schematic page.

Worst Path Highlight the worst path on the displayed schematic.

Worst Endpoints:1:5 Highlight the worst endpoints on the displayed schematic.

Table 5-5 Instance Pop-Up Menu

Menu Item Action

Show Instance:mainor new window

This item is displayed when the selected instance is hierarchical.Displays the hierarchical content of the instance.

Change Cellref Display a list of equivalent cells from which to choose areplacement cell. Highlight the cell and click Ok.

Show HDL:main ornew window

This item is displayed when the selected instance is hierarchical.Displays the HDL code of the instance in the editor window.

Show Properties... Display the name, type, reference, and don’t modify setting of theselected instance. Lists each pin and net connected to theinstance; double click on the pin or net to display additionalproperties.

Schematic Cone... Displays the cone in an expanded viewer window. Click the rightmouse button on the displayed objects to access the associatedpop-up menus.

Table 5-4 Commands Pop-Up Menu

Menu Item Action



Power This menu item is displayed only if you have the Ambit®

BuildGates® synthesis low power option, in which case pleaserefer to the Low Power Option of Ambit BuildGatesSynthesis and Cadence PKS.

Fanin Cone:input/output list

Highlight the selected fanin cone input or output.

Fanout Cone:input/output list

Highlight the selected fanout cone input or output.

Worst Path To:input/output list

Highlight the selected worst path for selected input or output.

Pin To Pin Path… Displays the pin-to-pin panel between the module bar and theschematic (see Figure 5-2 for a sample panel). Specify the to-from, from-to, or between pins for the desired object.

Worst Path Highlight the worst path on the selected instance.

Worst Endpoints:1:5 Highlight the worst endpoints on the selected instance.

Highlight Object Highlight the selected object.

Unhighlight Object Unhighlight the selected object.

Table 5-6 Net Pop-Up Menu

Menu Item Action

Show Properties... Display the name and “don’t modify” setting of the selected net.Lists each pin, instance, and input/output associated with the net;double click on the instance to display additional properties.

Power This menu item is displayed only if you have the AmbitBuildGates synthesis low power license, in which case pleaserefer to the Low Power Option of Ambit BuildGatesSynthesis and Cadence PKS.

Table 5-5 Instance Pop-Up Menu, continued

Menu Item Action



Pan to Net Source Highlight the selected net source and center it in the viewer. Listsinstances and ports that are sources of the highlighted net.

Pan to Net Sink Highlight the selected net sink and center it in the viewer. Listsinstances and ports that are sinks of the highlighted net.

Worst Path Highlight the worst path on the selected net.

Worst Endpoints:1:5 Highlight the worst endpoints on the selected net.



Table 5-7 Port Pop-Up Menu

Menu Item Action

Show Properties... Display the name, input/output, and net connection of theselected port. Lists each pin and net associated with the port;double click on the net to display additional properties.

Show Constraints... List the name of the port, input/output type, assertion signal,clock name, and early/late rise and fall times. For a description ofthe task, refer to “Displaying Port Constraints” on page 139.

Power This menu item is displayed only if you have the AmbitBuildGates synthesis low power option, in which case pleaserefer to the Low Power Option of Ambit BuildGatesSynthesis and Cadence PKS.

Fanout Cone Highlight the fanout cone associated with the selected port.


Worst Path Highlight the worst path on the selected port.

Worst Endpoints:1:5 Highlight the worst endpoints on the selected port.



Table 5-6 Net Pop-Up Menu, continued

Menu Item Action



Table 5-8 Bus and Bus Port Pop-Up Menu

Menu Item Action

Bus Commands... Display the bus command window (see Highlighting PathBetween Pins for a sample window and details on its use). Selectthe bus component on the left; select the command in the rightcolumn.

Worst Path Highlight the worst path on the selected bus or bus port.

Worst Endpoints:1:5 Highlight the worst endpoints on the selected bus or bus port.

Table 5-9 Pin Pop-Up Menu

Menu Item Action

Fanin Cone Highlight the fanin cone associated with the pin.

Fanout Cone Highlight the fanout cone associated with the pin.

Worst Path To Highlight the worst path to the selected pin. This path may or maynot overlap with the worst timing path in the current module.


Worst Path Highlight the worst path for the worst timing path in the currentmodule. This path may or may not overlap with the worst timingpath to the selected pin.

Worst Endpoints:1:5 Highlight the worst endpoints on the selected pin.





Highlighting Path Between Pins

The pin-to-pin panel, shown in Figure 5-2, is accessed from the several object pop-up menus.There are three ways to select the From and To pins on the pin-to-pin panel.

■ Type in the object name.

■ Click left mouse button on the down arrow next to the pin input field and select an objectfrom the history list of previously selected objects.

■ Place the cursor in the From or To pin input field; the diamond-shaped check box to theleft of the field is highlighted. Click left mouse button on the desired object on theschematic to list the object name in the input field.

Figure 5-2 Sample Pin-To-Pin Panel

To Highlight the Path Between Two Pins:

1. Click left mouse button on the Options box to select the path direction.

2. Input the From and To pins as described above.

3. Click left mouse button on the XDraw icon to highlight the selected path on theschematic. The objects and path are highlighted based on either module level or path(default) depending on the setting in View–Schematic Preferences–Highlighting–Coloring Modes.

4. Click left mouse button on the Close icon to close the pin-to-pin panel.

Close PanelXDraw Path Direction: To - From (default)

From - ToBoth Directions



Viewing Bus Properties

The bus command window, shown in Figure 5-3, is accessed from the bus and bus port pop-up menus described in Table 5-8. The right column contains commands that can be executedfor the bus components listed in the left column.

Commands are grayed-out and not executable if the function is invalid for the selected buscomponent. For example, an output data bus can have a fanin cone but not a fanout cone;therefore, the fanout cone command will not be listed in the commands.

The Fanin Cone, Fanout Cone, Worst Path to Pin, Highlight Object, and Pan to Sourcecommands simply highlight the specified parameter. Show Constraints displays a dialogbox containing port timing constraint information (see Figure 5-8).

Show Properties displays a net properties dialog box containing instance, pin, and directioninformation; see Figure 5-4 for a sample. Doubling clicking the left mouse button on aninstance name in the net properties dialog displays an instance properties dialog box with pinand net information for the selected instance. From there you can double click on a net namein the dialog and get another information box. You may continue double clicking on the objectslisted in the displayed dialog boxes to access additional related object information.

Figure 5-3 Sample Bus Commands Dialog

Commands are grayed-outif the design function isinvalid for the bus selection



Figure 5-4 Sample Net Properties Dialog

The sample task below describes how to display the net and instance properties of thedataout[7] bus port; refer to Figure 5-3 and Figure 5-4 for clarification.

Display Net and Instance Properties of a Bus Port:

1. Click right mouse button on bus port on the schematic to display the pop-up menu (referto Table 5-8); move cursor to Bus Commands. Release the mouse button.

2. A listing of the bus components and associated bus commands is displayed (seeFigure 5-3).

3. Click left mouse button on the desired bus component to highlight it.

4. Click left mouse button on the Show Properties button to display the net properties (seeFigure 5-4).

5. Double click left mouse button on a listed instance to display additional properties.

6. To close all of the displayed dialog boxes, click left mouse button on Cancel.

Double click an instanceto display another

information list



The Schematic Tool Bar

Table 5-10 defines the functions of the schematic viewer tool bar.

Table 5-10 The Schematic Tool Bar

Function Description

Normal/Gray Toggle between design display normal and gray modes. Gray modeis used to de-emphasise areas of the design.

Zoom Fit Display the full schematic page and the border of the viewer.

Zoom In Magnify the selected area of the design.

Zoom Out De-magnify the selected area of the design.

Clear Highlighting Unhighlight all objects and return the colors to normal.

Highlight Select Select all highlighted objects.

Unselect All Unselects all of the selected objects.

Up Hierarchy Ascend a level in the design hierarchy.

Down Hierarchy Descend a level in the design hierarchy or a level into the selectedinstance.

Last View Return to the last view displayed in the viewer.

Previous View Return to the previous view displayed in the viewer.

Search Search for objects in the schematic; for instructions refer toSearching for an Object on page 131.

Freeze Prevent changes to the schematic database. To unfreeze thedatabase, click Freeze again; the setting toggles between an onand off state. Operations that are not available during the databasefreeze are indicated by the schematic tool bar icons; grayed-outicons indicate the operation is not available.

Group Instances Group two or more instances into a new module. Hold down theShift key and click left mouse button to select each instance. In thedisplayed text entry field, enter the name of the new module.

Dissolve Instances Dissolve the contents of a module into the parent module. Holddown the Shift key and click left mouse button to select eachinstance.



Uniquify Instances Create a unique instance of the selected module. Hold down theShift key and click left mouse button to select each instance.

Save Schematic Print the current view or the full page (specified in View–SchematicPreferences–Printing–Scaling) to a postscript file. Specify filelocation and name in the displayed dialog box.

Print Schematic Print the current view or the full page (specified in View–SchematicPreferences–Printing–Scaling) to the default printer.

Close Close the current viewing window.

Table 5-10 The Schematic Tool Bar, continued

Function Description



The Module Title Bar

The module title bar (Figure 5-5) is located between the schematic viewer tool bar and theschematic viewer display and shows the module name, the instance name, and theassociated hierarchy of the current module. A history of previously selected modules ismaintained and can be displayed by clicking on the scroll down arrow and selecting themodule.

The columns on the far right indicate the page sequence of the schematic. If the paging is notsplit into multiple pages, the last column will contain the term “unspl” to indicate that amultipage schematic is compacted onto a single page.

There are two ways to split a multipage schematic:

■ View–Schematic Preferences–Paging–Page Size

■ Generate all Pages in the Commands Pop-Up Menu

Figure 5-5 Sample Module Title Bar

Module name Currently selectedPage x of n

Scroll list ofprevious modules

Instance name

Schematic

Horizontal slide bar

page number objectObject type



Searching for an Object

The search dialog (shown in Figure 5-6) allows you to search for a specific instance, net, port,bus, or module in the schematic or a list of all instances, nets, ports, bus, or modules in theschematic. You may have multiple search windows: one search window per schematicwindow.

The results of the search are displayed in the dialog box. A single left mouse click simplyhighlights the object. A double left mouse click displays and centers the selected object.

Figure 5-6 Search Objects Dialog

Search for a Specific Object:

1. Click left mouse button on Search icon on the schematic tool bar.The Search Objects Dialog is displayed.

2. Click left mouse button to select one object type.

3. Enter the name of the object for which to search. Be sure to clear any old search inputor characters from the entry line. The default entry is an asterisk, which provides a list ofall of the types of selected objects.

4. Left click Search. The object’s full name and location appears on the list.



5. Double click on the object on the list to display and center it on the viewer.

Search from a List of Objects:

1. Click left mouse button on Search icon on the schematic tool bar.The Search Objects Menu is displayed.

2. Click left mouse button to select one object type.

3. Enter an asterisk on the entry line. (Be sure to clear any old search input or charactersfrom the entry line.)

4. Left click Search. The full names and locations of all objects of the selected type appearon the list.

5. Double click on the desired object on the list to display and center it on the viewer.



Grouping Instances

Grouping instances allows you to select two or more instances in a module and put them ina new child module.

1. Hold down the Shift key and click left mouse button to select two or more instances.

2. Click left mouse button on Group Instances icon on the schematic tool bar.

3. Enter a name for the new module in the Enter Module Name box.Click Ok.

The selected instances are now grouped into a new module. In the current view the selectedinstances are replaced by one instance. The new module created from grouping theinstances is added to the design and displayed in the module hierarchy in the module browseras a child of the currently displayed module.



Dissolving Instances

Dissolving instances flattens two or more instances in a module to a single level of the parentmodule.

1. Click left mouse button to select a module that contains two or more instances.

2. Click left mouse button on Dissolve Instances icon on the schematic tool bar.

The instances are displayed in the design at the current level. The module name for thegrouped instances is removed from the module hierarchy in the module browser.



Creating a Unique Module

Uniquifying instances removes the dependency on an existing module and ties the instancesto a newly created module based on the original.

1. Hold down the Shift key and click left mouse button to select two or more instances.

2. Click left mouse button on Uniquify Instances icon on the schematic tool bar.

To uniquify a module you must select one or more instances in that module. The commandonly works on the instances in the displayed module. Other instances of the module may existat other levels of the design, but you must go to that level to make the change. You canperform a search to locate all the instances of a module and to find the names of theinstances.

You can have multiple instances of the same module. When you make a change to the parentmodule the change is reflected in all of the instances.



Displaying Logic Cones

Fanin and fanout logic cones can be displayed for pins and pin attachments on instances andports. The task below is for instances, but the procedure is the same for pins and ports.

1. Click right mouse button on an instance to display the pop-up menu (refer to InstancePop-Up Menu), move cursor to Fanin Cone, and highlight the desired input or output.Release the mouse button.

2. The logic cone path is highlighted.



Extracting Logic Cones

In Ambit BuildGates synthesis, a fanin cone is the logic feeding into a specified port or pin,and a fanout cone is the logic emanating from a specified port or pin. A section of the netlistspecified by the fanin or fanout cone of a selected object may be extracted and written out toa new module. A pin starting point must be specified: input pin for fanout and output pin forfanin. For a bus, the pins are displayed in the drop down list for selection.

The procedure below is for a fanin cone; the process is the same for a fanout cone.

1. Display the part of the netlist that contains the current module. Zoom in to the scale youprefer.

2. Click right mouse button in the schematic background to display the “Commands Pop-Up Menu” on page 120; move cursor to Extract Fanin Cone. Release the mousebutton.

3. The extract bar, shown in Figure 5-7, is displayed between the module bar and theschematic.

Figure 5-7 Extract Bar

4. If desired, select to extract only sequential elements. Default is only combinationalelements.

5. Click left mouse button on a pin; the pin name is written into the text box. (Or, you canenter a pin name in the text box.)

6. Click Extract Fanin. An informational message is displayed on the console stating thatthe extraction was performed.

7. To display the new module created by the extraction, select Rebuild Tree from the ModuleBrowser Pop-Up Menu.

In the schematic, the individual cones are grouped and replaced by a new module. Thecontents of the new module are displayed at a lower level of the design. The name of the newmodule is automatically assigned and based on the name of the module from which the conewas extracted. For fanin cones, the naming convention is: module_name_fin_n, where n isan integer starting with zero (0, 1, 2....). For example, the first fanin cone extracted for a

Close PanelDraw



module named “decode” is decode_fin_0 . Similarly, for fanout cones, the namingconvention is: module_name_fout_n.

The process must be repeated for each cone extracted. To extract a group of cones, you mustfirst group the instances using the Group Instances button. The ac_shell equivalentcommands do_extract_fanin and do_extract_fanout , allow multiple extractions in asingle command.



Displaying Port Constraints

1. Click right mouse button on a port to display the pop-up menu (refer to Table 5-7 onpage 123); move cursor to Show Constraints. Release the mouse button.

2. The port timing constraints are displayed (see Figure 5-8).

Figure 5-8 Sample Port Timing Constraints Listing



Printing a Schematic

A schematic can be printed to a postscript file or to the default printer (specified in File–Printer Setup). You specify whether to print the full module schematic or just the currentdisplayed view using View–Schematic Preferences–Printing–Scaling). The defaultscaling value is full page. In addition, page size, orientation, number of pages of a multi-pagemodule, and color parameters can be specified; refer to Table 3-12, “SchematicPreferences:Printing Options,” on page 57.

Set Print Scaling to Current View:

1. Select View–Schematic Preferences–Printing–Scaling–Current View.

2. Click Apply.

3. Click Ok.

Print to a File:

1. Display the part of the netlist that you want to save to a file. Zoom in to the scale youprefer.

2. Click left mouse button on Save Schematic icon on the schematic tool bar.The Save a File dialog box is displayed.

3. Enter the path and file name to save the schematic.

4. Click Ok.

Print to the Default Printer:

1. Display the schematic module that you want to save to print.

2. Click left mouse button on Print Schematic icon on the schematic tool bar.



6Setting Constraints

The logic synthesis process requires two user inputs: a functional (RTL) model of the designand a set of constraints on the design. The constraints are divided into two groups: timingconstraints and physical constraints. There are no user-specified constraints for design areabecause a design with smaller area (gate count) is always preferred over a design with largerarea, when all other characteristics (e.g., timing) are the same. Cadence® synthesis toolsalways strive for the smallest possible design area given timing and physical constraints.

The purpose of this chapter is to briefly introduce the concept of setting timing constraints Forcomplete information on the methodology of setting constraints, refer to Setting TimingConstraints in the manual Timing Analysis for Ambit BuildGates Synthesis andCadence PKS. For complete definitions of all timing commands and their options, pleaserefer to the Timing Analysis Commands chapter of the Command Reference for AmbitBuildGates Synthesis and Cadence PKS.

Units in Constraints

The values used in constraints represent many different quantities. Cadence synthesis toolsare “unitless” tools in the sense that when the quantities, whether constant or variable, arespecified in consistent units, there is no need to explicitly mention units.

The data in the technology library is stored in appropriate units for delay, load, drive,capacitance, etc. All data you supply must be consistent with these units for thecorresponding quantities.

Timing Constraints

Timing constraints guide the Cadence synthesis software to achieve specified performancein the resulting netlist. Performance generally refers to the maximum clock frequency at whichthe design implementation (netlist) can operate and the critical paths in the design.


Ambit BuildGates Synthesis User GuideSetting Constraints

Timing Analysis

Timing constraints can be thought of as timing specifications placed on certain module ports.The timing specification on an input port is referred to as signal arrival time; the timingspecification on an output port is referred to as signal required time. All timing constraintsare associated with an ideal clock.

Timing analysis is an integral part of logic synthesis and is performed to ensure that all timingspecifications are met. Cells are selected from technology libraries based on their functional,timing, and technology characteristics to achieve the goals set up by constraints. The timinganalyzer is built-in as part of the synthesis program and guides the cell selection process tosatisfy all the timing requirements.



7Optimizing Before Place-and-Route

This chapter describes the flow and the commands used to invoke and control variousoptimization stages before place-and-route to produce a desired netlist. Logic optimizationplays a key role in synthesis and consists of several processes, including: booleantransformations, flattening, structuring, technology-independent and -dependent mapping,hierarchical optimization, and context derivation.

The purpose of this chapter is to familiarize you with the commands used to optimize beforethe place-and-route stage, consequently, only a subset of the optimize commands is providedby way of example. The optimize examples in this chapter are presented in command lineinput format; GUI instructions are not provided. In addition, the example syntax may notinclude all possible options; the syntax shown is for example only.

For complete descriptions of all commands and their options, please refer to the CommandReference for Ambit BuildGates Synthesis and Cadence PKS. For information ontiming constraints, refer to Timing Analysis for Ambit BuildGates Synthesis andCadence PKS.

The hierarchical block diagram shown in Figure 7-1 will be used throughout this chapter toillustrate the use of various optimization commands.

Figure 7-1 Hierarchy of an Example Block

des_top

unit1 unit2

blk11 blk12 blk21 blk22 blk23


Ambit BuildGates Synthesis User GuideOptimizing Before Place-and-Route

The logic synthesis process can be thought of in two steps: technology-independentoptimization followed by technology-dependent mapping and optimization.

After the HDL modules are read, the functions (operations) are mapped to Ambit TechnologyLibrary (ATL) cells and eXtended Ambit Technology Library (XATL) cells using thedo_build_generic command. Some of the complex operations (e.g., addition,subtraction, increment) are also mapped to cells in AWACL components. If you have a licensefor the datapath option, a different set of components are used during mapping (refer toDatapath Synthesis on page 14 for a description of the datapath option).

For all the modules read in, a technology-independent netlist mapped to cells in ATL andXATL libraries is created. If a module description has not been read in, but the instance ofsuch modules exist in other module descriptions that make up the design, such instances aretreated as black boxes until the corresponding modules have been read and linked with therest of the design.

Running do_optimize Command

The simplest way to optimize your design is with the do_optimize command. Thedo_optimize command runs a series of do_xform_ commands that provide a basic andthorough optimization routine. Figure 7-2 provides a diagram referred to as the “onion,” whichshows the ”layers” of do_xform_ commands run by do_optimize. Command nameswithin the layers of the onion are transforms and have a prefix of do_xform_ . For example,“propagate_constants ” in the do_xform_optimize_generic layer is actuallydo_xform_propagate_constants .



Figure 7-2 Layers of the do_optimize “Onion”

As shown in Figure 7-2, the do_optimize command runs the following four transforms,which in turn (with the exception of do_xform_map ) run additional transforms:

■ do_xform_optimize_generic

■ do_xform_map

■ do_xform_optimize_slack

■ do_xform_timing_correction

For detail on the transforms, refer to Optimizing with Logic Transforms on page 155.

The do_optimize command applies to the hierarchy in and under the current module, asset by the set_current_module command (for further information on this command, seeUnits in Constraints on page 141). The results of optimization are stored in the database andare retrieved using the report_ and write_ group of commands.

propagate_constants

remove_redundancy

structure

map

restructure

clone

resize

buffer

reclaim_area

fix_design_rule_violations

do_xform_optimize_genericdo_optimize command

do_xform_optimize_slackdo_xform_timing_correction

Note: Command names within the layers of the onion are transforms and have a prefix of do_xform_.



The syntax of the do_optimize command is extensive and is defined in the CommandReference for Ambit BuildGates Synthesis and Cadence PKS.

Top-Down Optimization

Typically, designs that are not very large can be fully optimized in a single run. In this case,optimization is performed from the top level without first individually optimizing lower levelmodules. This process is referred to as top-down optimization.

The following commands are useful in top-down optimization:

■ do_build_generic

■ do_optimize

■ set_dont_modify

■ do_dissolve_hierarchy

■ do_uniquely_instantiate

Details of these commands are provided in this chapter and in the Command Reference forAmbit BuildGates Synthesis and Cadence PKS.

Bottom-Up Optimization

When a design is very large, it may take too long to synthesize the entire design in a singlerun. In this case, lower level modules can be optimized individually first with constraintsderived from top level constraints. These optimized lower level modules are then “stitchedtogether” and marked dont_modify . Then the next level of hierarchy is optimized until alllevels up to and including the top level are optimized. This process is referred to as bottom-up optimization.

The following commands are useful in bottom-up optimization:

■ do_build_generic

■ do_derive_context or do_time_budget

■ do_uniquely_instantiate

■ set_dont_modify

■ do_optimize



Details of these commands are provided in following sections of this chapter.

Deriving Constraints from Context

A context-based optimization requires that constraints for lower level modules be derivedfrom the higher level modules. That is, constraints set at the top level of the design are pusheddown the hierarchy so that each lower level module is optimized with the correct set ofconstraints. This approach is the basis for bottom-up synthesis.

The syntax for the command to derive constraints from each instance’s environment is asfollows:

do_derive_context [ instance_list ]

where:

instance_list is a list of hierarchical entities for which the context is derived. Thederived constraints are applied to the modules referred to by the instances in this list.

The context is derived by extracting the interface timing constraints and electrical constraintsfrom the surrounding environment of the instances specified in instance_list . Ifinstance_list is not provided, context is derived for the current module.

The instance_list may contain hierarchical path names, in which case the context isderived for those instances in the hierarchy. Each instance must have been uniquelyinstantiated using the do_uniquely_instantiate command if the module whenreferences has more than one instantiation.

The interface timing constraints include timing information about clock definitions, arrival timeon input ports, required time on output ports, and identification of multi-cycle and false paths.Electrical constraints include port capacitance and resistance, number of drivers, and load foreach port.

The derived context information is stored in the database, written out using thewrite_assertions command, and used to synthesize the individual modules.

For more information on deriving constraints from context, refer to Deriving the TimingContext for a Module in the Timing Analysis for Ambit BuildGates Synthesis andCadence PKS.



Time Budgeting

Time budgeting is the process of splitting the combinational delay requirements acrossmodule boundaries to allocate slack across all modules in a balanced manner. It allows youto start with initial time budget values rather than constraints derived from context, whichenables fewer synthesis iterations and quicker convergence to target performance. The timebudgeting is applied to the entire hierarchy below the current top level.

Note: For complete information on time budgeting, refer to “Bottom-Up Top-DownMethodology” in the “Choosing a Methodology” chapter in the Timing Analysis for AmbitBuildGates Synthesis and Cadence PKS.

The syntax for time budgeting command, do_time_budget , is as follows:

do_time_budget [ -top list_of_top_instances ] [ instance_list ]

where:

■ instance_list is a list of hierarchical entities that will be resynthesized after timebudgeting has been performed. Instances in this list should be sub-designs of instancesin list_of_top_instances.

■ -top list_of_top_instances is a list of instances from which to start thesynthesis. Only sub-designs under the list of specified instances are synthesized.

Blocks that cannot be change, (therefore will not be resynthesized), should not be on the timebudget list. This situation arises when certain blocks are treated as “Intellectual Property” (IP)blocks, or that need to be retained “as is” for various legacy or compatibility reasons.

The synthesis strategy with time budgeting is similar to characterizing the blocks, writingscripts and resynthesizing the blocks. The significant difference is that the time budgetingalgorithm automatically distributes the slack evenly on paths across multiple modules. Thesenew constraints are written out in a script form using the write_assertions command forthe next iteration of synthesis. The slack distribution strategy employed by thedo_time_budget command reduces the number of synthesis iterations required to reachthe target.

The time budgeting step performs time budget for paths with positive slack as well as negativeslack. In case of paths with positive slack, the time budget step ensures that the newconstraints will not cause negative slack. In case of paths with negative slack, the time budgetstep ensures that the new constraints will not make new negative slacks worse than theoriginal negative slacks.

The slack time is redistributed on arrival times and required times at various ports/nodes inthe path proportional to the delay of the path through an instance compared to the total pathdelay.



It is possible to use the set_data_budget_time command to force arrival and requiredtimes on particular pins. Such situations arise when hard-coded time budgets are requireddue to specific design requirements. When time budgeting is performed, the forced values willoverride the automatic slack allocation, thereby providing manual control over the automatictime budgets.

For example, in Figure 7-3, if path1 has a positive slack of 3ns and the delay through I1 istwice as long as the delay through I2 , the required time for I1 / p1 will get positive slack of2ns and I2 / p2 will get positive slack of 1ns.

Figure 7-3 Example of Slack do_time_budget Resultsplace-and-route

If a 2 ns delay is forced at I2 / p2 port (using the set_data_budget_time command), thenthe arrival time will have a slack of only 1ns at I1 / p1 .

The do_time_budget command generates (derives) constraints for all ports of theinstances in the instance list and saves them in the database. These constraints must bewritten out using write_assertions command. The new constraints files may then beused to resynthesize the instances I1 , I2 , I4 , and I5 .

Preserving Module Contents

Use the set_dont_modify command to preserve the optimization applied to modules,instances, or net.

The command syntax is as follows:

positive slack path

negative slack path

I1 I2 I3

I4 I5

do_time_budget { I1 I2 I4 I5 } // I3 is an IP block

path1

path2

p1 p2



set_dont_modify [-network] [-hierarchical] list_of_object_id

where:

■ list_of_object_id is a list of input ports or output instances, nets, or instancepins to preserve.

The ports must be input ports and instance pins must be output pins. When ports or instancepins are specified, it is equivalent to applying set_dont_modify on the net connected tothe port or instance pin. In effect, this command instructs the software to not modify the netconnected to the port or pin during the optimization process.

The -network option specifies the network connected to each port or net. The specifiednetwork is identified by traversing forward through all the nets starting from the port or drivingpin of the specified net. The path goes through the combinational cells to which the netsconnect and follows the output nets of the combinational cells until reaching a sequential cellor a black-box component. All nets and components on the specified network are marked asdont_modify during the optimization phase.

Using the -hierarchical option, the traversal is continued at lower levels of hierarchy inthe current module to preserve the network. If the -hierarchical option is not used, onlythe network visible at the current module is preserved; the network inside the hierarchicalinstances in the current module may be modified.

Due to its global nature, the clock network or reset network is frequently designed manually(i.e., routing, load balancing, etc.) and must be preserved throughout the optimizationprocess. For example, consider the block diagram shown in Figure 7-4, where the effect ofthe following command is shown in the highlighted path.

set_dont_modify -network -hierarchical rst

Figure 7-4 Example of Preserving a Net Using the set_dont_modify Command

rst

I1 I2

I3

I4

n1

n2



If the -hierarchical option was not used in the example above, the highlighted path in theinstance I4 (shown by the dotted line) and the nets n1 and n2 would not be preserved.

The following command preserves the clock network (connected to clk port) in des_topand its submodules:

set_dont_modify -network -hierarchical clk

If a module or list of modules is specified, the entire module(s) is marked for no modificationduring the optimization phase. Then, if the -hierarchical option is used, all the instancesin the current module are traversed recursively and the corresponding modules are markeddont_modify . Once a module is marked for no modifications, you cannot applythedo_uniquely_instantiate or do_dissolve_hierarchy commands on themodule. Lower level modules in the hierarchy of a dont_modify are implicitlydont_modify.

Preserving modules is also useful to maintain cells (macros, mega-functions, RAM, etc.) fromthe library. For example, to preserve a hand-built RAM module, use the following command:

set_dont_modify -hierarchical myRAM

An instance or list of instances can be marked dont_modify . The modules referenced bythese instances are implicitly dont_modify .

For example, if blk22 is an instance of a counter that you want to preserve in the hierarchy,use the following command:

set_dont_modify blk22

Uniquifying Instances

When a module in the design is instantiated more than once, each instantiation may have adifferent environment. In such cases, one instance may need to be optimized differently fromanother by placing different constraints on each. Therefore, each instance must be uniquelyassociated with a module.

The following command creates a unique module for each of the instances:

do_uniquely_instantiate [-hierarchical] [instance_list | module_list ]

where:

■ instance_list is a list of instances to be instantiated uniquely.

■ module_list is a list of modules to be instantiated uniquely.



Each instance in the instance_list is now referenced by a unique module, so thatdifferent constraints can be applied on each module and different transforms may beperformed on each module. If instance_list is not specified, unique modules will begenerated for all instances referring to the current module as set by theset_current_module command. The modules that contained the uniquely instantiatedinstances will be modified to reflect the change in binding of the instances to their respectiveunique modules.

If the - hierarchical option is used, all instances in the hierarchical tree of each instancein the current module are associated with uniquely created modules.

For example, if blk11 and blk23 are instances of an adder (mod_adder ) that needdifferent constraints during optimization, the command is as follows:

do_uniquely_instantiate blk11 blk23

or, if blk11 and blk23 are the only two instantiations of mod_adder:

do_uniquely_instantiate mod_adder

After the unique module names have been generated, the two instances will appear asfollows:

mod_adder_0 blk11(…port connections…);

mod_adder_1 blk23(…port connections…);

where mod_adder_0 and mod_adder_1 are the names of the unique adder modulescreated from mod_adder .

Timing optimizations can be performed on an instance only if it is uniquely instantiated. Allnon-uniquely instantiated modules are implicitly treated as a don’t modify condition.

Collapsing Hierarchy

Hierarchies in the design tend to restrict optimization in that logic across the boundariescannot be combined or restructured. Therefore, flattening a hierarchy can produce betterresults. Moreover, too many small hierarchies tend to produce inferior results and createunnecessary overhead CPU time.

The do_dissolve_hierarchy command dissolves hierarchical instances of modules byflattening the hierarchy of the instance. The command syntax is as follows:

do_dissolve_hierarchy [-hierarchical] [instance_list | module_list ]

where:



■ instance_list is a list of instances whose reference modules are to be dissolvedinto their respective parent modules.

■ module_list is a list of modules to be dissolved to their respective parent modules.

Each instance in the instance_list is expanded into its parent module such that all thelogic in the module referred to by the instance is now in the parent module. For user-specifiedinstances (as opposed to software-generated hierarchies that are dissolved), the new namesof the instances in the parent module are derived by appending a the hierarchical instancename to the original instance name. The hierarchical components inside the modulesreferenced by the instances are now components in the current module.

If the -hierarchical option is used, all hierarchical components are recursively expanded,starting from and including the specified instance or module.

If neither the instance_list nor module_list is specified, but the -hierarchicaloption is specified, all hierarchical components are recursively expanded to flatten the currentmodule. After expansion, the current module will contain only instances of library cells andinstances of modules marked by set_dont_modify command.

If neither module_list nor instance_list is specified and the hierarchicaloption is not specified, all instances referring to the current module are expanded in theirrespective parent modules.

For example, to dissolve unit2 in the design shown in Figure 7-1 , the command is asfollows:

do_dissolve_hierarchy find -instance unit2

The new design will appear as shown in Figure 7-5. Once dissolved, constraints cannot beplaced on unit2 since there is no longer an instance by that name in the design.

Figure 7-5 Design Hierarchy After Dissolving unit2

des_top

unit1

blk11 blk12

unit2_blk21 unit2_blk22 unit2_blk23



Incremental Optimization

In full design optimization, gate-level structures are built from scratch and mapped to thetarget technology. If the design has been synthesized once, the quality of design can beimproved using the incremental optimization approach. In this process, portions of the design(combinational logic, clock net, registers, etc.) can be extracted from the netlist andtransformations applied (resizing drivers, fixing hold time, etc.) to guide the tool for specificimprovements.

The following commands are useful in incremental optimization:

■ do_extract_critical

■ do_extract_fanin

■ do_extract_fanout

■ do_extract_non_critical



■ do_xform_fix_design_rule_violations

■ do_xform_fix_hold

■ do_xform_map

■ do_xform_resize

■ do_xform_structure

Applying Timing Corrections

Once the design is synthesized, certain amount of fine tuning can be done by applyingspecific transformations to the netlist. One such transformation is to improve on the timing ofthe critical path using the do_xform_timing_correction command. The timingcorrections for improving and for fixing late slack have already been applied as part of thedo_optimize command. Re-running this transform may be useful if logic is extracted andchanges are made, or if hold time or design rule violations are ignored during optimizationand require fixing. The do_xform_timing_correction command supports thisincremental optimization strategy.

The syntax of the do_xform_timing_correction command is extensive and is definedin the Command Reference for Ambit BuildGates Synthesis and Cadence PKS.



8Optimizing with Logic Transforms

This chapter provides a basic understanding of the logic optimization transforms. It assumesa basic knowledge of programming Tcl and familiarity with the logic optimization process.

The purpose of this chapter is to familiarize you with the transformation commands used inoptimization, consequently only a subset of the possible transforms is provided as examples.The examples in this chapter are presented in command line input format and may not includeall possible options; the syntax shown is for example only. For complete descriptions of allcommands and their options, please refer to the Command Reference for AmbitBuildGates Synthesis and Cadence PKS. For information on timing constraints, refer toTiming Analysis for Ambit BuildGates Synthesis and Cadence PKS.

Introduction to Transforms

A transform is a command that changes or transforms the structure of the logic in the currentdesign. During optimization, transforms are used repeatedly to reach design goals.Transforms examine the current logic implementation and perform changes that improve thelogic implementation according to a global cost function set by various constraints.

A fundamental advantage of the Ambit® BuildGates® synthesis software is the ability to calltransforms individually during logic optimization. For example, if a designer has taken the timeto structure logic at the RTL level, it is simple to bypass the “structuring” step of logicoptimization by omitting that step in the flow. In other situations it may be advantageous toperform only the buffer-insertion without modifying the cell selection of a netlist.

Transformations are performed only if the resulting netlist continues to meet all of the timingconstraints previously met and if the change to the netlist allows the design to meet additionalconstraints. The transforms do not modify logic if the quality of the netlist is not improved.

Below is a list of BuildGates synthesis transforms:

■ do_dissolve_hierarchy

■ do_optimize

■ do_xform_buffer


Ambit BuildGates Synthesis User GuideOptimizing with Logic Transforms

■ do_xform_clone

■ do_xform_fix_design_rule_violations

■ do_xform_fix_hold

■ do_xform_fix_multiport_nets

■ do_xform_footprint

■ do_xform_map

■ do_xform_unmap


■ do_xform_propagate_constants

■ do_xform_reclaim_area

■ do_xform_remove_redundancy

■ do_xform_resize

■ do_xform_structure

■ do_xform_restructure



The do_optimize command can be replaced by the following do_xform* commands:


■ do_xform_map - heir


Logic Optimization Steps

You can perform logic optimization in different ways using several different approaches. Thissection outlines one possible method that works well in practice. The process of logicoptimization can be broken down into the following steps:

1. Optimizing generic logic

2. Mapping of generic logic to technology-specific logic cells

3. Constraint-driven optimizing of technology-specific logic cells



A description of these steps and the transforms that implement them are included in thefollowing sections.

Optimizing Generic Logic

These optimizations operate on generic technology-independent representations of theunderlying logic of a design and thus minimize generic logic.

The do_dissolve_hierarchy command operates on both generic technology-independent and mapped logic. It is used for small designs or small blocks of unstructuredlogic which span module boundaries. A design which has been dissolved will be structuredall at once during do_xform_structure and care should be taken to insure that theunstructured design is not prohibitively large. The do_xform_optimize_genericcommand dissolves software-generated hierarchies that are smaller than a predeterminedthreshold.

Table 8-1 lists the transforms that operate on technology-independent representations of adesign.

Table 8-1 Transforms—Technology-Independent Representations

Transform Description

do_xform_propagate_constant

Evaluates the value at all input ports, and then if it is aconstant, it propagates that value to all submodules inthe hierarchy. This transform simplifies operations(additions, comparisons, etc.) involving constants andreduces the area of the design.

do_xform_remove_redundancy

Minimizes the logic by removing portions which areredundant or can be expressed using less logic. The-hierarchical option performs this transformationthroughout the design hierarchy starting at the currentmodule.



Mapping and Unmapping of Generic Logic

A single transform performs the mapping step do_xform_map . Each time do_xform_mapis called, portions of the logic are unmapped and then remapped according to the criteriaspecified. Although a single mapping may be sufficient, additional mappings can providemore precision. Table 8-2 defines three mapping passes to illustrate various uses of thetransform.

do_xform_structure Structures logic to exploit common sub-expressions andterms. The operation of this transform is controlled bythe option -priority area|time . The structuringand grouping are different depending on the priorityspecified. It structures logic expressions so sub-expressions and terms can be shared or replicated toimprove area and timing, respectively. If you have spenta lot of effort structuring your logic in the RTLdescription of your design, you may wish to avoid thisstep of logic optimization for a particular module. It isoptional, but needed for good results in most cases.

do_xform_optimize_generic

Performs the following sequence of all-genericoptimizations:

do_dissolve_hierarchydo_xform_propagate_constantdo_xform_structuredo_xform_remove_redundancy

Table 8-2 Mapping of Generic Logic

Mapping Pass Description

do_xform_map -hier Performs a straighforward mapping using theminimum area possible.

do_xform_map -hier -timing Adds the -timing option which directs themapper to perform mappings oncombinational blocks with cell selectionbased on timing.

Table 8-1 Transforms—Technology-Independent Representations, continued




The do_xform_unmap command will undo all of the previous mapping steps and unmaps togeneric gates. Buffering and drive-strength changes to improve timing do not appear in theunmapped resulting logic; however, certain changes in the logic structure (such as cloning)may persist.

Constraint-Driven Optimizing

Table 8-3 lists the transforms that improve the logic speed of critical paths.

do_xform_map -hier -timing-critical_offset 0.1-fanin_depth 3 -fanout_depth 3

Directs the mapper to operate on regions oflogic within 0.1 ns of the critical patha

including 3 levels of logic fanning in or out ofthe critical section/path.

a. The region as defined by the 0.1 -critical_offset range (worst slack) is a dynamic quantity whichchanges as optimization proceeds. Therefore, the size of the interval during each pass of the transform isa function of the worst slack in the current implementation of the design.

Table 8-3 Transforms—Improve the Logic Speed of Critical Paths


do_xform_buffer Inserts buffers that fix design rule violations(excessive fanout, slew-time, etc) on a net or thatimprove timing.

do_xform_clone Clones segments of logic which drive nets with alarge number of fanouts.

do_xform_optimize_slack Performs an iteration of all constraint-drivenoptimizations. It is equivalent to the constraint-driven optimizations done in the do_optimizecommand.

do_xform_reclaim_area Removes buffers, downsizes cells, and removescloned logic without affecting the negative slack inthe design.

do_xform_buffer_tree Inserts buffer trees on all nets.

Table 8-2 Mapping of Generic Logic, continued

Mapping Pass Description



The table below contains the transforms that perform specific applications.

do_xform_fast_optimize Uses a fast algorithm to simultaneously resize cellsand insert buffers to improve timing.

do_xform_resize Resizes the drive strengths of the cells, eitherupsizing or downsizing cells having the samefunctionality.

do_xform_restructure Performs selective re-factorization of logic toimprove timing while ensuring that the negativeslack is not affected. This transform operates on amapped netlist and performs selective unmappingand restructuring on logic in timing-critical regions.

do_xform_timing_correction Iteratively performs the following timingoptimization transformations.

do_xform_reclaim_areado_xform_bufferdo_xform_resizedo_xform_clonedo_xform_fix_design_rule_violationsdo_xform_fix_hold

Table 8-4 Transforms—Perform Specific Applications


do_xform_fix_design_rule_violations

Fixes only design rule violations. This transformmay affect the critical slack, but will solve designrule violations without affecting slack if at allpossible.

do_xform_fix_hold Fixes hold (early slack) violations with minimalimpact on setup (late slack) violations.

do_xform_fix_multiport_net Adds logic to ensure that no “assign” statementsappear in the netlist for nets which drive two portsor pass-through wires from input port to outputport.

Table 8-3 Transforms—Improve the Logic Speed of Critical Paths, continued




Summary Listing of Transform Commands

Table 8-5 groups the transforms by the representations or stages of the design in which theywork. ATL is the abbreviation for Ambit Technology Library (generic logic) and TSC is theabbreviation for Technology-Specific Cells (library elements).

do_xform_footprint This transform is similar to resizing but limited tocells which have the same footprint in the library.

Table 8-5 Transform Command Summary List

Command Description

ATL -> ATL do_xform_propagate_constant

do_xform_structure

do_xform_remove_redundancy

do_xform_optimize_generic

ATL -> TSC do_optimize

do_xform_map

Table 8-4 Transforms—Perform Specific Applications, continued




TSC -> TSC do_optimize

do_xform_timing_correction

do_xform_propagate_constant

do_xform_reclaim_area

do_xform_buffer

do_xform_clone

do_xform_restructure

do_xform_fix_design_rule_violations

do_xform_fix_hold

do_xform_footprint

do_xform_resize

do_xform_optimize_slack

do_xform_fast_optimize

do_xform_buffer_tree

TSC -> ATL do_xform_unmap

Table 8-5 Transform Command Summary List, continued

Command Description



9Optimizing After Place-and-Route

After designs are synthesized to meet timing and design rule constraints, place-and-route isperformed. During place-and-route, accurate capacitance and resistance information isextracted for nets, and precise delays can be calculated for timing arcs. However, deviationsin wire RC from wireload table values can significantly change post-layout timingcharacteristics. As a result, further timing and design rule optimization is often required.

The purpose of this chapter is to familiarize you with the commands used to optimize after theplace-and-route stage, consequently only a subset of the optimize commands is provided byexamples. The examples in this chapter are presented in command line input format and maynot include all possible options; the syntax shown is for example only. For completedescriptions of all commands and their options, please refer to the Command Referencefor Ambit BuildGates Synthesis and Cadence PKS. For information on timingconstraints, refer to Timing Analysis for Ambit BuildGates Synthesis and CadencePKS.

Timing Analysis

The timing environment and constraints may need a slight adjustment after backannotation.Timing adjustments are a result of having more accurate clock tree timing information in thedesign after place-and-route. Handling clock information varies for different flows. Clock treesinserted during the place-and-route stage yield accurate clock timing information previouslynot available. To use the accurate clock timing information during timing analysis andresynthesis, use the following command:

set_clock_propagation propagated

Setting the clock propagation inserts actual timing for all gate and wire delays along clocksignal routes, instead of using the zero delay assumption of the ideal clock. Because the clocktiming is now accurate and skew variances can be sensed for different clock signal arrivalpoints, the amount of clock uncertainty programmed with the set_clock_uncertaintycommand can be reduced or eliminated.

When analyzing backannotated timing information, it is useful to add the load, fanout, andslew fields to the report_timing format. To do this, use the following command:


Ambit BuildGates Synthesis User GuideOptimizing After Place-and-Route

set_global report_timing_format

Other fields can be added to the format as desired. Unexpected large capacitances may beannotated to nets. When this happens, it is helpful to analyze whether the capacitance canbe defrayed by reducing the fanout and how much timing improvement can be made bycorrecting slew rates.

To enhance timing analysis using report_timing , it is recommended that the -net switchbe used to separate the wire RC delay from the cell I/O delay. Wire delays are noted on acell’s input pins, and cell I/O delays are noted on a cell’s output pins.

Backannotating

After the place-and-route stage of the design, extraction tools calculate the capacitance andresistance information for individual nets. This net RC information may be used by a delaycalculator (external to the BuildGates synthesis tool) to create a new timing view of thedesign. Timing information is conventionally stored in a Standard Delay Format (SDF) file.Individual net RC and design SDF timing information is annotated to the design within theBuildGates synthesis software to provide an accurate timing and design rule violation view ofthe design.

It may seem redundant to annotate both RC and SDF timing information, but both annotationtypes are needed. Timing arcs and cell timing checks annotated with SDF override the delaycalculator within the software for the same parameters. Some SDF generators do notannotate all necessary arcs and timing checks, in which case the net RCs are useful forproper delay calculation. Also, SDF annotation does not cover important design ruleconsiderations such as signal slew (or ramp) times and capacitance information.Furthermore, the BuildGates synthesis software accepts only lumped net RC information.Delay calculators that use distributed RC information can calculate unique wire delays foreach receiver on a common net and store the parameters with SDF INTERCONNECTstatements.

A Script Showing the Backannotation of a Design

The following example script shows the reading and backannotation of a design.

# Read timing libraries

set TargetTech [read_alf stdcell_wccom.alf]

set_global target_technology $TargetTech

set_operating_conditions WORST_CASE

# load design



ions,

read_verilog chip.v

do_build_generic

set_top_timing_module chip

set_current_module chip

# Set up timing constraints on the design

source TimingConstraints.tcl

# Annotate Capacitance Information

source WireLoadAnnotation.tcl

# Annotate Resistance Information

source WireResistanceAnnotation.tcl

# Annotate SDF information - Worst Case Timing

read_sdf chip_wc.SDF

# Annotate SDF information - Best Case Timing

read_sdf -min -store_as_min chip_bc.SDF

The list below provides file descriptions for the above example:

■ TimingConstraints.tcl

Contains timing information to set clocks, data arrival and required times, and timing exceptsuch as false and multicycle paths on the design. TheTimingConstraints.tcl file is alsouseful for annotating wire-load models for the design.

■ WireLoadAnnotation.tcl

Contains wire capacitance settings for every interconnect in the design. The followingsyntax is used for annotating wire capacitance:

set_wire_capacitance capacitance_value path_to_net

■ WireResistanceAnnotation.tcl

Contains wire resistance settings for every interconnect in the design. The followingsyntax is used for annotating wire resistance:

set_wire_resistance resistance_value path_to_net

■ set_operating_conditions WORST_CASE

Loads the worst case timing library.

■ read_sdf -max -store_as_max chip_wc.SDF

Stores the worst case timing information.

■ read_sdf -min -store_as_min chip_bc.SDF



Stores the best case timing information.

Both worst case and best case SDF timing information is stored in the above example,although only a worst case timing library is loaded.

Reading SDF Data

The delay data extracted from a physical tool such as a floorplanner or a router can beimported using the Standard Delay Format (SDF) file. The syntax of the command is asfollows:

read_sdf filename

where:

■ filename is the name of the SDF file.

The design name in the SDF file must match the name of the current module. The timing datafrom the SDF file is applied to the current module and its hierarchy. Both the cell delay dataand the interconnect delay data are backannotated in the netlist. The minimum, typical andmaximum delays are used from the SDF file. The backannotated delays overwrite the delaysin the netlist database.

The name matching (of ports, nets, cells, and instances) between the SDF file and the netlistdatabase is case sensitive.

Optimizing to Correct Late and Early Slack

Before optimization begins, each module in the design must have only a single instancereferring to it. If a module is instantiated more than once, modification will not be made to themodule.

To automatically create copies of modules used more than once in the design and to bindinstances to unique modules, use the following command:

do_uniquely_instantiate -hierarchical



As shown in Figure 9-1, chip hierarchy is often organized with various JTAG modules, I/Ocells, and a synthesizable core at the highest level.

Figure 9-1 Common Chip Hierarchy

The synthesizable core contains the majority of the chip logic. The other peripheral modulesand cells at the top level are often manually instantiated. With this hierarchy structure, thepreferred optimization strategy is to use the worst case timing from the constraints applied atthe chip level, but perform all optimization work within the synthesizable core. This isaccomplished by setting the top timing module at the chip level and setting the current moduleto core before invoking the optimization transform.

set_current_module core

set_top_timing_module chip

To optimize the timing of the design by using cell resizing and buffer insertion, use thefollowing transform command:

do_xform_timing_correction -dont_reclaim_area -resize -buffer

Note: For all transforms except do_xform_optimize_slack , only the-dont_reclaim_area option disables all reclaim area. Fordo_xform_optimize_slack , the reclaim area is disabled in the final timing correctionphase.

Area reclamation is disabled to prevent removing buffers and their corresponding annotatednets.

If timing violations are still present after optimization, it is helpful to categorize the types oftiming failures. To report up to 1000 failing timing paths in a design, use the followingcommand:

report_timing -net -max_points 1000 -max_slack 0

Chip

Core Tap BoundaryScan Mod

I/OBuffer

RAM/ROM



After determining the root cause for the failures, it may be necessary to change the physicalplacement of the components to reduce critical path capacitance. More aggressive synthesistransforms, such as do_xform_optimize_slack, can also be used to restructure failingpaths, although annotated timing and parasitic information will be discarded for therestructured components.

To restructure failing paths (and discard annotated timing and parasitic information forrestructured components), use the following command:

do_xform_optimize_slack

Area reclamation with parasitic backannotation is recommended only through resizeoperations and can be performed with the following command before or after fixing late slack:

do_xform_reclaim_area -resize

Early or hold time violations are corrected next. For a full explanation of this process refer tothe Timing Analysis for Ambit BuildGates Synthesis and Cadence PKS, Finding and FixingViolations chapter.



10Report Generation

As the synthesis process transforms the design from its original RTL description to a finaltechnology-mapped netlist that meets all the constraints, information must be captured andanalyzed to see if synthesis goals are being met. This chapter lists the BuildGates synthesisreport generation commands and provides sample reports.

The purpose of this chapter is to familiarize you with the process of generating reports,consequently, only a subset of all of the possible report options are provided in the way ofexample. Most of the report examples in this chapter are presented in command line inputformat. The example syntax may not include all possible options; the syntax is for exampleonly.

For complete descriptions of all report commands and their options, please refer to theCommand Reference for Ambit BuildGates Synthesis and Cadence PKS. Forinformation on generating reports from the GUI, refer to Reports Menu Options on page 61.

The basic BuildGates synthesis report categories are listed below and defined in the followingsections.

■ Timing Reports on page 170

■ Area Reports on page 171

■ Library Reports on page 173

■ Hierarchy Reports on page 174

■ Design Rule Violations Reports on page 176

■ VHDL Library Reports on page 178

■ End Point Slack and Path Histogram Reports on page 180

■ Fanin and Fanout Reports on page 181

■ Finite State Machine Reports on page 184


Ambit BuildGates Synthesis User GuideReport Generation

Report Header

Most of the report print certain common information in a header. This information is intendedto help correlate the reported data with specific version of the software. The header containsthe following information:

■ Command used to generate the report

■ Options used with the command

■ Date and time the command was executed

■ Name of the program used to generate the report (ac_shell )

■ Release and Version number

■ Other relevant information on the specific report

Timing Reports

Below is a list of all timing-related report commands:

■ check_timing

■ report_timing

■ report_annotations

■ report_cell_instance_timing

■ report_clocks

■ report_library

■ report_net

■ report_path_exceptions

■ report_port

Report timing is explained in detail in the Timing Analysis for Ambit BuildGates Synthesis andCadence PKS. Please refer to the Generating and Understanding Timing Reportschapter.



Area Reports

The report for the area of the netlist can be generated using the following command:

report_area [-summary] [-hierarchical] [-cells][{ > | >> } filename ]

where:

■ filename is the name of the generated report file. If filename is given, the report iswritten to the file. If the filename is omitted, the report is displayed on the standardoutput.

If the -hierarchical option is used, the report is created for all the hierarchical modules inthe current module, otherwise only the current module area is reported.

If the -summary option is used, the area report only contains the summary information forthe current module. This is the default option. The summary report includes the followinginformation:

■ Current module

■ Wire load model

■ Cell area

■ Net area

■ Total area

If the -cells option is used, area report is printed on every cell in the current module. Thecell report includes the following information:

■ Summary report for current block

■ Summary report cumulative for the current design hierarchy

■ Name and count of cells used

■ Type of cells used

■ Area for each cell

■ Total cell area

■ Net area

■ Total area



Sample Area Report

Below is a sample area report generated from the following command:

report_area -summary -hierarchical > BG4.0_area_rep.rpt

+-------------------------------------------------------+

| Report | report_area |

|---------+---------------------------------------------|

| Options | -summary -hierarchical > BG4.0_area_rep.rpt |

+---------+---------------------------------------------+

| Date | 20010321.103245 |

| Tool | ac_shell |

| Release | v4.0-eng |

| Version | Mar 19 2001 06:11:48 |

+---------+---------------------------------------------+

| Module | reg8_1 |

+-------------------------------------------------------+

Summary Area Report

-------------------

+----------------------------------------------------------------+

| Module | Wireload | Cell Area | Net Area | Total Area |

|------------+------------+------------+------------+------------|

| reg8_1 | B0.5X0.5 | 84.00 | 13.83 | 97.83 |

+----------------------------------------------------------------+



Library Reports

The report_timing command is a timing-related command and is explained in detail in theTiming Analysis for Ambit BuildGates Synthesis and Cadence PKS. Please refer to theGenerating and Understanding Timing Reports chapter.



Hierarchy Reports

The hierarchy report describes the structural hierarchy as it exists at various stages in thesynthesis process. The hierarchy reported is always that of the netlist in memory, with thecurrent module as the top of the hierarchy. The command syntax is as follows:

report_hierarchy [-inst] [-tcl_list] [{> | >>} filename ]

where:

■ filename is the name of the generated report file. If the filename is omitted, thereport is displayed on the standard output.

The -inst option includes the instance name of the module instantiation in the output.Modules that are multiply instantiated will include a separate line of output for eachinstantiation.

The -tcl_list option reports the hierarchy in the form of a Tcl list.

If the hierarchy report is requested prior to any netlist generation, then RTL hierarchy isshown. If the mapping has been done, the mapped hierarchy is shown. The hierarchy reportuses the following symbols to distinguish hierarchical blocks:

b black box module (no subcomponents)

g generic (unmapped) module.

o optimized module

x “don’t modify” attribute is set for this module

m module contains a mapped view



Sample Hierarchy Report

Below is a sample hierarchy report generated from the following command:

report_hierarchy -inst > BG4.0_hierarchy_rep.rpt

|-cpu(m)||-accum1 -> reg8_1(m)||-alu1 -> alu(m)|||-i_317 -> AWACL_UNS_ADD_8_C(m)||-decode1 -> decode(m)||-ireg1 -> reg8_0(m)||-pcount1 -> count5(m)



Design Rule Violations Reports

The report for the design rule violations of the netlist can be generated using the followingcommand:

report_design_rule_violations [-hierarchical] [-ignore_clknet][-current_module_only] [-verbose] [-ignore_dont_modify_nets] [ { > | >> } filename ]

where:

■ filename specifies the name of the report file. If filename is not specified, thereport is displayed on standard output. filename must be the last argument in the list.

The -current_module_only option reports only the violations in the current module.

The -hierarchical option reports the violations for hierarchical ports.

The -ignore_clknet option prevents the reporting of the clock net violations.

The -ignore_dont_modify_nets option does not report design rule violations for netsthat are set dont_modify .

The -verbose option reports all design rules for every net and port in the design regardlessof whether there were any violations.



Sample Design Rule Violations Report

Below is a sample design rule violations report generated from the following command:

report_design_rule_violations -hierarchical > BG4.0_des_rule_vio_rep.rpt

+-----------------------------------------+

| Report | report_design_rule_violations |

|---------+-------------------------------|

| Options | -hierarchical |

+---------+-------------------------------+

| Date | 20010319.170054 |

| Tool | ac_shell |


| Version | Mar 19 2001 08:19:39 |

+---------+-------------------------------+

| Module | cpu |

+-----------------------------------------+

**** Design Rule Violation Report ****

Module: decode [decode1]

Net: sel_dat

Max Capacitance = 0.60 (i_823:Z [NR2])

Net Capacitance = 0.69

VIOLATION = -0.08

Module: alu [alu1]

Net: n_145

Max Capacitance = 0.29 (i_6:Z [NR4])


VIOLATION = -0.25

Module: cpu

Net: n_648

Max Capacitance = 0.60 (decode1:sel_dat [decode])


VIOLATION = -0.08

3 violation(s) found.



VHDL Library Reports

The report for the VHDL library for the design is generated using the following command:

report_vhdl_library [-verbose] [library] [{ > | >> } filename ]

where:

■ filename is the file to which the report is written.

■ library lists the mapping for the specified VHDL library.

The report_vhdl_library command lists the mappings between all the defined VHDLlibraries and the directories to which they are mapped. This command can be used to checkwhere BuildGates synthesis picks up VHDL units such as packages.

The -verbose option lists the contents of the VHDL library.



End Point Slack and Path Histogram Reports

The end point slack and path histogram can only be generated from the GUI. Please refer toEnd Point Slack Histogram Report on page 65 and Path Histogram Report on page 66 for afull description and samples of the reports.



Fanin and Fanout Reports

The fanin and fanout reports are generated using the following commands:

report_fanin [-level integer] [-tristate] [-sequential] [-hierarchical][{> | >>} filename ] [-maxline integer ] list_of_pin_path_or_id

report_fanout [-level integer] [-tristate] [-sequential] [-hierarchical][{> | >>} filename ] [-maxline integer ] list_of_pin_path_or_id

where:

■ filename is the name of the generated report file. If filename is given, the report iswritten to the file. If the filename is omitted, the report is displayed on the standardoutput.

■ list_of_pin_path_or_id is the Tcl list of pin or port path names or objectidentifiers on which to start the fanin or fanout cone search.

The -hierarchical option allows the command to traverse backwards across hierarchyboundaries to generate a report. By default for fanin, it will stop at the input port and it willreport on the fanin path starting from that port (treated as the start point). By default for fanout,it will stop at output ports and report the fanout path ending at that port (treated as the endpoint).

The -level option specifies the number of levels which need to be traversed for generatingthe report.

The -maxline option specifies the number of lines which need to be traversed forgenerating the report.

The -tristate option includes the tristates in the path.

The -sequential option includes the sequential cells in the path. By defaul, the reportingstops at the first sequential cell in the path.



Sample Fanin Report

Below is a sample fanin report generated from the following command. The fanout report issimilar and is not shown.

report_fanin -level 3 -hierarchical address > BG4.0_fanin_rep.rpt

+-----------------------------------------+

| Report | report_fanin |

|---------+-------------------------------|

| Options | -level 3 -hierarchial address |

+---------+-------------------------------+

| Date | 20010319.075258 |

| Tool | ac_shell |


| Version | Mar 19 2001 13:27:20 |

+---------+-------------------------------+

| Module | cpu |

+-----------------------------------------+

+------------------------------------------------------------+

| Level | From(Instance/Pin) | To(Instance/Pin) | Net |

|-------+--------------------+------------------+------------|

| 1 | ireg1/r[5] | i_8/A | iraddr[4] |

| 2 | i_8/Z | address[4] | address[4] |

+-------+--------------------+------------------+------------+

| 1 | pcount1/q[5] | i_8/B | pcout[4] |


+-------+--------------------+------------------+------------+

| 1 | decode1/sel_adr | i_8/S | n_670 |


+-------+--------------------+------------------+------------+

| 1 | ireg1/r[4] | i_9/A | iraddr[3] |


+-------+--------------------+------------------+------------+

| 1 | pcount1/q[4] | i_9/B | pcout[3] |


+-------+--------------------+------------------+------------+



+-------+--------------------+------------------+------------+

| 1 | ireg1/r[3] | i_10/A | iraddr[2] |




+-------+--------------------+------------------+------------+

| 1 | pcount1/q[3] | i_10/B | pcout[2] |


+-------+--------------------+------------------+------------+



+-------+--------------------+------------------+------------+

| 1 | ireg1/r[2] | i_11/A | iraddr[1] |


+-------+--------------------+------------------+------------+

| 1 | pcount1/q[2] | i_11/B | pcout[1] |


+-------+--------------------+------------------+------------+



+-------+--------------------+------------------+------------+

| 1 | ireg1/r[1] | i_12/A | iraddr[0] |


+-------+--------------------+------------------+------------+

| 1 | pcount1/q[1] | i_12/B | pcout[0] |


+-------+--------------------+------------------+------------+



+------------------------------------------------------------+



Finite State Machine Reports

The report for finite state machine (FSM) is generated using the following command:

report_fsm [-vector vector_name ] [-state_table] [-encoding] [-hierarchical][{> | >>} filename ]

where:

■ vector_name is the state vector name. If not specified, all FSMs in the current moduleare reported

■ filename is the name of the generated report file. If omitted, the report is displayed onthe standard output.

The -state_table option extracts a state transition table in a report form.

The -encoding option reports all state assignments for each selected FSM.

The -hierarchical option reports all FSMs in any module in the downward path of currentmodule.

If none of the above options are specified, a summary report with the following information isprinted:

■ Design (module) name, state vector name, file name and the line number at which it wasfound in the RTL model

■ Number of states in this FSM, initial state, equivalent states, unreachable states, terminalstates, preserved states, and number of transitions (arcs)

■ Number and name of inputs to this FSM, unused inputs and hold signal

■ Number and name of outputs from this FSM

■ Clock signal and edge (rising or falling) that controls transitions in this FSM

■ Encoding used, encoding size, whether any unreachable states were removed or anystates were merged

For information on finite state machines, refer to Finite State Machine Structure andOptimization chapter in the HDL Modeling for Ambit BuildGates Synthesis.



Sample FSM Report

Below is a sample FSM report generated from the following command.

report_fsm > BG4.0_fsm_rep.rpt

+---------------------------------------+

| Report | report_fsm |

|----------------+----------------------|

| Options | |

+----------------+----------------------+

| Date | 20010319.072056 |

| Tool | ac_shell |


| Version | Mar 19 2001 08:19:39 |

+----------------+----------------------+

| Current Module | fsm2 |

+---------------------------------------+

+----------------------------------------------------------+

| Finite State Machine Report |

|----------------------------------------------------------|

| Design | fsm2 |

| State Vector | state_reg |

| File | /ambit/regress/bg/fsm//fsm2.0347.v |

| Line | 31 |

+---------------------+------------------------------------+

| States | 4 |

| Initial states | (Sinit) |

| Equivalent states | (Sinit Sfirst0)(Ssecond1 Sthird1) |

| Unreachable states | <None> |

| Terminal states | <None> |

| Preserved states | <None> |

| Transitions | 10 |

+---------------------+------------------------------------+

| Inputs | 2 |

| Input names | (PI_188 i) |

| Unused inputs | <None> |

| Hold signal | <None> |

+---------------------+------------------------------------+

| Outputs | 1 |

| Output names | (e) |



+---------------------+------------------------------------+

| Clock | clk |

| Sense | rising-edge |

+---------------------+------------------------------------+

| Encoding | <None> |

| Encoding bit length | 3 |

+----------------------------------------------------------+



Customizing Report Column Width

The report table width is scaled to fit the size of the console. The size of the console iscontrolled by the set_global command line_length attribute, which has a default valueof 80 in the console.

In the GUI the line length is computed at startup and set to the width of the console window.If the option View–General Preferences–Console Window–Console Window–WrapLines is enabled, report table width is set to the total number of characters that can fit on oneline. If not enabled, a line length of 512 is set, effectively requiring you to use the horizontalscroll bar to view the report on the console.

The set_table_style command enables the disabling of printing of columns. It alsoenables setting a minimum and maximum size for each column, reversal of the presentationorder, control of left indent, and control of the sorting order of the columns. The syntax is asfollows:

set_table_style -name table_name [-reverse_rows] [-major_sort integer ][-minor_sort integer ] [-max_widths list_of_integers ][-min_widths list_of_integers ] [-indent integer ]



AUsing Tcl within ac_shell and pks_shell

This appendix is a quick-start to the Tcl language and discusses ac_shell and pks_shellconventions that are beyond the scope of the Tcl language.

This appendix contains the following information:

■ The Tcl Language on page 190

■ Procedures on page 190

■ Tcl Variables and Control Structures on page 191

■ Tcl Commands on page 194

■ Error Handling on page 197

There are several good texts on Tcl, including:

■ Practical Programming in Tcl and Tk by Brent B. Welch, Prentice Hall PublishingCompany

■ Tcl and the Tk Toolkit and TCL Reference by John K. Ousterhout, Addison-WesleyPublishing Company

Tcl and the Tk Toolkit is shipped with Ambit® BuildGates® synthesis. In addition, the website www.scriptics.com provides full documentation and an open source Tcl/Tk scriptinglanguage. Also, the website offers professional development tools, services and extensionsfor Tcl.

Note: In BuildGates synthesis syntax, curly braces indicate that you must make a choicefrom a list of arguments separated by OR-bars (see the Preface for clarification). In the Tcllanguage, curly braces mean that the text within the braces are to be interpreted verbatim. Todistinguish between the two functions of the braces, Tcl braces are presented in bold type inthis appendix.


Ambit BuildGates Synthesis User GuideUsing Tcl within ac_shell and pks_shell

The Tcl Language

The Tcl language contains very few rules and most of the complexity that exists can bedeferred until needed (such as substitution rules or regular expression matching). Theac_shell and pks_shell use Tcl as their command and extension languages.

Tcl is based on character strings. A Tcl command is a list of string arguments, and eachcommand returns a string. At this time, Tcl treats numbers as strings until they are evaluated.This will change in future Tcl versions.

Procedures

A fundamental advantage of Tcl is support for user-defined procedures, which correlate withbuilt-in Tcl commands, such as set and if , and with ac_shell commands, such asread_verilog and do_optimize .

Note: The method used to add ac_shell commands to the interface is the same methodused to interactively define a procedure, except that the ac_shell commands are staticallycompiled, and some are bound to C code instead of Tcl code.

For larger designs containing many lines of script, writing procedurally makes the code easierto maintain. For example:

ac_shell> source my_proc.tcl

ac_shell> my_read_library

ac_shell> my_set_constraints

where my_proc.tcl contains the two procedures or commands:

proc my_read_library {} {

#…commands…

}

proc my_set_constraints {} {

# …commands…

}

When sourcing my_proc.tcl , no action occurs. Two new Tcl commands are added to theexisting body of built-in commands and ac_shell commands. When the commands areinvoked, the Tcl engine interprets their code.



Tcl also supports a convenient demand-load mechanism for personal procedures to avoid thefirst source command above. See autoload in a standard Tcl reference book for moredetails.

Tcl procedures support arguments, such as:

proc my_set_constraints { clock_name period } {

puts “Creating $clock_name with period $period”

# …commands…

}

and arguments with defaults, such as:

proc my_set_constraints { clock_name { period 10 }} {

puts “Creating $clock_name with period $period”

# …commands…

}

This applet approach is recommended and should be extended to the entire synthesis flow.The top-level script should look similar to the code in the following example. Use of a uniqueprefix is recommended to avoid Tcl command name collisions.

Example: Top-Level Script Using the Applet Approach

# Synthesis for block ‘alu’

set design alu

set clock clk2

set period 8

my_set_project_globals

my_read_library

my_read_design_files $alu

my_set_default_time_budget $clock $period

# …commands…

Tcl Variables and Control Structures

Variables

Like most shells, Tcl allows for defining, modifying, and referencing variables, and using thesevariables in control structures.



There are no reserved shell variables in ac_shell . Tcl variables have no restrictions. Theset_global and get_global commands in ac_shell handle all of the global settingsthat affect synthesis operations. These commands are described in the Command Referencefor Ambit BuildGates Synthesis and Cadence PKS.

Character Strings

A variable has no type (everything is a character string), and does not need to be declared.The first occurrence is equivalent to the declaration.

ac_shell> set myvar 100

ac_shell> puts $myvar

100

ac_shell>

A variable has a global scope if the first occurrence of the variable is in the global context (notinside a procedure). If the first occurrence of a variable is inside a procedure, then it hasscope of that procedure and will not conflict with another variable having the same name in adifferent scope. The commands global, upvar, and uplevel allow the use of variablesacross scopes.

Using the $ Prefix

Use the $ prefix to get the value of a variable. In Tcl, placing the $ in front of a variable causesthe value of a variable to be substituted for that variable. This is shown in the followingexample:

set x 1

if { $x == 1 } {

# …

} else {

# …

}

Some commands use the variable value, as in the If statement above. Other commandsrequire the name of a variable as an argument (usually so they can modify it) as follows:

ac_shell> puts $x

1

ac_shell> incr x

2



Syntax

Tcl terminates all commands (built-in or user-defined) when it reaches a newline character ora semicolon in a line. The trailing left-brace in the if-else statement above is a mandated Tclstyle. Using the open brace before the new line character indicates that the text should beread as one argument to the if command.

Variables may also be used to hold lists of items, which can be defined recursively

ac_shell> set y { a b { c d }}

a b { c d }

ac_shell> foreach val $y { puts “$val” }

a

b

c d

Use double quotes to group items together with (one pass of) substitution, and curly bracesto group items together without any substitution.

ac_shell> set val 4

ac_shell> puts “$val”

4

ac_shell> puts $val

4

ac_shell> puts { $val }

$val

Note: In Tcl, the square brackets ([ ]) contain commands which are evaluated and returnvalues. In ac_shell , square brackets indicate bus indices.

Tcl supports the standard C language arithmetic operators, and also performs comparisonson numbers and strings, according to C language definitions. For example, use == to performa string comparison and use expr (Tcl command) to evaluate an expression:

ac_shell> set_port_capacitance [expr { 1 + 0.4 } ] {out[2]}

Note: Because Tcl treats square brackets ([ ]) differently, using square brackets whenreferring to a single bit of a bussed net requires enclosing the expression in braces ({ } ). Ifbraces are not used, the literal value of the calculated expression is given. This is similar tothe backquote in C-shell (see examples below).

The following results in an error:

ac_shell> set_port_capacitance [expr { 1 + 0.4 } ] out[2]



invalid command name “2”

The following examples show control structures:

while { $x == 1 } {

# ‘break’ and ‘continue’ are supported in ‘while” and ‘for’ loops

}

for { set i 0 } { $i < 10 } { incr i } {

puts $i

}

switch $x {

0 { puts “got a zero” }

1 { puts “got a one” }

default { puts “default case” }

# no break statements are needed in Tcl switch

}

Tcl supports associative array variables using the array command. Complex Tcl coderequires associative array variables.

Tcl Commands

find Command

The find command identifies pieces of a design by name or by partial name regularexpression, especially when setting constraints.

The Tcl language supports two methods of pattern matching: glob and regexp. The findcommand in ac_shell uses the glob style of matching by default, but supports the regularexpression style if necessary using the -regexp option.

The glob style is used in the C-shell for matching file names and supports * , ?, and [] meta-characters. The pattern matches any names that match completely (including wildcardcharacters).

ac_shell> find -port -input clk*

Hierarchical names with wildcards are supported, such as:



ac_shell> find -port -input i*/*/clk_?

The optional regexp style is the same as that used by sed , grep , and lex . It is morepowerful, but slightly different than the glob style in having a richer set of supported meta-characters and in that a match of a substring is sufficient to cause a pattern match.

Commonly used regexp meta-characters are . (a period) which matches any singlecharacter, ^ and $ which match the start and end, and * which matches 0 or more of thepreceding character (or atom in the general case where an atom can be defined withparentheses).

Because matching any substring is sufficient to cause a match with the name, this finds allthe input ports in the current module:

ac_shell> find -regexp -port -input

Beware of issuing a command like this with the -regexp option to identify a port named se :

ac_shell> set_false_path -from \

[find -regexp -port -input se]

Using this command will match all input ports containing the string se . Instead, use thestart and end meta-characters, enclosed in curly braces to prevent the Tcl engine frominterpreting them itself:

ac_shell> set_false_path -from \

[find -regexp -port -input { ^se$ } ]

get_names Command

The get_names command is similar to the find command in that it returns a name from anobject_id . The object_id is an ac_shell (not Tcl language) convention of assigning aunique integer to every design object, much like a pointer or handle. The find commandgoes from name to object_id , and get_names goes back:

ac_shell> find -port out

27462

ac_shell> get_names 27462

out

ac_shell> get_names [find -port out]

out



Most ac_shell commands that take a list of identifiers accept either names or object ids,since they are unambiguous (names cannot start with a number). Never enter numericalobject ids manually.

Abbreviating Commands

Tcl allows command name abbreviations, but the abbreviation must be unique. Theac_shell command argument handling also follows this rule, which is helpful for interactiveuse. However, when writing project scripts it is a good idea to use the full command andargument names to avoid an ambiguity with new commands in a later release of the productor when additional user procedures have been defined.

Searching for Commands

When executing a command, Tcl searches a list of built-in commands, ac_shellcommands, and user-defined procedures. Failing a match, it invokes a system call using thecommand, if it finds it in your path. This is very useful but can be confusing if you did notexpect a system call to take place, especially if you are not aware of the command in yourUnix path. Also, note that Unix shell features such as expanding ‘~’ to your home directory,are not available using this mechanism.

Accessing Environment Variables

Access environment variables using the global env Tcl array:

ac_shell> puts “Home directory is $env(HOME)”

Returning Unix Command Values

Obtain return values of Unix commands using the exec command:

set mydir [exec pwd]

-or-

set mydir [pwd]

cd $mydir



Error Handling

Any Tcl procedure (including your own) may call the Tcl error command. Most ac_shellcommands will call error when invoked with illegal syntax, or for other fatal errors such asfile-not-found.

When sourcing a script from either the command line of ac_shell or the source command,interpretation will stop if any command reports an error.

If you anticipate that invoking a command may return an error, then you should use one of thefollowing two methods:

■ Invoke ac_shell using the -continue flag

When an error is encountered ac_shell returns to the ac_shell prompt (no furthercommands are processed). The flag is used to prevent ac_shell from exiting upondetection of an error when invoking the ac_shell command through a script. The-continue flag only applies to the script sourced upon starting ac_shell using the-f option. For example,

ac_shell -continue -f run.tcl

The flag does not have any effect on subsequent scripts sourced from the ac_shellprompt.

Note: The command line option -continueOnScriptError is the same as the-continue flag and is still supported.

■ Use the Tcl catch command.

This is the preferred method because it allows more control over error handling. Forexample, if you refer to a file call_run.v that may not exist, you can do the following

ac_shell> set err [catch { read_verilog call_run.v } msg]

The variable err is set to 0 (success) or 1 (failure), and the optional variable msg is setto the error message that is produced by read_verilog , if one exists.



BQuick Reference

This appendix provides two methods of equating ac_shell commands to GUI menucommands. Table B-1 through Table B-12 are ordered according to the GUI menu in whichthe commands are presented. Table B-13 is an alphabetical list of ac_shell commands andthe corresponding GUI menu command.

Table B-1 Main Menu – File and ac_shell Equivalents

GUI Option/Command ac_shell Equivalent

New do_remove_design -all

Open read_adbread_alfread_verilogread_vhdlread_edifread_ctlfread_pdef (PKS only)

source tcl_filename

Save write_adbwrite_vhdlwrite_verilogwrite_pdef (PKS only)write_edifwrite_gcf_assertions

SavePreferences none

Save ConsoleLog none


Ambit BuildGates Synthesis User GuideQuick Reference

Printer Setup none

Exit none

Table B-2 Main Menu – Edit and ac_shell Equivalents


Cut none

Copy none

Paste none

Clear clear (Unix command)

User Command none

Table B-3 Main Menu – View and ac_shell Equivalents


Toolbar Hide none

Refresh View none

GeneralPreferences none (including nested options)

SchematicPreferences none (including nested options)

ConsoleMessage Monitor none

Table B-1 Main Menu – File and ac_shell Equivalents, continued




Table B-4 Main Menu – Commands and ac_shell Equivalents


Set OperatingParameters set_operating_parameters

Set TargetTechnology set_global -target_technology

Load DCL Rules load_dcl_rule

Unload DCLRules unload_dcl_rule

Check Netlist check_netlist

Check Timing check_timing

Check Test Rules check_dft_rules

Build Generic do_build_generic

Optimize do_optimize

Table B-5 Main Menu – Reports and ac_shell Equivalents


Timing report_timing

Area report_area

Library report_library

Hierarchy report_hierarchy

Design Rules report_design_rule_violations

VHDL Library report_vhdl_library

End Point SlackHistogram none

Path Histogram none



The Main Menu – Window commands are accessed through icons on the editor and viewertool bars. The table below lists only the GUI options/commands that have ac_shellequivalents.

The table below lists only the GUI module browser options/commands that have ac_shellequivalents.

Table B-6 Main Menu – Window and ac_shell Equivalents


Save and Parse write_verilog and read_verilogwrite_vhdl and read_vhdl

UniquifySchematicInstances do_uniquely_instantiate

Table B-7 Main Menu – Help and ac_shell Equivalents


About AmbitBuildGates

ac_shell displays a startup banner when opening

SchematicSymbol Utilities

none

Documentation none

Table B-8 Module Browser and ac_shell Equivalents


Set CurrentModule

set_current_module



The table below lists the only GUI variable browser command that has an ac_shellequivalent.

The table below lists the only HDL editor (within the work area tools area) command that hasan ac_shell equivalent.

The table below lists the only Tcl editor (within the work area tools area) commands that havean ac_shell equivalent.

Set Top TimingModule

set_top_timing_module

Set Don’t Modify set_dont_modify

Reset Don’tModify reset_dont_modify

Table B-9 Variable Browser and ac_shell Equivalent

GUI Command ac_shell Equivalent

set_global set_global

Table B-10 HDL Editor and ac_shell Equivalents


Save and Parse write_verilog and read_verilogwrite_vhdl and read_vhdl

Table B-8 Module Browser and ac_shell Equivalents, continued




The table below lists the constraints tool (within the work area tools area) options/commandsand the ac_shell equivalents.

Table B-11 Tcl Editor and ac_shell Equivalents


Save and Parse save the Tcl file and

source tcl-filename

Table B-12 Constraints Tool and ac_shell Equivalents


Ideal Clock Pop-Up Menu:

Refresh Clock Table none

New Ideal Clock set_clock

Port Clock Pop-Up Menu:

New Port Clock set_clock_rootset_clock_insertion_delayset_clock_required_time

Remove Clock Assertions remove_assertion

Port Constraints Pop-Up Menu:

Show Default Clock none

Toggle Polarity set_clock_rootset_clock_insertion_delay

Create Positive Edge Clock set_clock_rootset_clock_insertion_delay

Create Negative Edge Clock set_clock_rootset_clock_insertion_delay

Report Port Assertion none

Remove Port Assertion remove_assertion



Table B-13 ac_shell Commands and GUI Menu Equivalents

ac_shell Command GUI Menu Equivalent

check_dft_rules Main Menu – Commands –Check Test Rules

check_netlist Main Menu – Commands – Check Netlist

check_timing Main Menu – Commands – Check Timing

clear (Unix command) Main Menu – Edit – Clear

do_build_generic Main Menu – Commands – Build Generic

do_optimize Main Menu – Commands – Optimize

do_remove_design -all Main Menu – File – Open

do_uniquely_instantiate Schematic Editor – Uniquify Instances

load_dcl_rule Main Menu – Commands – Load DCL Rules

read_adb Main Menu – File – Open

read_alf Main Menu – File – Open

read_ctlf Main Menu – File – Open

read_edif Main Menu – File – Open

read_pdef (PKS only) Main Menu – File – Open

read_verilog Main Menu – File – Open

HDL Editor – Open HDL File

read_vhdl Main Menu – File – Open

HDL Editor – Open HDL File

remove_assertion Constraints Tool – Remove Port Assertions

report_area Main Menu – Reports – Area Report

report_design_rule_violations

Main Menu – Reports – Design Rules Report

report_hierarchy Main Menu – Reports – Hierarchy Report

report_library Main Menu – Reports – Library Report



report_timing Main Menu – Reports – Timing Report

report_vhdl_library Main Menu – Reports – VHDL Library Report

reset_dont_modify Module Browser – Reset Don’t Modify

set_clock Constraints Tool – New Ideal Clock

set_clock_root

set_clock_insertion_delay

Constraints Tool – New Port Clock ...Constraints Tool – Toggle PolarityConstraints Tool – Create Positive Edge ClockConstraints Tool – Create Negative Edge Clock

set_clock_required_time Constraints Tool – New Port Clock ...Constraints Tool – Toggle PolarityConstraints Tool – Create Positive Edge ClockConstraints Tool – Create Negative Edge Clock

set_current_module Module Browser – Set Current Module

set_dont_modify Module Browser – Set Don’t Modify

set_global Varible Browser – set_global

set_global target_technology

Main Menu – Commands – Set Target Technology

set_operating_parameters Main Menu – Commands – Set Operating Parameters

set_top_timing_module Module Browser – Set Top Timing Module

source filename Main Menu – File – Open

unload_dcl_rule Main Menu – Commands – Unload DCL Rules

write_adb Main Menu – File – Save

write_edif Main Menu – File – Save

write_gcf_assertions Main Menu – File – Save

write_pdef (PKS only) Main Menu – File – Save

write_verilog Main Menu – File – Save

HDL Editor – Save HDL File

write_vhdl Main Menu – File – Save

HDL Editor – Save HDL File

Table B-13 ac_shell Commands and GUI Menu Equivalents, continued

ac_shell Command GUI Menu Equivalent


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