Altera Altera Technical Technical Solutions Solutions SeminarSeminar

20002000

ScheduleSchedule Opening Opening Introduction Introduction FLEXFLEX®® 10KE Devices 10KE DevicesAPEXAPEX™™ 20K & Quartus 20K & Quartus™™OverviewOverviewDesign Integration Design Integration EDA IntegrationEDA IntegrationIntellectual PropertyIntellectual PropertyDesign IterationDesign IterationDesign OptimizationDesign OptimizationInternet InterfaceInternet InterfaceRoadmapRoadmap Quartus Demo Quartus Demo

AgendaAgendaIntroductionIntroductionFLEXFLEX®® 10KE Devices 10KE DevicesAPEXAPEX™™ 20K & 20K &

QuartusQuartus™™OverviewOverviewDesign IntegrationDesign IntegrationEDA IntegrationEDA IntegrationIntellectual PropertyIntellectual PropertyDesign IterationDesign IterationDesign OptimizationDesign OptimizationInternet InterfaceInternet InterfaceRoadmapRoadmap

u Routing Structure

u CoreSyn™ Synthesis

u Floorplanning

RelativeDelay

0

1

2

3

4

5

6

7

Carry Cascade Local Row Column

Potential Delay GapPotential Delay Gap

0

1

2

3

4

5

6

7

Carry Cascade Local Row Column

MegaLAB Level Eliminates GapMegaLAB Level Eliminates Gap

RelativeDelay

0

1

2

3

4

5

6

7

Carry Cascade Local MegaLAB Row Column

MegaLAB Helps Optimize MegaLAB Helps Optimize SpeedSpeed

EmbeddedEmbeddedSystemSystemBlockBlock(ESB)(ESB)

LAB

16

LAB

1

LAB

2

LELE

LE

LELE

LELELELELE

MegaLAB InterconnectMegaLAB Interconnect

160 LEs of Logic, Plus 2K RAM or 16 Macrocells

MultiCore Performance MultiCore Performance BenefitsBenefits

161 161 MHzMHz

166 MHz166 MHz

16-16-State, 5-Input/ State, 5-Input/ Output State Output State MachineMachine

129 129 MHzMHz 161 161 MHzMHz

FLEX FLEX 10KE10KE

APEX APEX 20K20KFunctionFunction MAX MAX

7000AE7000AE

5 5 x 5 Registered x 5 Registered I/O MultiplierI/O Multiplier 166 166 MHzMHz 59 59 MHzMHz

Embedded Product-Term Embedded Product-Term PerformancePerformance

8.6 ns 4.8 ns

tSU2.9 ns

P-TERM

EPF10K100E-1 EPM7064S-5

tCO4.7 ns

tD1.0 ns

REGLUT REG

tSU0.7 ns

tLAD3.9 ns

REG

P-TERM

APEX 20K-1 Speed Grade

tCO0.2 ns

REGLUT

CoreSynCoreSyn™™ Synthesis Optimizes Synthesis Optimizes MappingMapping

LUTLUTP-TermP-TermMemory

CoreSynSynthesis

PLLPLL

WriteWriteMemoryMemoryControlControl

ReadReadMemoryMemoryControlControl

MemoryMemoryControllerController

Usage ParameterUsage ParameterControl S/MControl S/M

FIFOFIFO

Can Be Performed Can Be Performed Manually or Manually or

AutomaticallyAutomatically

Efficient Floorplan EditorEfficient Floorplan Editor Flexible Editing Capabilities Flexible Editing Capabilities

Multi-Level Undo/RedoMulti-Level Undo/RedoDrag-and-Drop Assignments into Other Drag-and-Drop Assignments into Other

Quartus WindowsQuartus WindowsGrouped Drag-and-DropGrouped Drag-and-Drop

All Nodes Can Be Automatically All Nodes Can Be Automatically Located in Source FileLocated in Source File

Optimization SummaryOptimization Summary Optimize for Density and/or Optimize for Density and/or

PerformancePerformance MegaLAB Provides Higher PerformanceMegaLAB Provides Higher Performance CoreSyn Synthesis for Optimal CoreSyn Synthesis for Optimal

ImplementationImplementation Floorplanner Allows Quick Floorplanner Allows Quick

Identification of Paths and DelaysIdentification of Paths and Delays