All Programmable FPGA, hardware efficiency to software … · 2017. 10. 10. · Software Defined...
Transcript of All Programmable FPGA, hardware efficiency to software … · 2017. 10. 10. · Software Defined...
All Programmable FPGA, hardware efficiency to software programmers ecosystem
© Copyright 2017 Xilinx.
Traditional Compute Architectures Are Not Scalable
© Copyright 2017 Xilinx.
Heterogeneous Domain-Optimized Computing Platforms
© Copyright 2017 Xilinx.
FPGA Silicon Architecture
Logic
ArrayDSP Array
Standard FPGA
GTsIOs
Configuration Network
Programmable Interconnect
Config
PC
Ie
BRAM
Distr RAM
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All Programmable FPGA Silicon Architecture
Logic
Array
IOs
Zynq MPSoC (16nm)
A53
L1$
L2$
A53
L1$
A53
L1$
A53
L1$
System MMU
DD
R
Fla
sh
US
B
Gig
E
R5 R516Gbps
30Gbps
GTs
Config
Security
P-States
CC & SVM
Inte
rla
ke
n
Video
Enc
10
0 G
igE
PC
Ie
DSP Array
Configuration Network
Programmable Interconnect
GPU
X
PC
Ie
OCM
BRAM
URAM
Distr RAM
HBM
ADC
DAC
CC
IX
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Programming Heterogeneous Parallel Platforms
ASIC
Refugees
HW/SW
co-design
VHDL
C +
HLS
C + VHDL CPU Accel
C/C++ RTL RTL
Logic
CPU Accel
C/C++ RTL C/C++
RTL
CPU Accel
C/C++ C/C++ C/C++
Software
Programming
Intermediate
Representation
Bring power of C++ to
OpenCL
Next
Productivity
Frameworks
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Typically productivity improvement via:
Creation of HW-optimized functions in C/C++
Accelerated verification (>1000X RTL)
Automated, intelligent assembly (15x manual)
High-Level Hardware Design Environment
C
Libraries
HLS
High-Level IP
Creation
Automated IP Assembly
Design Methodology
IP Sub-
systems
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Domain Specific Compute Platform
JESD
In
CPRI
OutAXISDI HDMIAXI
Networking Shell Video Shell Wireless Shell
PR RegionPR Region
Host Bridge
EMAC EMAC
DMA
MEMC
AXI
CPU
PPP PPP PPP
Shell : Domain specific infrastructure (gray)
Role : ‘Donut holes’ in FPGA or on CPU executing programmable functions (white)
Host Bridge Host Bridge
DMA
MEMC
CPU
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One Board
Multiple Shells
Role
Shell
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Personas for All Programmable FPGA
End
application
SW platform
HW platform
Silicon and boards
HW designer
Software designer
Application developer
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Heterogeneous Compute Platforms in Datacenter
Machine Learning
ASICs (TPU by Google)
FPGA (Xilinx, Intel)
GPU (NVidia Tesla P4)
CPU Accelerators Memory Networking Other
How Server Components Change with Machine Learning
Storage
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Enabling
Cars and
Machines
to See it All
Autonomous Cars
Enabling Industry Growth Drivers: The ‘Megatrends’
Accelerating
Storage,
Networking,
and Compute
Cloud Computing
Enabling
Safe and Secure
Connected
Machines
Industrial IoT
Connecting
Any Band,
Any Standard,
Any Network
5G Wireless
Machine LearningEdge Cloud
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Xilinx
In-Memory Databases
Video Transcode
Machine Learning
NFV
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All Programmable FPGA Opportunities in the Cloud
Key-values dataflow
Mix of DRAM and NV
Software Defined
Storage
Moving window
dataflow
Bit level processing
(7bit, 8bit)
Massive compute
(MACs)
2D Parallel
Distributed memory
Broadcast
interconnect
Wireline speed
Bit level protocols
String search
Crypto & security
Deep Packet Inspection
SmartNICwww.netfpga.org
Software Defined SSDFidus Sidewinder-100
caffe
Compute Accelerationwww.tul.com.tw/ProductsFPGA.html
© Copyright 2017 Xilinx.
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Moving up the stack : Machine Learning Stack
Software Kernel development
APIs & Libraries
CNN Network Design Tools & Training Frameworks (e.g. CAFFE)
Reference Networks & Custom Networks
HW Platform development
Xilinx
Customers
OpenSource
CNN Compiler & Runtime
Machine Learning
Stack
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FaaS : FPGA as a Service
CPU FPGAAmazon EC2 F1 is a compute instance with
Xilinx FPGAs for hardware acceleration
F1 instances can be programmed using
SDAccel
An FPGA bitstream can be registered as an
Amazon FPGA Image (AFI)
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AWS F1 Platform Model
PCIe
Custom Kernels
DMA
DDR
AXI Interfaces
x86 Host CPU Xilinx FPGA
Custom Application
Drivers
OpenCL Runtime
OpenCL API
User
Application
Code
AWS F1
Platform
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From Cloud to Edge Computing
CLOUD
Data CenterEmbedded
Desktop
Mobile Server
……
IOT
The Edge/FogPerformance
Scale
Transactional
Real-time
Deterministic
Resourceful
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From Cloud to Edge Computing
Cloud
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Back to the Future
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Fog Computing in the Edge
Cloud
Edge
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Cameras Radar LIDAR Ultrasound Sound
Autonomous Driving
Autonomous Driving : 25+ sensors
100’s of TOPS
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From ADAS to Autonomous Driving
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Unique Value Prop FPGA
CPU/GPU
FPGA
1. Dataflow
2. Distributed Memory
3. Broadcast Interconnect
4. Reduced Precis. Arithmetic
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Application Development
Algorithm Development
Platform Development
DNN
CNNGoogLeNet
SSD
FCN …
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Xilinx Foundation at the EdgeVision Customers Using Xilinx
>80ProAV & Broadcast Suppliers
>60Smart Camera & Visualization Suppliers
>50Industrial Vision Equipment Makers
>10Medical Diagnostic Suppliers
>5VR/AR Equipment Makers
>80ADAS Models From 23 Makers
>5Drone Suppliers
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Breakouts in Integration & Programming
Breakout in System Integration
ALL Programmable Devices
ZynqMPSoCs
UltraScale+HBM/CCIX Enhanced FPGAs
SDxSoftware Defined Environments
ZynqRFSoCs
ALL Programmable Models
Breakout in Programming Models
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Setting the Course for the Next 5 Years
Goal: 5X Potential Users in 5 Years
1000s of SoC Teams with
SW and HW Engineers
>250,000 SW Engineers
>50,000 HW Engineers
For Highest Growth
Megatrends
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Inspiration from the software community
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Programming for the Edge
PYTHON Productivity for ZYNQ MPSoC
Porting SW Methods from the Cloud to Physical Reality of IOT Devices in the Edge
Leverage Python Open Source Community
Interactive & Modern User Interface Jupyter Notebooks
Unleash unique capabilities of All Programmable via curated
list of Overlay Libraries
© Copyright 2017 Xilinx.
The rise of productivity languages
Systems/Efficiency Languages
C, C++, OpenCL
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Hardware Systems
OS, hypervisor, drivers
Applications,
Programming Frameworks
Productivity Languages,
Python, Scala, ..
Program ZYNQ in a productivity language
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Hundreds of people maintain the Linux kernel,tens of millions of people use it!
Linux
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How can we support hundreds of thousands of Zynq programmers
with hundreds of bitstream developers?
Users:
Apps Programmers:
Device driver writers:
Kernel developers:
Programmers(embedded):
Hundreds of thousands
Tens of thousands
Thousands
Hundreds
Tens of millions
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Jupyter on Zynq
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Ubuntu Server
Tornado Server
IPython Kernel
ARM A9s
Dashboard
Terminal
Editor
Notebooks
Jupyter infrastructure consists of:
a suite of web browser tools
IPython kernel & Tornado web
server
On top of Ubuntu
All Native SW on Zynq CPU
subsystem
Jupyter
Overlays
Pyzynq Libraries
FPGA
Browser tools:
JavaScript,
HTML, CSS
Server Tools:
Python
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PYNQ community
Highlight third party overlays
and development
– BNN
– Apache Spark
– Japan user Group
– Soft GPU
– Video processing
– DSP FIR
– Tutorial
– CNN
Open Hardware examples
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Find out more at www.xilinx.com/university
www.pynq.io
Access Data Analytics, ML,
Instrumentation, IO programming
on FPGA in the Edge
Run FPGAs in the Cloud
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All Programmable Systems and Networks
HARDWARE
OPTIMIZED
SOFTWARE
DEFINED
Talent Development Ecosystem