AbstractA proposed temperature sensor is based on pure CMOS PTAT circuitry, a preamplifier and a sigma delta ADC capable of simple and efficient temperature sensor conversion to digital value. The designed PTAT circuit utilized temperature compensation technology to enhance the linearity. The temperature sensor, which occupies 0.475 mm2, is fabricated using the TSMC 0.18 m one-poly six-metal (1P6M) process. Measurement results show that the senor consume 46uA with a 1.5 V supply at 100 sample/s at room temperature. The sensor operates from -50C to 150C, archiving a 3 resolution of 0.8C.

I. INTRODUCTION

The temperature sensors with an on-chip analog-to-digital converters and digital control interface are widely used in measurement, instrumentation, and embedded system. The increment of on chip temperature sensing is mainly due to rapid development of process technology. As a result, these applications require small area, low power consumption, digital output and easy controlled to realize low cost and high performance with a desired inaccuracy below 1C.

Recent CMOS temperature sensors [1-3, 5-8] have designed for the modern system-on-chip (SOC) integration. However most of these designs used the parasitic bipolar junction transistors (BJT) as the part of its proposed to absolute temperature (PTAT) circuitry. The power consumption of the BJT based on reference voltage circuit is relatively high for low power application, and these circuits include resistors may change with different process and temperature. Furthermore in the deep sub-micron CMOS technology, the characteristic of BJT is getting worse and hardly to work on low power application. As a result, the design of smart temperature sensor has become a major challenge in deep sub- micron CMOS process.

Some other designs utilized time-to-digital or frequency-to-digital method to detect the temperature. However, these methods have it limitation in the high temperature range above 125C due to exponential leaking current and non-linear characteristic of CMOS transistor and parasitic BJTs. In this paper, we proposed pure CMOS temperature sensors, which are based on PTAT reference from a MOSFET operating in the sub-threshold region and a sigma delta converter. By utilized an high linear voltage reference proposed in our previous research [4], the working temperature range is pushed to 150C with 3 in inaccuracy of 0.8C.

* This work is supported by National Chip Implementation Center (CIC), National Science Council (contract number NSC-101-2220-E-009-019), and MoE ATU Program of Biomedical Electronics Translational Research Center at National Chiao Tung University, Taiwan.

This paper is organized as follows: Section II presents the principles of operation include system architecture and circuit level details. Section IV presents measurement results. Finally, Section V provides conclusions.

II. Principle of Operation The proposed temperature sensing system is shown in Fig.

1. The variation of the temperature can be measurement by the thermal sensor and transferred to the voltage that will be amplified by preamplifier. Then the voltage will be converted to a digital signal by A/D converter. In order to minimize cost and enhance accuracy of temperature measurement, a sigma delta A/D converter is extensively used because of its simplicity and high accuracy for CMOS process [1].

A. Pure CMOS PTAT circuit Fig. 2 shows the analog circuit part of proposed

temperature sensor. This circuitry use current mirror combines positive and negative temperature coefficients to generate the proportional to absolute temperature (PTAT) voltage reference. The PTAT core circuit is formed by M1-M11 and a high temperature compensation Mc-array cells that were selected by control bits to compensate the high temperature leakage current and enhance the linearity of PTAT reference circuits. In this circuit, M1 and M2 operate in weak inversion region, while M3 to M8 work as a negative feedback to ensure current ratio of M1-M2 pair. I-V characteristic of an NMOS transistor operated in the sub-threshold region can be written by (1) and (2)

)1)(exp(2 TDSVV

T

thGSTD emV

VVLWVI

= (1)

)1ln()ln(2

1 TDSVV

T

T

DTth

mGS eV

LWV

IVVV

= +

(2)

Where is the electron mobility in channel, VT is the thermal voltage, Vth is the threshold voltage, m is the sub threshold swing parameter, and W/L is the aspect ratio.

The VPTAT is the difference of VGS2 and VGS1 which both are operated in the weak inversion region and biased by the current ID6 and ID3, thus VPTAT can be written as

)ln()ln()ln(3

6

1

2

3

612 PVS

SSSV

IIVVVV TTD

DTGSGSPTAT ==== (3)

B. Preamplifier The preamplifier uses a feedback mechanisms and a differential operational amplifier (OPAMP) to convert a single-end signal to a differential signal, which is shown in

A 69 W CMOS Smart Temperature Sensor with an Inaccuracy of 0.8C (3) from -50C to 150C

Sheng-Cheng Lee and Herming Chiueh Department of Electrical and Computer Engineering,

National Chiao Tung University, Hsinchu 30010, Taiwan Phone: +886-3-5712121 ext 54597, Fax: +886-3-612-6519, E-mail: chiueh@ieee.org

978-1-4577-1767-3/12/$26.00 2012 IEEE

Figure 1. The block diagram of temperature sensing system

Fig. 3. The gain of preamplifier is obtained by adjusting the ratio of R1 to R2. To eliminate the drifting of output common mode voltage that appeared from the input offset and flicker noise by increasing the geometric size of the input transistors. Thus thermal noise is the only dominant source of the OPAMP.

C. Sigma Delta Modulator A low speed high resolution 2nd order CIFF sigma delta

modulator (SDM) is proposed to digitize temperature voltage output is shown in Fig. 4. The noise transfer function is design by Delta-Sigma Toolbox, an order=2, OSR=512, NTF (z), STF (z) is shown below

( )21

21

)111221()211(11

+++

=

zbabaazbazNTF (4)

1=STF (5) )()()()( zezNTFzXzY += (6)

From the eq. (6), it can be observed that the integration output does not contain input signal X (z), only quantization error E (z). Thus low amplitude at output of integrator can be achieved, and relax the slewing requirement of integrator. Non-linearity and distortion effects can be also greatly reduced due to the loop filter does not process the input signals.

The loop coefficients of (a1, a2, b1, b2) are determined from MATLAB behavior simulations and are set to [0.25, 1, 2.5, and 1]. Modulation with these coefficients is very tolerant to coefficient mismatches caused by capacitance mismatches and the gain error resulting from the switch capacitor technique. The proposed 2nd-order CIFF SDM is shown in Fig. 5, the circuit components of proposed modulator include the discrete time integrator, dynamic common mode feedback (CMFB) circuit, 1-bit quantizer and non-overlapped clock generator.

In the design of high resolution sigma delta modulator, the principal noise sources affecting the operation of first integrator are the sampling noise, clock jitter noise and the operational transconductance amplifier (OTA)s thermal noise and flick noise. The flick noise and offset can be reduced using the correlated double sampling (CDS) technique [9]. The modulator is used capacitor sharing

techniques to reduce chip area and enhance the amplifier bandwidth without bias current increase. Therefore the power consumption is reduced by OTA design.

The OTA in the loop filter is the principle analog block which consumes the maximum power and also dominates the performance of the modulator. As a result it is the critical building block that needs the most careful design consideration. The proposed OTA is based on a two-stage OTA, the first stage provides a high gain and low noise; the second stage provides large signal swing. Instead of cascode OTA, a two-stage OTA is used to isolates the gain and accomplish the requirements. Each stage can incorporate various amplifier topologies, but in order to maximize output swings, the second stage is configured as a simple common source stage. The sampling capacitors of the first stage were selected as 800 fF to minimize thermal noise and flicker noises of OTA. The second stage OTA is the same architecture, and the capacitors size is scaled down to 200 fF. The performance of the OTA achieves minimum simulated gain of 90dB (over process, power and temperature variation) and good output swing behavior, such as good slew rate, enough settling time and gain bandwidth product.

D. Decimation Filter In order to reduce quantization noise, the low-pass Sinc

decimation filter is utilized [11]. The transfer function of a Sinc decimation filter can be written as

( )3

13 111

=

zz

MzH

M (7)

Where M is the down-sampling ratio (DSR) of decimation filter. The Sinc filter is consisted of the integrators and the comb filter, and the minimum length of register without overflow can be calculated as

281512log31log 22min =+=+= DSRLB (8)

Based on the transfer function and the minimum register length, the signal flow is shown in Fig. 6. A configurable clock divider is designed in the decimation filter to support 256, 512 DSR.

The DSR is proportional to resolution but disproportional to conversion rate. The decimation filter with configurable DSR can meet the temperature sensor signal specification.

TemperatureCompensation

CMOS PTATCircuit

PreampliferAmplifier

Low Speed High resolution

SDM ADC

Trimming circuit

Decimation Filter

I2C Register Bank

D[15:0]

PCI2C

Interface

Figure 2. All CMOS PTAT reference circuit

Figure 3. The preamplifer circuit

Figure 4. The architecture of the 2nd CIFF modulator and 3 order decimation filter

By combining the proposed temperature sensor analog front end and ADC, the temperature sensor acquisition and analysis platform is completed. In the following session, the performance of implemented circuitry and platform is presented.

III. IMPLEMENTATION RESULTS

The temperature sensor chip has been fabricated in TSMC standard 0.18m CMOS process with 3.3V (pads) and 1.8V (core) supply (Fig. 7). The chip was packed into a duel-in-line package and mounted on a costumed printed circuit board. The whole chip size was 1.30.8 mm2, and core size was 0.950.5 mm2. The test environment includes temperature chamber, K-type thermal couple, Keithley 2400 DC power supply, HP33120A clock generator, and Humidity Chamber.

Vin1 12 Cs1 1 2

2Cs2

121

1Cff3 22

1

Cff22

1

Cff12

Quantizer

Q

Qb

QbQ

Vr+Vr-

1CK1

1

2 Cs1 1

2Vin2

2Cs2 1

2

11Cff3 2

2

1

Cff22

1

1

Cff12

2

2

CI1

CI1

1

1

CI2

CI2

1

12

2

CoffCoff

CoffCoff

Figure 5. Circuit of 2nd-order CIFF sigma-delta modulator

Figure 6. Signal flow of the decimation filter.

Figure 7. Micro-photograph of the proposed temperature sensor chip (The sensor + PGA 420 m 450 m; SDM modulator circuit: 430 m 450 m; decimation filter + I2C : 950 m 220 m)

All 8 packaged chips are measured from -50C to 150C in a temperature chamber. The PTAT voltage is show in Fig. 8. The average temperature coefficient of PTAT reference voltage is 0.8mv/C between -50C to 150C. In Fig. 9, one-point calibration based on 25C is applied to calculate the 3 inaccuracy with the digital output. With the temperature range of -50C to 150C, the 3 inaccuracy is less than 1C.

The performance of designed temperature sensor is summarized in Table I. The performance comparison of related research is shown in Table II. Among these designs, this work has widest temperature range from -50C to 150C and the power consumption is among three of the smallest.

M1M2

M3 M4 M5 M6

M7 M8

M9

M10

M11Mc1VPTAT

P

N

Vdd

M

Mc4

OUT+

OUT-

VCM

VPTATR1

R2

R1

R2

CF

CF

1

1

1

zz

Y(z)

1

1

1

zz

X(z)y1(z) y2(z)

b1

-

e(z)

M1z 1z 1z1z 1z 1z

a2a1

a1

1 28

28 28 28 16 16 16 16

1z 1z 1z

512

1z 1z 1z

1 28 28 16

1616

28 28

16 16

950 m

450 m

ADC

Decimation Filter + I2C

Sensor + PGA

1300 m

800 m

Figure 8. The volatge of VPTAT from -50C to 150C

TABLE I: MEASUREMENTED SPECIFICATION OF PROPOSED TEMPERATURE SENSOR

Specification Items Value or Feature

Technology 0.18m 1P6M CMOS Supply Voltage 1.5V ~ 1.8V Core Size Chip Size

0.950 x 0.60 mm2 1.3 x 0.8 mm2

Conversion rate 100 conversions/sec

VPTAT 0.25C

Digital Code 0.8C Power consumption 69 w

TABLE II: COMPARISON OF RELATED TEMPERATURE SENSORS

Reference Process Range Inaccuracy Power

Pertijs[1], JSSC 2005,

0.5um CMOS

-50C ~120C

0.5C 350W~ 750W

Lee[2], ISCAS 2006

0.25um CMOS

-55C ~125C

1.0C 300W~ 2.2mw

Makinwa[3] ISSCC 2008

0.7um CMOS

-55C ~125C

0.5C 12mW

Soumyanath[5] ISSCC 2009

32nm CMOS

-55C ~125C

0.45C 1.6mW

Huijsing[7] ISSCC 2009,

0.7um CMOS

-70C ~130C

0.25C 62.5W~ 137.5W

Makinwa[8] ISSCC 2010

0.7um CMOS

-55C ~125C

0.1% 7.8mW

Makinwa[9] ISSCC 2010

0.16um CMOS

-40C ~125C

0.25C 9W~ 12W

Makinwa[11] ISSCC 2012

0.16um CMOS

-55C ~125C

0.15C 5.1W~ 6.8W

This Work 0.18um CMOS

-50C ~150C

0.8C 69W

Figure 9. 3 Inaccuracy with one-point calibration at 25C

IV. CONCLUSION A CMOS temperature sensor with power consumption 69

W based on the sub-threshold MOS operation has been designed in TSMC 0.18um CMOS technology. The measured temperature error is from -50C to 150C with an inaccuracy of 0.8C (3). The measurement results show proposed design achieves the higher accuracy with extensive temperature range.

REFERENCES [1] M. A. P. Pertijs et al.A CMOS Smart Temperature Sensor With a 3

Inaccuracy of 0.1C From -55C to 125C, IEEE JSSC, vol. 40, no. 12, pp. 2805-2815, Dec. 2005.

[2] Ho-Yin Lee et al. CMOS thermal sensing system with simplified circuits and high accuracy for Biomedical Application, IEEE ISCAS, pp. 4370-4374, 2006.

[3] Van Vroonhoven et al. A CMOS Temperature-to-Digital Converter with an Inaccuracy of 0.5 C (3/spl sigma)from -55 to 125C, in Proc. IEEE ISSCC, 2008, pp. 576-637.

[4] Tso-sheng Tsai, Joseph and Herming Chiueh, High Linear Voltage References for on-chip CMOS Smart Temperature Sensor from -60C to 140C, IEEE ISCAS, pp.2689-2692, May. 2008.

[5] Li, Y.W. et al. A 1.05V 1.6mW 0.45C 3-resolution -based temperature sensor with parasitic-resistance compensation in 32nm CMOS, in Proc. IEEE ISSCC, 2009, pp. 340-341.

[6] Aita, A.L. et al. A CMOS temperature sensor with a batch-calibrated inaccuracy of 0.25C (3) from 70C to 130C, in Proc. IEEE ISSCC, 2009, pp. 342-343.

[7] Kamran Souri et al. A CMOS Temperature Sensor with an Energy-Efficient Zoom ADC and an Inaccuracy of 0.25C (3) from -40C to 125C, in Proc. IEEE ISSCC, 2010, pp. 310-312.

[8] Mahdi Kashmiri et al. A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS with an Absolute Inaccuracy of 0.1% from -55C to 125C, in Proc. IEEE ISSCC, 2009, pp. 342-343.

[9] C. Enz and G. Temes, Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE, vol. 84, no. 11, pp. 15841614,Nov. 1996.

[10] K. Souri, Y. Chae, and K. Markinwa. A CMOS Temperature Sensor with a Voltage-Calibrated Inaccuracy of 0.15 C (3 ) form -55 to 125 C, in Proc. IEEE ISSCC, 2012, pp. 208-209.

[11] E. B. Hogenauer, An Economical Class of Digital Filters for Decimation and Interpolation, IEEE Trans. Acoust, Speech, and Signal processing, vol. 29, no.2, pp. 455-162, Apr 1981.

0.55

0.6

0.65

0.7

0.75

0.8

0.85

-50 -35 -20 -5 10 25 40 55 70 85 100 115 130 145

VPTA

T Vo

ltage

Temperature (degree C)

S1,Rsq=0.9985S2,Rsq=0.9987S3,Rsq=0.9986S4,Rsq=0.9988S5,Rsq=0.9985S6,Rsq=0.9984S7,Rsq=0.9983

-1.00

-0.80

-0.60

-0.40

-0.20

0.00

0.20

0.40

0.60

0.80

1.00

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

Error T

empe

rature (

C)

Temperature ( C)