All-analog Digital Multimeter (DMM) · 2018-05-17 · All-analog Digital Multimeter (DMM) Submitted...
28
All-analog Digital Multimeter (DMM) Submitted in partial requirement for the completion of 6.101 Sam Chinnery * [email protected] May 17, 2018 Abstract This paper details the design and implementation of an all-analog digital multimeter (DMM). “All-analog” means the design will be implemented using minimal digital logic. 1 This is inher- ently difficult because it requires the use of analog circuitry to both acquire and digitize signals corresponding to parameters of the device under test (DUT). For this implementation I intro- duce a novel ADC topology, herein referred to as the analog modulus computation unit (ACU) for lack of a better name. Functionally, the meter measures one of four quantities: voltage, cur- rent, resistance or capacitance; in one of four ranges, for a total of 16 operational modes. The meter incorporates a three-digit seven-segment display for user interface. This design maintains greater than 5% accuracy across all modes, with many ranges being within ±1%. * Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology 1 Digital logic is used as necessary for multiplexing and flow control 1
Transcript of All-analog Digital Multimeter (DMM) · 2018-05-17 · All-analog Digital Multimeter (DMM) Submitted...
All-analog Digital Multimeter (DMM)Submitted in partial requirement for the completion of 6.101
Sam Chinnery∗
May 17, 2018
Abstract
This paper details the design and implementation of an all-analog digital multimeter (DMM).“All-analog” means the design will be implemented using minimal digital logic.1 This is inher-ently difficult because it requires the use of analog circuitry to both acquire and digitize signalscorresponding to parameters of the device under test (DUT). For this implementation I intro-duce a novel ADC topology, herein referred to as the analog modulus computation unit (ACU)for lack of a better name. Functionally, the meter measures one of four quantities: voltage, cur-rent, resistance or capacitance; in one of four ranges, for a total of 16 operational modes. Themeter incorporates a three-digit seven-segment display for user interface. This design maintainsgreater than 5% accuracy across all modes, with many ranges being within ±1%.
∗Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology1Digital logic is used as necessary for multiplexing and flow control
1
Contents
1 Introduction 3
2 Design overview 3
3 Analog frontend 43.1 Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.4 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Mixed-signal backend 114.1 Analog modulus computation unit (ACU) . . . . . . . . . . . . . . . . . . . . . . . . 114.2 Seven-segment display controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Performance 14
6 Conclusion 14
A Schematics 15
B Pictures 27
List of Figures
1 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Current module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Resistance module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Single and dual-op amp current pump configurations . . . . . . . . . . . . . . . . . . 86 Output and charging waveforms of 555 astable configuration . . . . . . . . . . . . . . 97 Capacitance module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Backend block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Magnitude comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210 Sample and hold amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
1 Introduction
Digital multimeters are inherently difficult to implement in the analog domain. Displaying thebase-10 representation of a quantity requires circuitry to discretize an analog signal and convertit into a user-friendly format. This report details the design of a meter that mimics the function-ality of a traditional digital multimeter using discrete analog components. The design includes adiscrete analog-to-digital converter (ADC), display driver, analog frontend and mixed-signal back-end. The device is prototyped on a breadboard using through-hole components with the eventualgoal of transferring the design onto a custom printed circuit board (PCB) using surface-mountedcomponents.
Section 2 is a high-level overview of the entire design, along with a functional block diagramof the system. Sections 3 and 4 are detailed component-level descriptions of each module in thefrontend and backend respectively. Section 5 is a qualitative analysis of the device’s performance.Section 6 concludes the report and summarizes the key challenges faced in designing this circuit.Finally, Appendix A is a comprehensive circuit diagram of the project.
2 Design overview
A block diagram of the system is presented in Figure 1. The design of the meter is divided intotwo main sections: frontend and backend. The frontend is mainly analog and consists of fourmodules that each convert one parameter to a voltage ranging from 0–5.99 V. The backend is amixed-signal circuit comprised of the analog modulus computation unit (ACU), a 1–10 V integervoltage reference, an analog state machine to store computed values, and a display driver to presentthe measured value to the user.
ControlLogic
Voltage
Current
Resistance
Capacitance
IntegerVoltage
Reference
ACU
StateControl
3
10
Display/Decoder
3
4
InputTerminals
Analog frontend Mixed-signal backend
Figure 1: System block diagram
3
The device under test (DUT) is connected to two input terminals. Depending on which rangethe user selects, this signal is connected via an analog multiplexer to one of four frontend modules.Each module produces an output voltage between 0 and 5.99 V that is proportional to the quantitybeing measured. The frontend modules support range switching, and are each configurable tooperate in one of four ranges. Both the current function and range are selected by the user withrotary switches.
The voltage module contains a programmable attenuator that divides the voltage at the inputterminals by a fixed value to produce a scaled voltage for the backend. The current module is aselectable shunt resistance designed to be connected in series with a load. A buffer amplifier scalesthe voltage dropped across this resistance to yield a voltage proportional to the series current. Theresistance module is a precision voltage-controlled current source that applies a constant current tothe DUT. An amplifier buffers the voltage developed across the load, which is directly proportionalto the resistance.
The output signal from the selected frontend module enters the backend, where it is digitized anddisplayed to the user. The ACU combines elements of a flash ADC and a folding ADC to produce athree-digit BCD output for use with seven-segment displays. It accomplishes this through the useof nine voltage comparators, with reference voltages set at integer values. The backend’s uniquenessis in its serialization: it reuses the same circuitry to perform three different computations. Throughuse of an analog “state machine,” the ACU implements short-term memory that enables an ADCto be constructed with fewer components than a traditional flash ADC while preserving accuracy.
3 Analog frontend
The following sections are component-level descriptions of each module in the analog frontend. Theinput of each module is connected to the DUT at all times; multiplexing functionality is imple-mented by use of two relays at the input of each module that isolates the circuit from the inputterminals if it is not currently selected.
Note: These sections and the remaining circuit descriptions make references to the schemat-ics found in Appendix A. Each section contains the appropriate schematic sheet for thatmodule. The sheet title and number can be found in the sheet’s title block (located in thetop-right corner of the page when viewed in portrait orientation).
3.1 VoltageReference: Appendix A, sheet 10 (“Four-range precision voltage divider/attenuator”)
The voltage module is a precision programmable attenuator that operates in four ranges. Theattenuator is a four-tap resistor divider, which operates according to the same principles as astandard resistor divider, but with more than two series elements. This topology was chosenbecause it presents the DUT with a constant load impedance regardless of the range, consistentwith many traditional multimeters on the market today. To mitigate measurement error due tothe high impedance of the divider, the selected tap is buffered by an instrumentation amplifier thatscales the reading to a value between 0 and 5.99 V. To calculate the values for the five resistors,we first consider the standard resistor divider equation:
Vout = Vin
(R2
R1 +R2
)where R1 and R2 are connected at a central node and R2 is connected to ground.
4
ProgrammableAttenuator
1/10
1/100
1/1,000
1/10,000
Av = 100
Input +
Input −Range
Output
4
(a) Functional diagram
Range Scale Vin/Vout1 600 mV 10
2 6.00 V 100
3 60.0 V 1,000
4 600 V 10,000
(b) Measurement ranges
Figure 2: Voltage module
For an attenuator with N taps, the absolute and relative voltages at the kth tap are given by:
Vout = Vin
(∑kn=1Rn∑Nn=1Rn
)=⇒ Vin
Vout=
∑Nn=1Rn∑kn=1Rn
(1)
where Rn is the nth resistor from the zero potential reference point. For this design, a four-decade divider was chosen, with division ratios (Vin/Vout) of 101, 102, 103 and 104. Typical digitalvoltmeters have a load impedance between 1 and 10 MΩ. This design uses a 10 MΩ attenuationnetwork to allow for the measurement of high-impedance circuits. From (1) we can see that, foreach tap,
VinVout
=10× 106∑k
n=1Rn
Expanding yields the following system of equations:
R1 +R2 +R3 +R4 +R5
R1= 10 000
R1 +R2 +R3 +R4 +R5
R1 +R2= 1 000
R1 +R2 +R3 +R4 +R5
R1 +R2 +R3= 100
R1 +R2 +R3 +R4 +R5
R1 +R2 +R3 +R4= 10
R1 +R2 +R3 +R4 +R5 = 10× 106
(2)
This system can be solved numerically to yield R1 = 1 kΩ, R2 = 9 kΩ, R3 = 90 kΩ, R4 = 900 kΩ,
5
and R5 = 9MΩ. Fortunately, Caddock, Inc. manufactures a divider network with exactly thesevalues, which was used for this project for simplicity.2
The buffer amplifier used for this module and for many others in the design is the INA114.It was chosen for its low input bias current (2 nA max) and extremely low offset voltage (50 µVmax). As is typical of instrumentation amplifiers, the INA114 provides connections for an externalresistor to set the gain of the amplifier. As given in the INA114 datasheet,3 the output transferfunction is given by:
Vo = G(V +in − V
−in ), where G = 1 +
50× 103
RG(3)
To obtain the scales listed in Figure 2, the gain of the amplifier should be set to 100. SubstitutingG = 100 into (3) yields RG = 505.1 Ω. For greater accuracy, a 100 Ω potentiometer was used inseries with a 470 Ω resistor to provide for user calibration of the voltage gain. Range selection isaccomplished with a CD4066 quad bilateral analog switch, which is used as a multiplexer to selecta tap on the divider network.
3.2 CurrentReference: Appendix A, sheet 3 (“Four-range selectable shunt/current to voltage converter”)
The current module is a four-range selectable current shunt. To measure current, the DUT isconnected in series with the meter, which selects one of four shunt resistances that will be usedto measure current. By Ohm’s Law, the voltage dropped across the resistor is equal to the seriescurrent times the resistance, or V = IR. In all cases, the voltage dropped across the resistor is setto 300 mV at the maximum rated current for that range, as this at this scale it is easy to constructshunt resistors using standard 5%, 1/4 watt resistors. Using the ranges shown in Figure 3, thevalues of the shunt resistances were determined to be 0.5 Ω, 5 Ω, 50 Ω and 500 Ω.
Input +
Input −
Range
Output
Av = 204
Rx
(a) Functional diagram
Range Scale Rx
1 600 µA 0.5 Ω
2 6.00 mA 5 Ω
3 60.0 mA 50 Ω
4 600 mA 500 Ω
(b) Measurement ranges
Figure 3: Current module
One terminal of each shunt resistor is connected directly to the positive input terminal, andthe other terminal is connected to an analog multiplexer that selects which resistance to connect
2Caddock part number 1776-C683Datasheet retrieved from https://www.ti.com/lit/ds/symlink/ina114.pdf
6
to the negative input terminal in order to complete the circuit. For the current module, the analogmultiplexer was constructed with relays instead of a CMOS switch—for current measurements, itis critical that little to no voltage is lost except in the shunt resistors for the highest accuracy.According to the CD4066 datasheet4, the typical on-resistance of one switch is 125 Ω, with VDD =15 V and TA = 25 C. As this is much greater than the entire shunt resistance for the lower ranges,current measurement would be extremely difficult without the use of relays.
Once again, the INA114 was used to buffer the output, this time with a gain of 6.00 V300 mV = 20.
For a gain of 20, RG should be 2.632 kΩ. For greater accuracy and to avoid using unusual resistorvalues, RG is implemented as a 2.4 kΩ resistor, a 150 Ω resistor, and a 100 Ω potentiometer inseries. For the relays in the current module, as well as those in all other modules, “snubber” diodesare connected in parallel with the relay coils to avoid damage to other parts of the circuit due toinductive kickback (back EMF).
3.3 ResistanceReference: Appendix A, sheet 8 (“Four-range precision current source/resistance to voltageconverter”)
The resistance module consists of a precision voltage-controlled current source (VCCS) driven by aconstant reference voltage, with four selectable current gains. The VCCS applies a constant currentto the DUT, and the voltage developed across the resistor is measured to give a value proportionalto the resistance. By Ohm’s Law, V = IR =⇒ R = V
I . For ease of implementation, outputcurrents were chosen to give a maximum voltage of 6.00 V at the maximum rated resistance foreach range.
Io Av = 1
Input +
Range
Input −Output
4
(a) Functional diagram
Range Scale Io1 6.00 kΩ 1 µA
2 60.0 kΩ 10 µA
3 600 kΩ 100 µA
4 6.00 MΩ 1 mA
(b) Measurement ranges
Figure 4: Resistance module
As seen in Figure 3b, the current source used to measure resistance must be able to produce awide range of currents, up to four decades (from 1 µA to 1 mA). Several current source and currentmirror topologies were tested for this circuit. Simple single-transistor BJT current sources wereunsuitable because of the significance of the base current IB at extremely low output currents. Usinga JFET solves this problem, but the JFET current source suffers from a limited range. VariousWilson current mirror5 derivatives were tested as well. The Wilson current mirror performed betterthan the single transistor source, but as the circuit is composed entirely of BJTs, each transistormust have a VBE greater than 0.6 V, which becomes a limiting factor when high variability isdesired.
4Datasheet retrieved from http://www.ti.com/lit/ds/symlink/cd4066b.pdf5See https://en.wikipedia.org/wiki/Wilson current mirror
7
One particularly interesting circuit is the Howland current mirror, which was actually developedby Professor Bradford Howland of MIT c. 1962.6 Figure 5a shows the original Howland currentpump. The circuit works as a differential amplifier that forces the voltage VREF to appear acrossR3, causing a constant current Io to flow through the load. The current Io can then be derived:
Io = VREF
(1
R3
), assuming
R1
R2=R3
R4(4)
However, this circuit has one glaring weakness: with normal op-amps, the output cannot swing asclose to the full supply voltage as is necessary. For example, with R1 = R2 = R3 = R4 = 10 kΩ,the output can only swing to about ±5 V. To solve this problem, an improved Howland currentpump was implemented as shown in Figure 5b.
R1 R2
R3 R4
Load Io
VREF
(a) Howland current pump
Load
Io
R
R
R
R
RSV −in
V +in
Io =V +in − V
−in
RS
(b) Improved Howland current pump
Figure 5: Single and dual-op amp current pump configurations
The dual op-amp configuration solves the problem with the basic configuration—the outputcan swing much closer to the rails due to the second op-amp’s use as a buffer. This configurationis capable of output swings of ±10 V with ±15 V supplies and exhibits a much higher linearitythan the basic configuration. To select the output current for each range, one of four values of RS
is selected with a CD4066. For the desired output currents of 1 µA, 10 µA, 100 µA and 1 mA,the values of RS can be determined by the equation in Figure 5b to be 1 MΩ, 100 kΩ, 10 kΩ,and 100 Ω, respectively. Once again, these resistances are implemented with fixed-value resistorsin series with potentiometers to allow the unit to be calibrated for maximum accuracy.
3.4 CapacitanceReference: Appendix A, sheet 1 (“Four-range capacitance to voltage converter”)
The capacitance module measures the amount of time taken to charge the DUT through a knownresistance. The first stage of this process is the relaxation oscillator, which is implemented using a555 timer in the astable configuration. In this configuration the timing capacitor both charges anddischarges through the same resistor, resulting in a duty cycle of roughly 50%. The characteristicwaveforms of an astable 555 oscillator can be seen in Figure 6. In this configuration, the output
6See http://www.ti.com/lit/an/snoa474a/snoa474a.pdf
8
frequency of the astable oscillator can be derived using the familiar RC time constant equation(many tedious computations omitted):
V (t) = V0
(1− exp
(−tτ
))=⇒ f =
1
2RC ln 2≈ 1
0.693 (2RC)(5)
If R is held constant, this configuration of the 555 timer is valuable because it generates a signalwhose frequency is inversely proportional to a capacitance, up to some constant. Moreover, due tothe single-resistor circuit, a “scaling factor” can be applied to this frequency and can be varied bychanging only one resistor.
2
Figure 6: Output and charging waveforms of 555 astable configuration
The signal from the output of the 555 timer then is applied to a frequency to voltage converter.The converter is implemented using an LM331, which is typically used as a voltage-to-frequencyconverter.7 However, it lends itself to the opposite purpose as well, as it contains all the requisitecomponents for implementing a frequency to voltage converter. Much of the LM331 is functionallysimilar to the 555 timer—it implements an RC timing function that is triggered by a thresholdcomparator with a reference at 2/3 of the supply voltage. Moreover, the LM331 implements anR-S flip-flop in the trigger circuit and a bandgap voltage reference to allow for more precise timing.
To use the LM331 as a frequency-to-voltage converter, the input signal is first differentiated byan RC network to produce a string of pulses. These pulses trigger the timing circuit and cause thedevice to output a current that is proportional to the input frequency. A resistor is connected inparallel with the output to convert the output current to a voltage, thus completing the frequencyto voltage converter. The converter in this implementation generates an output voltage with a fixedslope of 1 V/kHz. This voltage is directly proportional to the frequency, and therefore inverselyproportional to the capacitance.
7See http://www.ti.com/lit/ds/symlink/lm331.pdf
9
As shown in Figure 7, the capacitance module next takes the reciprocal of this voltage togenerate a signal that is directly proportional to the capacitance of the DUT. The reciprocaloperation is accomplished by using an analog multiplier in the feedback loop of an op-amp. Themultiplier causes the amplifier to behave as if it were outputting a voltage a factor of A timeshigher, where the multiplier computes the product A×B.
555Astable
Frequencyto
Voltage Vout =1
Vin
Range
Input +
Input −
VREF
4
Av = 1
Output
Figure 7: Capacitance module
For this design, four capacitance ranges were implemented: 6.00 nF, 60.0 nF, 600 nF and6.00 µF. Since the maximum output voltage of the capacitance module should be 6.00 V, it followsthat the minimum input voltage to the reciprocal circuit should be 1
6 V, as any voltage lower thanthat would result in an output higher than 6 V. For the lowest voltage to appear at the outputof the frequency to voltage converter, the lowest frequency must be present at its input, whichmeans the timing capacitor for the 555 timer must be at its maximum value for the selected range.Since the frequency to voltage converter was designed to have a slope of 1 V/kHz, the minimumfrequency must be 1000
6 ≈ 167 Hz. Given this and (5), the four values of R for the 555 timer maybe calculated:
For range 1 (6 nF),1
2R(6× 10−9) ln 2=
1000
6=⇒ R ≈ 721 kΩ
Similar computations for ranges 2 (60 nF), 3 (600 nF) and 4 (6 µF) yield R = 72.1 kΩ, 7.21 kΩ, and721 Ω, respectively. These resistors are implemented using potentiometers in series with fixed-valueresistors to allow for calibration. The resistors are selected using a CD4066 analog switch. Thevery lowest value resistor (721 Ω) appears on the schematic to be lower than expected (max 490 Ω),but this was done intentionally to compensate for the ∼150 Ω internal resistance of the CD4066.
The frequency to voltage converter is implemented with a conversion slope of 1 V/kHz. This isadjustable via a potentiometer which slightly varies the reference current input to the LM331. Theoutput of this frequency-to-voltage converter must be buffered before being used elsewhere, as theconverter has a high output impedance by nature.
Analog division is implemented with the AD633 analog multiplier used in the feedback loopof an LM358 general-purpose op-amp. As implemented in this design, the division circuit has atransfer function of:
Vout = −10
(V1V2
)The factor of 10 is due to an internal voltage reference in the AD633. To eliminate this factor, areference voltage of 100 mV is used to cancel out the 10. The voltage reference is obtained via avoltage divider that divides a 1 V reference from elsewhere in the design by 10. As this voltage
10
is the wrong polarity, the INA114 used to buffer the output has a gain of -1 to generate a strictlypositive output voltage.
4 Mixed-signal backend
The following sections contain component-level descriptions of each module in the mixed-signalbackend. At a high level, the backend is simply an analog-to-digital converter that displays theoutput voltage from the frontend on a seven-segment display. This function is accomplished bythe analog modulus comparator (ACU), a seven-segment display controller, and various controllogic. The backend circuitry is unlike the frontend because it uses two supply voltages: the same±15 V supply used for the frontend, and a +5 V supply for all digital ICs. The 74LS07 high-voltage open-drain hex non-inverting buffer was used for level conversions throughout the backendas necessary.
4.1 Analog modulus computation unit (ACU)Reference: Appendix A, sheets 5–6 (“Analog modulus comparator,” sections 1 and 2)
0.1
0.01
1 2 3
MagnitudeComparator
PriorityEncoder
Display/Decoder
State controller
Input
VREF
Av = 10
10
4
33
Figure 8: Backend block diagram
The ACU converts an analog voltage to digital signals through a serialized process. By operatingas a state machine with three states, the ACU reuses the same circuitry to perform all the necessarycomputations for conversion. The core of the ACU is a ten-window magnitude comparator and apriority encoder. The magnitude comparator computes the floor of the input signal (bVinc). Itsoutput is a ten-bit bus where the lowest n bits are active, where n is the floor of the input signal.The bits are ordered from lowest to highest (lowest voltage window to highest voltage window) and
11
applied to a priority encoder. The priority encoder assigns a priority to each input and returns thebinary representation of the highest-priority active bit. This process can be seen in Figure 8.
The output of the priority encoder is also used to generate an analog voltage that representsthe floor of the input signal. The binary output is used with an analog multiplexer to select one often integer voltage references. That signal is then subtracted from the input to yield a voltage thatrepresents the remainder of the input signal when divided by 1 (Vin % 1). A differential amplifierthen multiplies this signal by 10 and stores it in one of two analog “registers.” This forms the basisof the conversion process—for each digit, the floor of the input signal is computed and displayedto the user. At the same time, the remainder voltage is generated and stored in memory.
For each of the three states of the ACU, input multiplexing circuitry selects one of three differentsignals to be used as the input to the magnitude comparator: the output of the frontend, or oneof two analog “registers.” At the end of state 1, the amplified remainder voltage is stored in thefirst register, representing the tenths’ place of the decimal expansion of the input. The processis repeated again for state 2, this time storing the result in a register that holds the hundredths’place. For state 3, the input of the ACU is taken from the second register and displayed to theuser. Technically, this means that the ACU computes a four-digit decimal expansion of the input,but this result is not stored in memory.
...
10VREF
Vin
1 V
2 V
10 V
Q1
Q2
Q10
Figure 9: Magnitude comparator
RL
Vin
HOLD
CH
Av = 1
Figure 10: Sample and hold amplifier
The magnitude comparator is implemented using two LM339 quad comparators and a singleLM393 dual comparator, as shown in Figure 9. The non-inverting input of each comparator isconnected to a reference voltage, and all the inverting inputs are tied together to the module input.This implements an inverse window comparator function—for example, if the input voltage is 4.5volts, four comparators will output a logic low. As both the LM339 and LM393 are open-drainoutput, all outputs are pulled up to the +5 V supply through resistor networks. Each analog registeris a sample-and-hold amplifier, as seen in Figure 10. For this design, the AD582 was chosen for itsversatility and ease of use. The sample-and-hold amplifier operates as the name suggests—whenthe digital input is active, the sampling switch closes and the hold capacitor charges to the inputvoltage. When the digital input is inactive, the sampling switch opens and the output amplifier“holds” the voltage in the capacitor.
As mentioned above, the ACU operates from both a ±15 and +5 V DC supply. The split supplyis used for all analog components (comparators, analog switches, amplifiers and sample-and-hold
12
circuits). The 74LS07 is used with a pull-up network for logic level conversion.8 The 74LS147priority encoder is used in this implementation.9 The 74LS147 operates with active-low logic, so2N7000 MOSFETs are used to invert the outputs before connecting them to the seven-segmentdisplay drivers. The DG406 16-channel analog multiplexer is used to select the reference voltage.10
The INA114 with a gain of 10 was used to implement both subtraction and multiplication for thecomputed remainder voltages. From (3), RG must be 5.556 kΩ for a gain of 10. This implementationuses a 5.1 kΩ and a 470 Ω fixed resistor in series with a 100 Ω potentiometer for greater accuracy.
4.2 Seven-segment display controllerReference: Appendix A, sheet 4 (“Three-digit seven-segment display controller”)
The seven-segment controller is fairly simple. It uses the CD4511 BCD-to-7-segment latch decoderto convert the inverted output of the priority encoder to a human-readable format.11 The CD4511was chosen because of its latching feature, which enables the data lines of all three drivers to bebused together while only updating one digit at a time. The digit switching is accomplished usingthe three outputs of the ring oscillator described in Section 4.3. These outputs, however, transitionfar too quickly (around 250 Hz) for the display to be readable while updating. To solve this, eachdigit select signal is diode OR-ed with a master digit clock so the display updates much more slowly(about 3 times per second).
For this design I used incandescent seven-segment displays instead of traditional LED displays.This has the advantage of having a much wider viewing angle than LED displays and being moreaesthetically appealing. Additionally, it can operate regardless of polarity instead of being strictlycommon-anode or common-cathode. The disadvantage of this is that the segments draw morecurrent individually (as much as 20 mA per segment), resulting in an average current draw ofaround 300 mA. This, however, is not problematic as the system was designed to be run from anAC wall transformer with high current output capability.
4.3 Timing and control logicReference: Appendix A, sheets 9 and 7 (“Timing and control logic,” sections 1 and 2)
The control logic provides a user interface for the meter. Two rotary switches are employed: one toselect the mode (voltage, current, resistance or capacitance) and another to select the range. Themode selection switch controls the relays contained in each frontend module to determine which oneis active. Additionally, it drives an analog multiplexer that selects the active input to the backend.The range selection switch drives the selection inputs of the CD4066 switches contained in everyfrontend module.
This module also generates timing signals that are used throughout the design. Three D-typeflip-flops are used to implement a three-state ring (Overbeck) counter.12 The ring counter wasfound to be extremely sensitive to interference, often interfering with itself through supply voltagetransients. To mitigate this, an error detection circuit was designed to reset the counter in theevent it returns an invalid output state. Diode logic was used to reset the circuit according to thefollowing expression (A, B and C are the three outputs of the ring counter):
(AB +BC +AC) + (ABC +ABC)
8See http://www.ti.com/lit/ds/symlink/sn74ls07.pdf9See http://www.ti.com/lit/ds/symlink/sn54ls148.pdf
10See https://www.intersil.com/content/dam/Intersil/documents/dg40/dg406-407.pdf11See http://www.ti.com/lit/ds/symlink/cd4511b.pdf12For diagrams and further information, see https://en.wikipedia.org/wiki/Ring counter
13
This handles the five failure modes of the counter. The first three modes occur when one additionalbit is injected into the counter, which results in two outputs being on at the same time. The lattertwo occur when the outputs are either all high or low.
5 Performance
When the unit is fully assembled and runs uninterrupted, it operates quite reliably. By far theleast reliable element of the entire circuit is the ring oscillator. The ring oscillator operates in sucha manner that if any interference affects any of the three flip-flop inputs and causes it to changestates, the operation of the oscillator is permanently affected (until the next power cycle). Tomitigate this, the diode logic described in Section 4.3 was used to automatically reset the oscillatorin the event of an error. I believe much of the failures of this module are due to the breadboardconstruction—if the circuit were implemented on a PCB with proper grounding and shorter pathlengths, the interference would likely be much less. Similarly, transients on the power rails becameproblematic during prototyping, especially due to the 7-segment displays. Substantial amounts ofbypass capacitors partially resolved this problem, keeping supply transients to a maximum of 100mV. Still, ground loops are an issue as always with breadboards, but this issue would also be fixedif the design were implemented on a PCB.
By the nature of the ACU, the unit occasionally performs poorly when measuring voltages nearan integer (e.g. 1.01 V). This is due to the offset voltage of the magnitude comparator—it becomesincreasingly difficult to resolve which window a voltage is in (0–1 V or 1–2 V in this case) the nearerthe input voltage is to an integer value. To resolve this, comparators with lower offset voltagescould be used and the voltage references could be made more precise. This would narrow the rangeof indeterminate input voltages, resulting in a more consistent measurement.
The measurement accuracy of the unit can be adjusted to be remarkably precise. The voltage,current, and resistance modules were all able to be calibrated to within ±1 % across all ranges.The capacitance module was more difficult, as it is more complex so there are more independentvariables that must all be adjusted to achieve a high accuracy. To further complicate things, themeasured capacitance of the DUT can vary slightly with the frequency at which the capacitor ismeasured due to varying impedance. Still, the module maintains a ±5 % accuracy across all ranges.
6 Conclusion
Overall, the project was very successful. This project was particularly challenging due to itscomplexity: each module has many nuances and difficulties of its own, and there are at least 10such modules in the project. However, I believe the strength of this design is in its modularity: eachfrontend and backend module is a separate circuit that can be debugged and tested individually.Because of this, it was possible to build each module as a separate “subproject” and get it completelyworking before integrating it into the final design.13 This also streamlined the integration process,as all that needed to be done once all the modules was working was make connections to the controlcircuit.
For a future revision, it would be interesting to implement the entire design on a PCB usingmore precise components. This would have the effect of reducing overall size, as in its present formthe project occupies seven breadboards. Moreover, improved grounding would reduce the groundloop effect, mitigate interference and provide for overall more accurate measurements.
13Anecdotal note: While each module was functional, complete integration of all the modules was not reacheduntil April 30, the day before checkoffs
14
Appendix A Schematics
The following pages contain a complete schematic diagram of the project. The first sheet is atop-level system diagram, showing each successive sheet of the schematic as a hierarchical blockand the connections between various blocks. The following pages are diagrams for the individualmodules. The design contains many potentiometers for user calibration, which I saw as a possiblesource of confusion for the reader (it could be difficult to determine what they all do). For increasedreadability, each potentiometer is accompanied by a description of what it adjusts (for example,“Av = 10” means the potentiometer should be adjusted to yield a gain of 10 for the amplifier towhich it is connected).
15
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
-15
V
+5V
+15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
A
To
p-le
vel s
yste
m d
iagr
am
A
11
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
A
To
p-le
vel s
yste
m d
iagr
am
A
11
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
A
To
p-le
vel s
yste
m d
iagr
am
A
11
1M
on
day,
Ma
y 14
, 20
18
VO
L
Vo
ltage
IN_
NIN
_P
OU
T
EN
R[4
..1]
AC
U2
Mu
ltipl
exi
ng/s
tora
ge
FL
OO
R
OU
TIN V
TH
SE
L[3
..1]
CA
P
Ca
paci
tanc
e
IN_
NIN
_P
OU
T
VR
EF
EN
R[4
..1]
CU
R
Cu
rren
t
IN_
NIN
_P
OU
T
EN
nR
[4..1
]
AC
U1
Mo
dul
us
com
para
tor
A
VR
EF
[10.
.1]
IN
DCB
FL
OO
R
P1
PW
R
1234
P2
INP
UT
12
DIS
Dis
pla
y
A DCB nS
EL[
3..1
]
CL
K
RE
S
Re
sist
ance
IN_
NIN
_P
OU
T
VR
EF
EN
R[4
..1]
RE
F
Vo
ltage
ref
ere
nce
VR
EF
[10.
.1]
CT
L1
Tim
ing
and
co
ntr
olnI
nR
[4..1
]
nC
nRnV
MO
DE
0M
OD
E1
nS
EL[
3..1
]S
EL
[3..
1]
CT
L2
Ran
ge
sele
ctio
n
MO
DE
0M
OD
E1
nV
nI
nR
nC
nR
[4..1
]
IN_
VIN
_I
IN_
RIN
_C
OU
T
R[4
..1]
EN
_V
EN
_I
EN
_R
EN
_C
CL
K
IN_
NIN
_P
VREF7VREF1
OU
T_V
OU
T_I
OU
T_R
OU
T_C
OU
T_V
OU
T_I
OU
T_R
OU
T_C
16
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
6nF
GA
IN
60nF
GA
IN
600n
F G
AIN
6uF
GA
IN
1.0
V/k
Hz
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
OU
T
VR
EF
R[4
..1
]
EN
IN_
NIN
_P
EN
+15
V
+15
V
+15
V
-15
V
-15
V
+15
V
+15
V
-15
V
+15
V
-15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
AA
Fo
ur-
ran
ge c
apac
itan
ce t
o vo
ltage
co
nve
rte
r
A
21
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
AA
Fo
ur-
ran
ge c
apac
itan
ce t
o vo
ltage
co
nve
rte
r
A
21
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
AA
Fo
ur-
ran
ge c
apac
itan
ce t
o vo
ltage
co
nve
rte
r
A
21
1M
on
day,
Ma
y 14
, 20
18
U3
A
CD
406
6B
IN/O
UT
1
OU
T/IN
2
VD
D1
4
CT
RL
13
R1
41
0k
U6
AD
633
W7
X1
1
X2
2
Y1
3
Y2
4
Z6
+V
CC
8
-VC
C5
-+
U4
B
LM
358
5 67
8 4
Q1
2N
70
00 R7
100
k
U2
LM
331
IOU
T1
IRE
F2
FOUT3
GND4
RC
5
TH
RE
SH
6
CO
MP
IN7
VS8
U3
C
CD
406
6B
IN/O
UT
4
OU
T/IN
3
VD
D1
4
CT
RL
5
R12
62k
R8
1k
R11
10k
R19
390
R13
62k
R18
100
RL1
RE
LA
Y S
PS
T
43
1 2
-+
U4A
LM
358
3 21
8 4
R1
51
0k
R3
6.8
k
R17
6.2
k
D1
1N
914
R2
10k
U3
B
CD
406
6B
IN/O
UT
11
OU
T/IN
10
VD
D1
4
CT
RL
12
RL2
RE
LA
Y S
PS
T
43
1 2
R16
1k
R9
620
k
R1
10k
R1
0
30k R
20
10k
C4
1uF
C1
100
n
R6
100
k
U5
INA
114
-VIN
2+
VIN
3
V-
4
VO
6
V+
7
RE
F5
RG
1
RG
8
R5
68k
C2
10n
F
C3
330
pF
U1
LM
555
OU
T3
RS
T4
VC
C8
GN
D1
CV
5
TR
G2
TH
R6
DS
CH
G7
R4
12k
U3
D
CD
406
6B
IN/O
UT
8
OU
T/IN
9
VD
D1
4
CT
RL
6
R1
R2
R3
R4
17
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Av
= 2
0
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
nR
[4..1
]
OU
T
IN_
P
IN_
N
EN
+5V
+15
V
-15
V
+5V
+5V
+5V
+5V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
DA
Fo
ur-
ran
ge s
ele
cta
ble
sh
unt/
curr
ent
to
volta
ge c
onv
ert
er
A
31
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
DA
Fo
ur-
ran
ge s
ele
cta
ble
sh
unt/
curr
ent
to
volta
ge c
onv
ert
er
A
31
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
DA
Fo
ur-
ran
ge s
ele
cta
ble
sh
unt/
curr
ent
to
volta
ge c
onv
ert
er
A
31
1M
on
day,
Ma
y 14
, 20
18
R30
150
RL
6
RE
LA
Y S
PS
T
43
1 2
D3
1N
91
4
R2
91
00
D4
1N
914
R21
1k
D5
1N
914
RL
7
RE
LA
Y S
PS
T
43
1 2
RL
8
RE
LA
Y S
PS
T
43
1 2
R24
100
RL
5
RE
LA
Y S
PS
T
43
1 2
R3
1
2.4
k
R26
10
R28
1
RL
3
RE
LA
Y S
PS
T
43
1 2
R23
100
R25
10
D6
1N
914
R27
1 U7
INA
114
-VIN
2+
VIN
3
V-
4
VO
6
V+
7
RE
F5
RG
1
RG
8
D2
1N
914
R22
1k
RL
4
RE
LA
Y S
PS
T
43
1 2n
R1
nR
2
nR
3
nR
4
nR
1
nR
2
nR
3
nR
4
18
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
A B C D
nS
EL[
3..1
]
CL
K
+5V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
FA
Th
ree
-dig
it se
ven
-se
gmen
t di
spla
y co
ntr
olle
r
A
41
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
FA
Th
ree
-dig
it se
ven
-se
gmen
t di
spla
y co
ntr
olle
r
A
41
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
FA
Th
ree
-dig
it se
ven
-se
gmen
t di
spla
y co
ntr
olle
r
A
41
1M
on
day,
Ma
y 14
, 20
18
U10
451
1
A7
B1
C2
D6
LT
3
BI
4
LE
5
a1
3
b1
2
c1
1
d1
0
e9
f1
5
g1
4
VD
D1
6
X1
A0
208 COM
1
E12
D13
G14
F15
A16
B17
C18
E29
D210
G211
F212
A213
B214
C215
E316
D317
G318
F319
A320
B321
C322
DP23
R3
31
0k
U9
451
1
A7
B1
C2
D6
LT
3
BI
4
LE
5
a1
3
b1
2
c1
1
d1
0
e9
f1
5
g1
4
VD
D1
6
R3
41
0k
D1
1
1N
914
R3
21
0k
U8
451
1
A7
B1
C2
D6
LT
3
BI
4
LE
5
a1
3
b1
2
c1
1
d1
0
e9
f1
5
g1
4
VD
D1
6
D7
1N
914
D1
0
1N
914
D8
1N
914
D9
1N
914
D1
2
1N
914
E1D1G1F1A1B1C1E2D2G2F2A2B2C2E3D3G3F3A3B3C3
G1
F1
E1
D1
C1
B1
A1
A2
B2
C2
D2
E2
F2
G2
A3
B3
C3
D3
E3
F3
G3
nS
EL1
nS
EL2
nS
EL3
19
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
VR
EF
[10.
.1]
IN
FL
OO
RD
CB
A
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+5V
+5V
+15
V
-15
V
+5V
+5V
+15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
GA
An
alo
g m
od
ulu
s co
mpa
rato
r, s
ectio
n 1
A
51
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
GA
An
alo
g m
od
ulu
s co
mpa
rato
r, s
ectio
n 1
A
51
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
GA
An
alo
g m
od
ulu
s co
mpa
rato
r, s
ectio
n 1
A
51
1M
on
day,
Ma
y 14
, 20
18
U14
C
74L
S07
56Q
32
N70
00
U14
B
74L
S07
34
Q2
2N
7000
R37
10k
12345
-+
U1
3D
LM
339
11
10
13
3 12
-+
U1
3A
LM
339
7 61
3 12
-+
U1
3C
LM
339
9 81
4
3 12
-+
U1
2B
LM
339
5 42
3 12
R3
5
10k
123456
-+
U1
6A
LM
393
3 21
8 4
Q5
2N
70
00
-+
U1
2D
LM
339
11
10
13
3 12
-+
U1
2C
LM
339
9 81
4
3 12
U14
A
74L
S07
12
14 7
Q4
2N
70
00
-+
U1
2A
LM
339
7 61
3 12
-+
U1
3B
LM
339
5 42
3 12
U1
5
DG
406
A3
14
A2
15
A1
16
A0
17
EN
18
D2
8
S1
19
S2
20
S3
21
S4
22
S5
23
S6
24
S7
25
S8
26
S9
11
S1
01
0
S1
19
S1
28
S1
37
S1
46
S1
55
S1
64
V+
1
V-
27
U14
D
74L
S07
98
R36
10k
123456
U1
1
74L
S14
7VC
C1
6
GN
D8
Q0
9
Q1
7
Q2
6
Q3
14
D1
11
D2
12
D3
13
D4
1
D5
2
D6
3
D7
4
D8
5
D9
10
-+
U1
6B
LM
393
5 67
8 4
VR
EF
1
VR
EF
2
VR
EF
3
VR
EF
4
VR
EF
5
VR
EF
6
VR
EF
7
VR
EF
8
VR
EF
9
VR
EF
10
CM
P1
CM
P2
CM
P3
CM
P4
CM
P5
CM
P6
CM
P7
CM
P8
CM
P9
CM
P1
0
CM
P[1
0..1
]
CM
P1
CM
P2
CM
P3
CM
P4
CM
P5
CM
P6
CM
P7
CM
P8
CM
P9
CM
P1
0
CM
P1
CM
P2
CM
P3
CM
P4
CM
P5
CM
P6
CM
P7
CM
P8
CM
P9
VR
EF
1V
RE
F2
VR
EF
3V
RE
F4
VR
EF
5V
RE
F6
VR
EF
7V
RE
F8
VR
EF
9V
RE
F1
0
A1
5B
15
C15
D15
A1
5B
15
C1
5D
15
20
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
Av
= 1
0
NU
LL NU
LL
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
SE
L[3
..1]
VT
H
IN
FL
OO
R
OU
T
+5V
+15
V
+15
V+
15V
+15
V+
15V
+15
V
-15
V
+5V
+15
V
+15
V
-15
V
+15
V
-15
V
-15
V
-15
V
+5V
+5V
-15
V
+15
V
+15
V+
15V
+15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
HA
An
alo
g m
od
ulu
s co
mpa
rato
r, s
ectio
n 2
A
61
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
HA
An
alo
g m
od
ulu
s co
mpa
rato
r, s
ectio
n 2
A
61
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
HA
An
alo
g m
od
ulu
s co
mpa
rato
r, s
ectio
n 2
A
61
1M
on
day,
Ma
y 14
, 20
18
R53
47
0
U1
9
AD
582
+V
S9
-VS
5
OU
T7
LO
GIC
+1
LO
GIC
-1
0
+IN
2
-IN
8
CH
6
NU
LL3
NU
LL4
Q6
2N
7000
R43
10k
Q7
2N
7000
R49
10k
R4
01
0k
Q8
2N
70
00
R4
81
0k
Q9
2N
7000
-+
U2
3
LM
311
2 37
56
41
8
R4
73
0k
Q10
2N
7000
D1
41
N91
4
C7
100
n
Q11
2N
70
00
R46
10k
Q12
2N
7000
D1
51
N91
4
R5
01
0k
R3
93
0k
C6
4.7
n
U2
1C
CD
406
6B
IN/O
UT
4
OU
T/IN
3
VD
D1
4
CT
RL
5
U22
INA
114
-VIN
2+
VIN
3
V-
4
VO
6
V+
7
RE
F5
RG
1
RG
8
R41
10k
R45
10k
R4
41
0k
U17
A
74L
S07
12
14 7
C8
4.7
n
R42
10k
R5
41
M
RL
9
RE
LA
Y S
PS
T
43
1 2
R5
51
.2k
U2
1B
CD
406
6B
IN/O
UT
11
OU
T/IN
10
VD
D1
4
CT
RL
12
D1
6
LE
D
R52
100
R38
10k
U21
A
CD
406
6B
IN/O
UT
1
OU
T/IN
2
VD
D1
4
CT
RL
13
R51
5.1
k
C5
100
n
U2
4
INA
114
-VIN
2+
VIN
3
V-
4
VO
6
V+
7
RE
F5
RG
1
RG
8
D1
31
N91
4
U17
B
74L
S07
34
U17
C
74L
S07
56
U1
8
AD
582
+V
S9
-VS
5
OU
T7
LO
GIC
+1
LO
GIC
-1
0
+IN
2
-IN
8
CH
6
NU
LL3
NU
LL4
SE
L1
SE
L2
SE
L3
OU
T2
MOD
OU
T1
MO
D
SEL1
SE
L2
SE
L3
IN_
BU
F
IN_BUF
OUT1
OUT2
21
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
MO
DE
0
MO
DE
1n
V nI
nR
nC
nR
[4..1
]
IN_
VIN
_I
IN_
RIN
_C
OU
T R[4
..1]
EN
_V
EN
_I
EN
_R
EN
_C
CLK
+5V
+15
V
+15
V
+15
V
+15
V
+15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
KA
Tim
ing
and
co
ntr
ol l
ogi
c, s
ect
ion
2
A
71
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
KA
Tim
ing
and
co
ntr
ol l
ogi
c, s
ect
ion
2
A
71
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
KA
Tim
ing
and
co
ntr
ol l
ogi
c, s
ect
ion
2
A
71
1M
on
day,
Ma
y 14
, 20
18
U2
5D
74L
S07
98
R5
91
0k
Q15
2N
70
00U
25F
74L
S07
13
12
Q16
2N
70
00
R5
8
100
k
Q17
2N
70
00
C9
1uF
U2
6
405
1
EN
6
A1
1
B1
0
C9
VD
D1
6
VE
E7
X3
X0
13
X1
14
X2
15
X3
12
X4
1
X5
5
X6
2
X7
4
R57
10k
1 2345
U2
5B
74L
S07
34
Q14
2N
70
00
Q19
2N
70
00
R60
10k
12345
Q20
2N
70
00
C1
01
00nF
U2
5A
74L
S07
12
14 7
U2
5C
74L
S07
56
Q13
2N
70
00
U27
LM
555
OU
T3
RS
T4
VC
C8
CV
5
TR
G2
TH
R6
DS
CH
G7
Q18
2N
70
00
U2
5E
74L
S07
11
10
R56
10k
1 234567
D17
1N
91
4
nR
1
nR
2
nR
3
nR
4R2
R1
R4
R3
R1
R2
R3
R4
22
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
6M G
AIN
600k
GA
IN
60k
GA
IN
6k G
AIN
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
VR
EF
R[4
..1
]
EN
IN_
N
IN_
P
OU
T
+15
V
-15
V
+15
V
-15
V
+15
V
+15
V
-15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
BA
Fo
ur-
ran
ge p
reci
sion
cu
rre
nt s
ourc
e/r
esis
tanc
e to
vo
ltag
e co
nve
rter
A
81
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
BA
Fo
ur-
ran
ge p
reci
sion
cu
rre
nt s
ourc
e/r
esis
tanc
e to
vo
ltag
e co
nve
rter
A
81
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
BA
Fo
ur-
ran
ge p
reci
sion
cu
rre
nt s
ourc
e/r
esis
tanc
e to
vo
ltag
e co
nve
rter
A
81
1M
on
day,
Ma
y 14
, 20
18
-+
U2
8B
LM
358
5 67
8 4
U2
0A
CD
406
6B
IN/O
UT
1
OU
T/IN
2
VD
D1
4
CT
RL
13
RL1
1
RE
LA
Y S
PS
T
43
1 2
R62
10k
R72
910
R61
10k
D18
1N
91
4
RL1
0
RE
LA
Y S
PS
T
43
1 2
R6
4
10k
R6
3
10k
R66
1M
U2
0B
CD
406
6B
IN/O
UT
11
OU
T/IN
10
VD
D1
4
CT
RL
12
R65
100
k
U2
9
INA
114
-VIN
2+
VIN
3
V-
4
VO
6
V+
7
RE
F5
RG
1
RG
8
R68
100
kU
20C
CD
406
6B
IN/O
UT
4
OU
T/IN
3
VD
D1
4
CT
RL
5
R67
10k
-+
U28
A
LM
358
3 21
8 4
R70
9.1
kU
20D
CD
406
6B
IN/O
UT
8
OU
T/IN
9
VD
D1
4
CT
RL
6
R69
1k
R71
100
R1
R2
R3
R4
23
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
SA
MP
FR
EQ
nR
[4..1
]
nV
nI
nR
nC
MODE0
MODE1
SE
L[3
..1]
nS
EL[
3..1
]
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
JA
Tim
ing
and
co
ntr
ol l
ogi
c, s
ect
ion
1
A
91
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
JA
Tim
ing
and
co
ntr
ol l
ogi
c, s
ect
ion
1
A
91
1M
on
day,
Ma
y 14
, 20
18
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
JA
Tim
ing
and
co
ntr
ol l
ogi
c, s
ect
ion
1
A
91
1M
on
day,
Ma
y 14
, 20
18
U34
A
74L
S74
D2
CL
K3
Q5
Q6
VC
C1
4P
RE
4C
LR
1
D2
41
N91
4
R89
4.7
k
D34
LE
D
D3
1
1N
914
R7
51
0k
R83
10k
R88
4.7
k
D3
6L
ED
D3
0
1N
914
R7
61
0k
D3
5L
ED
D2
9
1N
914
U31
LM
555
OU
T3
RS
T4
VC
C8
CV
5
TR
G2
TH
R6
DS
CH
G7
R8
71
00k
R84
10k
SW
1
SW
DIP
-BC
D44
C1
83
16
25
C2
D2
01
N91
4
D4
0L
ED
D1
9
1N
914
R7
41
0k
D39
LE
D
R8
2
330
C11
1uF
D2
81
N91
4
R7
31
0k
D2
5
1N
914
Q22
2N
7000
D38
LE
D
D2
71
N91
4
D3
7L
ED
D33
LE
D
Q25
2N
70
00
R79
10k
U32
A
74L
S74
D2
CL
K3
Q5
Q6
VC
C1
4P
RE
4C
LR
1
R86
1.2
kQ
242
N70
00
U3
3B
74L
S13
9
A1
4
B1
3
G1
5
Y0
12
Y1
11
Y2
10
Y3
9
D3
2L
ED
D2
21
N91
4
SW
3
SW
DIP
-BC
D44
C1
83
16
25
C2
R81
4.7
k
R77
10k
Q21
2N
7000
D2
1
1N
914
R80
4.7
k
D2
31
N91
4
U32
B
74L
S74
D1
2
CL
K1
1
Q9
Q8
VC
C1
4P
RE
10
CL
R1
3
U3
3A
74L
S13
9
A2
B3
G1
Y0
4
Y1
5
Y2
6
Y3
7
VCC16
SW
2R
ES
ET
R8
51
0k
Q23
2N
70
00
D2
61
N91
4
R78
10k
SEL3
SEL2
SEL1
ER
RO
R
ERROR
nR
1n
R2
nR
3n
R4
nR1
nR2
nR3
nR4
nV
nI
nR
nC
nSEL1
nSEL2
nSEL3
SE
L1
SE
L2
SE
L3
nS
EL1
nS
EL2
nS
EL3
24
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
CA
DD
OC
K17
76-C
68
Av
= 1
00
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
R[4
..1]
IN_
P
IN_
N
EN
OU
T
+15
V
+15
V
-15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
CA
Fo
ur-
ran
ge p
reci
sion
vo
ltag
e d
ivid
er/
atte
nuat
or
A
10
11
Mo
nda
y, M
ay
14,
2018
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
CA
Fo
ur-
ran
ge p
reci
sion
vo
ltag
e d
ivid
er/
atte
nuat
or
A
10
11
Mo
nda
y, M
ay
14,
2018
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
CA
Fo
ur-
ran
ge p
reci
sion
vo
ltag
e d
ivid
er/
atte
nuat
or
A
10
11
Mo
nda
y, M
ay
14,
2018
U35
INA
114
-VIN
2+
VIN
3
V-
4
VO
6
V+
7
RE
F5
RG
1
RG
8
R91
900
k
RL
12
RE
LA
Y S
PS
T
43
1 2
U3
0B
CD
406
6B
IN/O
UT
11
OU
T/IN
10
VD
D1
4
CT
RL
12
RL
13
RE
LA
Y S
PS
T
43
1 2
R90
9M
R92
90k
R9
6
470
U3
0C
CD
406
6B
IN/O
UT
4
OU
T/IN
3
VD
D1
4
CT
RL
5
R93
9k
R94
1k
U3
0A
CD
406
6B
IN/O
UT
1
OU
T/IN
2
VD
D1
4
CT
RL
13
R95
100
U3
0D
CD
406
6B
IN/O
UT
8
OU
T/IN
9
VD
D1
4
CT
RL
6
D41
1N
91
4
R1
R2
R3
R4
25
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
All-
anal
og D
igita
l Mul
timet
er (
DM
M)
RE
F T
RIM V
RE
F[1
0..1
]
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
+15
V
-15
V
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
EA
Pre
cisi
on
1-1
0V
inte
ger
volta
ge r
efe
renc
e
A
11
11
Mo
nda
y, M
ay
14,
2018
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
EA
Pre
cisi
on
1-1
0V
inte
ger
volta
ge r
efe
renc
e
A
11
11
Mo
nda
y, M
ay
14,
2018
Titl
e
Siz
eD
ocu
me
nt N
umbe
rR
ev
Da
te:
She
et
of
016
-SC
H0
008
EA
Pre
cisi
on
1-1
0V
inte
ger
volta
ge r
efe
renc
e
A
11
11
Mo
nda
y, M
ay
14,
2018
R11
11
00
R1
091
0k
-+
U37
B
LM
324
5 67
4 11R
112
100
U3
6A
D5
81/T
O
+V
S1
GND3
VO
UT
2
-+
U38
A
LM
324
3 21
4 11
R1
024
.3k
-+
U37
A
LM
324
3 21
4 11
-+
U38
C
LM
324
10 9
8
4 11
R1
141
0k
R11
51
00
R1
131
0k
R11
61
00
R10
31
00R
104
100
-+
U39
B
LM
358
5 67
8 4
R1
181
0k
R10
71
00
R11
91
00
R1
171
0k
R10
81
00
R97
10k
R12
01
00
-+
U38
B
LM
324
5 67
4 11
R1
061
0k
R99
12
R1
011
0k
-+
U37
D
LM
324
12
13
14
4 11
-+
U39
A
LM
358
3 21
8 4
-+
U37
C
LM
324
10 9
8
4 11
R1
101
0k
R1
051
0k
R9
81
k
R1
001
0k
-+
U38
D
LM
324
12
13
14
4 11
VR
EF
1
VR
EF
2
VR
EF
3
VR
EF
4
VR
EF
5
VR
EF
6
VR
EF
7
VR
EF
8
VR
EF
9
VR
EF
10
VR
ES
1
VR
ES
2
VR
ES
3
VR
ES
4
VR
ES
5
VR
ES
7
VR
ES
8
VR
ES
9
VR
ES
10
VR
ES
6
VR
ES
[10
..1]
VR
ES
[10
..1]
VR
ES
10
VR
ES
5
VR
ES
9V
RE
S4
VR
ES
8V
RE
S3
VR
ES
7V
RE
S2
VR
ES
6V
RE
S1
26
Appendix B Pictures
The following are photos of the project, taken at various stages of development.
27
28
