ALIASES RESOLVED - InformaticaNapoli · w w w . c h i n a f i x . c o m table_bomgroup_item...

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TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD


DRAWING

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICALApple Inc.

NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

IV ALL RIGHTS RESERVED

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

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8 7 6 5 4 2 1

12

APPDCK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISIONREV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

08/06/2014 PROTO1A

Schematic / PCB #’s

SCHEM,MLB,X425

ALIASES RESOLVED

1 OF 82

<PART_DESCRIPTION>

<SCH_NUM>

<ECODATE><ECN><REV> <ECO_DESCRIPTION>

1 OF 118

<BRANCH>

<E4LABEL>

SMC CLEAN_X305

50 01/15/2014

41KEYBOARD/TRACKPAD (2 OF 2) CLEAN_X305

49 05/30/2014

40KEYBOARD/TRACKPAD (1 OF 2) CLEAN_X305_PEG

48 02/18/2014

39USB 3.0 CONNECTORS J15_MLB

46 10/31/2012

38Camera 2 of 2 CLEAN_X305

40 06/24/2014

37Camera 1 of 2 CLEAN_X305

39 06/24/2014

36SSD Connector CLEAN_X305_PEG

37 02/18/2014

35X87 CONNECTOR CLEAN_X305

35 01/15/2014

34DDC Crossbar J15_REFERENCE

34 11/16/2012

33Thunderbolt Connector B CLEAN_X305

33 06/24/2014

32Thunderbolt Connector A CLEAN_X305

32 06/24/2014

31Thunderbolt Mobile Support CLEAN_X305

30 06/24/2014

30Thunderbolt Host (2 of 2) T29_RR

29 01/14/2013

29Thunderbolt Host (1 of 2) T29_RR

28 01/14/2013

28DDR3 Termination J15_MLB

27 10/31/2012

27DDR3 SDRAM Bank B (2 OF 2) J15_MLB

26 10/31/2012

26DDR3 SDRAM Bank B (1 OF 2) J15_MLB

25 10/31/2012

25DDR3 SDRAM Bank A (2 OF 2) J15_MLB

24 10/31/2012

24DDR3 SDRAM Bank A (1 OF 2) J15_MLB

23 10/31/2012

23DDR3 VREF MARGINING CLEAN_X305

22 01/14/2014

22CPU Memory S3 Support CLEAN_X305G

21 07/01/2014

21Project Chipset Support J15_REFERENCE

20 01/14/2013

20Chipset Support J15_REFERENCE

19 12/18/2012

19CPU & PCH XDP J15_MLB

18 10/31/2012

18PCH DECOUPLING J15_REFERENCE

17 12/18/2012

17PCH Grounds J15_REFERENCE

16 12/18/2012

16PCH Power J15_REFERENCE

15 12/18/2012

15PCH GPIO/MISC/NCTF CLEAN_X305_PEG

14 02/18/2014

14PCH PCI-E/USB J15_REFERENCE

13 12/18/2012

13PCH DMI/FDI/PM/GFX/PCI J15_REFERENCE

12 12/18/2012

12PCH RTC/HDA/JTAG/SATA/CLK J15_REFERENCE

11 12/18/2012

11CPU Decoupling J15_REFERENCE

10 12/18/2012

10CPU Ground J15_REFERENCE

9 12/18/2012

9CPU Power J15_REFERENCE

8 12/18/2012

8CPU DDR3 Interfaces J15_REFERENCE

7 12/18/2012

7CPU Clock/Misc/JTAG/CFG J15_REFERENCE

6 12/18/2012

6CPU DMI/PEG/FDI/RSVD CLEAN_X305_PEG

5 02/18/2014

5PD Parts J15_MLB

4 10/31/2012

4BOM Configuration J15_MLB

3 10/31/2012

3BOM Configuration CLEAN_X305

2 05/30/2014

2

82 SIDLE_J45

12/10/2012118

Project Specific Constraints

81 SIDLE_J45

12/10/2012117

SMC Constraints

80 SIDLE_J45

12/10/2012116

Camera Constraints

79 SIDLE_J45

12/10/2012115

Thunderbolt Constraints

78 SIDLE_J45

12/10/2012114

Memory Constraints

77 CLEAN_X305_PEG

02/18/2014113

PCH Constraints 2

76 SIDLE_J45

12/10/2012112

PCH Constraints 1

75 CLEAN_X305_PEG

02/18/2014111

CPU Constraints

74 SIDLE_J45

12/10/2012110

PCB Rule Definitions

73 J15_MLB

10/31/2012105

NC & No Test

72 J15_MLB

10/31/2012104

Functional Test Points

71 J15_MLB

10/31/2012102

Signal Aliases

70 CLEAN_X305

05/30/2014100

Power Aliases

69 CLEAN_X305G

01/14/201495

RIO Connectors

68 CLEAN_X305_PEG

02/18/201483

eDP Display Connector

67 CLEAN_X305

05/30/201481

Power Control 1/ENABLE

66 CLEAN_X305_PEG

02/18/201480

Power FETs

65 CLEAN_X305

05/30/201479

X249 Boost Power Supply

64 CLEAN_X305

01/15/201478

Misc Power Supplies

63 CLEAN_X305_PEG

02/19/201477

LCD/KBD Backlight Driver

62 CLEAN_X305_PEG

02/18/201476

1V05V POWER SUPPLY

61 CLEAN_X305_PEG

02/18/201475

5V / 3.3V Power Supply

60 CLEAN_X305

01/15/201474

1.35V DDR3L SUPPLY

59 J15_MLB

10/31/201273

CPU VR12.5 VCC Power Stage

58 CLEAN_X305_PEG

02/24/201472

CPU VR12.5 VCC Regulator IC

57 CLEAN_X305

01/15/201471

PBus Supply & Battery Charger

56 CLEAN_X305_PEG

02/18/201470

DC-In & Battery Connectors

55 CLEAN_X305

06/24/201466

AUDIO: JACK TRANSLATORS

54 CLEAN_X305

06/24/201465

AUDIO: JACK

53 JOE_J45

07/30/201364

AUDIO: SPEAKER AMP

52 JOE_J45

07/30/201363

AUDIO:CODEC, DIGITAL

51 JOE_J45

07/30/201362

AUDIO:CODEC, ANALOG

50 CLEAN_X305_PEG

02/18/201461

SPI Debug Connector

49 J15_MLB

10/31/201260

Fan Connectors

48 CHANG_J45

11/26/201258

Thermal Sensors

47 CLEAN_X305

01/14/201456

Debug Sensors

46 CLEAN_X305_PEG

02/18/201455

Load Side Voltage and Current Sensing

45 CLEAN_X305_PEG

02/18/201454

High Side Voltage and Current Sensing

44 CHANG_J45

11/26/201253

SMBus Connections

43 CLEAN_X305

05/30/201452

SMC Project Support

Table of Contents MASTER

1 MASTER

1

Contents SyncDate(.csa)

Page Page(.csa) Date

SyncContents42 CLEAN_X305

06/24/201451

SMC Shared Support

LAST_MODIFIED=Wed Aug 6 13:00:04 2014

TITLE=MLBABBREV=ABBREV

SCHEM,MLB,X305051-00330 CRITICALSCH1

PCBF,MLB,X305820-00138 CRITICALPCB1

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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM



TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

Module Parts

COMMON/DEVEL BOM

BOM Variants

DRAM SPD Straps

X425 BOM Groups

BOM ConfigurationSYNC_MASTER=CLEAN_X305 SYNC_DATE=05/30/2014

SMC_PROG:BASE,BOOTROM_PROG:PROTO1A,TBTROM:PROGX425_PROGPARTS

BKLT:PROD,SENSOR_NONPROD:NX425_PVT

X425_COMMON2 EDP:YES,XDP,SSD_PWR_EN:GPIO,CAM_WAKE:NO,SAMCONN,APCLKRQ:ISOL,DDRREG_PGD:N,CRW_SPRT,WLAN_SW:SIL

X425_DEVEL:ENG ALTERNATE,XDP_DEBUG,S0PGOOD_ISL,SENSOR_NONPROD:Y,SENSOR_NONPROD_R,BKLT:ENG,DBGLED,X249:BOOST

X425_COMMONCOMMON PARTS,MLB,X425685-00039

X425_DEVEL:ENG985-00043 DEV,MLB,X425

X425_COMMON1 CPUMEM:S0,TBTHV:P15V,SKIP_5V3V3:AUDIBLE,CPUPEG:X8X8,S2_PWR:S0,SMC_SUSACK:YES

ALTERNATE,XDP_DEBUG,BKLT:PROD,SENSOR_NONPROD:N,DBGLEDX425_DEVEL:DVT

XDP_CONN,XDP_PCHXDP_DEBUG

X425_COMMON ALTERNATE,COMMON,X425_COMMON1,X425_COMMON2,X425_PROGPARTS

985-00043 DEV,MLB,X4251 DEVEL_BOMCRITICALDEVEL

685-00039 COMMON PARTS,MLB,X425 BASE BASE_BOMCRITICAL1

MICRON_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:LRAM:MICRON_1866

RAM:HYNIX_1866_S HYNIX_1866_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

337S00057 CRW,SR1ZW,PRQ,C0,2.2,47W,4+3E,1.2,6M,BGA CRITICALU05001 CPU_CRW:BETTER

IC,SDRAM,25NM,512MX8,DDR3L-1866,78B FBGA HYNIX_1866_S333S0802 16 U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570 CRITICAL

IC,QEWV,LPT-M,HM87,C2,SR199,PRQ,FCBGA337S4542 U11001 CRITICAL

RAM:HYNIX_1866 HYNIX_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM:MICRON_1866_S MICRON_1866_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

XDP_DEBUGX425_DEVEL:PVT

BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:HYNIX_1866PCBA,MLB,CTO,16G-HYN,X425639-00534

PCBA,MLB,CTO,16G-MIC,X425639-00535 BASE_BOM,DEVEL_BOM,CPU_CRW:CTO,RAM:MICRON_1866

337S00058 U05001 CPU_CRW:BESTCRITICALCRW,SR1ZX,PRQ,C0,2.5,47W,4+3E,1.2,6M,BGA

337S00059 CRW,SR1ZY,PRQ,C0,2.8,47W,4+3E,1.2,6M,BGA CPU_CRW:CTOCRITICAL1 U0500

IC,SDRAM,4GBIT,DDR3L-1600,GEMMA,96B FBGA CRITICAL1 U4000333S0700

U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670IC,SDRAM,4GBIT,DDR3-1866,V80A,78B,FBGA MICRON_1866333S0719 CRITICAL32

IC,SDRAM,25NM,512MX8,DDR3L-1866,78B FBGA U2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2400,U2410,U2420,U2430,U2440,U2450,U2460,U2470,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570,U2600,U2610,U2620,U2630,U2640,U2650,U2660,U2670 HYNIX_186632333S0802 CRITICAL

IC,SDRAM,4GBIT,DDR3-1866,V80A,78B,FBGA MICRON_1866_S333S0719 16 CRITICALU2300,U2310,U2320,U2330,U2340,U2350,U2360,U2370,U2500,U2510,U2520,U2530,U2540,U2550,U2560,U2570

IC,BCM15700A2,S2 PCIE CMRA,8X8,208FCBGA CRITICAL338S1264 U39001

1 U2800 CRITICAL338S1247 IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

<BRANCH>

<SCH_NUM>

<E4LABEL>

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TABLE_ALT_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

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Apple Inc.


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Alternate Parts

EFI ROM

SMC

Programmables - All builds

IC,SMC-B1,40MHZ/50DMIPS,SCPL FW,157BGA CRITICAL SMC_PROG:BLANK338S1214 1 U5000

CRITICALIC,SMC-B1,EXT (V2.24A31) PROTO 1A,X425341S00125 SMC_PROG:BASE1 U5000

SYNC_DATE=10/31/2012SYNC_MASTER=J15_MLB

BOM Configuration

DDS alt to STALL371S0713 371S0558

376S0820376S1080 ALL Diodes alt to On Semi

376S1217 376S0855 Toshiba alt to DiodesALL

Kemet alt to Sanyo128S0376128S0371 ALL

197S0480197S0481 ALL Epson Alt to NDK

138S0811138S0846 Samsung alt to MurataALL

127S0162127S0164 ALL Rohm alt to Vishay

152S1645152S0461 ALL Cyntec alt to Vishay

155S0667 155S00008 ALL Panasonic alt to TDK

NXP alt to Diodes376S0855376S1129 ALL

376S1128 NXP alt to DiodesALL376S1089

128S0364 128S0264 ALL Kemet alt to Sanyo

197S0478 NDK Alt to EpsonALL197S0479

138S0739 138S0706 ALL Samsung alt to Murata

ALL Diodes alt to Fairchild376S1053 376S0604

128S0311 128S0329 ALL NEC alt to Sanyo

311S0649 311S0541 ALL ON alt to Toshiba

138S0732 138S0715 ALL Rohm alt to Vishay

Samsung alt to Murata138S0803 ALL138S0639

138S0674138S0843 Samsung alt to MurataALL

U6100 CRITICALIC,SERIAL FLASH,64MB,3V,WSON,6X5MM BOOTROM_BLANK:MAC1335S00006

CRITICAL BOOTROM_PROG:PROTO1AIC,EFI ROM (VXXXX) PROTO 1A,X425 U61001341S00131

Infineon alt to InfineonALL377S0184 377S00011

On Semi alt to InfineonALL377S00011377S0155

740S00003 ALL AEM alt to Tyco740S0135

376S00014 376S0761 ALL Toshiba alt to Vishay

333S0700333S0704 ELPIDA to HYNIXALL

IC,SERIAL FLASH,64MB,3V,WSON,6X5MM BOOTROM_BLANK:WINU6100 CRITICAL1335S00007

T29,FALCON RIDGE(VXXXX)PROTO 1A,X425341S00133 U28901 TBTROM:PROGCRITICAL

IC,SERIAL SPI FLASH ROM,4MBIT,50MHZ,USON335S0915 U2890 TBTROM:BLANKCRITICAL1

<BRANCH>

<SCH_NUM>

<E4LABEL>

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|

|

|

|

X425 StAND OFF

SMT GND TEST PONTS RIO FLEX BRACKET BOSS (860-00166)X425 POGO PINS

817-00335

|-----------------------

806-00452

|

|

-----------------------

|

||

|

860-1448

|

||

||

|

|

|

|

|

|

|

||

||

||

Frame Holes

||

|

||

|

||

|

|

|

|

|||

|

|

806-9391

|

|

817-00336

APN 806-2247

-----------------------

860-00167860-00173

-----------------------

X425 THERMAL MODULE STANDOFF860-00184

1

SH0425OMIT_TABLE

STDOFF-4.5OD1.8H-SM

1

ZT04152.8R2.3

1

SH0423STDOFF-4.5OD1.8H-SM

OMIT_TABLE

1

ZT0470

SL-1.1X0.45-1.4x0.75

TH-NSP

1

SH0450

SHLD-MLB-USB-J45

SM

1

SH0432POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

1


SM

1

SH0435SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

1

ZT0471

SL-1.1X0.45-1.4x0.75

TH-NSP

1

ZT0472

SL-1.1X0.45-1.4x0.75

TH-NSP

1

ZT0473TH-NSP

SL-1.1X0.45-1.4x0.75

1

ZT0450

SL-2.3X3.9-2.9X4.5

TH-NSP

2

1

SH04402.9OD1.2ID-1.35H-SM

2

1

SH04412.9OD1.2ID-1.35H-SM

2

1

SH04432.9OD1.2ID-1.35H-SM

2

1

SH04442.9OD1.2ID-1.35H-SM

1

ZT0490SMT-PAD-NSP

2.1SM2.0MM-CIR

1

ZT04912.1SM2.0MM-CIR

SMT-PAD-NSP1

ZT0492SMT-PAD-NSP

2.1SM2.0MM-CIR

1

BR0401MLB-MTG-BRKT-J5TH

1


SM

2

1

SH04602.9OD1.2ID-1.35H-SM

2

1

SH04612.9OD1.2ID-1.35H-SM

1

SH04275.0OD1.85ID-2.35H-SM

2

1

SH04622.9OD1.2ID-1.35H-SM

2

1

SH04672.9OD1.2ID-1.35H-SM

2

1

SH04662.9OD1.2ID-1.35H-SM

2

1

SH04652.9OD1.2ID-1.35H-SM

1

SH04803.5OD1.85ID-2.0H

1

SH04813.5OD1.85ID-2.0H

1

SH04265.0OD1.85ID-2.35H-SM

1

SH04295.0OD1.85ID-2.35H-SM

1

SH04285.0OD1.85ID-2.35H-SM

2

1

SH04742.9OD1.2ID-1.35H-SM

2

1

SH04722.9OD1.2ID-1.35H-SM

2

1

SH04732.9OD1.2ID-1.35H-SM

2

1

SH04702.9OD1.2ID-1.35H-SM

2

1

SH04712.9OD1.2ID-1.35H-SM

1

SH0451SM

SHLD-FENCE-MLB-T29-X305

1

SH04465.0OD2.9ID-2.38H

1

SH04455.0OD2.9ID-2.38H-FD2

1

SH04244.5OD1.9H-SM-X304

1


SM

1


SM

860-00184 STANDOFF,THERMAL/FAN,W/O MYLAR,X3052 SH0423,SH0425 CRITICAL

PD PartsSYNC_MASTER=J15_MLB SYNC_DATE=10/31/2012

1946-3819 EDGE_BOND CRITICALD2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC

GND

GND

GND

GND

GND

GND

MAKE_BASE=TRUE

<BRANCH>

<SCH_NUM>

<E4LABEL>

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IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DDIB_TXP3

DDIB_TXN2

DDIB_TXP1

DDIB_TXN1

DDIB_TXP0

DDIC_TXP3

DDIC_TXN3

DDIC_TXN2

DDIC_TXP1

DDID_TXN2

DDID_TXP2

DDID_TXN3

DDID_TXP3

DDID_TXN0

DDID_TXP0

DDID_TXN1

DDID_TXP1

EDP_AUXN

EDP_HPD

EDP_AUXP

EDP_TXN1

EDP_TXP0

EDP_TXP1

DDIB_TXP2

DDIB_TXN3

DDIC_TXN0

DDIC_TXP0

DDIC_TXN1

DDIB_TXN0

EDP_RCOMP

EDP_DISP_UTIL

FDI_TXN0

FDI_TXP0

FDI_TXN1

FDI_TXP1

DDIC_TXP2

EDP_TXN0

SYM 10 OF 12

FDI

DIGITAL DISPLAY INTERFACES

EDP

DAISY_CHAIN_NCTF

RSVD139

RSVD138

RSVD137

RSVD136

RSVD135

RSVD134

RSVD133

RSVD132

DAISY_CHAIN_NCTF

SYM 12 OF 12RESERVED

TP

TP

TP

TP

TP

TP

TP

TP

NCNCNCNCNCNCNCNC

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

DMI_RX1

DMI_TX3

DMI_TX2

DMI_TX1

DMI_TX0

DMI_TX3*

DMI_TX2*

DMI_TX1*

DMI_TX0*

DMI_RX3

DMI_RX2

DMI_RX0

DMI_RX3*

DMI_RX2*

DMI_RX1*

DMI_RX0*

PEG_RX15

PEG_RX14

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

FDI_CSYNC

DISP_INT

PEG_RCOMP

PEG_TX0*

PEG_TX1*

PEG_TX2*

PEG_TX3*

PEG_TX4*

PEG_TX5*

PEG_TX6*

PEG_TX7*

PEG_TX8*

PEG_TX9*

PEG_TX10*

PEG_TX11*

PEG_TX12*

PEG_TX13*

PEG_TX14*

PEG_TX15*

PEG_RX0*

PEG_RX1*

PEG_RX2*

PEG_RX3*

PEG_RX4*

PEG_RX5*

PEG_RX6*

PEG_RX7*

PEG_RX8*

PEG_RX9*

PEG_RX10*

PEG_RX11*

PEG_RX12*

PEG_RX13*

PEG_RX14*

PEG_RX15*

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9

PEG_TX10

PEG_TX11

PEG_TX12

PEG_TX13

PEG_TX14

PEG_TX15

DMI

PCI EXPRESS BASED INTERFACE SIGNALS

FDI

SYM 1 OF 12

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

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8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Each corner of CPU has two testpoints.Other corner test signals connected in

Port D pins out of order

CPU Daisy-Chain Strategy:

NO_TESTNO_TEST

to match Intel symbol.

daisy-chain fashion. Continuity shouldexist between both TP’s on each corner.

35 71 75

71

71

28 71 75

71

71

28 71 75

28 71 75

28 71 75

71

71

71

71

35 71 75

35 71 75

35 71 75

35 71 75

71

71

71

71

28 71 75

28 71 75

28 71 75

28 71 75

71

71

71

71

35 71 75

35 71 75

35 71 75

35 71 75

71

71

71

71

28 71 75

28 71 75

28 71 75

28 71 75

71

71

71

71

B14

D12

A14

C12

B12

D14

A12

C14

AG6

E14

E12

F14

F15

B16

D16

B17

D17

A16

C16

A17

C17

B20

D20

B21

D21

A20

C20

A21

C21

B24

D24

B25

D25

A24

C24

A25

C25

U0500BGA

OMIT_TABLE

HASWELL

2

1R053024.9

402MF-LF1/16W1%

2

1R0531

402MF-LF1/16W5%10k

G17

G14

AN37

AN35

AG45

AF9

AE9

AD45

D54

D1

C54

C3

C2

C1

BF53

BF52

BF51

BF4

BF3

BF2

BE54

BE53

BE52

BE3

BE2

BE1

BD54

BD1

BC54

BC1

B54

B53

B52

B3

B2

A53

A52

A51

A4

A3

U0500BGA

OMIT_TABLE

HASWELL

1TP0500TP-P6

1 TP0501TP-P6

1 TP0511TP-P6

1 TP0531TP-P6

1TP0510TP-P6

1TP0520TP-P6

1TP0530TP-P6

1TP0521TP-P6

12 75

12 73 75

12 73 75

12 73 75

12 73 75

12 73 75

12 75

12 73 75

12 75

12 75

12 73 75

12 73 75

12 73 75

12 73 75

12 73 75

12 73 75

2

1R051024.91%

MF-LF1/16W

402

12 75

12 75

J1

J4

G2

J6

E2

G5

E4

D6

T2

T3

R3

R1

R5

T5

B5

C6

J2

J3

G3

J5

E3

G4

D4

E6

T1

T4

R4

R2

R6

T6

C5

B6

L3

M3

L1

M5

A9

C9

F9

A10

Y1

Y4

V2

V3

Y5

M1

D10

F10

L4

M4

L2

L5

B9

D9

E9

B10

Y2

Y3

V1

V4

V5

M2

C10

E10

AH6

F11

AG1

AG3

AF3

AF1

AG2

AG4

AF4

AF2

AC2

AC4

AB4

AB1

AC1

AC3

AB3

AB2

F12

U0500BGA

HASWELL

OMIT_TABLE

35 71 75

35 71 75

35 71 75

71

35 71 75

71

71

71

28 71 75

28 71 75

71

28 71 75

28 71 75

71

71

71

35 71 75

35 71 75

35 71 75

SYNC_DATE=02/18/2014SYNC_MASTER=CLEAN_X305_PEG

CPU DMI/PEG/FDI/RSVD

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<0>

TP_PEG_D2RP<15>TP_PEG_D2RP<14>TP_PEG_D2RP<13>TP_PEG_D2RP<12>PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_P<1>PCIE_TBT_D2R_P<2>

=PEG_D2R_P<6>=PEG_D2R_P<7>PCIE_TBT_D2R_P<0>

=PEG_D2R_P<5>=PEG_D2R_P<4>PCIE_SSD_D2R_P<3>PCIE_SSD_D2R_P<2>

PCIE_SSD_D2R_P<0>

TP_PEG_D2RN<15>

TP_PEG_D2RN<13>TP_PEG_D2RN<14>

PCIE_TBT_D2R_N<3>TP_PEG_D2RN<12>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<0>PCIE_TBT_D2R_N<1>

=PEG_D2R_N<6>=PEG_D2R_N<7>

=PEG_D2R_N<5>

PCIE_SSD_D2R_N<3>=PEG_D2R_N<4>

PCIE_SSD_D2R_N<1>PCIE_SSD_D2R_N<2>

TP_PEG_R2D_CP<15>

TP_PEG_R2D_CP<13>TP_PEG_R2D_CP<14>

TP_PEG_R2D_CP<12>PCIE_TBT_R2D_C_P<3>PCIE_TBT_R2D_C_P<2>PCIE_TBT_R2D_C_P<1>PCIE_TBT_R2D_C_P<0>

=PEG_R2D_C_P<6>=PEG_R2D_C_P<7>

=PEG_R2D_C_P<5>=PEG_R2D_C_P<4>PCIE_SSD_R2D_C_P<3>PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_P<0>PCIE_SSD_R2D_C_P<1>

TP_PEG_R2D_CN<15>

TP_PEG_R2D_CN<13>TP_PEG_R2D_CN<14>

TP_PEG_R2D_CN<12>

PCIE_TBT_R2D_C_N<2>PCIE_TBT_R2D_C_N<3>

=PEG_R2D_C_N<5>=PEG_R2D_C_N<4>PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_N<0>PCIE_SSD_R2D_C_N<1>PCIE_SSD_R2D_C_N<2>

PCIE_TBT_R2D_C_N<1>PCIE_TBT_R2D_C_N<0>=PEG_R2D_C_N<7>=PEG_R2D_C_N<6>

CPU_PEG_RCOMP

DMI_S2N_N<2>

DP_INT_ML_C_P<3>DP_INT_ML_C_N<3>DP_INT_ML_C_P<2>DP_INT_ML_C_N<2>

TRUE CPU_DC_BE53_BF53

CPU_DC_A3_B3 TRUECPU_DC_A4

DP_TBTSNK0_ML_C_P<0>

PPVCOMP_S0_CPU

DP_INT_ML_C_P<1>

CPU_DC_BC54

TRUECPU_DC_A3_B3

CPU_DC_BF51

CPU_DC_B54_C54TRUE

DMI_S2N_N<0>

CPU_EDP_RCOMP

HDMI_CLK_P

PPVCCIO_S0_CPU

DP_INT_AUXCH_C_N

PPVCOMP_S0_CPU

DMI_N2S_N<2>

DMI_N2S_P<1>

DMI_N2S_N<3>

DMI_N2S_N<0>DMI_N2S_N<1>

DMI_N2S_P<3>

DMI_S2N_P<2>

FDI_INT

FDI_CSYNC

DMI_S2N_P<1>DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<3>

DMI_N2S_P<0>

DMI_N2S_P<2>

DP_INT_ML_C_N<0>


TP_EDP_DISP_UTIL

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK1_ML_C_N<1>DP_TBTSNK1_ML_C_P<0>DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_N<3>DP_TBTSNK0_ML_C_P<2>

DP_INT_ML_C_P<0>

DP_INT_ML_C_N<1>

TP_DP_IG_D_MLN<1>TP_DP_IG_D_MLP<0>

HDMI_CLK_NTP_DP_IG_D_MLP<2>TP_DP_IG_D_MLN<2>

DP_TBTSNK1_ML_C_P<1>DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_N<3>DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK0_ML_C_N<1>DP_TBTSNK0_ML_C_P<1>DP_TBTSNK0_ML_C_N<2>


DP_INT_AUXCH_C_P

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<0>

DP_IG_A_HPD_L

CPU_DC_A53_B53 TRUE

TRUECPU_DC_A52_B52

TRUECPU_DC_B2_C3

TRUECPU_DC_A53_B53TRUECPU_DC_A52_B52

TRUECPU_DC_BE3_BF3TRUECPU_DC_BE2_BF2TRUECPU_DC_BD54_BE54

TRUECPU_DC_BE2_BF2TRUECPU_DC_BD1_BE1TRUECPU_DC_BD54_BE54

TRUECPU_DC_BD1_BE1

TRUECPU_DC_B54_C54

CPU_DC_BE52_BF52TRUE

CPU_DC_C1_C2TRUECPU_DC_C1_C2TRUECPU_DC_B2_C3TRUE

TRUECPU_DC_BE52_BF52TRUECPU_DC_BE3_BF3

CPU_DC_D1

CPU_DC_BF4

CPU_DC_BC1

TRUECPU_DC_BE53_BF53

CPU_DC_A51

CPU_DC_D54

5 OF 82

5 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

75

68 71 75

68 71 75

68 71 75

68 71 75

5

5

28 71 75

5 8

68 71 75

5 5

75

69 71 72 75

6 8 10 18 58

68 71 75

5 8

68 71 75

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

68 71 75

68 71 75

71

71

69 71 72 75

71

71

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

28 71 75

68 71 75

71

71

20

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

5

w w w

. c h

i n a

f i x

. c o

mBI

BI

BI

BI

BI

IN

IN

OUT

BI

NC

OUT

BI

SSC_DPLL_REF_CLKP

BCLKP

BCLKN

DPLL_REF_CLKP

DPLL_REF_CLKN

CATERR*

PROCHOT*

PROC_DETECT*

PECI

BPM7*

BPM6*

BPM5*

BPM4*

BPM2*

BPM3*

BPM1*

BPM0*

DBR*

TDO

TDI

TRST*

TMS

TCK

PREQ*

PRDY*

SM_DRAMRST*

SM_RCOMP2

SM_RCOMP1

SM_RCOMP0

PLTRSTIN*

PWRGOOD

THERMTRIP*

PM_SYNC

SM_DRAMPWROK

SSC_DPLL_REF_CLKN

THERMAL

DDR3

PWR

JTAG

CLOCK

SYM 2 OF 12

OUT

IN

IN

IN

IN

IN

IN

RSVD_TP24

RSVD_TP25

RSVD_TP26

RSVD49

RSVD48

RSVD47

RSVD_TP4

RSVD_TP23

RSVD_TP35

RSVD_TP36

RSVD_TP37

RSVD_TP18

RSVD_TP17

CFG15

CFG13

CFG14

CFG12

CFG7

CFG8

CFG9

CFG10

CFG11

TESTLO_F20

CFG4

CFG3

CFG2

CFG5

CFG6

CFG1

CFG0

TESTLO_F21

VSS_F51

VSS_F52

VSS_G19

VCC_F22

VSS_H53

VSS_H51

VSS_H52

VSS_H54

CFG17

CFG18

CFG19

CFG16

CFG_RCOMP

RSVD92

RSVD93

RSVD94

RSVD95

RSVD9

RSVD10

RSVD41

RSVD42

RSVD16

RSVD50

RSVD52

RSVD51

RSVD_TP1

RSVD11

RSVD_TP38

RSVD_TP39

RSVD_TP27

RSVD_TP28

RSVD_TP2

RSVD_TP3

RESERVEDSYM 11 OF 12

NCNC

NCNC

NCNC

NCNC

NC

NC

NCNC

NC

IN

OUT

IN

IN

IN

OUT

ININ

INOUT

BI

BI

BI

Apple Inc.


124578

B

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8 7 6 5 4 3

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A


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12

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

(IPU)

(IPU)

These can be placed close to

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPD)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

J1800 and only for debug access

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.

18 75

18 75

18 75

18 75

18 75

2

1R0611PLACE_NEAR=U0500.F50:157mm

402MF-LF1/16W

5%10K

12 21 75

14 18 75

14 42 75

14 42 75

2

1R0614

PLACE_NEAR=U0500.BB52:12.7mm

1001%1/16WMF-LF402 2

1R0613751%1/16WMF-LF402


2

1R06121001%1/16WMF-LF402


41 75

2

1R06015%

1/16W

402

62

MF-LF

2 1

R0603

402MF-LF

5%

56

1/16W

41 42 58 75

M53

M51

D53

M49

N49

N54

Y6

V6

BB52

BB53

BB51

BE51

AP48

F50

E50

C51

N52

N53

D52

L54

G51

AE6

AC6

F53

G50

P51

U51

P53

R49

N50

P49

R50

R51

AA6

AB6

U0500BGA

HASWELL

OMIT_TABLE

21

11 75

11 75

11 75

11 75

11 75

11 75

H54

H53

H52

H51

G19

F52

F51

F22

F21

F20

L53

L52

L51

G6

G24

G21

G12

G10

F6

F25

F24

F1

E1

BE4

BD3

A6

A5

N51L50

L49

H50

G53

F8

F16

E5

BD4

BC4

B50

AU27

AU26

AM48

AL6

AH49

R54

Y54

Y49

W51

V51

AB49

Y50

AE49

AC49

V52

V53

Y51

Y52

R52

R53

V54

U53

W53

Y53

AD49

AG49

U0500HASWELL

OMIT_TABLE

BGA

2

1R0690

MF-LF402

1/16W1%49.9

2

1R068049.9

1%1/16WMF-LF

402

2

1R068549.9

1%1/16WMF-LF

402

2

1R0649

402MF-LF

5%1K

1/16W

NOSTUFF

2

1R0643

MF-LF402

1/16W5%

NOSTUFF

1K

2

1R0641NOSTUFF

1K5%

1/16WMF-LF

402 2

1R0640NOSTUFF

1K5%1/16WMF-LF402

2

1R0647NOSTUFF

1K5%

1/16WMF-LF

4022

1R06461K5%

1/16WMF-LF

402

CPUCFG6_PD

2

1R06451K5%1/16WMF-LF402

CPUCFG5_PD

2

1R0644

402MF-LF1/16W

5%

EDP:YES

1K

2

1R0642

402MF-LF1/16W5%1K

NOSTUFF

2

1R06213.32K

402MF-LF1/16W

1%

PLACE_NEAR=U0500.AP48:51.562mm

2

1R0648

402MF-LF1/16W

5%1K

NOSTUFF

18 72 75

18 72 75

18 72 75

18 72 75

18 72 75

18 72 75

18 72 75

2

1R06201.82K

PLACE_NEAR=R0621.2:1mm

1%1/16WMF-LF

402

12 75

14 18 19 75

18 75

18 75

18 75

CPUCFG5_PDCPUPEG:X8X8

CPUCFG6_PD,CPUCFG5_PDCPUPEG:X8X4X4

SYNC_MASTER=J15_REFERENCE SYNC_DATE=12/18/2012

CPU Clock/Misc/JTAG/CFG

PP1V35_S3RS0_CPUDDR

CPU_CFG<2>

PPVCCIO_S0_CPU

CPU_PROCHOT_L

CPU_CFG<9>CPU_CFG<3>

CPU_CFG<16>



CPU_RESET_L

CPU_PWRGD

CPU_CLK135M_DPLLREF_N

PM_THRMTRIP_L

TP_CPU_RSVD_TP17

CPU_CFG<18>

TP_CPU_RSVD_TP39TP_CPU_RSVD_TP38



CPU_CFG<19>

CPU_TESTLO_F20

CPU_CFG<0>

TP_CPU_RSVD_TP18

CPU_TESTLO_F21

TP_CPU_RSVD_TP47

TP_CPU_RSVD_TP23

TP_CPU_RSVD_TP3

CPU_CFG_RCOMP



CPU_CFG<16>

CPU_CFG<17>

CPU_CFG<3>

XDP_CPU_PRDY_L

XDP_CPU_TMS

XDP_DBRESET_L

XDP_BPM_L<0>XDP_BPM_L<1>


XDP_BPM_L<4>XDP_BPM_L<5>XDP_BPM_L<6>

XDP_CPU_TDOXDP_CPU_TDI

XDP_CPUPCH_TRST_L

TP_CPU_RSVD_TP24

TP_CPU_RSVD_TP35

CPU_CFG<4>


CPU_CFG<5>CPU_CFG<6>CPU_CFG<7>CPU_CFG<8>



CPU_CFG<15>

TP_CPU_RSVD_TP36

TP_CPU_RSVD_TP4

TP_CPU_RSVD_TP1


TP_CPU_RSVD_TP37

PPVCC_S0_CPU

CPU_SM_RCOMP<1>CPU_SM_RCOMP<0>

PM_SYNC

CPU_CLK135M_DPLLREF_P

CPU_CLK135M_DPLLSS_NCPU_CLK135M_DPLLSS_P

DMI_CLK100M_CPU_NDMI_CLK100M_CPU_P

CPU_PECI

TP_CPU_RSVD_TP2

CPU_CATERR_L

CPU_PROCHOT_R_L

XDP_CPU_TCK

XDP_CPU_PREQ_L

CPU_MEM_RESET_L

CPU_SM_RCOMP<2>

XDP_BPM_L<7>

PM_MEM_PWRGD

<BRANCH>

<SCH_NUM>

<E4LABEL>

6 OF 118

6 OF 82

8 10 21 66 67 70 82

6 18 75

5 8 10 18 58

6 18 75

6 18 72 75

6 18 75

6 18 75

6 18 75

6 18 75

6 18 75

18 75

18 75

6 18 75

6 18 75

6 18 75

6 18 75

18 75

6 18 75

18 75

6 18 72 75

6 18 75

6 18 75

6 18 75

6 18 75

6 18 75

6 18 75

18 75

18 75

18 75

18 75

18 75

18 75

8 10 46 59 70 72

75

75

75

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

OUT

NC

NC

NC

NC

NCNCNCNCNCNCNC NC

NC

NCNCNC

NCNC

NC

NC

NC

NCNCBI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

RSVD160

RSVD161SA_DQ60

SA_DQ59

RSVD163

RSVD164

RSVD166

RSVD167

RSVD169

RSVD170

SA_MA15

SA_MA14

SA_MA10

SA_CKN2

RSVD168

RSVD165

RSVD162

RSVD25

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

SA_DQ45

SA_DQ46

SA_DQ47

SA_DQ6

SA_DQ5

SA_DQ7

SA_DQ10

SA_DQ3

SA_DQ4

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ35

SA_DQ34

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ29

SA_DQ28

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ14

SA_DQ13

SA_DQ9

SA_DQ2

SA_DQ1

SA_DQ0

SA_DQ30

SA_CKE0

SA_CKE2

SA_CKE3

SA_CS0*

SA_CS2*

SA_CS3*

SA_ODT0

SA_ODT1

SA_ODT2

SA_BS0

SA_ODT3

SA_BS2

SA_BS1

SA_RAS*

VSS_BC21

SA_WE*

SA_CAS*

SA_MA1

SA_MA0

SA_MA3

SA_MA2

SA_MA4

SA_MA6

SA_MA5

SA_MA7

SA_MA8

SA_MA9

SA_MA11

SA_MA12

SA_MA13

SA_DQS0

SA_DQS1

SA_DQS2

SA_DQS3

SA_DQS5

SA_DQS4

SA_DQS6

SA_DQS7

SA_DQSN0

SA_DQSN1

SA_DQSN2

SA_DQSN3

SA_DQSN4

SA_DQSN5

SA_DQSN6

SA_DQSN7

SM_VREF

SA_DQ20

SA_CS1*

SA_CKE1

SA_CKN0

SA_CKP0

SA_CKN1

SA_CKP1

SA_CKP2

SA_CKN3

SA_CKP3

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ8

SA_DQ11

SA_DQ12

MEMORY CHANNEL A

SYM 3 OF 12

VSS_AU30

SB_BS2

SB_CKP3

SB_CKN3

SB_CKP2

SB_CKN2

SB_CKP1

SB_CKN1

SB_CKP0

SB_DQS7

SB_DQS6

SB_DQS2SB_DQ63

SB_DQ62

SB_DQ61

SB_DQ60

SB_DQ59SB_DQSN7

SB_DQ58

SB_DQ57SB_DQSN5

SB_DQ56SB_DQSN4

SB_DQ55

SB_DQ54SB_DQSN2

SB_DQ53SB_DQSN1

SB_DQ52SB_DQSN0

SB_DQ51

SB_DQ50SB_MA15

SB_DQ49SB_MA14

SB_DQ48SB_MA13

SB_DQ47SB_MA12

SB_DQ46SB_MA11

SB_DQ45SB_MA10

SB_DQ44SB_MA9

SB_DQ43SB_MA8

SB_DQ42SB_MA7

SB_DQ41SB_MA6

SB_DQ40SB_MA5

SB_DQ39SB_MA4

SB_DQ38SB_MA3

SB_DQ37SB_MA2

SB_DQ36SB_MA1

SB_MA0

SB_CAS*

SB_WE*

SB_RAS*SB_DQ30

SB_DQ27

SB_BS1SB_DQ26

SB_BS0SB_DQ25

SB_DQ24SB_ODT3

SB_DQ23SB_ODT2

SB_DQ22SB_ODT1

SB_DQ21SB_ODT0

SB_DQ20

SB_CS3*SB_DQ19

SB_CS2*SB_DQ18

SB_CS1*SB_DQ17

SB_CS0*SB_DQ16

SB_DQ15

SB_CKE3SB_DQ14

SB_DQ13

SB_DQ12

SB_DQ11SB_CKE2

SB_DQ10

SB_DQ9

SB_DQ8

SB_CKE1SB_DQ7

SB_DQ6

SB_DQ5

SB_DQ4

SB_DQ3

SB_DQ2

SB_DQ1

SB_DQ0

SB_DQ35

SB_DQ34

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQS4

SB_DQS3

SB_DQS5

SB_DQS1

SB_DQS0

SB_DQSN6

SB_DQSN3

RSVD172

RSVD173

RSVD174

RSVD175

RSVD176

RSVD177

RSVD178

RSVD179

RSVD180

RSVD181

SB_CKE0

SB_CKN0

RSVD171

SB_DQ28

SB_DQ29

MEMORY CHANNEL B

SYM 4 OF 12

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNC

NCNC

NCNC

NCNCNC

NC

NCNC

NC

NCNCNC

NCNC

NCNC

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



22 75

22 75

22

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

23 27 78

23 27 78

24 27 78

24 27 78

24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

BC21

AM6

AN6

BF21

BF20

BD17

BF17

BF16

BC16

BC32

BE27

BC28

BF27

BC27

BF32

BE28

BF28

BE31

BE32

BE20

BC31

BF31

BD20

BD27

BD28

AT2

BA3

BE7

BD12

AY46

AW52

AP53

AJ52

AT3

BA2

BD7

BE12

BA46

AW53

AP52

AJ53

AN52

AN54

AK53

AR3

AR2

AU4

AU2

AK52

AR4

AR1

AU1

AU3

AW1

AW4

BB2

BB3

AW2

AW3

AH51

BC2

BB4

BD6

BE5

BF9

BD9

BC6

BE6

BE9

BC9

AH53

BE11

BD11

BD14

BE14

BF11

BC11

BC14

BF14

BA43

BA49

AK54

AY43

AY45

BA45

BA47

AY49

AY47

AY53

AY54

AV54

AV51

AK51

AY51

AY52

AV53

AV52

AR54

AR52

AN51

AN53

AR53

AR51

AH52

AH54

AR6

BD16

BE17

BC17

BE16

BC23

BF23

BC25

BF25

BD23

BE23

BD25

BE25

BD34

BC34

BF34

BE34

BE21

BD32

BD21

BC20

BD31

BC53

BA40

BA39

AY40

AY39

AW40

AW39

AV40

AV39

AU40

AU39

U0500BGA

HASWELL

OMIT_TABLE

AU30

AW23

AV23

AW19

AV19

BA19

AY20

AU32

BA32

AV32

AT30

AY32

AW32

AV30

AY30

BA35

AW36

AU20

AW35

AY35

AU23

AW30

BA30

AL2

AW8

AW10

AW16

BD43

BD48

AU46

AD52

AL3

AW6

AW12

AW15

BE43

BE48

AV46

AD53

AU49

AU47

AE53

AK3

AK2

AM4

AM1

AE52

AK4

AK1

AM3

AM2

AY6

AU6

AY8

AV8

BA6

AV6

AC51

BA8

AU8

AV10

AY10

BA12

AV12

AU10

BA10

AY12

AU12

AC53

AU15

AY15

AV16

AY16

AV15

BA15

AU16

BA16

BE42

BD42

AE54

BC44

BF44

BF42

BC42

BD44

BE44

BF47

BE47

BD50

BD49

AE51

BC47

BD47

BE49

BC49

AV49

AV47

AU45

AU43

AV45

AV43

AC52

AC54

AW20

AU19

AY19

BA20

AY27

AY26

AV26

AV27

BA27

BA26

AW26

AW27

AV36

AV35

AU35

AU36

AV20

BA36

BA23

AY23

BF39

BF37

BE39

BE38

BE37

BD39

BD38

BD37

BC39

BC37

AY36U0500BGA

HASWELL

OMIT_TABLE

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

23 24 78

24 27 78

23 27 78

24 27 78

23 27 78

23 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

23 24 27 78

25 27 78

25 27 78

25 27 78

26 27 78

26 27 78

26 27 78

25 27 78

25 26 27 78

25 26 27 78

26 27 78

25 27 78

26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 27 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

25 26 78

CPU DDR3 InterfacesSYNC_MASTER=J15_REFERENCE SYNC_DATE=12/18/2012

MEM_A_DQ<2>MEM_A_DQ<3>

MEM_A_CS_L<1>

MEM_A_DQ<45>

MEM_A_DQ<54>

MEM_A_DQ<51>

MEM_A_DQ<53>


MEM_A_DQ<4>MEM_A_DQ<5>MEM_A_DQ<6>MEM_A_DQ<7>MEM_A_DQ<8>MEM_A_DQ<9>MEM_A_DQ<10>MEM_A_DQ<11>MEM_A_DQ<12>MEM_A_DQ<13>


MEM_A_DQ<18>MEM_A_DQ<19>MEM_A_DQ<20>








MEM_A_DQ<38>MEM_A_DQ<39>MEM_A_DQ<40>MEM_A_DQ<41>MEM_A_DQ<42>MEM_A_DQ<43>MEM_A_DQ<44>

MEM_A_DQ<46>MEM_A_DQ<47>MEM_A_DQ<48>MEM_A_DQ<49>MEM_A_DQ<50>

MEM_A_DQ<52>


MEM_A_DQ<61>


MEM_B_DQ<4>MEM_B_DQ<3>MEM_B_DQ<2>MEM_B_DQ<1>MEM_B_DQ<0>



MEM_B_DQ<19>

MEM_B_DQ<17>

MEM_B_DQ<15>

MEM_B_DQ<20>

MEM_B_DQ<24>MEM_B_DQ<23>MEM_B_DQ<22>MEM_B_DQ<21>

MEM_B_DQ<25>






MEM_B_DQ<55>MEM_B_DQ<54>MEM_B_DQ<53>

MEM_B_DQ<51>


MEM_B_DQ<61>

MEM_B_DQ<63>MEM_B_DQ<62>

MEM_A_DQ<60>

MEM_B_CLK_N<0>MEM_B_CLK_P<0>MEM_B_CKE<0>

MEM_B_CLK_N<1>MEM_B_CLK_P<1>MEM_B_CKE<1>

MEM_B_CS_L<0>MEM_B_CS_L<1>

MEM_B_ODT<0>MEM_B_ODT<1>

MEM_B_BA<0>MEM_B_BA<1>MEM_B_BA<2>

MEM_B_RAS_LMEM_B_WE_LMEM_B_CAS_L

MEM_B_A<0>MEM_B_A<1>MEM_B_A<2>MEM_B_A<3>MEM_B_A<4>MEM_B_A<5>MEM_B_A<6>MEM_B_A<7>MEM_B_A<8>MEM_B_A<9>MEM_B_A<10>MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>MEM_B_A<14>MEM_B_A<15>

MEM_A_CLK_N<0>MEM_A_CLK_P<0>MEM_A_CKE<0>

MEM_A_CLK_N<1>MEM_A_CLK_P<1>MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>MEM_A_ODT<1>

MEM_A_BA<0>MEM_A_BA<1>MEM_A_BA<2>

MEM_A_RAS_LMEM_A_WE_LMEM_A_CAS_L

MEM_A_A<0>MEM_A_A<1>MEM_A_A<2>MEM_A_A<3>MEM_A_A<4>MEM_A_A<5>MEM_A_A<6>MEM_A_A<7>MEM_A_A<8>MEM_A_A<9>MEM_A_A<10>MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>MEM_A_A<14>MEM_A_A<15>

MEM_B_DQS_N<7>MEM_B_DQS_N<6>MEM_B_DQS_N<5>MEM_B_DQS_N<4>MEM_B_DQS_N<3>MEM_B_DQS_N<2>MEM_B_DQS_N<1>MEM_B_DQS_N<0>

MEM_B_DQS_P<5>MEM_B_DQS_P<4>MEM_B_DQS_P<3>MEM_B_DQS_P<2>MEM_B_DQS_P<1>MEM_B_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<5>MEM_A_DQS_N<6>

MEM_A_DQS_N<4>MEM_A_DQS_N<3>MEM_A_DQS_N<2>MEM_A_DQS_N<1>MEM_A_DQS_N<0>

MEM_A_DQS_P<6>MEM_A_DQS_P<7>

MEM_A_DQS_P<5>MEM_A_DQS_P<4>MEM_A_DQS_P<3>MEM_A_DQS_P<2>MEM_A_DQS_P<1>MEM_A_DQS_P<0>

MEM_A_DQ<17>

MEM_A_DQ<14>

CPU_DIMMB_VREFDQ

CPU_DIMMA_VREFDQ

MEM_B_DQ<52>


MEM_B_DQS_P<7>MEM_B_DQS_P<6>

CPU_DIMM_VREFCA

MEM_B_DQ<16>

MEM_B_DQ<18>

7 OF 1187 OF 118

<BRANCH>

<SCH_NUM>

<E4LABEL>

7 OF 827 OF 82

<E4LABEL>

<SCH_NUM>

<BRANCH>

w w w

. c h

i n a

f i x

. c o

m

BI

OUT

IN

PWR_DEBUG*

RSVD64

RSVD76

VCCIO_OUT

VCC

VCC

VDDQ

FC_D3

FC_D5

VSS_B51

VCC_SENSE

VCOMP_OUT

VCC_M6

VCC_L6

RSVD70

RSVD72

RSVD73

RSVD74

RSVD66

RSVD67

RSVD69

RSVD65

FC_F17

VSS_AB50(RSVD)

VSS_AD50(RSVD)

VSS_AJ50(RSVD)

VSS_AK49(RSVD)

VSS_AM50(RSVD)

VSS_AN49(RSVD)

VSS_AP49(RSVD)

VSS_AP50(RSVD)

VSS_V50(RSVD)

RSVD79(VSS)

VIDALERT*

VIDSCLK

VIDSOUT

RSVD68

RSVD71

VSS_E52

IVR_ERROR

IST_TRIGGER

RSVD75

VSS_AG50(RSVD)

VSS_AJ49(RSVD)

SYM 5 OF 12

VCC

VCC

POWER

SYM 6 OF 12

IN

OUT

NCNCNCNC

NCNC

NCNCNCNC

NC

NC

NC

IN

Apple Inc.


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6 3



to avoid any extraneous connections.

Max load: 300mA

R0810.2:

R0800.2:

R0802.2:

Max load: 300mA

NOTE: Aliases not used on CPU supply outputs

for BDW CPU support.Connections are required

21

R08120

5%1/16WMF-LF402

58 75

2

1R0802110

PLACE_NEAR=U0500.J50:2.54mm

402

1/16W1%

MF-LF

21

R08110

402

5%

MF-LF1/16W

58 75

21

R0810

PLACE_NEAR=U0500.J53:38mm

5%

402MF-LF1/16W

4358 75

2

1R0800

PLACE_NEAR=R0810.1:2.54mm

751%

1/16WMF-LF

402

V50

E52

B51

AP50

AP49

AN49

AM50

AK49

AJ50

AJ49

AG50

AD50

AB50

J50

J52

J53

BE33

BE30

BE26

BE22

BE18

BD33

BD30

BD26

BD22

BB36

BB34

BB31

BB30

BB27

BB26

BB22

BB21

AY18

AW33

AW29

AW25

AW22

AV37

AT36

AT32

AT27

AT23

AT19

AT13

AR33

AR31

AR29

AK6

D51

C50

M6

L6

H29

H27

H26

H25

H24

H23

H21

H20

H19

H18

H17

H16

H14

H13

H12

H11

G48

G46

G45

G43

G42

G39

G38

G36

G34

G32

G31

G29

G27

F48

F46

F45

F43

F42

F39

F38

F36

F34

F32

F31

F28

F27

E48

E46

E45

E43

E42

E39

E38

E36

E34

E32

E31

E28

E27

D48

D46

D45

D43

D42

D39

D38

D36

D34

D32

D31

D28

D27

C48

C46

C45

C43

C42

C39

C38

C36

C34

C32

C31

C28

C27

B48

B46

B45

B43

AA9

AA8

AA47

AA46

A48

A46

A45

A43

A42

A39

A38

A36

W9

V49

U49

J31

J26

J21

J17

J12

AR49

AN33

AN31

AN22

AN18

AH9

F19

AM49

W49

F17

D5

D3

U0500

OMIT_TABLE

HASWELLBGA

Y8

Y46

Y45

W8

W47

W46

V8

V46

V45

U9

U8

U47

U46

T46

T45

R9

R8

R47

R46

P8

P46

P45

N9

N8

N47

N46

N44

N43

N42

N40

N39

N38

N37

M9

M8

M46

M45

M44

M43

M42

M40

M39

M38

M37

L8

L47

L46

L44

L43

L42

L40

L39

L38

L37

K9

K8

K48

K46

K45

K44

K43

K40

K38

J9

J8

J48

J46

J45

J43

J42

J40

J39

J38

J37

J36

J33

J29

J24

J19

J14

J10

H9

H8

H48

H46

H45

H43

H42

H40

H39

H38

H37

H36

H34

H33

H32

H31

H30

B42

B39

B38

B36

B34

B32

B31

B28

B27

AR46

AR45

AR43

AR41

AR39

AR37

AR35

AP9

AP8

AP47

AP46

AP44

AP43

AP42

AP41

AP40

AP39

AP38

AP37

AP36

AP35

AP34

AP33

AP32

AP31

AP30

AP29

AP27

AP26

AP25

AP24

AP23

AP22

AP21

AP20

AP19

AP18

AP17

AP16

AP15

AP14

AP13

AP12

AP10

AN9

AN8

AN46

AN45

AN44

AN43

AN42

AN41

AN40

AN39

AN38

AN36

AN34

AN32

AN30

AN29

AN27

AN26

AN25

AN24

AN23

AN21

AN20

AN19

AN17

AN16

AN15

AN14

AN13

AN12

AN10

AM9

AM8

AM47

AM46

AL9

AL8

AL46

AL45

AK8

AK47

AK46

AJ46

AJ45

AH8

AH47

AH46

AG8

AG46

AF8

AE8

AE47

AE46

AD8

AD46

AC9

AC8

AC47

AC46

AB8

AB46

AB45

A34

A32

A31

A28

A27

U0500

OMIT_TABLE

HASWELL

BGA

18

2

1R0860PLACE_NEAR=U0500.C50:50.8mm

PLACE_SIDE=BOTTOM

1001/16WMF-LF

402

5%

58 75

19

SYNC_DATE=12/18/2012SYNC_MASTER=J15_REFERENCE

CPU Power

PP1V05_S0_CPU_VCCSTCPU_VCCST_PWRGD

PPVCC_S0_CPU

PPVCC_S0_CPU

CPU_VIDSOUT_R

MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

PPVCCIO_S0_CPUMIN_LINE_WIDTH=0.4 mm

TP_CPU_RSVD_TP78

PP1V35_S3RS0_CPUDDR

CPU_VIDALERT_R_L

TP_CPU_IVR_ERROR

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=1.05V

PPVCOMP_S0_CPUMIN_NECK_WIDTH=0.2 mm

CPU_VIDALERT_L

CPU_VIDSOUTCPU_PWR_DEBUG


CPU_VCCSENSE_P

CPU_VIDSCLK_RCPU_VIDSCLK

<SCH_NUM>

<E4LABEL>

<BRANCH>

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5 6 10 18 58

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5

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mVSSVSS

GROUNDSYM 7 OF 12

VSS VSS

SYM 8 OF 12GROUND

VSS

VSS

VSS_SENSE

VSS_NCTF

VSS_AB48(RSVD)

VSS_AR22(RSVD)

VSS_G18(RSVD)

VSS_P9(RSVD)

SYM 9 OF 12

OUT

Apple Inc.


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AT4

AT39

AT37

AT35

AT33

AT29

AT26

AT25

AT22

AT20

AT18

AT16

AT15

AT12

AT10

AT1

AR9

AR8

AR7

AR50

AR5

AR48

AR26

AR24

AR20

AR18

AR16

AR14

AR12

AP7

AP54

AP51

AN7

AN50

AN5

AN48

AN4

AN3

AN2

AN1

AM7

AM54

AM53

AM52

AM51

AM5

AL7

AL5

AL48

AL4

AL1

AK9

AK7

AK50

AK5

AK48

AJ54

AJ51

AJ48

AH7

AH50

AH5

AH48

AH4

AH3

AH2

AH1

AG9

AG7

AG54

AG53

AG52

AG51

AG5

AG48

AF7

AF6

AF5

AE7

AE50

AE5

AE48

AE4

AE3

AE2

AE1

AD9

AD7

AD54

AD51

AD48

AC7

AC50

AC5

AC48

AB9

AB7

AB54

AB53

AB52

AB51

AB5

AA7

AA5

AA48

AA4

AA3

AA2

AA1

A44

A40

A37

A33

A30

A26

A22

A19

A15

A11 U0500HASWELL

OMIT_TABLE

BGA

BB9

BB7

BB6

BB5

BB49

BB48

BB47

BB46

BB44

BB43

BB42

BB41

BB39

BB38

BB37

BB33

BB32

BB28

BB25

BB23

BB20

BB18

BB17

BB16

BB15

BB14

BB12

BB11

BB10

BA9

BA53

BA52

BA51

BA50

BA5

BA42

BA4

BA37

BA33

BA29

BA25

BA22

BA18

BA13

B8

B49

B44

B40

B37

B33

B30

B26

B22

B19

B15

B11

AY9

AY50

AY42

AY37

AY33

AY29

AY25

AY22

AY13

AW9

AW54

AW51

AW50

AW5

AW49

AW47

AW46

AW45

AW43

AW42

AW37

AW18

AW13

AV9

AV50

AV5

AV42

AV4

AV33

AV3

AV29

AV25

AV22

AV2

AV18

AV13

AV1

AU9

AU5

AU42

AU37

AU33

AU29

AU25

AU22

AU18

AU13

AT9

AT8

AT6

AT54

AT53

AT52

AT51

AT50

AT5

AT49

AT47

AT46

AT45

AT43

AT42

AT40 U0500HASWELL

OMIT_TABLE

BGA

Y9

Y7

Y48

W7

W54

W52

W50

W48

V9

V7

V48

U7

U6

U54

U52

U50

U5

U48

U4

U3

U2

U1

T48

D50

R7

R48

P9

P7

P6

P54

P52

P50

P5

P48

P4

P3

P2

P1

G1

F54

E54

D2

C53

BF6

BF50

BF5

BF49

BD53

BD2

BB54

BB1

BA54

BA1

B4

A8

A50

A49

N7

N48

M7

M54

M52

M50

M48

L9

L7

L48

K7

K6

K5

K4

K3

K2

K1

J7

J54

J51

J49

J44

H7

H49

H44

G9

G8

G7

G54

G52

G49

G44

G40

G37

G33

G30

G26

G25

G23

G20

G18

G16

G13

G11

F5

F49

F44

F40

F4

F37

F33

F30

F3

F26

F2

E8

E53

E51

E49

E44

E40

E37

E33

E30

E26

E25

E24

E22

E21

E20

E19

E17

E16

E15

E11

D8

D49

D44

D40

D37

D33

D30

D26

D22

D19

D15

D11

C8

C52

C49

C44

C40

C4

C37

C33

C30

C26

C22

C19

C15

C11

BF7

BF48

BF46

BF43

BF41

BF38

BF36

BF33

BF30

BF26

BF22

BF18

BF15

BF12

BF10

BE46

BE41

BE36

BE15

BE10

BD51

BD5

BD46

BD41

BD36

BD18

BD15

BD10

BC7

BC52

BC50

BC5

BC48

BC46

BC43

BC41

BC38

BC36

BC33

BC30

BC3

BC26

BC22

BC18

BC15

BC12

BC10

AR22

AB48

U0500

HASWELL

OMIT_TABLE

BGA

58 75

2

1R0960PLACE_NEAR=U0500.D50:50.8mmPLACE_SIDE=BOTTOM

402MF-LF1/16W5%100

CPU GroundSYNC_MASTER=J15_REFERENCE SYNC_DATE=12/18/2012

CPU_VCCSENSE_N

9 OF 82

<E4LABEL>

<SCH_NUM>

<BRANCH>

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PLACEMENT_NOTE (C1080-C1089):


CAPs for Acoustic control (C102E-C103F)


CAPs for Acoustic control (C109A-C102D)

CPU VCORE DecouplingIntel recommendation: 4x 470uF 4mOhm (3 CPU-side, 1 opposite), 20x 22uF 0805 (10 CPU-side, 10 opposite near edge, 4x 10uF 0603 (2 CPU-side, 2 opposite), 20x 1uF 0402 (under CPU)




Apple Implementation: 8x 210uF(2x nostuff) 6mOhm, 44x 10uF 0402, 4x 10uF 0402, 20x 1uF 0402

NOTE: Intel decoupling recommendations from Shark Bay Mobile Platform Power Delivery Design Guide (doc #487822, Rev 0.8 dated January 2012), Section 5.

Apple Implementation: 2x 0.01uF 0402 (second cap is on CPU VR page)Intel recommendation: 1x 0.1uF 0402, 1x 4.7uF 0805

CPU VCCST Decoupling

CPU VDDQ DecouplingIntel recommendation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402 Apple Implementation: 2x 330uF, 8x 10uF 0603, 10x 1uF 0402


CPU VCCIO Decoupling

PLACEMENT_NOTE (C1068-C1076:

Apple Implementation: 1x 0.1uF 0201, 1x 4.7uF 0402

(Z = 1.5mm, place on tall side next to CPU & under heat pipe)

Intel recommendation: 2x 0.01uF 0402 (1 near CPU, 1 near SVID pull-ups)

2

1 C1009

0402

1UF

X6S-CERM10V10%

Place on bottom side of U0500

2

1 C1008

0402


10%10VX6S-CERM

1UF

2

1 C1007

0402


10%1UF10VX6S-CERM

2

1 C1031

NO STUFF

20%

Place near inductors on bottom side.

CRITICAL

20UF

X5R-CERM4V

0402-2

2

1 C100610%10VX6S-CERM


1UF

04022

1 C1005


1UF10%

0402X6S-CERM10V2

1 C10041UF10%10VX6S-CERM


04022

1 C1003

0402


1UF10V10%

X6S-CERM2

1 C1002


10V10%1UF

0402X6S-CERM2

1 C1001

0402


10V10%1UF

X6S-CERM2

1 C1000

0402


1UF10V10%

X6S-CERM

2

1 C1030

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1029

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1027

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1026

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-2

2

1 C102020%

NO STUFF

Place near U0500 on bottom side

20UF

X5R-CERM4V

0402-22

1 C1021

NO STUFF

20%


20UF

X5R-CERM4V

0402-22

1 C1022

NO STUFF

20%


20UF

X5R-CERM4V

0402-22

1 C109A20%

NO STUFF

20UF

X5R-CERM4V

0402-2

2

1 C1025

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1024

NO STUFF

CRITICAL

20%20UF

X5R-CERM4V

0402-22

1 C1028

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C103220%


20UF4V

0402-2X5R-CERM

CRITICAL

NO STUFF

2

1 C1033

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1039

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1038

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1037

NO STUFF

CRITICAL

20%


20UF

X5R-CERM4V

0402-22

1 C1036

NO STUFFPlace near inductors on bottom side.

20%

CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1035

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1034

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-2

2

1 C1079

X7R-CERM0402

16V

0.01UF10%

2

1 C1089

0402

10%10V

1UF


X6S-CERM2

1 C1088


10V

1UF10%

X6S-CERM0402

2

1 C1087

0402

10%


10V

1UF

X6S-CERM2

1 C10861UF10V

0402


10%

X6S-CERM2

1 C10851UF


10%10V

0402X6S-CERM2

1 C1084

X6S-CERM0402


10%10V

1UF

2

1 C1083

10V

0402


1UF

X6S-CERM

10%2

1 C1082

0402X6S-CERM

1UF


10V10%

2

1 C1081

0402

Place on bottom side of U100.

1UF

X6S-CERM10V10%

2

1 C1080

X6S-CERM0402


10%1UF10V

2

1 C1043

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1042

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1041

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-22

1 C1040

NO STUFF

20%


CRITICAL

20UF

X5R-CERM4V

0402-2

3 2

1C1098

2.0V

330UF-6MOHM

D15T-ECGLT-COMBOPOLY-TANT

CRITICAL

20%3 2

1C1099

D15T-ECGLT-COMBO

2.0V20%330UF-6MOHM

POLY-TANT

CRITICAL

2

1 C1019

0402


10%10VX6S-CERM

1UF

2

1 C1018

0402


1UF

X6S-CERM10V10%

2

1 C1017

0402


1UF

X6S-CERM10V10%

2

1 C1016

0402


10%10VX6S-CERM

1UF

2

1 C1015

0402


10%10VX6S-CERM

1UF

2

1 C1014

X6S-CERM0402


1UF10V10%

2

1 C1013

0402


X6S-CERM

10%10V

1UF

2

1 C1012

0402


10%10VX6S-CERM

1UF

2

1 C1011

0402


10%10VX6S-CERM

1UF

2

1 C1010

0402

10%10V


X6S-CERM

1UF

2

1 C1065


CRITICAL

X5R-CERM0402-2

4V

20UF20%

2

1 C1064


X5R-CERM0402-2

4V

20UF20%

CRITICAL

2

1 C1063CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1062CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1061CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1060CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1059CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1058CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1057CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1056CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1055CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1054CRITICAL


0402-2

4V

20UF20%

X5R-CERM2

1 C1053


CRITICAL

X5R-CERM0402-2

4V

20UF20%

2

1 C1052CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1051CRITICAL


X5R-CERM4V20%20UF

0402-22

1 C1050CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1049CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1048CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1047CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1046CRITICAL

X5R-CERM0402-2

4V

20UF20%

2

1 C1045CRITICAL


20%4VX5R-CERM0402-2

20UF

2

1 C1044CRITICAL


20%4VX5R-CERM0402-2

20UF

2

1 C1067CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1066CRITICAL


X5R-CERM0402-2

4V

20UF20%

2

1 C1068

POLY-TANT2.5V20%210UF

CASE-B2S

CRITICAL

2

1 C1069

POLY-TANTCASE-B2S

20%210UF

CRITICAL

2.5V 2

1 C1070

CASE-B2S

2.5V20%210UF

CRITICAL

POLY-TANT2

1 C107120%2.5V

CRITICAL

CASE-B2SPOLY-TANT

210UF

NO STUFF

2

1 C1072

2.5V

210UF

CRITICAL

20%

CASE-B2SPOLY-TANT

2

1 C1073

POLY-TANT

CRITICAL

2.5V20%

NO STUFF

CASE-B2S

210UF2

1 C1074CRITICAL

CASE-B2S

2.5VPOLY-TANT

20%210UF

2

1 C107520%2.5V

CASE-B2SPOLY-TANT

210UF

CRITICAL

2

1 C1076

CASE-B2S

2.5V20%

POLY-TANT

CRITICAL

210UF2

1 C107720%2.5V

CASE-B2S

210UF

CRITICAL

POLY-TANT

2

1 C109B20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C109C

NO STUFF

20%20UF

X5R-CERM4V

0402-22

1 C109D20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C109E20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C109F20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C101A20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C101B20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C101C20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C101D20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C1023


20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C101E20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C101F20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C102A20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C102B20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C102C20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C102D20%

NO STUFF

20UF

X5R-CERM4V

0402-2

2

1 C103F20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C103E20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C103D20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C103C20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C103B20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C103A20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C102F20%

NO STUFF

20UF

X5R-CERM4V

0402-22

1 C102E20%

NO STUFF

20UF

X5R-CERM4V

0402-2

2

1 C109220%4VX6S


0402

10UF

2

1 C109320%10UF4V


X6S0402

2

1 C1094

X6S4V

10UF20%

0402


2

1 C109520%10UF4VX6S


04022

1 C109620%4VX6S


0402

10UF

2

1 C1097

4VX6S

10UF


0402

20%2

1 C1090


4V20%

X6S

10UF

04022

1 C109110UF20%4VX6S


0402

2

1 C108A

PLACE_NEAR=U0500.D5:12.7mm

0201CERM-X5R6.3V10%0.1UF

BDW_SPRT

2

1 C108B


4.7UF

X5R6.3V

402

20%

BDW_SPRT

21

R1080

MF-LF

5%

603

0

1/10W

BDW_SPRTSYNC_MASTER=J15_REFERENCE SYNC_DATE=12/18/2012

CPU DecouplingPP1V05_S0_CPU_VCCSTMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

PP1V35_S3RS0_CPUDDR

PP1V05_S0

PPVCC_S0_CPU

PPVCCIO_S0_CPU

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6 8 21 66 67 70 82

14 15 17 18 42 62 67 70 72

6 8 46 59 70 72

5 6 8 18 58

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IN

IN

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

HDA_SDI1

HDA_SDI2

TP25

TP22

HDA_DOCK_RST*/GPIO13

SATA_RXP0

SATA_RXP5/PERP2

SATA_RXN5/PERN2

TP8

SRTCRST*

RTCX1

RTCX2

HDA_BCLK

DOCKEN*/GPIO33

SATA_RCOMP

SATA_TXN0

SATA_TXP4/PETP1

SATA_TXP1

SATA_TXN4/PETN1

SATA_TXN1

SATA0GP/GPIO21

SATALED*

SPKR

JTAG_TDI

JTAG_TDO

JTAG_TMS

TP20

JTAG_TCK

INTRUDER*

HDA_SYNC

HDA_SDI3

HDA_SDO

SATA_RXP2

SATA_RXN2

SATA_TXN2

SATA_TXP2

SATA_RXN3

SATA_RXP3

SATA_TXN3

TP9

SATA_IREF

SATA1GP/GPIO19

SATA_TXP0

SATA_RXN1

SATA_RXP1

RTCRST*

INTVRMEN

SATA_RXN0

SATA_RXP4/PERP1

SATA_RXN4/PERN1

SATA_TXP3

SATA_TXP5/PETP2

SATA_TXN5/PETN2

HDA_SDI0

HDA_RST*

JTAG

(1 OF 11)

RTC

AZALIA SATA

CLOCKS

(2 OF 11)

PCIECLKRQ2*/GPIO20/SMI*

CLKOUT_33MHZ4

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

PCIECLKRQ0*/GPIO73

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_PCIE_P6

CLKOUT_PCIE_N6

CLKOUT_PCIE_N2

CLKOUT_PCIE_P2

TP18

TP19

CLKOUT_PCIE_N3

CLKOUT_PCIE_P3

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE_P5

CLKOUT_PCIE_N5

PCIECLKRQ1*/GPIO18

CLKOUT_DPNS_N

CLKOUT_DPNS_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_PCIE_N4

CLKOUT_PCIE_P4

PEG_A_CLKRQ*/GPIO47

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_PCIE_P7

CLKOUT_PCIE_N7

XTAL25_OUT

XTAL25_IN

ICLK_IREF

DIFFCLK_BIASREF

CLKIN_GND_N

CLKIN_GND_P

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_33MHZ2

CLKIN_SATA_P

CLKIN_SATA_N

CLKOUTFLEX0/GPIO64

CLKIN_33MHZLOOPBACK

CLKOUT_33MHZ0

CLKOUT_33MHZ1

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX3/GPIO67

CLKOUT_33MHZ3

REFCLK14IN

CLKIN_DOT96_P

CLKIN_DOT96_N

PCIECLKRQ3*/GPIO25

PEG_B_CLKRQ*/GPIO56

PCIECLKRQ4*/GPIO26

PCIECLKRQ7*/GPIO46

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PCIE_N0

CLKOUT_PCIE_P0

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

NCNC

NCNC

NCNCNC

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



NOTE: SSC control is ganged on PCIe 0-3 and 4-7 clocks. PEG-attached (CPU) PCIe devices must use one set, while PCH-attached PCIe devices use the other set. If 2 or less devices are attached to PEG the CLKOUT_PEG outputs can be used for those devices.

(IPD-DOCKEN#?)

(IPD)

NOTE: ENET pair only used if SD Card Reader is USB3.

Secondary HDD/SSD (SATA only)

Primary HDD/SSD (SATA only)

Reserved: ODD

Unused

PCIe:

SATA Port assignments:

Reserved: Ethernet(if not combo w/SD Card)

Unused

(IPD)

(IPU)

(IPD-boot)

(IPD-boot)

Unused clock terminations for FCIM Mode

(IPD)

(IPD)

(IPU-PLTRST#)

Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.

(IPD-PWROK)

(IPD-PWROK)

(IPD-PWROK)

(IPD-PWROK)

(IPD-PWROK)

(IPU-RSMRST#)

(IPU-RSMRST#)

(IPD-PWROK)

(IPD-PWROK)

(IPD-PWROK)

(IPD-PWROK)

1.5V -> 1.1V

(IPU)

(IPD-PLTRST#)

(IPD)

If HDA = S0, must also ensure that signal cannot be high in S3.

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

19 76

52 77

2

1R1100330K1/20W

5%

201MF

2

1R1101

1/20W5%

201MF

1M2

1R1102

1/20W5%

201MF

20K

2

1R1103

1/20W5%

201MF

20K

2

1 C1103

10V10%

402X5R

1UF

2

1C1102

10V10%

402X5R

1UF

2

1R1130

1/20W1%

201MF

7.5K

PLACE_NEAR=U1100.AY5:2.54mm11 71

18 72

18 72

18 72

18 72

21

R1172340

MF-LF402

1%1/16W

2

1R11731K

1/20W1%

201MF

19 76

18

11 18

34 77

34 77

37 77

18

37 77

11 35

11 36

11 28

6 75

6 75

6 75

6 75

19 77

11 71

28 77

28 77

21R1177MF1/20W5% 201

4.7K

21R1178 4.7K2011/20W5% MF

21R1134 10KMF 2015% 1/20W

21R1142 10KMF 2015% 1/20W21R1169 10KMF 2015% 1/20W21R1144 10KMF 2015% 1/20W21R1145 10KMF 2015% 1/20W21R1147 10KMF 2015% 1/20W

12R1114 10KMF 2015% 1/20W21R1115 10KMF 2011/20W5%

21R11431/20W5% 201MF

10K

21R11331/20W5% 201MF

10K

21R11791/20W

10KMF 2015%

21R11461/20W5% 201MF

10K21R1148

1/20W5% 201MF10K

52 77

52 77

52 77

52 77

21R1191 10KMF 2015% 1/20W

21R1192 10KMF 2015% 1/20W

21R1193 10KMF5% 1/20W 201

21R1194 10KMF 2015% 1/20W

21R1195 10KMF 2015% 1/20W

21R1196 10KMF 2015% 1/20W

21R1197 10KMF 2015% 1/20W

21R11705% 201MF

10K1/20W

21R1171 10KMF 2015% 1/20W

BA2

BB2

F8

C26

AB6

B9

AL10

AP3

AR15

AW15

AT13

AW13

AW10

AY8

AP15

AV15

AR13

AY13

AV10

AW8

BE14

BB13

BE12

BD9

BE10

BE8

BC14

BD13

BC12

BB9

BC10

BC8

AY5

BD4

AU2

AT1

B4

B5

D9

AD1

AD3

AE2

AB3

G10

A8

A22

A24

F22

G22

K22

L22

C24

C22

B25

B17

U1100

OMIT_TABLE

LYNXPOINTMOBILEFCBGA

AL44

AM43

AD39

AD38

F45

U4

AF6

Y3

AE4

AA2

V3

T3

AF3

AF1

AB1

AM45

AN44

F39

F36

F38

C40

Y38

Y39

AB36

AB35

AJ42

AB39

AE42

AF45

AD45

AB45

AA42

Y45

AJ44

AB40

AE44

AF43

AD43

AB43

AA44

Y43

AH45

AH43

AF36

AF35

AJ39

AJ40

AF40

AF39

A40

F41

B42

E44

D44

BC6

BE6

AT24

AR24

G33

H33

AW24

AY24

D17

U1100

MOBILELYNXPOINT

OMIT_TABLE

FCBGA

6 75

6 75

73 75

73 75

21R1110PLACE_NEAR=U1100.B25:1.27mm

MF 2015% 1/20W33

21R1113PLACE_NEAR=U1100.A24:1.27mm

2015% 1/20W33

MF

21R11111/20W5% 201MF

33

PLACE_NEAR=U1100.A22:1.27mm

21R1112PLACE_NEAR=U1100.C24:1.27mm

33MF 2015% 1/20W

19 77

73 77

19 77

73 76

73 76

73 76

73 76

73

73

11 18

12

R1190

1/20WMF

1%PLACE_NEAR=U1100.AN44:2.54mm

201

7.5K

11 71

21R1176 10KMF 2015% 1/20W

35 77

35 77

11 71

73 76

73 76

73 76

73 76

PCH RTC/HDA/JTAG/SATA/CLKSYNC_DATE=12/18/2012SYNC_MASTER=J15_REFERENCE

ENET_CLKREQ_L

NC_PCIE_CLK100M_PEGBN

PCH_PEGCLKRQB_L_GPIO56

ENET_MEDIA_SENSE_RDIV

XDP_PCH_TCK

ENET_MEDIA_SENSE_RDIVDP_TBT_SEL

HDA_SDOUT

HDA_SDIN0

PCH_CLK96M_DOT_N

PCH_SPKRDP_TBT_SEL

PCH_SRTCRST_L

PCH_INTRUDER_L

HDA_SYNC_R

PP1V5_S0

PCH_INTRUDER_LPCH_INTVRMEN_L

PCH_SRTCRST_L

RTC_RESET_L

PPVRTC_G3H

SYSCLK_CLK25M_SB

NC_HDA_SDIN3

NC_HDA_SDIN1

PCH_DIFFCLK_BIASREF

PCH_CLK14P3M_REFCLK

PCH_CLKIN_GNDNPCH_CLKIN_GNDP

PCH_CLK100M_SATA_P

NC_PCH_GPIO66_CLKOUTFLEX2NC_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_PCH_NPCIE_CLK100M_PCH_P

DMI_CLK100M_CPU_N

NC_PCIE_CLK100M_ENETN

SYSCLK_CLK32K_RTC

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_BIT_CLK

XDP_PCH_TMS

XDP_PCH_TDO

PP1V5_S0

SSD_CLKREQ_L

NC_PCH_GPIO64_CLKOUTFLEX0

PCH_SATALED_L

XDP_DD2_ENETSD_CLKREQ_LAP_CLKREQ_L

PCH_CLKRQ5_L_GPIO44PEG_CLKREQ_LPCH_CLKRQ7_L_GPIO46

ENET_CLKREQ_L

HDA_SYNC

HDA_RST_L

PCH_INTVRMEN_L

RTC_RESET_L

PCH_SPKR

XDP_PCH_TDI


PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

PCH_CLK96M_DOT_PPCH_CLKRQ5_L_GPIO44

NC_PCIE_CLK100M_PE5N

NC_PCI_CLK33M_OUT3

PCH_CLKRQ7_L_GPIO46

NC_PCIE_CLK100M_SWNNC_PCIE_CLK100M_SWP

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_GPUN

NC_PCI_CLK33M_OUT2

NC_PCIE_CLK100M_GPUP

PCIE_CLK100M_SSD_PPCIE_CLK100M_SSD_N

PCIE_CLK100M_AP_NPCIE_CLK100M_AP_P

XDP_DD3_AP_CLKREQ_L

PCIE_CLK100M_CAMERA_NPCIE_CLK100M_CAMERA_P

CAMERA_CLKREQ_L

TBT_CLKREQ_L

PEG_CLKREQ_L

PCIE_CLK100M_TBT_NPCIE_CLK100M_TBT_P

NC_ITPXDP_CLK100MNNC_ITPXDP_CLK100MP

LPC_CLK33M_SMC_RNC_LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

XDP_DC1_SATARDRVR_ENDP_AUXCH_ISOL_L

PP1V5_S0

PCH_CLK100M_SATA_N

CPU_CLK135M_DPLLREF_PCPU_CLK135M_DPLLREF_N

CPU_CLK135M_DPLLSS_PCPU_CLK135M_DPLLSS_N

DMI_CLK100M_CPU_P

NC_PCIE_CLK100M_PEGBP

PCH_PEGCLKRQB_L_GPIO56

NC_PCIE_CLK100M_ENETP

CAMERA_CLKREQ_LTBT_CLKREQ_L

NC_HDA_SDIN2

HDA_SDOUT_R

TP_PCIE_ENET_R2D_CNTP_PCIE_ENET_R2D_CP

NC_SATA_F_D2RN

TP_PCIE_ENET_D2RPTP_PCIE_ENET_D2RN

NC_SATA_D_D2RN

NC_SATA_D_R2D_CP

NC_SATA_D_D2RPNC_SATA_D_R2D_CN

NC_SATA_F_R2D_CP

NC_SATA_F_D2RPNC_SATA_F_R2D_CN

XDP_DC0_DP_AUXCH_ISOL_LXDP_DC1_SATARDRVR_EN

NC_SATA_ODD_R2D_CPNC_SATA_ODD_R2D_CNNC_SATA_ODD_D2RPNC_SATA_ODD_D2RN

NC_SATA_A_R2D_CPNC_SATA_A_R2D_CNNC_SATA_A_D2RPNC_SATA_A_D2RN

NC_SATA_B_D2RNNC_SATA_B_D2RPNC_SATA_B_R2D_CNNC_SATA_B_R2D_CP

PCH_SATALED_L

PCH_SATA_RCOMP

SSD_CLKREQ_L

NC_PCIE_CLK100M_ENETSDNNC_PCIE_CLK100M_ENETSDP

XDP_DD2_ENETSD_CLKREQ_L

PP3V3_SUSPP3V3_S0

11 OF 82

11 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

73

11

11 71

77

11

11 71

11 77

11 77

77

11 12 13 15 17 19 52 64 67 69 70 72

11 77

11 77

11 77

11

12 15 19 70

73

73

77

77

73

73

77

77

73

77

77

11 12 13 15 17 19 52 64 67 69 70 72

11 35

73

11

11 18

18 34

11

11 71

11

11 71

11 77

11

11

73

76

77 11

73

73

11

73

73

73

73

73

73

11 18

18

11 12 13 15 17 19 52 64 67 69 70 72

77

73

11

73

11 36

11 28

73

19 77

73

73

73

73

73

73

73

73

73

73

73

73

11

76

12 13 14 15 17 50 64 66 67 70

12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 66

67 68 70 72 82

w w w

. c h

i n a

f i x

. c o

m

IN

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

DAC_IREF

VGA_IRTN

VGA_VSYNC

VGA_HSYNC

PIRQH*/GPIO5

PIRQG*/GPIO4

DDPC_AUXN

EDP_BKLTEN

EDP_VDDEN

GPIO54

GPIO51

GPIO55

GPIO53

DDPC_CTRLCLK

DDPB_CTRLDATA

DDPB_CTRLCLK

DDPC_CTRLDATA

EDP_BKLTCTL

PIRQF*/GPIO3

DDPC_HPD

DDPC_AUXP

DDPD_AUXP

DDPB_HPD

DDPD_HPD

PIRQE*/GPIO2

DDPD_CTRLDATA

DDPD_CTRLCLK

VGA_RED

PIRQA*

GPIO52

GPIO50

PIRQD*

PIRQC*

PIRQB*

PME*

PLTRST*

DDPB_AUXN

VGA_BLUE

VGA_GREEN

DDPB_AUXP

DDPD_AUXN

VGA_DDC_DATA

VGA_DDC_CLK

CRT

PCI

DISPLAY

(5 OF 11)

EDP

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

SYSTEM POWER

MANAGEMENT

(4 OF 11)

DMI

FDI

SUSACK*

RI*

DPWROK

BATLOW*/GPIO72

PWRBTN*

RSMRST*

DRAMPWROK

SLP_LAN*

SLP_A*

PWROK

SLP_SUS*

ACPRESENT/GPIO31

SLP_WLAN*/GPIO29

DSWVRMEN

SLP_S4*

DMI_TXN1

DMI_TXN3

DMI_TXN2

DMI_TXP1

DMI_TXP0

TP5

PMSYNCH

DMI_RXN0

TP15

TP16

TP13

TP17

DMI_RXN1

SYS_RESET*

FDI_RXP1

FDI_RXN1

FDI_RXP0

FDI_RXN0

APWROK

TP21

SUSWARN*/SUSPWRNACK/GPIO30

DMI_TXN0

FDI_RCOMP

DMI_TXP2

DMI_TXP3

DMI_IREF

TP12

DMI_RCOMP

TP7

WAKE*

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

DMI_RXP0

DMI_RXP3

DMI_RXP2

DMI_RXP1

TP10

SLP_S3*

CLKRUN*

SYS_PWROK

DMI_RXN2

FDI_IREF

FDI_INT

FDI_CSYNC

DMI_RXN3

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

NCNCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

OUT

OUT

IN

IN

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



VGA DAC Disabled per SB

Redundant to pull-up on audio page

Redundant to pull-up on audio page

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPU)

(IPD-DeepSx)

(IPU-PWROK&PCIRST#)

(IPU)

(OD)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

DG v1.0 (Table 12-18).

(IPD-DeepSx)

5 75

5 75

2

1R1200

PLACE_NEAR=U1100.AY17:12.7mm

7.5K1%

MF1/20W

201

5 75

5 75

5 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

5 73 75

N44

V45

U39

N42

U44

M45

M43

T45

AD10

Y11

M15

L15

F17

G17

M20

K17

L20

H20

AL6

C12

A10

B13

C10

A12

G36

K36

N36

H39

N38

N40

J44

J42

K38

R36

R35

K45

K43

K40

R39

R40

H43

H45

U40

U1100

OMIT_TABLE

LYNXPOINTMOBILEFCBGA

2

1R1215330K

MF1/20W

201

5%

12 45 66 67

2

1R1209100K

MF1/20W

201

5%

19 41 72 77

18 19 41 72 77

6 21 75

12 19 72 77

12 19 72 77

67 72 77

12 18 41 77

41 42

12 30 41 43

12 34 36 72 77

12 41

20 41

42

12 41 67

12 21 34 38 41 67 69 72

12 21 41 67 72

6 75

41 72 77

12R1223 100KMF1/20W 2015%

21R1225 1KMF1/20W 2015%

21R1291 10KMF1/20W 2015%

12R1222 100KMF1/20W 2015%

12R1221 100KMF1/20W 2015%

12R1224 100KMF1/20W 2015%

12R1284 100KMF1/20W 2015%

12R1281 100KMF1/20W 2015%

K3

AV17

AY45

AB10

AU42

AV43

AV45

AU44

AW17

AW44

AM1

AD7

J4

Y6

R6

U7

D2

F1

Y7

C6

H1

G5

F3

J2

N4

F10

K1

AY3

AL36

AJ36

AL35

AJ35

AR44

AT45

AL40

AL39

C8

H3

L13

BC18

BB17

BC20

BB21

BE18

BD17

BE20

BD21

AW20

AR17

AP20

AY22

AV20

AP17

AR20

AW22

AY17

BE16

AN7

K7

AB7

E6

U1100

MOBILELYNXPOINT

FCBGA

OMIT_TABLE

12 68 71 72

12 63 71 72

63 71

5 75

2

1R12101%

7.5K

PLACE_NEAR=U1100.AR44:12.7mm

MF1/20W

201

21R1261 10KMF1/20W 2015%

21R1263 10KMF1/20W 2015%

21R1262 10KMF1/20W 2015%

21R1260 10KMF1/20W 2015%

21R1233 10KNO STUFF

MF1/20W 2015%

21R1231 10KMF1/20W 2015%

21R1214NO STUFF

100KMF1/20W 2015%

21R1230 10KMF1/20W 2015%

21R1217 100KMF1/20W 2015%21R1218 10KMF1/20W 2015%

12 71

21R1216 10KMF1/20W 2015%

12 71

12 29

12 71

18 20 21 72

12 71

12 71

12R1240 10KMF1/20W 2015%

21R1239 3.0KMF1/20W 2015%

43

12 71

2

1R1205

201

10K

MF1/20W

5%

2

1R1287NO STUFF

10K5%

1/20WMF201

43

43

2

1R1286

MF

05%

1/20W

0201

SMC_SUSACK:NO

SYNC_DATE=12/18/2012SYNC_MASTER=J15_REFERENCE

PCH DMI/FDI/PM/GFX/PCI

PP1V5_S0

SDCONN_OC_L

AUD_I2C_INT_L

NC_PCI_PME_L

PLT_RESET_L

PM_PCH_PWROK

BT_PWRRST_L

ENET_LOW_PWR_PCH

PCI_INTA_L

PCI_INTD_L

AUD_IPHS_SWITCH_EN_PCH

TP_PCH_STRP_ESI_L

TP_PM_SLP_A_L

PM_SLP_S3_L

TP_PCH_SLP_WLAN_L

PM_CLKRUN_L

PCIE_WAKE_L

TP_PCH_SLP_LAN_L

PCI_INTC_LPCI_INTB_L

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

EDP_IG_BKL_PWM

PM_BATLOW_L

PM_PCH_SYS_PWROK

DMI_S2N_P<3>DMI_S2N_P<2>DMI_S2N_P<1>DMI_S2N_P<0>

DMI_S2N_N<3>

DMI_S2N_N<1>DMI_S2N_N<2>

DMI_S2N_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1>DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<3>DMI_N2S_N<2>DMI_N2S_N<1>DMI_N2S_N<0>

AUD_IP_PERIPHERAL_DET

DP_TBTSNK0_HPD

NC_DP_IG_D_AUXCHP

DP_TBTSNK0_AUXCH_C_P

NC_DP_IG_D_AUXCHNDP_TBTSNK1_AUXCH_C_N

HDMI_DDC_CLKHDMI_DDC_DATA

DP_TBTSNK1_DDC_CLK

DP_TBTSNK0_DDC_CLKDP_TBTSNK0_DDC_DATA

TP_PCH_STRP_BBS1

PM_SLP_S4_L

FDI_INTFDI_CSYNC

TP_PCH_SLP_S0_L

PM_DSW_PWRGD

PCH_DSWVRMEN

PPVRTC_G3H

DP_TBTSNK0_AUXCH_C_N

PP1V5_S0

PM_MEM_PWRGD

PM_RSMRST_L

PM_SYSRST_L

DP_TBTSNK1_DDC_DATA

TBT_PWR_REQ_L

HDMI_HPDDP_TBTSNK1_HPD


PP3V3_S0

SMC_ADAPTER_EN

PCH_STRP_TOPBLK_SWP_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PCH_FDI_RCOMP

PM_PWRBTN_L

PM_BATLOW_L

PM_CLKRUN_L

ENET_LOW_PWR_PCH

BT_PWRRST_L

SDCONN_OC_L

AUD_IP_PERIPHERAL_DETTBT_PWR_REQ_L

AUD_I2C_INT_L

PCIE_WAKE_L

PM_SLP_S4_L

PM_SLP_SUS_L

EDP_IG_BKL_ONEDP_IG_PANEL_PWR

PP3V3_S5

PM_SYNC

PM_SLP_SUS_L

PM_SLP_S5_L

PM_SLP_S3_L

PP3V3_S0

PCH_DMI_RCOMP

AUD_IPHS_SWITCH_EN_PCH

PM_PWRBTN_L

PM_PCH_PWROK

PP3V3_SUS

PCH_SUSACK_L

PCH_RI_L

PCH_SUSWARN_L

12 OF 82

12 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

11 12 13 15 17 19 52 64 67 69 70 72

73

28 71

73

28 71 75

73

28 71 75

69 71 72

69 71 72

33 71

33 71

33 71

77

11 15 19 70

28 71 75

11 12 13 15 17 19 52 64 67 69 70 72

33 71

20 69 71 72

28 71

28 71 75

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

12 18 41 77

12 30 41 43

12 41

12 71

12 71

12 71

12 71

12 29

12 71

12 34 36 72 77

12 21 34 38 41 67 69 72

12 45 66 67

12 63 71 72

12 68 71 72

14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 41 67

12 21 41 67 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68

70 72 82

12 71

11 13 14 15 17 50 64 66 67 70

w w w

. c h

i n a

f i x

. c o

mBI

BI

BI

BI

IN

IN

OUT

IN

OUT

IN

BI

IN

OC1*/GPIO40

OC2*/GPIO41

OC5*/GPIO9

OC0*/GPIO59

OC3*/GPIO42

OC6*/GPIO10

OC4*/GPIO43

OC7*/GPIO14

USB2P6

USB2N6

USB2P5

USB2N7

USB2N5

USB2N13

USB2P0

USB2P4

USB2P10

USB2P2

USB2P3

USB2P8

PETN7

PETP6

PETN4

PETN3

PETN1_USB3TN3

PCIE_IREF

USB3TP6

USB3TN5

USB3TN1

PETN8

PETP8

PETN5

PCIE_RCOMP

USB3TN6

USB3TN2

USB3TP1

PETP7

PETN6

PETP1_USB3TP3

TP11

USB3TP5

USB3TP2

PETP5

TP6

USB2N0

USB2N4

USB2N10

PERN6

PERP3

PERP1_USB3RP3

PERP6

PERN5

PERN3

PERN1_USB3RN3

USB3RN5

USB3RN2

PERP5

USB3RP5

USB3RP2PERN7

PERP7

PERN4

PERN2_USB3RN4

PERP4

PERP2_USB3RP4

USB3RN6

USB3RN1

USB3RP6

USB3RP1

PERP8

PERN8

USB2N1

USB2N2

USB2N3

USB2N9

USB2P9

USB2N8

USB2P7

USB2N11

USB2P13

USB2P1

PETP4

USB2P11

PETP2_USB3TP4

PETN2_USB3TN4

PETP3

USB2N12

USB2P12

TP23

TP24

USBRBIAS*

USBRBIAS

(9 OF 11)

USB

PCI-E

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

SML0CLK

SML1ALERT*/PCHHOT*/GPIO74

LDRQ1*/GPIO23

LAD1

TP3

TP4

TP2

TP1

SPI_CS1*

SERIRQ

SPI_CS0*

SPI_IO2

SPI_IO3

SPI_CLK

SPI_CS2*

SPI_MISO

SPI_MOSI

LAD2

SML1DATA/GPIO75

CL_RST*

SML1CLK/GPIO58

LDRQ0*

TD_IREF

CL_CLK

CL_DATA

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

LAD0

SML0DATA

LFRAME*

LAD3

SMBUS

LPC

(3 OF 11)

SPI

C-LINK

IN

BI

BI

OUT

BI

OUT

OUT

BI

BI

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNC

NCNC

NCNC

NCNC

BI

BI

BI

BI

OUT

BI

IN

IN

OUT

OUT

BI

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SSD (Gumstick)

Unused

PCIe Port Assignments:

(& Ethernet if combo)SD Card Reader

PCIe/USB3 Port Assignments:

USB3 Port Assignments:

(PCIe-only)Or PCIe switch if TBT/SSD

Lane 1

Lane 0

(PCIe-only)

SSD (Gumstick)

Or PCIe switch if TBT/SSD



SSD (Gumstick)

SSD (Gumstick)

(PCIe-only)Lane 2

(PCIe-only)Lane 3

Camera

AirPort

(IPU/IPD)

(IPU/IPD)

(IPU)

(IPU)

(IPU-LDRQ1#?)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPD)

(IPU)

(IPU)

(IPU)

Reserved: SD (HS)

Reserved: WiFi (HS)

Ext A (LS/FS/HS)

Ext C (LS/FS/HS)

USB Port Assignments:

Reserved: PSOC (Legacy Trackpad)

Unused

Unused

Unused

Ext D (LS/FS/HS)

Reserved: Camera

Ext A (SS)

Ext B (SS)

USB3 Port Assignments:

Ext D (SS)

IR

BT

Trackpad(IPD)

Ext C (SS)

Ext B (LS/FS/HS)

73 76

73 76

73 76

73 76

12R13671/20W5% 201MF

10K

21R1368 10KMF 2015% 1/20W

21R1361 10K1/20W MF 2015%21R1362 10K

MF 2015% 1/20W

21R1360 10KMF 2011/20W5%

21R1369 10KMF 2015% 1/20W

13 18

13 18

18

13 18

18

13 18

38 76

13 18

K24

K26

BE28

BC26

BC24

BD23

BD27

BE26

BD25

BE24

AP29

AV29

AV26

AP26

AR29

AW29

AW26

AR26

C30

C32

H29

L31

G31

D33

C34

C36

G24

F26

C28

D29

C38

D37

A30

A32

G29

K31

F31

B33

A34

A36

F24

G26

A28

B29

A38

B37

BB29

M33

L33

BC30

BD41

BC40

BE38

BB37

BC36

BC34

BB33

BC32

BD42

BE40

BC38

BD37

BE36

BE34

BD33

BE32

AN39

AT39

AW38

AV36

AR33

AY33

AR31

AY31

AN38

AT40

AY38

AW36

AT33

AW33

AT31

AW31

BD29

BE30

M1

N2

T1

M3

P1

U2

V1

P3

U1100OMIT_TABLE

MOBILELYNXPOINT

FCBGA

38 76

38 76

38 76

38 76

38 76

69 72 76

69 72 76

69 76

69 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

73 76

50 77

50 77

BE43

BE44

BC45

BA45

AY43

AH1

AH3

AJ2

AJ4

AJ10

AL7

AJ7

AJ11

N11

K6

H6

R7

U8

N8

U11

R10

N7

AL11

B21

G20

D21

C18

A18

C20

A20

AF7

AF10

AF11

U1100

MOBILELYNXPOINT

OMIT_TABLE

FCBGA

44 77

44 77

44 77

44 77

18 44 69 71 72 77

18 44 69 71 72 77

2

1R1300

PLACE_NEAR=U1100.BD29:12.7mm

1/20W

201MF

1%7.5K

21R1340201MF5% 1/20W

3321R1341

MF 2015% 1/20W33

21R13432015%

331/20W MF

21R1342MF 201

335% 1/20W

21R13445% 201MF1/20W

33

13 20

13 41

21R13501/20W5% 201MF

10K

41 77

41 77

41 77

41 77

41 77

2

1R13808.2K

MF1/20W

201

1%

34 76

34 76

73 76

73 76

39 72 76

39 72 76

21R13551/20W5% 201MF

10K21R1354

1/20W5% 201MF10K

21R13531/20W5% 201MF

10K

21R13201/20W5% 201MF

10K21R1321

1/20W5% 201MF10K

50 77

50 77

13 50 77

13 50 77

18

21R1351 10KMF 2015% 1/20W

21R13931/20W5% 201MF

1K21R1392

1/20W5% 201MF1K

69 72 76

20 69 72 77

20 69 72 77

20 69 72 77

20 69 72 77

69 72 76

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

34 77

34 77

34 77

34 77

37 77

37 77

37 77

37 77

2

1R13701%1/20W

201MF

22.6

PLACE_NEAR=U1100.K24:11.4mm

PCH PCI-E/USBSYNC_MASTER=J15_REFERENCE SYNC_DATE=12/18/2012

PP3V3_S3PP3V3_S3RS0_CAMERA

XDP_DB3_SDCONN_STATE_CHANGE_L

CAMERA_PWR_EN

PP3V3_S0

PP3V3_SUSPP3V3_SUS

XDP_DA1_USB_EXTC_OC_LXDP_DA0_USB_EXTA_OC_L

TBT_PWR_EN_PCH

LPC_SERIRQ

SSD_PWR_EN

XDP_DB0_USB_EXTB_OC_L

SD_PWR_ENXDP_DB1_USB_EXTD_OC_L

PCH_SMBALERT_L

SPI_IO<3>SPI_IO<2>

PCH_SML0ALERT_LPCH_SML1ALERT_L

NC_USB3_EXTC_D2RN

USB3_EXTB_R2D_C_P

XDP_DA2_SSD_PWR_EN

NC_USB_6P

TP_USB_CAMERAP

NC_USB3_EXTC_R2D_CN

LPC_AD_R<1>LPC_AD_R<2>LPC_AD_R<3>

LPC_FRAME_R_L

NC_LPC_DREQ0_L

PCH_PCIE_RCOMPXDP_DB2_SD_PWR_EN

NC_USB3_EXTD_R2D_CP

NC_USB3_EXTD_D2RPNC_USB3_EXTD_D2RN

PP1V5_S0

NC_USB_6N

NC_USB_PSOCP

NC_USB_7N

NC_USB_PSOCN

NC_USB_4P

NC_USB_SDP

NC_USB_WLANP

NC_USB_4N

TP_USB_CAMERAN

NC_USB_SDN

NC_USB_WLANN

NC_USB_7P

XDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DB1_USB_EXTD_OC_LXDP_DB0_USB_EXTB_OC_LXDP_DA3_CAMERA_PWR_EN

XDP_DA1_USB_EXTC_OC_LXDP_DA0_USB_EXTA_OC_L

NC_USB3_EXTD_R2D_CN

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTC_D2RP

USB3_EXTB_R2D_C_NUSB3_EXTB_D2R_P

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N

USB3_EXTA_R2D_C_N

USB3_EXTA_D2R_NUSB3_EXTA_D2R_P

USB_TPAD_P

NC_USB_IRP

USB_TPAD_N

USB_BT_P

NC_USB_IRN

USB_BT_N

NC_USB_EXTDPNC_USB_EXTDN

USB_EXTB_PUSB_EXTB_N

NC_USB_EXTCPNC_USB_EXTCN

USB_EXTA_PUSB_EXTA_N

LPC_FRAME_L

LPC_AD<1>

LPC_AD<3>LPC_AD<2>

LPC_AD<0>

PCH_SML1ALERT_L

TBT_PWR_EN_PCH

TP_SPI_CS1_L

LPC_SERIRQ

SPI_CS0_R_L

SPI_IO<2>

SPI_IO<3>

SPI_CLK_R

TP_SPI_CS2_L

SPI_MISO

SPI_MOSI_R

NC_CLINK_RESET_L

PCH_TD_IREF

NC_CLINK_CLK

NC_CLINK_DATA

PCH_SMBALERT_L

SMBUS_PCH_CLK

PCH_SML0ALERT_L

SML_PCH_1_DATASML_PCH_1_CLK

SML_PCH_0_DATASML_PCH_0_CLK

SMBUS_PCH_DATA

LPC_AD_R<0>

PCH_USB_RBIAS

NC_PCIE_SSD_R2D_CP<2>

NC_PCIE_SSD_D2RN<3>NC_PCIE_SSD_D2RP<3>

NC_PCIE_SSD_R2D_CP<3>NC_PCIE_SSD_R2D_CN<3>

NC_PCIE_SSD_D2RP<2>

NC_PCIE_SSD_R2D_CN<2>

NC_PCIE_SSD_D2RN<2>

NC_PCIE_SSD_R2D_CN<0>

NC_PCIE_SSD_R2D_CN<1>NC_PCIE_SSD_R2D_CP<1>

NC_PCIE_SSD_D2RN<1>

NC_PCIE_SSD_R2D_CP<0>

PCIE_AP_D2R_NPCIE_AP_D2R_P

PCIE_AP_R2D_C_NPCIE_AP_R2D_C_P

PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_N

NC_USB3_SPARE_D2RPNC_USB3_SPARE_D2RN

NC_USB3_SPARE_R2D_CPNC_USB3_SPARE_R2D_CN

USB3_SD_D2R_NUSB3_SD_D2R_P

USB3_SD_R2D_C_NUSB3_SD_R2D_C_P

NC_PCIE_SSD_D2RP<1>

NC_PCIE_SSD_D2RP<0>NC_PCIE_SSD_D2RN<0>

<BRANCH>

<SCH_NUM>

<E4LABEL>

13 OF 118

13 OF 82

20 21 44 46 47 66 69 70 72

36 47 70

13 18

18 36

11 12 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 66

67 68 70 72 82

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

13 18

13 18

13 20

13 41

18 66

13 18

18 69 72

13 18

13

13 50 77

13 50 77

13

13

73 76

73

11 12 15 17 19 52 64 67 69 70 72

73 76

73

73 76

73

73

73 76

73

73

73 76

73

73 76

13

73

73

73

13

13

76

73

73

73

73

w w w

. c h

i n a

f i x

. c o

mOUT

BI

IN

OUT

OUT

IN

BI

ININ

OUT

IN

OUT

GPIO24

GPIO57

GPIO27

TACH4/GPIO68

SCLOCK/GPIO22

THRMTRIP*

BMBUSY*/GPIO0

SLOAD/GPIO38

GPIO35/NMI*

GPIO34

SDATAOUT1/GPIO48

SDATAOUT0/GPIO39

SATA5GP/GPIO49

SATA3GP/GPIO37

GPIO28

GPIO15

SATA4GP/GPIO16

TACH0/GPIO17

VSS

GPIO8

PLTRST_PROC*

TP14

LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

TACH2/GPIO6

TACH1/GPIO1

VSS

TACH7/GPIO71

TACH6/GPIO70

TACH5/GPIO69

PECI

PROCPWRGD

RCIN*

VSS

SATA2GP/GPIO36

CPU/MISC

(6 OF 11)

GPIO

OUT

OUT

BI

OUT

IN

OUT

BI

OUT

OUT

OUT

IN

IN

IN IN

OUT

TABLE_BOMGROUP_ITEM



Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Cactus Ridge: TBT_CIO_PLUG_EVENT, requires pull-down & isolation.

Pull-up/down on chipset support page (depends on TBT controller)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.Systems with chip-down memory should add pull-downs on another page and set straps per software.

Falcon Ridge: TBT_CIO_PLUG_EVENT_L, requires pull-up (S0), no isolation necessary.

(IPU-Boot/SATA5GP?)

NOTE: GPIO0 pull-up/down on project-specific page

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD)

(IPU-RSMRST#)

(IPU-DeepSx)

(IPU-Boot/SATA4GP?)

(IPU-Boot?)

(IPU-Boot?)

NOTE: GPIO70 pull-up/down on project-specific page

6 18 75

14 71

14 71

14 20

18

14 20

14 50 72

6 42 75

2

1R14725%

201

1/20WMF

10K

RAMCFG3:H

2

1R14735%

201

1/20WMF

10K

RAMCFG2:H

2

1R14745%

201

1/20WMF

10K

RAMCFG1:H

2

1R14755%

201

1/20WMF

10K

RAMCFG0:H

14 41

14 20

14 41

14 71

N10

A4

E45

E1

D1

BE3

BE2

BD45

BD44

BD2

BD1

BC1

BA1

B45

B44

B2

B1

A44

A43

A41

A2

A5

C45

BE5

BE41

AN10

AV1

H15

G13

D13

C16

G15

A14

F13

C14

AT7

AN4

AM3

BB4

AK3

AN2

AK1

AT3

AT6

AV3

AU4

AY1

K13

Y1

U12

AP1

AN6

AD11

R11

Y10

AB11

AT8 U1100OMIT_TABLE

MOBILELYNXPOINT

FCBGA

12R14115% 2011/20W MF

20K

12R14955% 2011/20W MF

100K

21R14915% 2011/20W MF

10K21R1492

5% 2011/20W MF10K

21R14935% 2011/20W MF

100K

21R14945% 2011/20W MF

10K

21R14845% 2011/20W MF

10K

21R14905% 2011/20W MF

100K

21R14965% 2011/20W MF

10K

21R14855% 2011/20W MF

10K

12R14125% 2011/20W MF

10K

29

14 18

12R14985% 2011/20W MF

10K

21R14505% 2011/20W MF

10K21R1455

5% 2011/20W MF10K

21R14705% 1/20WMF

43201

NO STUFF

21R1440MF

1/20W0201

5%0

21R1456 390201

1/20WMF5%

CRW_SPRT

6 42 75

14 71

20 28

18

14 71

6

21R14865% 2011/20W MF

10K21R1499

5% 2011/20W MF10K

12R14135% 2011/20W MF

10K

14 71

21R14895% 2011/20W MF

10K

18

14 71

14 18

2

1R1457

MF-LF402

1/16W

1K5%

BDW_SPRT

18 20 20

21

PCH GPIO/MISC/NCTFSYNC_MASTER=CLEAN_X305_PEG SYNC_DATE=02/18/2014

R1456 BDW_SPRT1117S0201 RES,MF,1A MAX,0.0 OHM,5%,0201,BLACK

RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

ISOLATE_CPU_MEM_L

SMC_WAKE_SCI_L

XDP_DD0_SSD_PCIE_SEL_L

WOL_EN

SMC_RUNTIME_SCI_L

FW_PME_L

TBT_CIO_PLUG_EVENT_L

PM_THRMTRIP_L_R

PCH_PROCPWRGD

PM_THRMTRIP_L

PCH_PECI

PCH_A20GATE

PCH_RCIN_L

PP1V05_S0

CPU_PECI

SD_SEL_PCIE_L_USB_H

JTAG_ISP_TDO

PP3V3_SUS

XDP_DD0_SSD_PCIE_SEL_LMEM_VDD_SEL_1V5_L

LPCPLUS_GPIOJTAG_TBT_TMS_PCH

XDP_DC2_ODD_PWR_EN_LJTAG_ISP_TCK

JTAG_ISP_TDI

PCH_RCIN_L

PP3V3_S5

PP3V3_S0

SPIROM_USE_MLB

CPU_RESET_L

CPU_PWRGD

PCH_A20GATE

SMC_RUNTIME_SCI_LWOL_EN

TBT_GO2SX_BIDIRSMC_WAKE_SCI_L

FW_PWR_EN_PCH

MLB_RAMCFG0

SPIROM_USE_MLB

JTAG_ISP_TDO

JTAG_ISP_TDI

XDP_DC3_JTAG_ISP_TCK

XDP_DC2_ODD_PWR_EN_L

XDP_FC1_GPU_GOOD

DPMUX_UC_IRQ

FW_PME_LDPMUX_UC_IRQ

MLB_RAMCFG2

MLB_RAMCFG3

FW_PWR_EN_PCH

XDP_FC0_HDD_PWR_EN

MEM_VDD_SEL_1V5_L

LPCPLUS_GPIO

TBT_GO2SX_BIDIR

TBT_POC_RESET_L

XDP_DD1_MLB_RAMCFG1

PP3V3_S0

JTAG_TBT_TMS_PCH

14 OF 82

14 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

42 77

14

14 77

10 15 17 18 42 62 67 70 72

14 20

11 12 13 15 17 50 64 66 67 70

14 18

14 71

14 71

14 20

14 18

18 20

14 20

14 77

12 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

14 50 72

14

14 41

14 71

14 71

14 41

14 71

20

14 71

14 71

20

20

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

w w w

. c h

i n a

f i x

. c o

mDCPSUS1

DCPSUSBYP

VCCADAC1_5

VSS

VCCVRM

VCCVRM

VCCVRM

VCCVRM

VCCIO

VCCIO

VCCIO

VCCIO

VCCIO

VCCASW

VCC3_3

DCPSUS3

VCCSUS3_3

VCCADACBG3_3

VCC

CRT

USB3

CORE

PCIE/DMI

(7 OF 11)

FDI

HVCMOS

SATA

VCCMPHY

DCPSUS2

VCCUSBPLL

VCCSPI

DCPSST

VCCRTC

VSS

VCCVRM

VCCVRM

VCCIO

VCCCLK3_3

VCCCLK

VCCASW

VCC3_3

VCC3_3VCC3_3

VCC

VCC

V_PROC_IO

DCPRTC

VCCSUSHDA

VCCSUS3_3

VCCDSW3_3

VCCSUS3_3

VCCSUS3_3

VCCIO

VCCCLK

THERMAL

(8 OF 11)

GPIO/LPC

USB

HDA

RTC

CPU

SPI

CLK/MISC

NC

NCNC

NC

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10mA Max, 1mA Idle

VCCSUS3_3: 261mA Max, 6mA Idle

VGA DAC Disabled per SBDG v1.0 (Table 12-18).

VCC3_3: 133mA Max, 3mA Idle

VCCIO: 3629mA Max, 264mA Idle

VCCVRM: 183mA Max, 68mA Idle



6uA Max (3.0V, room temperature)

VCCASW: 670mA Max, 34mA Idle

22mA Max, 1mA Idle

4mA Max, 2mA Idle




??mA Max, ??mA Idle

NOTE: Pin name is VCC but really is 3.3V







Powered in DeepSx




VCCCLK3_3: 55mA Max, 11mA Idle

VCC: 1.312 A Max, 130mA Idle


VCCCLK: 306mA Max, 89mA Idle




??mA Max, ??mA Idle

??mA Max, ??mA Idle

Current data from LPT EDS (doc #486708, Rev 1.0).

15 mA Max, 1mA Idle

2

1C1532

CERM402

BYPASS=U1100.A6::6.35mm

0.1UF10V20%

2

1 C1531

402


1UF

CERM6.3V10%

2

1C1533

CERM


0.1UF

402

10V20%

P43

BE22

BB44

AN11

AK28

AK26

AJ32

AJ30

AM20

AM18

AK22

AK20

AK18

AT22

AR22

AP22

AN35

AN34

AM22

V24

V22

V20

V18

U24

U22

U20

U18

AA18

Y22

Y20

Y18

M31

P45

AD28

AD26

AD24

AD22

AD20

AA26

R32

R30

AA24

Y26

AG24

AG22

AG20

AG18

AE26

AE24

AE22

AE20

AE18

U14

AJ28

AJ26

Y12

U1100

FCBGA

CKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2Gnd

MOBILELYNXPOINT

OMIT_TABLE

M24

AW40

AF34

U35

A26

U26

R28

R26

R24

R22

R20

K8

AD12

A6

Y30

V30

V28

U36U30

A16

AG32

AG30

AE32

AE30

AD36

AD35

V32

U32

M29

M26

L29

L26

AD34

AA32

AA30

Y32

R18

L17

AK32

AK30

AG14

AF12

AE14

L24

AP45

P20

P18

AJ14

AJ12

Y35

AA14

P16

P14

U1100OMIT_TABLE

LYNXPOINT

FCBGAMOBILE

2

1C155010%

6.3V

1UF

PLACE_NEAR=R1550.1:2.54mm

CERM402

21

R1550

1%

MF-LF1/20W

5.11

201

PLACE_NEAR=U1100.U14:2.54mm

2

1 C1590

BYPASS=U1100.P14::6.35mm

402CERM10V20%0.1UF

2

1 C1580

BYPASS=U1100.AA14::6.35mm

0.1UF

402CERM

20%10V

PCH PowerSYNC_DATE=12/18/2012SYNC_MASTER=J15_REFERENCE

PPVOUT_S0_PCH_DCPRTCMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

PPVOUT_S0_PCH_DCPSSTMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V


PP3V3_SUS

PP3V3_SUS

PP1V05_S0

PP3V3_S5

PP1V05_S0

PP1V05_S0

PP1V5_S0

PP3V3_S0

PP1V05_S0_PCH_VCC_CLK_F

PP1V5_S0

PP1V05_S0

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

PPVOUT_S5_PCH_DCPSUSBYP_RMIN_NECK_WIDTH=0.2 mmVOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 mmPPVOUT_S5_PCH_DCPSUSBYP

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP1V05_S0

PP3V3_S0

PP3V3_SUS

PP1V05_S0

PP1V05_S0

PP3V3_SUS

PP1V05_S0

PP1V5_S0

PP3V3_SUS

PPVRTC_G3H

PP3V3_S0

PP1V05_S0

PP1V5_S0

PP1V5_S0

PP1V5_S0

PP1V5_S0

PP1V05_S0

PP1V05_S0

<BRANCH>

<SCH_NUM>

<E4LABEL>

15 OF 118

15 OF 82

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

10 14 15 17 18 42 62 67 70 72

12 14 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

17

11 12 13 15 17 19 52 64 67 69 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

10 14 15 17 18 42 62 67 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 50 64 66 67 70

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

11 12 13 14 15 17 50 64 66 67 70

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 14 15 17 50 64 66 67 70

11 12 19 70

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

w w w

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VSS

VSS(10 OF 11)

VSSVSS

(11 OF 11)VSS

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Y8

Y40

AM16

Y36

Y34

Y28

Y24

Y16

Y14

W44

W2

V43

V26

AM32

V16

V14

U6

U42

U38

U34

U28

U16

U10

T43

AM30

R8

R44

R38

R34

R2

R16

R14

R12

P32

P30

AM28

P28

P26

P24

P22

N6

N39

N35

N12

M22

M17

AM26

L44

L2

K39

B15

B11

AY7

AY29

AY26

AY20

AY15

AM24

AY10

F43

AW2

AV6

AV40

BB25

AV33

AV31

AV24

AV22

AM14

AV13

D42

AT38

AT36

AT29

AT26

AT20

AT17

AT15

AT10

AL8

AK16

AR2

AP43

AP31

AP24

AP13

AN8

AN42

AN40

AN36

AL38

AL34 U1100

MOBILE

OMIT_TABLE

LYNXPOINT

FCBGA

AB38

AB34

AB12

AA4

AA28

AA22

AA20

AA16

BC28

K33

K29

K20

K15

K10

H7

H40

H36

H31

H26

H24

H22

H17

H13

H10

G8

G44

G38

G2

D4

BC16

F33

F29

F20

F15

AV7

D25

BD7

BD39

BD35

BD31

AT43

AY36

BD19

BD15

BD11

BA40

B7

B39

B35

B31

B27

B23

B19

BB42

BC22

AL2

AL12

AK45

AK43

AK24

AK14

AJ8

AJ6

AJ38

AJ34

AJ24

AJ22

AJ20

AJ18

AJ16

AG44

AG28

AG26

AG2

AG16

AF8

AF38

AE28

AE16

AD8

AD6

AD40

AD32

AD30

AD18

AD16

AD14

AC44

AC2

AB8

U1100LYNXPOINTMOBILE

OMIT_TABLE

FCBGA


PCH Grounds

16 OF 82

16 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

w w w

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(PCH 1.05V CPU I/F PWR)PCH V_PROC_IO BYPASS

(PCH 1.05V USB2 PWR)

PCH VCC BYPASS

Current data from LPT EDS (doc #486708, Rev 1.0).

183mA Max, 68mA Idle

??mA Max, ??mA Idle

(PCH 1.05V ME CORE PWR)PCH VCCASW BYPASS

(PCH 1.05V PCIe/DMI/SATA/USB3 PWR)PCH VCCIO BYPASS

PCH VCCVRM BYPASS

(PCH 3.3V SPI PWR)

PCH VCCSUS3_3 BYPASS(PCH 3.3V SUSPEND PWR)

PCH VCCSPI BYPASS

(PCH 3.3V THERMAL PWR)

PCH CLK VCC BYPASS(PCH 1.05V CLK PLL PWR)

PCH VCCCLK BYPASS

(PCH 1.05V DIFFCLK PWR)PCH VCCCLK BYPASS

(PCH 1.05V SSC100 PWR)

PCH VCCCLK BYPASS(PCH 1.05V SSC PWR)

(PCH 1.05V USB2 PLL PWR)

Not documented in EDS!PCH VCC BYPASS(PCH 1.05V CORE PWR)

PCH VCCUSBPLL BYPASS

(PCH 1.05V FDI PWR)PCH VCCIO BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCCCLK3_3 BYPASS(PCH 3.3V CLK PWR)

PCH VCC3_3 BYPASS(PCH 3.3V USB2 PWR)

PCH VCC3_3 BYPASS

(PCH 1.5V VCCVRM PWR)PCH VCCSUSHDA BYPASS

PCH VCCDSW3_3 BYPASS

PCH VCCIO BYPASS

(PCH 3.3V DSW PWR)

(PCH 3.3V/1.5V HDA PWR)

670mA Max, 34mA Idle

(PCH 3.3V FUSE PWR)

(PCH 3.3V SUSPEND USB PWR)PCH VCCSUS3_3 BYPASS

(PCH 1.05V DIFFCLK135 PWR)PCH VCCCLK BYPASS

(PCH 3.3V SUSPEND RTC PWR)PCH VCCSUS3_3 BYPASS

PCH VCC3_3 BYPASS(PCH 3.3V HVCMOS PWR)

PCH VCC3_3 BYPASS

2

1C1777

6.3VCERM402

1UF10%

BYPASS=U1100.AG30::6.35mm

2

1C17781UF

CERM402

10%6.3V

BYPASS=U1100.AD35::6.35mm

2

1C17801UF

CERM402

10%6.3V


2

1C17821UF

CERM402

10%6.3V


2

1 C17641UF

CERM402

10%6.3V

BYPASS=U1100.AM18::6.35mm

2

1 C17521UF

CERM402

10%6.3V

PLACE_NEAR=U1100.V20:2.54mm

2

1 C17511UF

CERM402

10%6.3V


2

1C1750

6.3V

22UF20%

603X5R-CERM-1


2

1 C17581UF

CERM402

10%6.3V

BYPASS=U1100.AE18::6.35mm

2

1 C17631UF

CERM402

10%6.3V

BYPASS=U1100.AK20::6.35mm

2

1 C17571UF

CERM402

10%6.3V


2

1C175510UF

X5R603

20%6.3V

BYPASS=U1100.AG18::12.7mm

2

1 C1756

CERM402

1UF10%6.3V


2

1 C17621UF

CERM402

10%6.3V


2

1 C1761

6.3V10%

402CERM

1UF


2

1C176010UF

20%6.3V

603X5R


2

1C1776

6.3VCERM402

1UF10%


2

1C1770

6.3V

402CERM

10%1UF

BYPASS=U1100.U35::6.35mm

2

1C17721UF

CERM402

10%6.3V

BYPASS=U1100.AN34::6.35mm

2

1C17740.1UF

20%10V

402CERM


2

1 C17870.1UF

CERM

20%

402

10V

BYPASS=U1100.AJ12::6.35mm

2

1C1785

6.3V

402

1UF10%

CERM


2

1 C17860.1UF20%

402CERM10V


2

1C1723

402CERM6.3V

1UF10%


2

1C17260.1UF

20%

CERM10V

402BYPASS=U1100.R30::6.35mm

2

1C17280.01UF

0402X7R-CERM

10%16V


2

1C17300.1UF

20%

CERM10V

402BYPASS=U1100.L24::6.35mm

2

1C17320.1UF

20%10V

402CERM


2

1C1734

402CERM

1UF10%

6.3V

BYPASS=U1100.P18::6.35mm

2

1 C17911UF

X5R402

10%10V

BYPASS=U1100.AP45::6.35mm

2

1C1790NO STUFF

10UF

X5R603

20%6.3V

BYPASS=U1100.AP45::12.7mm

21

L1790OMIT_TABLECRITICAL

4.7UH-170MA-0.321OHM

0603

21

R1790

MF-LF402

5%1/16W

12

1C174010UF

X5R603

20%6.3V

BYPASS=U1100.AF34::12.7mm

2

1C1722

CERM6.3V

1UF10%

402

BYPASS=U1100.M29::6.35mm

2

1C1721

402CERM6.3V

1UF10%

BYPASS=U1100.L29::6.35mm

2

1C1720

BYPASS=U1100.L26::6.35mm

402CERM6.3V

1UF10%

2

1C1700

10V20%

CERM

0.1UF

402BYPASS=U1100.A16::6.35mm

2

1C17040.1UF

20%

402

10VCERM

BYPASS=U1100.R20::6.35mm

2

1C17021UF

CERM402

10%6.3V


2

1C17081UF

BYPASS=U1100.K8::6.35mm

10%6.3VCERM402

2

1C1706

BYPASS=U1100.R26::6.35mm

0.1UF20%10V

402CERM

2

1C171020%

0.1UF10V

402CERM



PCH DECOUPLING

113S0022 1 RES,FF,0 OHM,(020OHM MAX),2A,0603 L1790

PP3V3_SUS

PP3V3_SUS

PP1V05_S0

PP3V3_S0

PP1V05_S0

PP1V05_S0

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP1V05_S0

PP3V3_S0

PP3V3_S0PP3V3_SUS

PP3V3_SUS

PP1V05_S0

PP1V05_S0_PCH_VCC_CLK_R

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM

PP1V5_S0PP1V5_S0PP1V5_S0PP1V5_S0PP1V5_S0

PP1V5_S0

PP1V5_S0

PP1V5_S0

PP1V05_S0

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCC_CLK_F

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

<BRANCH>

<SCH_NUM>

<E4LABEL>

17 OF 118

17 OF 82

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

10 14 15 17 18 42 62 67 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69 70 72

12 14 15 18 19 21 31 32 34 61 64 66 67 70 71 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82 11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

10 14 15 17 18 42 62 67 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

10 14 15 17 18 42 62 67 70 72

15

w w w

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IN

OUT

IN

IN

IN

OUT

OUT IN

OUT

OUT

OUT

OUTIN

INOUT

OUT

OUT

IN

IN

IN

OUTIN

OUTIN

OUT IN

BI

BI

BI

BI

TP

TP

TP

TP

IN

OUT

OUT

OUT

NCNC

Y

NC NC

VCC

GND

AIN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

OUT

NCNC

BI

IN

IN

IN

IN

IN

IN

IN

IN

TP

TP

TP

TP

TP

TP

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

BI

IN

OUT

IN

OUT

OUT

OUT

INOUT

GVER 5

SD

GVER 5

SD

GVER 5

SD

GVER 5

SD

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Merged (CPU/PCH) Micro2-XDP

support chipset debug. Use with 921-0133 Adapter Flex toNOTE: This is not the standard XDP pinout.

OBSDATA_C0

OBSFN_D0

OBSDATA_C2

OBSFN_C1

TCK0

TDI and TMS are terminated in CPU.

PCH/XDP Signals(All 10 R’s)

Non-XDP Signals

PCH/XDP Signal Isolation Notes:

’Output’ non-XDP signals require pulls.

signal path needs to split between routefrom PCH to J1850 and path to non-XDPsignal destination (to minimize stub).

Unused PCH/XDP Signals

’Output’ PCH/XDP signals require pulls.

R187x and R189x should be placed where

OBSFN_B1OBSFN_B0

OBSDATA_A3OBSDATA_A2

OBSDATA_A1OBSDATA_A0

OBSDATA_B0

OBSDATA_B3

VCC_OBS_AB

Extra BPM Testpoints

CPU JTAG Isolation

SDA

TCK1SCL

HOOK2

HOOK1

HOOK3

OBSDATA_B2

PWRGD/HOOK0

518S0847

TDOTRSTnTDITMS

VCC_OBS_CDRESET#/HOOK6

ITPCLK#/HOOK5

OBSDATA_D3

DBR#/HOOK7

XDP_PRESENT#

OBSDATA_D2

OBSDATA_B1

OBSFN_A0OBSFN_A1

OBSFN_C0

OBSDATA_C1

OBSDATA_C3

OBSDATA_D0OBSDATA_D1

OBSFN_D1

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

20

11

21R1897201

SHORT

OMIT

NONE NONENONE

21R1896201

SHORTNONE NONENONE

OMIT

21R1872201NONE

OMIT

NONE NONESHORT

13

21R1875201NONE

SHORTNONE NONE

OMIT

11 18

11

11 18

21R1890201

OMIT

SHORTNONENONENONE

13 38

13 69 72

13

14 20

21R1893201

SHORTNONENONE NONE

OMIT

13

21R1894201NONE NONE NONE

SHORT

OMIT

13

21R1879201

SHORT

OMIT

NONE NONE NONE11

11 18

14

11 18

11 34

13 66 13

14 18 14 18

21R1895201

SHORTNONENONENONE

OMIT

14 35

13

13

14

14

1 TP1810TP-P61 TP1811TP-P61 TP1812TP-P61 TP1813TP-P6

6 18 72 75

6 18 72 75

6 72 75

12R18615% 2011/20W MF

51XDP

PLACE_NEAR=U1100.AE2:28mm

12R18605% 2011/20W MF

XDP51

PLACE_NEAR=U1100.AD3:28mm

12R18625% 2011/20W MF

XDP51

PLACE_NEAR=U1100.AD1:28mm

12R18665% 2011/20W MF

XDP51

PLACE_NEAR=U1100.AB3:28mm

6 72 75

2

1R18455%

201

1/20WMF

330K

4

6

51

3

2

U184574LVC1G07GF

SOT8912

1C1845

16V

0201X5R-CERM

0.1UF10%

19 41 58 67 72

21R18205% 2011/20W MF

51XDP

PLACE_NEAR=U0500.M49:28mm

12R18235% 2011/20W MF

51XDP

PLACE_NEAR=U0500.N54:28mm

6 75

6 75

6 75

6 75

6 75

6 75

6 75

6 75

6 75

2

1R18305%150

402MF-LF1/16W

12 20 21 72

11 18 72

11 18 72

11 18 72

21R18055% 2011/20W MF

XDP1K

PLACE_NEAR=U0500.AG7:2.54mm

6 75

6 75

6 75

6 19 75

2

1 C1806

CERM-X5R

0.1UF10%6.3V

0201

XDP

2

1 C1801XDP

6.3VCERM-X5R0201

0.1UF10%

9

8 7

64 63

62 61

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1800

CRITICALXDP_CONN

DF40RC-60DP-0.4VM-ST-SM1

2

1C1800XDP

6.3VCERM-X5R

0201

0.1UF10%

6 72 75

6 72 75

6 75

6 75

6 75

6 72 75

6 75

6 75

6 75

1 TP1802TP-P61 TP1803TP-P61 TP1804TP-P61 TP1805TP-P61 TP1806TP-P61 TP1807TP-P6

6 75

6 75

6 75

6 75

6 75

6 75

2

1C1804XDP

6.3VCERM-X5R

0201

0.1UF10%

2

1R18315%1K

XDP

MF-LF402

1/16W

6 75

6 75

6 75

8

13 44 69 71 72 77

13 44 69 71 72 77

11 18 72

21R18005% 2011/20W MFPLACE_NEAR=U0500.F50:2.54mm

1KXDP

21R18025%

002011/20W MF

XDP

PLACE_NEAR=U5000.J3:2.54mm

21R18045%

0XDP

402MF-LF1/16W

6 14 75

12 41 77

12 19 41 72 77

6 18 72 75

12R18245% 2011/20W MF

51XDP

PLACE_NEAR=U0500.M53:28mm

21R1876201

OMIT

NONENONENONESHORT

14 18 20 14 18 20

1

2

6

Q1840

PLACE_NEAR=J1800.53:28mm

SOT563

CRITICAL

XDPDMN5L06VK-7

4

5

3

Q1840


SOT563XDPDMN5L06VK-7

CRITICAL

4

5

3

Q1842CRITICAL

XDP SOT563DMN5L06VK-7


1

2

6

Q1842

XDP


SOT563

CRITICAL

DMN5L06VK-7


CPU & PCH XDP

XDP_PCH_TDI

XDP_CPU_TDI

XDP_JTAG_CPU_ISOL_L

XDP_CPU_TMS

XDP_PCH_TMS

XDP_CPUPCH_TRST_LMAKE_BASE=TRUEXDP_CPUPCH_TRST_L

XDP_TRST_L

XDP_CPU_TDO

XDP_PCH_TDO

XDP_CPU_PRESENT_L

XDP_CPU_VCCST_PWRGDXDP_CPU_PWRBTN_L

XDP_SYS_PWROK

SMBUS_PCH_DATA

XDP_CPU_TCK

PP5V_S0

CPU_PWRGD

PP1V05_S0

PP1V05_S0

XDP_CPUPCH_TRST_L

XDP_CPU_TDO

XDP_PCH_TMS

XDP_PCH_TDO

XDP_PCH_TCK

PP3V3_S5

ALL_SYS_PWRGD

CPU_CFG<18>


CPU_CFG<19>

CPU_PWR_DEBUG PLT_RESET_L


XDP_DBRESET_L

CPU_CFG<1>

XDP_CPU_PREQ_L

CPU_CFG<0>




XDP_PCH_TCK

CPU_CFG<3>

XDP_BPM_L<2>

XDP_BPM_L<6>

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

PM_PCH_SYS_PWROK

PM_PWRBTN_L

XDP_CPU_TCK

AP_CLKREQ_L

XDP_FC0_HDD_PWR_EN

XDP_DA1_USB_EXTC_OC_L

XDP_DB1_USB_EXTD_OC_L

XDP_FC1_GPU_GOOD

SMBUS_PCH_CLK

XDP_CPU_PRDY_L

USB_EXTA_OC_L

CAMERA_PWR_ENSSD_PWR_EN

USB_EXTB_OC_L

SDCONN_STATE_CHANGE_LSD_PWR_EN

DP_AUXCH_ISOL_L

XDP_DC2_ODD_PWR_EN_LJTAG_ISP_TCKSSD_PCIE_SEL_L

XDP_DA0_USB_EXTA_OC_L

XDP_DA3_CAMERA_PWR_ENXDP_DA2_SSD_PWR_EN

XDP_DB0_USB_EXTB_OC_LXDP_DB2_SD_PWR_ENXDP_DB3_SDCONN_STATE_CHANGE_L

XDP_DC1_SATARDRVR_EN MAKE_BASE=TRUE

XDP_DC3_JTAG_ISP_TCKXDP_DC2_ODD_PWR_EN_L MAKE_BASE=TRUE

XDP_DD0_SSD_PCIE_SEL_L

XDP_DD2_ENETSD_CLKREQ_LXDP_DD1_MLB_RAMCFG1

XDP_DC1_SATARDRVR_EN

XDP_DD3_AP_CLKREQ_L

XDP_DD1_MLB_RAMCFG1 MAKE_BASE=TRUEXDP_DD2_ENETSD_CLKREQ_L MAKE_BASE=TRUE

XDP_DC0_DP_AUXCH_ISOL_L

PP1V05_SUS

XDP_PCH_TDI

XDP_CPURST_L

PPVCCIO_S0_CPU

CPU_CFG<10>

CPU_CFG<9>


CPU_CFG<2>

CPU_CFG<8>

CPU_CFG<11>

<BRANCH>

<SCH_NUM>

<E4LABEL>

18 OF 82

18 OF 118

6 18 72 75

19 37 49 58 59 62 63 66 67 70 71 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

6 18 72 75

6 18 72 75

11 18 72

11 18 72

11 18 72

12 14 15 17 19 21 31 32 34 61 64 66 67 70 71 72 82

6 18 72 75

64 70

11 18 72

5 6 8 10 58

w w w

. c h

i n a

f i x

. c o

m

IN

IN OUT

OUTIN

OUT

OUT

OUT

OUT

NCNC

IN

OUT

OUT

OUT

OUT

OUTIN

IN

Y

A

B 08

Y

A

B 08

IN

32.768K

GND THRM

VOUT

X2

X1

25M_A

25M_B

25M_C

VIOE_25M_A

VIOE_25M_B

VIOE_25M_C

VG3HOT

NC

VDD

PAD

VER 3

D

SG

GVER 5

SD

NC

YA

B

NCGND

VCC

OUT

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6 3



(SLG3NB148C). addressed in upcoming part at least S4. Both issues to be complicates VDD_25M power, forcing 1.2V VDDIO. Falcon Ridge also edge on 25MHZ_B when powered fromNOTE: SLG3NB148A provides slow rising

No bypass necessary

System RTC Power Source & 32kHz / 25MHz Clock Generator

PCH 33MHz Clocks

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.If high, ME is disabled. This allows for full re-flashing of SPI ROM.

PCH Reset Button

VDDIO_25M_A: SB power rail for XTAL circuit.

TBT XTAL Power

IPD = 9-50k

NOTE: 30 PPM crystal required

NOTE: ALL_SYS_PWRGD must remain low until at least 5ms after all rails are valid.

No Coin-Cell: 3.42V G3Hot (no RC)

For SB RTC Power

to reduce VBAT draw.

VBAT and +V3.3A areinternally ORed to

+V3.3A should be first

create VDD_RTC_OUT.

available ~3.3V power

VDDIO_25M_B: Camera power rail for XTAL circuit.VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

Coin-Cell: VBAT (300-ohm & 10uF RC)

GreenClk 25MHz Power

Camera XTAL PowerSB XTAL Power

No Coin-Cell: 3.3V S5Coin-Cell & No G3Hot: 3.3V S5Coin-Cell & G3Hot: 3.42V G3Hot

SMC controls strap enable to allow in-field control of strap setting.Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH PWROK Generation

PCH ME Disable Strap

VCCST (1.05V S0) PWRGDWF: Do we need this?

6 18 75 21

R1996XDP

402

1/16WMF-LF

0

5%

21

R1955

1/20W


MF

22

201

5%

11 77 41 77

11 77 21

R1959

PLACE_NEAR=U1100.A40:6.35mm

22

MF1/20W

201

5%

11 77

2

1R1997

SILK_PART=SYS RESET402MF-LF1/16W

OMIT

5%0

2

1R19955%1/16W

402MF-LF

1K

12 41 72 77

11 76

11 76

28 76

2

1 C1910

402CERM

10%6.3V

1UF

2

1C19021UF

402-1

10V10%

X5R2

1C1920

10V

402CERM

20%0.1UF

2

1C19220.1UF

402CERM10V20%

2

1R1906

402

1/16WMF-LF

1M

NO STUFF

5%

2

1C19240.1UF

10VCERM402

20%

21

R1905

1/16WMF-LF402

0

5%

2 1

C1905

5%

0402

50VC0G

12PF

21

C1906

5%

0402

12PF

50VC0G

41 42

2

1R19211K

MF1/20W

201

5%

2

1R1920100K

MF1/20W

201

5%

11 77

37 76

1

2R1948

MF1/20W5%0

0201

NO STUFF

12 19 72 77

12 19 72 77

21

R19491K

1/16W

402

5%

MF-LF

12 18 41 72 77 58

18 41 58 67 72

3

8

4

6

5

U1950

CKPLUS_WAIVE=UNCONNECTED_PINS

SOT833

PLACE_NEAR=U1100.AD7:7MM

74LVC2G08GT/S505

CKPLUS_WAIVE=UNCONNECTED_PINS

7

8

4

2

1

U1950SOT833

74LVC2G08GT/S5052

1R1950

1/16W

2.0K

MF-LF402

5%

2

1 C195020%10V

402

BYPASS=U1950::5MM

CERM

0.1UF

29 30 41 42

2

1R1947

MF1/20W

0201

05%

3

4

1

14

6

11

13

5

17

2

16

10

7

12

15

8

9

U1900

CRITICALTQFN

SLG3NB148CV

31

42

Y1905CRITICAL

25.000MHZ-20PPM-12PF-85C3.2X2.5MM-SM

12

6Q1920

DMN5L06VK-7SOT563

4

5

3

Q1920DMN5L06VK-7

SOT563

4

6

5

3

1

2

U1930SOT891

CRITICAL

74AUP1G09

BDW_SPRT

2

1C19300.1UF

10%16V

X5R-CERM0201

BDW_SPRT

2

1R193010K5%

201

1/20WMF

BDW_SPRT

8


Chipset Support

PM_PCH_PWROKMAKE_BASE=TRUE

PP3V3_S5

PM_PCH_PWROK

PP1V05_S0_CPU_VCCST

CPU_VCCST_PWRGD

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDEPP1V5_S0

SPI_DESCRIPTOR_OVERRIDE_L

PP3V3_S5

PP3V3_S5

PCH_CLK33M_PCIINPCH_CLK33M_PCIOUT

SYSCLK_CLK25M_X2

SYSCLK_CLK25M_X1

PP1V2_CAM_XTALPCIEVDD

PP3V42_G3H

PP1V5_S0

SYSCLK_CLK25M_TBTSYSCLK_CLK25M_CAMERASYSCLK_CLK25M_SB

SYSCLK_CLK25M_X2_RPPVRTC_G3H

SYSCLK_CLK32K_RTC

PP3V3_S0

ALL_SYS_PWRGD

LPC_CLK33M_SMC_R

XDP_DBRESET_L PM_SYSRST_L

HDA_SDOUT_R

PP5V_S0

PP3V3_S0

CPUVR_PGOODPM_S0_PGOOD

PM_PCH_PWROK

SMC_DELAYED_PWRGD

PM_PCH_SYS_PWROKSYS_PWROK_R

PP3V42_G3H

LPC_CLK33M_SMC

PP3V3_TBTLC

<BRANCH>

<SCH_NUM>

<E4LABEL>

19 OF 118

19 OF 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 19 72 77

8 10

11 12 13 15 17 19 52 64 67 69 70 72

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71

72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

36

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 15 70

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51

52 55 66 67 68 70 72 82

18 37 49 58 59 62 63 66 67 70 71 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

20 28 29 70

w w w

. c h

i n a

f i x

. c o

mOUT

OUT

OUT

OUT

OUT

OUT

OUTIN

IN

IN OUT

OUT

IN

IN

OUT

OUT IN

IN

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

GND

1Y

VCC

1A

3Y 3A

2A 2Y

Y

B

A

IN

GVER 5

SD

GVER 5

SD

IN

OUT

OUT

OUT

OUT

OUT

ING

SYM_VER_1

D

S

OUT

IN

IN

08

Y1

Y2

GNDB2

VCC

A1B1A2

OUT

OUT

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RIO SD Card Reader Support

Falcon Ridge JTAG Isolation

RR output is open-drain, no isolation necessary

To/From RR

Pull-up values TBD

Platform Reset ConnectionsUnbuffered

(Pull-ups on PCH page)

GS3 Connector Support

HDMI HPD pull-down

LCD HPD Inverter

Buffered

(Pull-Up on CPU Page)

To/From PCH

DEVSLP not supported on LPT-H

RAM Configuration Straps

GPIO Glitch Prevention

U2060 supports I/O’s powered when VCC=0V

TBTLC can be on when S0 is off, and vice-versa

To/From PCH

From RIO Connector

Must pull signal correctly even if always USB or PCIeFlexible I/O Configuration Strap

SD Card Reader is always USB3 in this implementaton.Flexible I/O Aliases

Falcon Ridge Support

TBT_PWR_EN must be high for JTAG ProgrammingIsolation ensures no leakage to RR or PCH

18

14

14 18

14

14

2

1R2002

201MF

1/20W5%1K

RAMCFG0:L

2

1R2011

201

RAMCFG1:L

1K5%

MF1/20W

2

1R2012

201

RAMCFG2:L

MF1/20W

5%1K

2

1R2013

201

1/20WMF

5%1K

RAMCFG3:L

2

1R2070

201

5%1/20W

MF

10K

35

2

1R2040470K

5%1/20W

MF201

20 28 13

12 41

2

1R2075

1/20W

201MF

5%10K

14 20 28 14 20 28

14

2

1R2030

201

5%1/20W

MF

100K

13 20 69 72 77

13 20 69 72 77

13 20 69 72 77

13 20 69 72 77 13 20 69 72 77

13 20 69 72 77

13 20 69 72 77

13 20 69 72 77

14

14

14

28

2

1R2063

201MF1/20W5%10K

28

2

1R206210K

201

5%1/20WMF

2

1R2061

201MF

1/20W5%

10K

69 72

2

1C2060

X5R-CERM

10%0.1UF

16V

0201

2

1R2010

201

100K5%

1/20WMF

12 69 71 72

2

5

7

84

6

3

1

U2060

CRITICAL

SN74AUP3G07DQERX2SON

4

5

3

1

2

U2030CRITICAL

TC7SZ08FEAPESOT665

2

1C20800.1UF

CERM10V20%

402

28

4

5

3

Q2040DMN5L06VK-7

SOT5631

2

6

Q2040DMN5L06VK-7SOT563

2

1R2080

MF-LF1/16W

100K

402

5%

5

4

1

2

3

U2080

MC74VHC1G08

CRITICAL

SC70-HF

21

R2091

5%

0

MF-LF1/16W

402

21

R2087

5%

402MF-LF1/16W

0

21

R2088

5%

402

0

1/16WMF-LF

21

R2085

5%

402

1/16WMF-LF

0

2

1C203010%

0.1UF

0201CERM-X5R

6.3V

2

1R2041

201

470K5%1/20WMF

12 18 21 72 21

R208333

1/16WMF-LF402

5%

36

28

34

35

41

68

2

1

3

Q2010DMN32D2LFB4DFN1006H4-3

5

14 18

20 28

3

7

8

4

6

2

5

1

U2000

74LVC2G08GT/S505

CRITICAL

SOT8332

1 C201310%0.1UF

X5R-CERM0201

16V

28

28 41 42 43


Project Chipset Support

RIO_SDCONN_STATE_CHANGE_L

PP3V3_S3

SDCONN_STATE_CHANGE_L

USB3_SD_R2D_C_PMAKE_BASE=TRUE

PP3V3_S0

PP3V3_S0

PP3V3_S0

USB3_SD_D2R_P

JTAG_TBT_TMS

PP3V3_S0

JTAG_TBT_TMS_PCH

JTAG_ISP_TDO

JTAG_ISP_TDI JTAG_TBT_TDI


LPC_PWRDWN_LTBT_PWR_EN_PCH

JTAG_TBT_TCK

TBT_PWR_EN

MLB_RAMCFG0XDP_DD1_MLB_RAMCFG1MLB_RAMCFG2MLB_RAMCFG3

MAKE_BASE=TRUEUSB3_SD_D2R_N

USB3_SD_D2R_PMAKE_BASE=TRUE

USB3_SD_R2D_C_NMAKE_BASE=TRUE

USB3_SD_R2D_C_P

USB3_SD_D2R_N

USB3_SD_R2D_C_N

SD_SEL_PCIE_L_USB_H

SSD_DEVSLP

LCD_HPD

DP_IG_A_HPD_L

PP3V3_S0

SSD_RESET_L

AP_RESET_L

CAM_PCIE_RESET_L

PP3V3_S4

TBT_PCIE_RESET_L

PLT_RST_BUF_LMAKE_BASE=TRUE

HDMI_HPD

MAKE_BASE=TRUETBT_CIO_PLUG_EVENT_L

JTAG_ISP_TCKTBT_PWR_EN

SMC_LRESET_LPLT_RESET_LMAKE_BASE=TRUE

PP3V3_TBTLC

JTAG_TBT_TDO

SMC_PME_S4_DARK_L

SMC_PME_SDCONN

<BRANCH>

<SCH_NUM>

<E4LABEL>

20 OF 118

20 OF 82

13 21 44 46 47 66 69 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51

52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48

49 51 52 55 66 67 68 70

72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

34 39 40 42 43 46 47 65 66 67 69 70 71 72

19 28 29 70

w w w

. c h

i n a

f i x

. c o

m

IN IN

IN

OUT

OUT

OUT

IN

IN

IN

G

D

S

OUT

VER 3

D

SG

VER 3

D

SG

GVER 5

SD

G VER 5

S D

VER 3

D

SG

VER 3

D

S G

VER 3

D

SG

VER 3

D

S G

VER 3

D

SG

VER 3

D

SG

OUT

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Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN CPUVDDQ_EN

5 0 1 1 1 0 (*) 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

1 0 1 1 1 1 1 1 1

2 0 0 1 1 1 1 0 1

3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

6 0 1 1 1 1 1 1 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

CPUVDDQ_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

75mA max load @ 0.75V

S0

to

S3

to

60mW max power

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

S0

MEMVTT ClampEnsures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

MEM S0 "PGOOD" for CPU

14 12 41 67 72

12 18 20 72

2

1R2102

402

1/16W

100K

CPUMEM:S0

5%

MF-LF

21 60 71

2

1R2110

402

10K

MF-LF1/16W5%

CPUMEM:S0

2

1R2115CPUMEM:S0

100K5%

1/16WMF-LF

402

23 24 25 26

2

1R21161K

CPUMEM:S0

5%1/16W

402MF-LF

66

2

1R210510K

1/16W

CPUMEM:S0

5%

MF-LF402

12 34 38 41 67 69 72

2

1R2101

MF-LF402

5%

CPUMEM:S0

1/16W

100K

21 60 71

2

1R2151CPUMEM:S0

5%

402

100K

1/16WMF-LF

2

1C21510.001UF

NO STUFF

50V20%

CERM402

2

1R2150CPUMEM:S0

105%

MF-LF603

1/10W

21

R2117

402MF-LF

0

5%1/16W

CPUMEM:S3

6 21

2

1R2121

402

43.2K

1/16W1%

MF-LF

2

1R2120

1%

MF-LF1/16W

27.4K

402

4

3

5 Q2120

SOT-563

DMB53D0UV

CRITICAL

2

1R2122

5%10K

MF-LF1/16W

402

1

2

6

Q2120CRITICAL

SOT-563

DMB53D0UV

6 12 75

2

1C2120

10V

0.047UF10%

X5R-CERM0402

2

1 C2116CPUMEM:S0

0.1UF

10VCERM402

20%

2

1C21170.047UF

201

6.3VX5R

10%

NO STUFF

12

6Q2100

CPUMEM:S0

DMN5L06VK-7SOT563

CRITICAL1

2

6Q2110

SOT563

DMN5L06VK-7

CRITICALCPUMEM:S0

1

2

6

Q2115

CRITICALCPUMEM:S0

DMN5L06VK-7SOT563

4

5

3

Q2115

SOT563

DMN5L06VK-7

CRITICALCPUMEM:S0

45

3Q2100

DMN5L06VK-7

CRITICAL

SOT563

CPUMEM:S0

45

3 Q2110

SOT563

DMN5L06VK-7

CRITICALCPUMEM:S0

12

6Q2105CRITICALCPUMEM:S0

DMN5L06VK-7SOT563

45

3 Q2105DMN5L06VK-7SOT563

CRITICALCPUMEM:S0

12

6Q2150

CPUMEM:S0

DMN5L06VK-7SOT563

CRITICAL

45

3Q2150

SOT563

DMN5L06VK-7

CPUMEM:S0CRITICAL

22

CPU Memory S3 Support

SYNC_MASTER=CLEAN_X305G SYNC_DATE=07/01/2014

MEMRESET_ISOL_LS5V_L

CPU_MEM_RESET_L

PP3V3_S3

MEMPWR_DIV

PM_MEM_PWRGD_L

PM_MEM_PWRGDPP3V3_S5

PPVTT_S0_DDR

PP5V_S3

PLT_RESET_L

MEMVTT_EN

PM_SLP_S3_L

PM_SLP_S4_L

MEMVTT_EN

VTTCLAMP_L

VTTCLAMP_EN

PP1V35_S3RS0_CPUDDR

CPUVDDQ_EN_L

CPUVDDQ_EN

ISOLATE_CPU_MEM_L

PP5V_S3

MEMVTT_EN_L

PP1V35_S3

MEM_RESET_LMAKE_BASE=TRUECPU_MEM_RESET_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

21 OF 118

21 OF 82

13 20 44 46 47 66 69 70 72

12 14 15 17 18 19 31 32 34 61 64 66 67 70 71 72 82

27 60 70 72

21 37 60 66 67 70 72

6 8 10 66 67 70 82

21 37 60 66 67 70 72

46 60 66 70 72

w w w

. c h

i n a

f i x

. c o

mIN

IN

IN

G VER 5

S D

G VER 5

S D

G VER 5

S D

G VER 5

S D

IN

Apple Inc.


124578

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A


PAGE

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



of margining option.

LPDDR3 (1.2V) ?.??mV per step

DDR3L (1.35V) 6.99mV per step

NOTE: CPU DAC output step sizes:

DDR3 (1.5V) 7.70mV per step

NOTE: CPU has single output for VREFCA.

Connected to 4 DRAMs.

Margined target:

DAC Channel:

PCA9557D Pin:

DAC range:

Nominal value

VRef current:

DAC step size:

A

0.600V (DAC: 0x2E.5)

0.300V - 0.900V (+/- 300mV)

0.000V - 1.199V (0x00 - 0x5D)

+73uA - -73uA (- = sourced)

6.36mV / step @ output

2

C

3

MEM B VREF DQ

DDR3L (1.35V)

0.337V - 1.013V (+/- 337.5mV)

0.675V (DAC: 0x34)


MEM A VREF CA

0.000V - 1.354V (0x00 - 0x69)


MEM B VREF CA

4

C

1.200V (DAC: 0x5D)

0.800V - 1.600V (+/- 400mV)



LPDDR3 (1.2V)

0.000V - 2.397V (0x00 - 0xBA)

0.972V - 1.714V (+/- 371mV)

DDR3L (1.35V)

5

D

MEM VREG

1.343V (DAC: 0x68)

0.000V - 2.694V (0x00 - 0xD1)



DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

MEM A VREF DQ

B

LPDDR3 (1.2V)

1

CPU-Based Margining

VRef DividersAlways used, regardless

2

1R22211K

201MF

1%1/20W

2

1R22411K

MF201

1/20W1%

2

1R22221K


MF201

1%1/20W

21

R222024.9

1/20W1%

201MF

2

1R22611K1%

MF201

1/20W

2

1R22421K


MF201

1%1/20W

21

R2240

201

24.9

1/20W1%

MF

2

1R22621K

MF201

1/20W1%


21

R2260

1/20W1%

201MF

24.9

21

R22232

1/20WMF

1%

0201

2

1 C2220

6.3V10%0.022UF

0201X5R-CERM

21

R22432

1/20W1%

MF0201

2

1 C2240

0201

6.3V

0.022UF10%

X5R-CERM

21

R2263

0201

2

MF

1%1/20W

2

1 C22600.022UF

X5R-CERM6.3V10%

0201

7 75

7 75

7

1

2

6

Q2220CRITICAL

DMN5L06VK-7SOT563

4

5

3

Q2220SOT563

CRITICAL

DMN5L06VK-7

1

2

6

Q2260CRITICAL

SOT563DMN5L06VK-7

4

5

3

Q2260CRITICAL

SOT563DMN5L06VK-7

21

SYNC_MASTER=CLEAN_X305

DDR3 VREF MARGININGSYNC_DATE=01/14/2014

PP1V35_S3_MEM

PP0V75_S3_MEM_VREFDQ_AMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_BMIN_LINE_WIDTH=0.3 mm

MEM_VREFDQ_A_RC

MEM_VREFCA_RC


PP0V75_S3_MEM_VREFCAMIN_LINE_WIDTH=0.3 mmMIN_LINE_WIDTH=0.3 mm


CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

CPU_MEM_VREFCA_ISOLMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm


CPU_DIMMA_VREFDQ

CPU_MEM_VREFDQ_B_ISOLMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

MEM_VREFDQ_B_RC

CPU_MEM_VREFDQ_A_ISOLMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm

MEMRESET_ISOL_LS5V_L

<BRANCH>

<E4LABEL>

22 OF 82

22 OF 118

<SCH_NUM>

23 24 25 26 46 70 78

23 24 71 75 78

25 26 71 75

23 24 25 26 71 75 78

w w w

. c h

i n a

f i x

. c o

m

NCNCNC

NCNCNC

NC

NCNC

NC

NC NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNC NC

NC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.


124578

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

2

1C2340

X5R-CERM

2.2UF

402

10V20%

2

1C2341

X5R-CERM

2.2UF

402

10V20%

2

1 C234310%0.1UF

0201CERM-X5R6.3V 2

1 C234410%0.1UF

0201CERM-X5R6.3V 2

1 C234510%0.1UF

0201CERM-X5R6.3V 2

1 C235310%0.1UF

0201CERM-X5R6.3V 2

1 C235410%0.1UF

0201CERM-X5R6.3V 2

1 C23550.1UF10%6.3VCERM-X5R0201

2

1 C236310%0.1UF

0201CERM-X5R6.3V 2

1 C236410%0.1UF

0201CERM-X5R6.3V 2

1 C236510%0.1UF

0201CERM-X5R6.3V 2

1 C237310%0.1UF

0201CERM-X5R6.3V 2

1 C237410%0.1UF

0201CERM-X5R6.3V 2

1 C237510%0.1UF

0201CERM-X5R6.3V

1

2R2300

201

2401%1/20WMF

1

2R2310

201

1/20W1%240

MF1

2R2320

201

2401%1/20WMF

1

2R2330

201MF1/20W

2401%

2

1C2307

201

0.47UF20%4V

CERM-X5R-1

2

1 C230910%

201X5R6.3V

0.047UF

2

1C230810%

201X5R

6.3V

0.047UF

2

1 C231910%

201X5R6.3V

0.047UF

2

1C231810%

201X5R

6.3V

0.047UF2

1C2317

201CERM-X5R-1

4V20%

0.47UF

2

1 C232910%

201X5R6.3V

0.047UF

2

1C232810%

201X5R

6.3V

0.047UF2

1C2327

201

0.47UF4V20%

CERM-X5R-1 2

1 C233910%

201X5R6.3V

0.047UF

2

1C233810%

201X5R

6.3V

0.047UF2

1C2337

201

0.47UF

CERM-X5R-14V20%

2

1 C237910%

201X5R6.3V

0.047UF

2

1C237810%

201X5R

6.3V

0.047UF2

1C2377

201

20%4V

CERM-X5R-1

0.47UF

2

1 C236910%

201X5R6.3V

0.047UF

2

1C236810%

201X5R

6.3V

0.047UF2

1C2367

201

20%4V

CERM-X5R-1

0.47UF

2

1 C235910%

201X5R6.3V

0.047UF

2

1C235810%

201X5R

6.3V

0.047UF

1

2R2370

201

2401%1/20WMF

1

2R2360

201MF1/20W1%240

2

1C2357

201

20%4V

CERM-X5R-1

0.47UF

2

1 C234910%

201X5R6.3V

0.047UF

2

1C234810%

201X5R

6.3V

0.047UF2

1C2347

201

0.47UF20%4V

CERM-X5R-1

1

2R2350

201

2401%1/20WMF

1

2R2340

201MF1/20W1%240

2

1 C233510%0.1UF

0201CERM-X5R6.3V2

1 C233410%0.1UF

0201CERM-X5R6.3V2

1 C233310%0.1UF

0201CERM-X5R6.3V2

1 C232510%0.1UF

0201CERM-X5R6.3V2

1 C232410%0.1UF

0201CERM-X5R6.3V2

1 C232310%0.1UF

0201CERM-X5R6.3V2

1 C2315

CERM-X5R0201

10%0.1UF6.3V2

1 C231410%0.1UF

0201CERM-X5R6.3V2

1 C231310%0.1UF

0201CERM-X5R6.3V2

1 C230510%0.1UF

0201CERM-X5R6.3V2

1 C230410%0.1UF

0201CERM-X5R6.3V2

1 C230310%0.1UF

0201CERM-X5R6.3V2

1C2301

X5R-CERM

2.2UF

402

10V20%

2

1C2300

X5R-CERM

2.2UF20%10V

4022

1C231120%10V

402

2.2UF

X5R-CERM

2

1C235120%10V

402

2.2UF

X5R-CERM

2

1C2310

X5R-CERM402

10V20%

2.2UF

2

1C235020%10V

402

2.2UF

X5R-CERM

2

1C232120%10V

402

2.2UF

X5R-CERM

2

1C236120%10V

402X5R-CERM

2.2UF

2

1C2320

402

10V20%

2.2UF

X5R-CERM

2

1C2360

10V

402

2.2UF

X5R-CERM

20%

2

1C233120%10V

402

2.2UF

X5R-CERM2

1C2330

402

10V20%

2.2UF

X5R-CERM

2

1C237120%10V

402X5R-CERM

2.2UF

2

1C2370

X5R-CERM402

20%10V

2.2UF

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2300DDR3-1333

OMIT_TABLE

FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2310OMIT_TABLE

DDR3-1333FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2320OMIT_TABLE

DDR3-1333FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2330DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2340OMIT_TABLE

DDR3-1333FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2350OMIT_TABLE

DDR3-1333FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2360DDR3-1333

OMIT_TABLE

FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2370FBGA

DDR3-1333

OMIT_TABLE

SYNC_MASTER=J15_MLB SYNC_DATE=10/31/2012

DDR3 SDRAM Bank A (1 OF 2)

PP0V75_S3_MEM_VREFDQ_APP0V75_S3_MEM_VREFCAPP0V75_S3_MEM_VREFDQ_A

PP1V35_S3_MEM

PP1V35_S3_MEM

MEM_A_ZQ<5>

MEM_A_A<4>

PP0V75_S3_MEM_VREFDQ_APP0V75_S3_MEM_VREFCA

MEM_A_DQ<6>

MEM_A_A<11>

MEM_A_A<11>

MEM_A_DQS_N<5>

PP0V75_S3_MEM_VREFCAPP0V75_S3_MEM_VREFDQ_A


PP0V75_S3_MEM_VREFDQ_A

MEM_A_CLK_N<0>MEM_A_CLK_P<0>

MEM_A_RAS_L

MEM_A_ZQ<7>

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L

MEM_A_BA<0>MEM_A_BA<1>

MEM_RESET_L

MEM_A_A<9>MEM_A_A<8>


MEM_A_A<5>

MEM_A_A<1>

PP0V75_S3_MEM_VREFCA

PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>

MEM_A_A<10>


MEM_A_BA<2>


MEM_A_DQ<62>

MEM_A_DQS_N<7>

MEM_A_CKE<0>MEM_A_CS_L<0>

MEM_A_DQS_P<7>

MEM_A_DQ<63>

MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_DQS_P<6>


MEM_A_RAS_L

MEM_A_ZQ<6>

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<5>

MEM_A_A<1>


MEM_A_A<10>


MEM_A_BA<2>


MEM_A_DQ<54>

MEM_A_DQS_N<6>


MEM_A_DQ<55>



MEM_A_A<2>

PP1V35_S3_MEM


MEM_A_RAS_L

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<5>

MEM_A_A<1>

PP1V35_S3_MEM

MEM_A_A<0>


MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>


MEM_A_DQ<46>


MEM_A_DQS_P<5>

MEM_A_DQ<47>


MEM_A_A<2>MEM_A_DQ<32>

MEM_A_CAS_L

MEM_A_DQ<37>


MEM_A_RAS_L

MEM_A_ZQ<4>

MEM_A_WE_L

MEM_A_ODT<0>


MEM_RESET_L



MEM_A_A<5>

MEM_A_A<1>


MEM_A_A<0>


MEM_A_A<10>


MEM_A_BA<2>


MEM_A_DQ<38>

MEM_A_DQS_N<4>


MEM_A_DQS_P<4>

MEM_A_DQ<39>

MEM_A_DQ<36>MEM_A_DQ<35>MEM_A_DQ<34>MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_CKE<0>


MEM_A_CLK_N<0>MEM_A_RAS_L

MEM_A_ZQ<3>

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<5>

MEM_A_A<1>


PP1V35_S3_MEM

MEM_A_A<0>


MEM_A_A<10>


MEM_A_BA<2>


MEM_A_DQ<26>

MEM_A_DQS_N<3>

MEM_A_CS_L<0>

MEM_A_DQS_P<3>

MEM_A_DQ<29>



PP1V35_S3_MEM

MEM_A_A<2>

MEM_A_A<4>



MEM_A_RAS_L

MEM_A_ZQ<2>

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<5>

MEM_A_A<1>


MEM_A_A<0>


MEM_A_A<10>

MEM_A_BA<2>


MEM_A_DQ<20>

MEM_A_DQS_N<2>


MEM_A_DQS_P<2>

MEM_A_DQ<19>


MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQ<14>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_DQ<9>

MEM_A_A<0>

MEM_A_DQ<7>


MEM_A_CLK_N<0>MEM_A_RAS_L

MEM_A_ZQ<1>

MEM_A_WE_L

MEM_A_ODT<0>

MEM_A_CAS_L


MEM_RESET_L





MEM_A_A<10>


MEM_A_BA<2>


MEM_A_DQ<8>

MEM_A_DQS_N<1>


MEM_A_DQS_P<1>

MEM_A_DQ<12>

MEM_A_DQ<13>MEM_A_DQ<11>MEM_A_DQ<15>MEM_A_DQ<10>

MEM_A_A<2>

MEM_A_A<7>

PP1V35_S3_MEM

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_DQS_N<0>


MEM_A_A<2>MEM_A_DQ<0>


MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_DQ<2>


MEM_A_BA<2>


MEM_A_A<10>

MEM_A_A<13>




MEM_RESET_L


MEM_A_CAS_L

MEM_A_ODT<0>

MEM_A_WE_L

MEM_A_ZQ<0>

MEM_A_RAS_LMEM_A_CLK_P<0>MEM_A_CLK_N<0>

<BRANCH>

<SCH_NUM>

<E4LABEL>

23 OF 118

23 OF 82

22 23 24 71 75 78

22 23 24 25 26 71 75 78

22 23 24 71 75 78

22 23 24 25 26 46 70 78

22 23 24 25 26 46 70 78

7 23 24 27 78

22 23 24 71 75 78

22 23 24 25 26 71 75 78

7 24 78

7 23 24 27

78

7 23 24 27

78

7 24 78

22 23 24 25 26 71 75 78

22 23 24 71 75 78

7 24 78

7 24 78

22 23 24 71 75 78

7 23 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

21 23 24 25 26

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 78

7 24 78

7 23 27 78

7 23 27 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 46 70 78

7 23 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78 7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 27 78

22 23 24 71 75 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

21 23 24 25 26

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 78

7 24 78

7 23 27 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 24 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27 78

22 23 24 71 75 78

7 23 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 46 70 78

7 23 27

78

7 23 24 27 78

7 23 24 27 78

7 24 78

22 23 24 71 75 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

7 23 24 27 78 7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27 78

7 23 24 27 78

7 23 24 27 78

7 23 27

78

w w w

. c h

i n a

f i x

. c o

m

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

NCNCNCNC

NCNCNC

NC

NCNC

NC

NC NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2440DDR3-1333

OMIT_TABLE

FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2450DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2460DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2470DDR3-1333

FBGA

OMIT_TABLE

1

2R2400

201

1/20WMF

1%240

1

2R2410

201

2401%1/20WMF

1

2R2420

201

1/20W

240

MF

1%

1

2R2430

201

2401%1/20WMF

2

1C2407

201

0.47UF20%4V

CERM-X5R-1 2

1 C240910%

201X5R6.3V

0.047UF

2

1C240810%

201X5R

6.3V

0.047UF

2

1 C241910%

201X5R6.3V

0.047UF

2

1C241810%

201X5R

6.3V

0.047UF2

1C2417

201

20%4V

CERM-X5R-1

0.47UF

2

1 C242910%

201X5R6.3V

0.047UF

2

1C242810%

201X5R

6.3V

0.047UF2

1C2427

201

20%4V

CERM-X5R-1

0.47UF

2

1 C243910%

201X5R6.3V

0.047UF

2

1C243810%

201X5R

6.3V

0.047UF2

1C2437

201

20%4V

CERM-X5R-1

0.47UF

2

1 C247910%

201X5R6.3V

0.047UF

2

1C247810%

201X5R

6.3V

0.047UF2

1C2477

201

0.47UF

CERM-X5R-14V20%

2

1 C246910%

201X5R6.3V

0.047UF

2

1C246810%

201X5R

6.3V

0.047UF2

1C2467

201

4V20%

0.47UF

CERM-X5R-12

1 C245910%

201X5R6.3V

0.047UF

2

1C245810%

201X5R

6.3V

0.047UF

1

2R2470

201MF1/20W1%240

1

2R2460

201

2401%1/20WMF

2

1C2457

201CERM-X5R-1

0.47UF4V20%

2

1 C244910%

201X5R6.3V

0.047UF

2

1C244810%

201X5R

6.3V

0.047UF2

1C2447

201

0.47UF

CERM-X5R-14V20%

1

2R2450

201MF1/20W1%240

1

2R2440

201

2401%1/20WMF

2

1C2440

10VX5R-CERM

2.2UF

402

20%

2

1C2400

X5R-CERM

2.2UF20%10V

402

2

1C2441

X5R-CERM

2.2UF

402

10V20%

2

1C2401

X5R-CERM

2.2UF

402

10V20%

2

1C2450

X5R-CERM

20%10V

402

2.2UF

2

1C2410

402

10V20%

2.2UF

X5R-CERM

2

1C24512.2UF

20%10V

402X5R-CERM

2

1C241120%10V

402

2.2UF

X5R-CERM

2

1C246020%10V

402

2.2UF

X5R-CERM 2

1C246120%10V

402

2.2UF

X5R-CERM

2

1C2420

402

10V20%

2.2UF

X5R-CERM 2

1C242120%10V

402

2.2UF

X5R-CERM

2

1C247020%10V

402X5R-CERM

2.2UF

2

1C247120%10V

402

2.2UF

X5R-CERM

2

1C2430

402

10V20%

2.2UF

X5R-CERM 2

1C243120%10V

402

2.2UF

X5R-CERM

2

1 C244310%0.1UF

0201CERM-X5R6.3V 2

1 C244410%0.1UF

0201CERM-X5R6.3V

2

1 C240310%0.1UF

0201CERM-X5R6.3V 2

1 C240410%0.1UF

0201CERM-X5R6.3V

2

1 C244510%0.1UF

0201CERM-X5R6.3V 2

1 C245310%0.1UF

0201CERM-X5R6.3V

2

1 C240510%0.1UF

0201CERM-X5R6.3V 2

1 C241310%0.1UF

0201CERM-X5R6.3V

2

1 C245410%0.1UF

0201CERM-X5R6.3V

2

1 C241410%0.1UF

0201CERM-X5R6.3V

2

1 C245510%0.1UF

0201CERM-X5R6.3V 2

1 C246310%0.1UF

0201CERM-X5R6.3V

2

1 C241510%0.1UF

0201CERM-X5R6.3V 2

1 C242310%0.1UF

0201CERM-X5R6.3V

2

1 C246410%0.1UF

0201CERM-X5R6.3V 2

1 C246510%0.1UF

0201CERM-X5R6.3V

2

1 C242410%0.1UF

0201CERM-X5R6.3V 2

1 C242510%0.1UF

0201CERM-X5R6.3V

2

1 C247310%0.1UF

0201CERM-X5R6.3V

2

1 C243310%0.1UF

0201CERM-X5R6.3V

2

1 C247410%0.1UF

0201CERM-X5R6.3V

2

1 C243410%0.1UF

0201CERM-X5R6.3V

2

1 C247510%0.1UF

0201CERM-X5R6.3V

2

1 C243510%0.1UF

0201CERM-X5R6.3V

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2400OMIT_TABLE

FBGADDR3-1333

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2410OMIT_TABLE

FBGADDR3-1333

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2420DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2430OMIT_TABLE

DDR3-1333FBGA


DDR3 SDRAM Bank A (2 OF 2)

MEM_A_A<10>

MEM_A_A<14>


MEM_A_A<5>



MEM_A_RAS_L

MEM_A_ZQ<15>

MEM_A_WE_L

MEM_A_ODT<1>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<6>

MEM_A_A<1>


PP1V35_S3_MEM

MEM_A_A<0>



MEM_A_BA<2>

MEM_A_A<15>

MEM_A_DQ<61>

MEM_A_DQS_N<7>


MEM_A_DQS_P<7>

MEM_A_DQ<60>


MEM_A_A<2>

MEM_A_DQ<43>


MEM_A_DQS_N<5>


MEM_A_RAS_L

MEM_A_ZQ<14>

MEM_A_WE_L

MEM_A_ODT<1>

MEM_A_CAS_L


MEM_RESET_L

MEM_A_A<9>

MEM_A_A<6>


PP1V35_S3_MEM

MEM_A_A<0>

MEM_A_A<13>


MEM_A_BA<2>


MEM_A_DQ<53>

MEM_A_DQS_N<6>


MEM_A_DQS_P<6>

MEM_A_DQ<52>


MEM_A_A<2>

MEM_A_CLK_N<1>

MEM_A_DQS_N<4>


MEM_A_ODT<1>


MEM_A_RAS_LMEM_A_CAS_L

MEM_A_BA<1>

MEM_RESET_L



MEM_A_A<6>



MEM_A_A<10>

MEM_A_A<3>

MEM_A_BA<2>


MEM_A_DQ<45>


MEM_A_DQS_P<5>

MEM_A_DQ<44>


MEM_A_DQ<40>

MEM_A_A<2>


MEM_A_CLK_P<1>MEM_A_RAS_L

MEM_A_ZQ<12>

MEM_A_WE_L

MEM_A_ODT<1>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<6>

MEM_A_A<1>


PP1V35_S3_MEM

MEM_A_A<0>


MEM_A_A<10>


MEM_A_BA<2>



MEM_A_DQS_P<4>

MEM_A_DQ<36>

MEM_A_DQ<39>MEM_A_DQ<34>MEM_A_DQ<35>MEM_A_DQ<32>MEM_A_DQ<33>

MEM_A_A<2>

MEM_A_WE_L

MEM_A_A<0>

MEM_A_CLK_N<1>



MEM_A_ZQ<11>

MEM_A_WE_L

MEM_A_ODT<1>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<6>

MEM_A_A<1>


PP1V35_S3_MEM

MEM_A_A<0>


MEM_A_A<10>


MEM_A_BA<2>


MEM_A_DQ<25>

MEM_A_DQS_N<3>


MEM_A_DQS_P<3>

MEM_A_DQ<30>



MEM_A_A<6>


MEM_A_DQ<18>

MEM_A_DQS_P<2>

MEM_A_CS_L<1>MEM_A_CKE<1>

MEM_A_DQS_N<2>

MEM_A_DQ<23>


MEM_A_BA<2>


MEM_A_A<10>


PP1V35_S3_MEM


MEM_A_A<1>



MEM_RESET_L


MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_WE_L

MEM_A_ZQ<10>

MEM_A_RAS_LMEM_A_CLK_P<1>MEM_A_CLK_N<1>


MEM_A_DQ<10>

PP0V75_S3_MEM_VREFDQ_APP0V75_S3_MEM_VREFCA

MEM_A_DQ<13>

PP1V35_S3_MEM

MEM_A_CS_L<1>

MEM_A_CLK_N<1>

MEM_A_A<15>

MEM_A_DQS_N<0>


MEM_A_RAS_L

MEM_A_ZQ<9>

MEM_A_WE_L

MEM_A_ODT<1>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<6>



MEM_A_A<10>


MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQS_N<1>


MEM_A_DQS_P<1>

MEM_A_DQ<11>



MEM_A_A<2>

PP1V35_S3_MEM

MEM_A_A<15>

MEM_A_A<13>



MEM_A_ZQ<8>

MEM_A_ODT<1>

MEM_A_CAS_L


MEM_RESET_L



MEM_A_A<6>

MEM_A_A<1>


MEM_A_A<0>


MEM_A_A<10>


MEM_A_BA<2>

MEM_A_A<14>

MEM_A_DQ<1>

MEM_A_CKE<1>

MEM_A_DQS_P<0>

MEM_A_DQ<3>


MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<41>MEM_A_A<4>

MEM_A_A<1>

MEM_A_A<8>MEM_A_A<7>MEM_A_DQ<46>

MEM_A_BA<0>

MEM_A_WE_L

MEM_A_ZQ<13>

PP1V35_S3_MEM

PP1V35_S3_MEM

<BRANCH>

<SCH_NUM>

<E4LABEL>

24 OF 118

24 OF 82

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

7 23 24 27 78

22 23 24 71 75 78

7 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

21 23 24 25 26

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78 7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 78

7 23 78

7 24 27 78

7 24 27 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 24 27 78

7 23 78

7 23 24 27

78

7 23 24

27 78

7 23 24 27 78

7 23 78

7 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 78

7 23 78

7 23 78

7 24 27 78

7 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

21 23 24 25 26

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 78

7 23 24 27 78

22 23 24 71 75 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 78

7 23 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

22 23 24 71 75 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

21 23 24 25 26

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 78

7 23 78

7 24 27 78

7 24 27 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 78

7 23 24 27 78 7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27

78

22 23 24 25 26 46 70 78

22 23 24 25 26 71 75 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 24 27

78

22 23 24 71 75 78 22 23 24 71 75 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 24 27 78

7 24 27 78

7 23 24 27 78

7 23 78

7 24 27 78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27

78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 78

7 23 24 27 78

22 23 24 25 26 46 70 78

7 23 24 27 78

7 23 24 27 78

22 23 24 71 75 78

7 24 27

78

7 23 24 27 78

7 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 71 75 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

7 23 78

7 23 24 27 78

22 23 24 71 75 78 22 23 24 71 75 78

7 23 24 27 78

7 23 24 27 78

7 23 24 27 78

22 23 24 25 26 46 70 78

22 23 24 25 26 46 70 78

w w w

. c h

i n a

f i x

. c o

m

NCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

NCNCNC

NC

NCNC

NC

NC NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NC

NCNCNC

NC

NCNCNC

NC

NCNC

NC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NCNCNCNC

A12/BC*

A13

VSS

RAS*

BA2

BA1

BA0

VSSQ

NF/DQ5

NF/DQ4

CS*

CKE

NF/TDQS*

DM/TDQS

DQS*

DQS

VREFDQ

NC

CK*

CK

ZQ

WE*

ODT

CAS*

RESET*

A9

A8

A6

A7

A5

A1

VREFCA

VDDQVDD

A0

A11

A10/AP

A4

A3

A14

NF/DQ6

NF/DQ7

DQ3

DQ2

DQ1

DQ0

NC

A2

A15

(SYM VER 2)

NC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2550OMIT_TABLE

DDR3-1333FBGA

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2560DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2570DDR3-1333

FBGA

OMIT_TABLE

1

2R2500

201MF1/20W1%240

1

2R2510

201

2401%1/20WMF

1

2R2520

201MF1/20W

2401%

1

2R2530

201MF

2401%1/20W

2

1C2507

201CERM-X5R-1

20%4V

0.47UF

2

1 C250910%

201X5R6.3V

0.047UF

2

1C250810%

201X5R

6.3V

0.047UF

2

1 C251910%

201X5R6.3V

0.047UF

2

1C251810%

201X5R

6.3V

0.047UF2

1C2517

201

20%4V

CERM-X5R-1

0.47UF

2

1 C252910%

201X5R6.3V

0.047UF

2

1C252810%

201X5R

6.3V

0.047UF2

1C2527

201

0.47UF20%4V

CERM-X5R-1 2

1 C253910%

201X5R6.3V

0.047UF

2

1C253810%

201X5R

6.3V

0.047UF2

1C2537

201

20%4V

CERM-X5R-1

0.47UF

2

1 C257910%

201X5R6.3V

0.047UF

2

1C257810%

201X5R

6.3V

0.047UF2

1C2577

201

20%4V

CERM-X5R-1

0.47UF

2

1 C256910%

201X5R6.3V

0.047UF

2

1C256810%

201X5R

6.3V

0.047UF2

1C2567

201

20%4V

CERM-X5R-1

0.47UF

2

1 C255910%

201X5R6.3V

0.047UF

2

1C255810%

201X5R

6.3V

0.047UF

1

2R2570

201

2401%1/20WMF

1

2R2560

201MF

2401/20W1%

2

1C2557

201CERM-X5R-1

20%4V

0.47UF

2

1 C254910%

201X5R6.3V

0.047UF

2

1C254810%

201X5R

6.3V

0.047UF2

1C2547

201CERM-X5R-1

0.47UF4V20%

1

2R2550

201

2401%1/20WMF

1

2R2540

201MF1/20W1%240

2

1C2540

X5R-CERM

2.2UF

402

10V20%

2

1C25002.2UF

X5R-CERM

20%10V

402

2

1C2541

X5R-CERM

2.2UF

402

10V20%

2

1C255020%10V

402

2.2UF

X5R-CERM

2

1C2501

X5R-CERM

2.2UF

402

10V20%

2

1C2510

402

10V20%

2.2UF

X5R-CERM

2

1C255120%10V

402

2.2UF

X5R-CERM

2

1C251120%10V

402

2.2UF

X5R-CERM

2

1C256020%10V

402

2.2UF

X5R-CERM 2

1C256120%10V

402

2.2UF

X5R-CERM

2

1C2520

402

10V20%

2.2UF

X5R-CERM 2

1C252120%10V

402

2.2UF

X5R-CERM

2

1C257020%10V

402

2.2UF

X5R-CERM 2

1C257120%10V

402X5R-CERM

2.2UF

2

1C2530

402

20%

X5R-CERM10V

2.2UF

2

1C253120%10V

402

2.2UF

X5R-CERM

2

1 C254310%0.1UF

0201CERM-X5R6.3V 2

1 C254410%0.1UF

0201CERM-X5R6.3V

2

1 C250310%0.1UF

0201CERM-X5R6.3V 2

1 C250410%0.1UF

0201CERM-X5R6.3V

2

1 C254510%0.1UF

0201CERM-X5R6.3V 2

1 C255310%0.1UF

0201CERM-X5R6.3V

2

1 C250510%0.1UF

0201CERM-X5R6.3V 2

1 C251310%0.1UF

0201CERM-X5R6.3V

2

1 C255410%0.1UF

0201CERM-X5R6.3V

2

1 C251410%0.1UF

0201CERM-X5R6.3V

2

1 C255510%0.1UF

0201CERM-X5R6.3V 2

1 C256310%0.1UF

0201CERM-X5R6.3V

2

1 C251510%0.1UF

0201CERM-X5R6.3V 2

1 C252310%0.1UF

0201CERM-X5R6.3V

2

1 C256410%0.1UF

0201CERM-X5R6.3V 2

1 C256510%0.1UF

0201CERM-X5R6.3V

2

1 C252410%0.1UF

0201CERM-X5R6.3V 2

1 C252510%0.1UF

0201CERM-X5R6.3V

2

1 C257310%0.1UF

0201CERM-X5R6.3V

2

1 C253310%0.1UF

0201CERM-X5R6.3V 2

1 C253410%0.1UF

0201CERM-X5R6.3V

2

1 C257410%0.1UF

0201CERM-X5R6.3V 2

1 C257510%0.1UF

0201CERM-X5R6.3V

2

1 C253510%0.1UF

0201CERM-X5R6.3V

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2500DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2510DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2520DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2530DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2540DDR3-1333

FBGA

OMIT_TABLE


DDR3 SDRAM Bank B (1 OF 2)

MEM_B_A<4>MEM_B_A<3>

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_ZQ<6>

MEM_B_ZQ<2>

MEM_B_A<2>

MEM_B_A<6>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_CLK_N<0>MEM_B_CLK_P<0>

MEM_B_RAS_L

MEM_B_ZQ<7>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<0>MEM_B_BA<1>

MEM_RESET_L



MEM_B_A<5>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>

MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_CKE<0>MEM_B_CS_L<0>

MEM_B_DQS_P<7>

MEM_B_DQ<63>

MEM_B_DQ<61>MEM_B_DQ<60>MEM_B_DQ<59>MEM_B_DQ<58>MEM_B_DQ<57>MEM_B_DQ<56>

MEM_B_A<2>



MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L

MEM_B_BA<1>

MEM_RESET_L


MEM_B_A<5>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>

MEM_B_BA<2>


MEM_B_DQ<54>

MEM_B_DQS_N<6>


MEM_B_DQS_P<6>

MEM_B_DQ<55>



MEM_B_A<5>

MEM_B_DQ<32>



MEM_B_RAS_L

MEM_B_ZQ<5>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<46>

MEM_B_DQS_N<5>


MEM_B_DQS_P<5>

MEM_B_DQ<47>


MEM_B_A<2>



MEM_B_RAS_L

MEM_B_ZQ<4>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<5>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<38>

MEM_B_DQS_N<4>


MEM_B_DQS_P<4>

MEM_B_DQ<39>


MEM_B_A<2>

MEM_B_WE_L MEM_B_WE_L


MEM_B_ODT<0>

MEM_B_WE_L

MEM_B_DQ<19>



MEM_B_RAS_L

MEM_B_ZQ<3>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<5>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<31>

MEM_B_DQS_N<3>


MEM_B_DQS_P<3>

MEM_B_DQ<24>


MEM_B_A<2>


MEM_B_DQ<20>

MEM_B_DQ<17>

MEM_B_A<5>


MEM_B_RAS_L

MEM_B_ODT<0>

MEM_B_CAS_L


MEM_RESET_L

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<22>

MEM_B_DQS_N<2>


MEM_B_DQS_P<2>


MEM_B_DQ<18>MEM_B_A<2>


MEM_B_A<12>



MEM_B_RAS_L

MEM_B_ZQ<1>

MEM_B_WE_L

MEM_B_ODT<0>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<5>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<15>

MEM_B_DQS_N<1>


MEM_B_DQS_P<1>

MEM_B_DQ<8>



MEM_B_A<2>

PP1V35_S3_MEM


MEM_B_DQ<0>

MEM_B_CKE<0>

MEM_B_DQ<5>



MEM_B_RAS_L

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<5>

MEM_B_A<1>


MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<7>

MEM_B_DQS_N<0>

MEM_B_CS_L<0>

MEM_B_DQS_P<0>


MEM_B_A<2>

PP1V35_S3_MEM

<BRANCH>

<SCH_NUM>

<E4LABEL>

25 OF 118

25 OF 82

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 25 26 71 75

7 25 27 78

7 25 27 78

7 25 26 27 78

7 25 26 27 78

7 25 27 78

7 25 26 27 78

7 25 26 27 78

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Apple Inc.


124578

B

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8 7 6 5 4 3

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PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




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L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2630DDR3-1333

FBGA

OMIT_TABLE

H9

H4

D10

C10

B9

D2

B3

J10

F9

D9

A9

F3

N2

L2

J2

N10

L10

B2

A2

E2

J9

E10

E3

C2

B10

M10

M2

K10

K2

G3

G9

D8

A10

A3

N3

F4

G2

A8

E8

D3

E9

E4

N11N1

H10

H2

F10

F2

A11

A4

A1

D4

C4

C9

C3

C8

B4

B8

H3

G10

G8

F8

G4

J4

K9

J3

M4

N9

M3

M9

L3

L9

K3

L4

J8

N8

N4

K8

M8

H8

L8

K4

U2640DDR3-1333

FBGA

OMIT_TABLE

DDR3 SDRAM Bank B (2 OF 2)SYNC_MASTER=J15_MLB SYNC_DATE=10/31/2012


MEM_B_DQ<2>

PP1V35_S3_MEM

MEM_B_DQ<51>

MEM_B_BA<2>MEM_B_CLK_P<1>MEM_B_CLK_N<1>


MEM_B_A<1>

MEM_B_CKE<1>



MEM_B_RAS_L

MEM_B_ZQ<15>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<6>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>



MEM_B_DQ<61>

MEM_B_DQS_N<7>


MEM_B_DQS_P<7>

MEM_B_DQ<60>



MEM_B_DQ<47>

MEM_B_CS_L<1>


MEM_B_RAS_L

MEM_B_ZQ<14>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L




MEM_B_A<0>


MEM_B_A<10>

MEM_B_A<4>

MEM_B_BA<2>


MEM_B_DQ<53>

MEM_B_DQS_N<6>MEM_B_DQS_P<6>

MEM_B_DQ<52>



MEM_RESET_L

MEM_B_A<5>

MEM_B_DQ<41>

PP1V35_S3_MEM



MEM_B_RAS_L

MEM_B_ZQ<13>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L


MEM_B_A<6>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<45>

MEM_B_DQS_N<5>


MEM_B_DQS_P<5>

MEM_B_DQ<44>

MEM_B_DQ<46>


MEM_B_A<2>



MEM_B_CLK_P<1>


MEM_B_CLK_N<1>MEM_B_RAS_L

MEM_B_ZQ<12>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L



MEM_B_A<1>


MEM_B_A<0>


MEM_B_A<10>

MEM_B_BA<2>


MEM_B_DQ<37>

MEM_B_DQS_N<4>


MEM_B_DQS_P<4>

MEM_B_DQ<36>


MEM_B_A<2>

MEM_B_WE_L



MEM_B_RAS_L

MEM_B_ZQ<11>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<6>

MEM_B_A<1>


PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<28>

MEM_B_DQS_N<3>


MEM_B_DQS_P<3>

MEM_B_DQ<30>



MEM_B_A<8>MEM_B_DQ<19>

PP1V35_S3_MEM



MEM_B_RAS_L

MEM_B_ZQ<10>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L




PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<21>

MEM_B_DQS_N<2>


MEM_B_DQS_P<2>

MEM_B_DQ<23>



MEM_B_A<2>MEM_B_A<2>MEM_B_A<1>MEM_B_A<0>

MEM_B_DQS_N<1>

MEM_B_DQ<12>


MEM_B_DQ<3>

MEM_B_CKE<1>



MEM_B_RAS_L

MEM_B_ZQ<9>

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<6>



MEM_B_A<10>


MEM_B_BA<2>


MEM_B_CS_L<1>

MEM_B_DQS_P<1>

MEM_B_DQ<10>


MEM_B_A<11>

MEM_B_CS_L<1>



MEM_B_RAS_L

MEM_B_ZQ<8>

MEM_B_ODT<1>

MEM_B_CAS_L


MEM_RESET_L



MEM_B_A<6>

MEM_B_A<1>

PP1V35_S3_MEM

MEM_B_A<0>


MEM_B_A<10>


MEM_B_BA<2>


MEM_B_DQ<4>

MEM_B_DQS_N<0>

MEM_B_CKE<1>

MEM_B_DQS_P<0>


MEM_B_DQ<5>

MEM_B_DQ<1>MEM_B_A<2>

PP1V35_S3_MEM

<BRANCH>

<SCH_NUM>

<E4LABEL>

26 OF 118

26 OF 82

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7 25 78

22 23 24 25 26 46 70 78

7 25 78

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78

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7 25 26 27 78

7 26 27 78

22 25 26 71 75

7 26 27 78

7 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

21 23 24 25 26

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 25 26 27 78

7 25 26 27

78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

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7 26 27 78

7 25 78

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7 25 26 27 78 7 25 26 27 78

7 25 78

22 25 26 71 75

7 25 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

7 25 26 27 78

7 25 26 27

78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

21 23 24 25 26

7 25 26 27 78

22 23 24 25 26 46 70 78

22 25 26 71 75

7 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 25 26 27 78

7 25 26 27

78

7 25 26 27 78 7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 26 27

78

22 25 26 71 75

7 25 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 25 26 71 75

7 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

21 23 24 25 26

7 25 26 27 78

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7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 25 26 27 78

7 25 26 27

78

7 25 26 27 78

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22 23 24 25 26 46 70 78

22 25 26 71 75

7 26 27 78

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7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

22 23 24 25 26 46 70 78

7 25 26 27 78

7 25 26 27

78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78 7 25 26 27 78

7 25 26 27 78

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22 25 26 71 75

7 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 71 75 78

7 25 26 27

78

7 25 26 27 78 7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 25 26 71 75

7 26 27 78

7 26 27 78

7 25 26 27 78

7 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 46 70 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

7 25 26 27 78

22 23 24 25 26 46 70 78

w w w

. c h

i n a

f i x

. c o

m

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Place Source Cterm at neckdown at first DRAM

MEM Clock TerminationPlace RC end termination after last DRAM

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

7 25 26 78

81RP27301/32W 4X02015%

36

81RP27035%

361/32W 4X0201

81RP27021/32W 4X02015%

36

72RP27011/32W

365% 4X0201

54RP27014X02011/32W5%

36

72RP27024X02011/32W

365%

72RP27064X02011/32W

365%

2

1 C2704

CERM-X5R-14V20%0.47UF

201

2

1 C270220%4VCERM-X5R-1

0.47UF

201

2

1 C270020%4VCERM-X5R-1

0.47UF

201

2

1 C272320%4VCERM-X5R-1

0.47UF

201

72RP27285% 4X02011/32W

36

2

1 C272720%4V

0.47UF

CERM-X5R-1201

2

1 C272520%4VCERM-X5R-1

0.47UF

201

2

1 C270720%

CERM-X5R-1

0.47UF4V

201

2

1 C270320%0.47UF

CERM-X5R-14V

201

2

1 C27050.47UF

CERM-X5R-14V20%

201

2

1C2765

PLACE_NEAR=U2600.F8:3.2mm 25V

3.3PF

C0G0201

+/-0.25PF

21

R276630

1/20WMF

5%

201

2

1C2755

PLACE_NEAR=U2470.F8:3.2mm C0G0201

25V+/-0.25PF3.3PF

72RP27301/32W

364X02015%

21

R276530

1/20WMF

5%

201

21

R2756

5%

MF1/20W

30

201

21

R2755

5%

30

MF201

1/20W

21

C2766

6.3VCERM-X5R

0201

0.1UF

10%

21

C2756

6.3VCERM-X5R

0201

0.1UF

10%

21

C2751

6.3VCERM-X5R

0201

0.1UF

10%

21

C2761

6.3VCERM-X5R

0201

0.1UF

10%

21

R275030

1/20WMF

5%

201

72RP2724 364X02011/32W5%

21

R2751

5%

MF1/20W

30

201

2

1C2750

PLACE_NEAR=U2370.F8:3.2mm 25V

3.3PF

C0G0201

+/-0.25PF

21

R276030

MF1/20W5%

201

21

R276130

MF

5%

201

1/20W

2

1C2760

25V

3.3PF

C0G0201

+/-0.25PFPLACE_NEAR=U2500.F8:3.2mm

7 23 78

7 23 78

7 25 78

7 25 78

7 24 78

2

1 C273020%4VCERM-X5R-1

0.47UF

201

7 24 78

7 26 78

7 26 78

81RP27054X02011/32W5%

367 24 78

72RP27054X02015%

361/32W

7 23 24 78

72RP2725 364X02011/32W5%

7 25 26 78

63RP27251/32W5% 4X0201

36

2

1 C27280.47UF

CERM-X5R-14V20%

201

7 25 26 78

81RP27255% 1/32W 4X0201

367 25 26 78

63RP2705 365% 1/32W 4X0201

7 23 24 78

54RP2705 365% 1/32W 4X0201

7 23 24 78

54RP27254X0201

365% 1/32W

7 25 26 78

2

1 C272620%4VCERM-X5R-1

0.47UF

201

81RP27205% 1/32W 4X0201

36

7 26 78

7 25 26 78

7 25 26 78

7 25 26 78

7 25 78

7 25 78

7 25 26 78

7 25 26 78

7 25 26 78

7 26 78

7 26 78

7 25 26 78

7 25 26 78

7 25 26 78

7 25 78

7 25 26 78

7 25 26 78

7 25 26 78

7 25 26 78

7 23 24 78

7 23 24 78

7 23 78

7 23 78

7 23 24 78

7 25 26 78

7 23 24 78

7 23 24 78

7 23 24 78

7 23 24 78

7 23 24 78

54RP27241/32W 4X02015%

36

54RP27304X02015%

361/32W

63RP27201/32W

364X02015%

72RP27204X02011/32W

365%

72RP2722 361/32W 4X02015%

7 25 26 78

54RP27224X02011/32W

365%

63RP27265%

361/32W 4X0201

63RP27284X02011/32W

365%54RP27285%

361/32W 4X0201

72RP2726 365% 1/32W 4X0201

63RP27241/32W 4X0201

365%

63RP2722 365% 4X02011/32W

54RP27205%

361/32W 4X0201

81RP2728 365% 1/32W 4X0201

81RP27244X02015% 1/32W

367 25 26 78

81RP27225%

364X02011/32W

54RP2726 364X02011/32W5%

2

1 C272420%4V

0.47UF

CERM-X5R-1201

2

1 C27220.47UF4V20%

CERM-X5R-1201

2

1 C2720

CERM-X5R-1

0.47UF20%4V

201

63RP27065% 1/32W 4X0201

36

81RP2701 365% 4X02011/32W

63RP27014X02011/32W5%

36

54RP27041/32W5%

364X0201

72RP27041/32W5% 4X0201

36

7 25 26 78

54RP27074X02011/32W5%

36

54RP2702 365% 4X02011/32W

63RP27031/32W 4X02015%

36

81RP27075%

364X02011/32W

2

1 C27100.47UF

CERM-X5R-14V20%

201

2

1 C27080.47UF

CERM-X5R-14V20%

201

2

1 C27060.47UF

CERM-X5R-14V20%

201

72RP27075% 4X02011/32W

36

7 23 24 78

7 23 24 78

63RP27301/32W 4X02015%

36

7 23 24 78

7 24 78

7 23 24 78

7 23 24 78

7 23 24 78

7 23 24 78

7 23 78

7 23 24 78

7 23 24 78

7 23 24 78

81RP27264X02011/32W

365%

7 24 78

7 23 24 78

54RP2703 361/32W5% 4X0201

81RP27044X0201

361/32W5%

54RP2706 361/32W5% 4X0201

63RP27024X0201

365% 1/32W

63RP27041/32W 4X02015%

36

72RP27031/32W5% 4X0201

36

63RP27071/32W5% 4X0201

36

81RP2706 364X02011/32W5%


DDR3 Termination

MEM_B_CLK0_TERM_R

MEM_A_CLK1_TERM_RMEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CLK0_TERM_R



PPVTT_S0_DDR




MEM_A_CS_L<1>MEM_A_A<15>

MEM_A_ODT<1>MEM_A_A<10>

MEM_A_RAS_LMEM_A_CKE<0>


MEM_A_A<5>MEM_A_BA<1>

MEM_A_BA<2>MEM_A_WE_L

MEM_A_A<0>MEM_A_BA<0>


MEM_B_BA<1>MEM_B_A<0>

MEM_B_CKE<1>MEM_B_ODT<1>

MEM_B_CAS_LMEM_B_A<15>


PPVTT_S0_DDR


MEM_B_A<8>MEM_B_A<1>MEM_B_A<11>MEM_B_A<13>

MEM_A_CAS_LMEM_A_ODT<0>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_B_A<12>

MEM_B_CS_L<1>MEM_B_A<3>MEM_B_A<2>

MEM_B_WE_LMEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_RAS_LMEM_B_ODT<0>

MEM_B_CS_L<0>MEM_B_BA<2>

MEM_B_A<10>

MEM_A_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CLK1_TERM_RMEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_A_CLK_P<1>

<BRANCH>

<SCH_NUM>

<E4LABEL>

27 OF 118

27 OF 82

21 27 60 70 72

21 27 60 70 72

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

BI

BI

IN

IN

IN

IN

OUT

OUT

OUT

BI

BI

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

VCC

DO/IO1

GND THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P

DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1

PETN_1

PETP_2

RSENSE

PETN_2

PETP_3

PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR

GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD

GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO

PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO

PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1

PERN_1

PERP_2

PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK

TDO

TEST_EN

TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO

PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI

TMS

PERN_0

PERP_3

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SNK0 AC Coupling

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

Used for straps in host modedepends on the code in the flash.

Security strap setting is XORed with

If strap != bit then security is enabled?

(TBT_SPI_CS_L)

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:8 - GPIO_159 - GPIO_11

15 - PB_LSRX14 - PB_LSTX13 - GPIO_1012 - GPIO_12

10 - GPIO_1411 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_32 - GPIO_2

4 - GPIO_5

1 - GPIO_1

7 - PCIE_RST_3_N6 - PCIE_RST_2_N

DEBUG: For monitoring current/voltagebit in the flash, so the active-level

2

1R28905%

3.3K

201

1/20WMF

12 71

12 71

2

1R2825

201

1/20WMF

5%100

31

31 79

31 79

31

31 79

31 79

31 79

31 73 79

31 79

31 73 79

32

32 79

32 79

32

32 79

32 79

32 79

32 79

32 79

32 79

2

1R28305%

100K

201

1/20WMF

2

1R28315%

100K

201

1/20WMF

31 79

31 79

2

1R2893

201

1/20W

3.3K5%

MF

21C282910% 16VX5R-CERM0.1UF 0201

12 71 75

12 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

21C282816V10%

X5R-CERM0.1UF 0201

21C282710% 16VX5R-CERM0.1UF 0201

21C282616V10%

X5R-CERM0.1UF 0201

21C282510% 16VX5R-CERM0.1UF 0201

21C282416V10%0.1UF X5R-CERM

0201

21C282310% 16VX5R-CERM0.1UF 0201

21C282216V10%

X5R-CERM0.1UF 0201

2

1R2855

MF1/20W

201

1K1%

21C282110% 16VX5R-CERM0.1UF 0201

21C282010% 16VX5R-CERM0.1UF 0201

21C283010% 16VX5R-CERM

02010.1UF21C283110% 16VX5R-CERM0.1UF 0201

21C283210% 16VX5R-CERM0.1UF 0201

21C283310% 16VX5R-CERM0.1UF 0201

21C283410% 16V0.1UF X5R-CERM

0201

21C283510% 16VX5R-CERM0.1UF 0201

21C283610% 16VX5R-CERM0.1UF 0201

21C283710% 16VX5R-CERM0.1UF 0201

21C283810% 16VX5R-CERM0.1UF 0201

21C283910% 16V0.1UF X5R-CERM

0201

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

2

1C2890

402CERM6.3V10%1UF

BYPASS=U2890::2mm

12 71 75

12 71 75

31

31

32

32

20

32 79

32 79

32 79

32 79

32 79

32 79

32

20

20

20

20

31 79

31 79

31 79

31 79

31

28 30 31

31

28 31

28 32 33

32

28 32

28 29

20 41 42 43

11

19 76 21

R2895806

1%1/20WMF201

2

1R28965%1K

201MF1/20W

2

1R2899NO STUFF

201

10K1/20W

5%

MF

11 77

11 77

29

2

1R2815OMIT

NONE

0201NONENONE

NOSTUFF

2

1R2888

MF1/20W

201

10K5%

2

1R28875%1/20WMF201

10K

2

1R288610K

MF1/20W

201

5%

NO STUFF

2

1R2885

MF1/20W

201

10K5%

NO STUFF

2

1R28805%

201

1/20WMF

100K

20

28 33

14 20

2

1R2883100K

MF1/20W

201

5%

3

8

9

7

4

25

1

6U2890

CRITICALOMIT_TABLE

W25X40CLXIG

USON

4MBIT

28 30

28 31 32

2

1R2861

MF1/20W

201

10K5%

2

1R28635%10K

201

1/20WMF

2

1R2867NO STUFF

5%10K

201

1/20WMF

2

1R28625%10K

201

1/20WMF

2

1R2881100K

5%

201

1/20WMF

2

1R28295%

MF1/20W

201

10K

2

1R28845%

201

1/20WMF

100K

2

1R2882100K5%

201

1/20WMF

28 71

2

1R28785%

201

1/20WMF

100K

2

1R2879100K

MF1/20W

201

5% 2

1R2832100K

MF1/20W

201

5%

AB23

AA24

AA4

AB1

AB7

W8

R6

U6

W2

AA6

L8

AD1

U20

AB21

AD21

W20R4

AD17

AD13

AD9

AD5

AD19

AD15

AD11

AD7

P5

AA18

AB15

AA12

AB9

AB19

AA16

AB13

AA10

V3

M5

P7

N6

A22

B23

A20

B21

M1

D3

W24

U24

W22

U22

R24

N24

R22

N22

K3

K1

N8

J6

M3

A18

B19

A16

B17

K5

P1

L24

J24

L22

J22

G24

E24

G22

E22

L4

L2

W18

W16

AC24

AD23

M7

V7

T7

Y1

Y7

H5

L6

U2

F1

V1

AD3

AB3

W6

T3

T1

F3P3

R2N2

R8

Y3

AA2

T5

U8

AC2

J4

J2

A14

B15

A12

B13

A10

B11

A8

B9

U4

H3

H1

E6

D5

E8

D7

E10

D9

E12

D11

AB5

G4

G2

E14

D13

E16

D15

E18

D17

E20

D19

U2800FALCON RIDGE

CRITICAL

OMIT_TABLE

FCBGA21C2801 16V10%0.1UF 0201X5R-CERM

21C2800X5R-CERM16V

0.1UF 10% 0201

21C2802X5R-CERM16V

0.1UF 10% 0201

21C28030.1UF X5R-CERM

16V10% 0201

2

1R28923.3K1/20W

MF

5%

201

21C2804 16V0201X5R-CERM10%0.1UF


16V10% 0201


16V10% 0201


16V10% 0201

21C284010% 02010.1UF X5R-CERM16V

21C284102010.1UF X5R-CERM10% 16V

21C284202010.1UF X5R-CERM10% 16V

2

1R28915%3.3K

201

1/20WMF

21C284302010.1UF X5R-CERM10% 16V

21C284502010.1UF X5R-CERM10% 16V

21C28440201X5R-CERM0.1UF 10% 16V

21C28460201X5R-CERM0.1UF 16V10%

21C28470.1UF 10% 16V X5R-CERM 0201

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

Thunderbolt Host (1 of 2)SYNC_MASTER=T29_RR SYNC_DATE=01/14/2013

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<1>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

PP3V3_TBTLC

DP_TBTSRC_HPD

PP3V3_S4_TBT

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBTTBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

PP3V3_S4_TBT

TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBTROM_WP_L

TBTROM_HOLD_L


DP_TBTSNK0_AUXCH_N



PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>












PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>


DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_P<0>





DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_D2R_N<3>


PP3V3_TBTLC

SYSCLK_CLK25M_TBT

TBT_A_HV_ENTBT_B_DP_PWRDN

PP3V3_TBTLC

DP_TBTSNK0_ML_N<3>

PCIE_TBT_D2R_N<0>

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_N<0>

JTAG_TBT_TMSJTAG_TBT_TDI

TBT_A_HV_ENTBT_A_CIO_SELTBT_A_DP_PWRDN

TBT_A_LSRXTBT_A_LSTX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

TBT_A_D2R_P<1>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG1_BUFTBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

TBT_SPI_CS_L

TBT_TEST_PWR_GOODTBT_TEST_ENJTAG_TBT_TDOJTAG_TBT_TCK

TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSPTBT_MONOBSN

TBT_THERMDP

TBT_SPI_MOSI

TP_TBT_MONDC0TP_TBT_MONDC1

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>PCIE_TBT_R2D_P<2>

PCIE_TBT_R2D_N<1>PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

DP_TBTPB_AUXCH_C_P

TBT_B_LSRXTBT_B_LSTX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_P<1>

TBT_B_DP_PWRDNTBT_B_CIO_SELTBT_B_HV_EN

TBTDP_AUXIO_ENTBT_DDC_XBAR_EN_L

TBT_B_CONFIG2_RCTBT_B_CONFIG1_BUF

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_B_D2R_P<0>

TBT_GPIO7HDMITBTMUX_SEL_TBT

SMC_PME_S4_DARK_LTBT_PWR_EN

NC_DP_TBTSRC_ML_CP<0>




DP_TBTSRC_HPD

TBT_GPIO2

TBT_TMU_CLK_OUT

SYSCLK_CLK25M_TBT_R

TBT_DFT_STRAP_1TBT_ROM_SECURITY_XORTBT_DFT_STRAP_3

TP_TBT_PCIE_RESET0_L

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

TBT_RBIAS

PCIE_TBT_D2R_C_N<3>PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<2>

TBT_RSENSE

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<1>PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0>PCIE_TBT_D2R_C_N<0>


DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

NC_DP_TBTSRC_ML_CN<0>




TBT_EN_CIO_PWR_L

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

TBT_A_R2D_C_N<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_N<3>

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<0>

TBT_B_D2R_N<1>

TBT_B_R2D_C_N<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

PCIE_CLK100M_TBT_N

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_AUXCH_CPNC_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_N<1>DP_TBTSNK1_ML_P<1>

TBT_PCIE_RESET_L

TBT_BATLOW_L

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_N<2>

28 OF 82

28 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

19 20 28 29 70

19 20 28 29 70

28

28 29 30 46 70

28 29

28 71

28 33

28 31 32

28 29 30 46 70

28 30

28 32 33

28 31

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

19 20 28 29 70

28 30 31

28 32

19 20 28 29 70

28 75

73 75

73 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

79

79

79

48 82

79

73 75

73 75

73 75

73 75

73 75

73 75

73

73

73

73

28

76

73 75

73 75

73 75

73 75

73 75

73 75

73 75

73 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

28 75

73

73

73

73

73

73

73

28 75

28 75

w w w

. c h

i n a

f i x

. c o

m

NC

VOUT

GNDON

VIN

IN

OUTIN

IN

D

SYM_VER_3

SG

OUT

GND

SENSE

ENABLE SENSE_OUT

CT

VCC

VER 3

D

S G

G VER 5

S D

VCC1P0_CIO

VSS

VCC3P3_RDV_DECAP

VCC3P3_LC

VCC3P3

VCC1P0_RDV_DECAP

SVR_VCC1P0

VSS

SVR_AMON

SVR_IND

GND

VCC

SYM 2 OF 2

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



X425 Implementation: 3 X 20uF

1900 mA EDP

POC input to RR - 150 mA EDP

Isolated to reduce noise from SVR

25 mA EDP

J45 Implementation: 4 X 10uF

SVR input to RR - 1100 mA EDP

100 mA EDP

Internal switch not functional on RR.

11.5 mOhm Max

Max Current = 4A (85C)

2.4 W (Single-Port)

U2950TPS22920

Push-pull output

Part

Type

R(on)@ 1.05V

8 mOhm Typ

Load Switch

EDP: 1.25 A

1200 mA EDP700 mA EDP

3.1 W (Dual-Port)

Delay = 4.04ms nominal

TBT "POC" Power-up Reset

Vth = 2.508V nominal

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

1.05V TBT "CIO" Switch

Pull-up (S0) on PCH page

2

1C2906

6.3VX5R

1.0UF20%

0201-1

2

1C2911

6.3V

1.0UF20%

0201-1X5R2

1C2910

0201-1

1.0UF20%

6.3VX5R

21

L2920680NH-30%-3.6A-35MOHM

CRITICAL

SM

2

1C2922

0402-2X5R-CERM

4V20%

20UFK

A

D2920CRITICAL

SOD-323NSR1020MW2T1G

2

1R2945

MF201

100K5%1/20WC1

B1

A1

C2

B2

A2

D2

D1

U2940CSP

TPS22920

CRITICAL

2

1 C2940

0201-1X5R

20%6.3V

1.0UF

2

1 C2981

0201-1

6.3VX5R

1.0UF20%

2

1 C2980

0201-1

6.3VX5R

1.0UF20%

2

1C297020%

X5R0201-1

6.3V

1.0UF

28

2

1C296020%

1.0UF

X5R6.3V

0201-12

1C2961

0201-1

6.3VX5R

1.0UF20%

2

1C2953

0402-1CERM-X5R

10UF20%

6.3V2

1C295220%

0402-1CERM-X5R

6.3V

10UF

2

1C295120%

10UF

CERM-X5R6.3V

0402-12

1C295010UF

20%

0402-1CERM-X5R

6.3V2

1

XW2960SM

PLACE_NEAR=C2953.1:1mm

28

2

1C2995

X7R16V

0201

10%330PF

2

1R299124.9K1%

201MF1/20W

2

1 C2990

402

0.1UF10%

X5R25V

14

2

1R2995

1/20W

100K

201MF

5%

19 30 41 42

2

1R2990

201MF1/20W

100K5%

21

3

Q2995DMN32D2LFB4DFN1006H4-3

2

1C2991

0402

0.001UF50V10%

X7R-CERM

12

6

4

3

2

1

5

U2990

CRITICAL

USONTPS3895ADRY

2

1R29925%

MF201

100K1/20W

12

6Q2945DMN5L06VK-7SOT563

4

5

3

Q2945

SOT563

DMN5L06VK-7

2

1C2923NOSTUFF

20%20UF

4V

0402-2X5R-CERM

Y9

AC12

Y23

Y21

Y19

Y17

Y15

Y13

Y11

V9

V23

V21

AC10

V13

U16

U12

T9

T23

T21

T17

T13

R20

R16

AB17

R12

P9

P23

P21

P13

N20

N16

N12

M9

M23

AB11

M21

M13

L20

L12

K23

K21

K13

J20

J16

J14AA8

H23

H21

G8

G6

G20

F9

F7

F5

F23

F21

AA22

F19

F17

F15

F13

F11

E4

D23

D21

C8

C6

AA20

C4

C24

C22

C20

C2

C18

C16

C14

C12

C10

AA14

B7

B1

AC8

AC6

AC4

AC22

AC20

AC18

AC16

AC14

A24

A2

W10

R18

N18

L18

H7

H17

H15

H13

Y5

W4

V5

N4

H11

E2

D1

K17

K15

J18

H9

H19

G18

G16

W14

G14

W12

V17

V15

U18

T19

P19

M19

L16

K7

K19

G12

G10

R10

P15

P11

N14

N10

M11

L10

K11

V11

U14

U10

T15

T11

R14

J12

J10

V19

P17

M17

M15

L14

K9

J8

B3

A6

A4

B5

U2800FALCON RIDGE

CRITICAL

OMIT_TABLE

FCBGA

2

1C290320%

X5R6.3V

0201-1

1.0UF

2

1C292020%4V

X5R-CERM0402-2

20UF

2

1C2921

X5R-CERM

20UF

0402-2

4V20%

2

1C2904

X5R6.3V20%

1.0UF

0201-12

1C2905

6.3VX5R

1.0UF20%

0201-12

1C2900

X5R0201-1

6.3V

1.0UF20%

2

1C2901

0201-1

20%6.3VX5R

1.0UF

2

1C2902

X5R

20%

0201-1

1.0UF6.3V 2

1C2932

0201-1

6.3VX5R

1.0UF20%

2

1C2931

0201-1

6.3VX5R

20%1.0UF

2

1C2930

0201-1

6.3VX5R

1.0UF20%

SYNC_DATE=01/14/2013SYNC_MASTER=T29_RR

Thunderbolt Host (2 of 2)

PP3V3_TBTLC

TBT_POC_RESET_L TBTPOCRST_MR_L

SMC_DELAYED_PWRGD

PP3V3_S4_TBT

TBTPOCRST_SENSE TBTPOCRST_CT

TBT_PWR_ON_POC_RST_L

PP1V05_TBT

TBT_EN_CIO_PWR

TBT_EN_CIO_PWR_LTBT_PWR_REQ_L

PP3V3_S0

PP3V3_S0


P1V05TBT_SW

DIDT=TRUESWITCH_NODE=TRUE


VOLTAGE=1.05VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMPP1V05_TBTRDV


VOLTAGE=3.3VMIN_NECK_WIDTH=0.15 MM

PP3V3_TBTLC

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMPP3V3_TBTRDV

MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

PP3V3_S4_TBT_F

PP3V3_S4_TBT


PP1V05_TBTCIO

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.50 MMPP1V05_TBT

VOLTAGE=1.05V

<BRANCH>

<SCH_NUM>

<E4LABEL>

29 OF 118

29 OF 82

19 20 28 29 70

28 29 30 46 70

29

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

19 20 28 29 70 28 29 30 46 70

29

w w w

. c h

i n a

f i x

. c o

m

IN

S

G

DNC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND GND

NC

SNS1

SNS2

IN

SYM_VER_2

G S

D

OUT

D

SYM_VER_3

SG

IN

VER 3

D

S G

VER 3

D

S G

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Max Vgs: 10V

Vout = 1.6V * (1 + Ra / Rb)

Freq = 480KHz

8-13V Input

Thunderbolt 15V Boost Regulator

NOTE: MIRROR C3096 and C3098

BATLOW# Isolation

(NONE)

(NONE)

- =PP15V_TBT_REG (15V Boost Output)

Pull-up on RR page

Rds(on): 46mOhm @ 4.5V Vgs

Voltage not specified here,

BOM options provided by this page:

Page NotesPower aliases required by this page:

Signal aliases required by this page:

Second FET needed for

<R2>

for 2S.Changes required

UVLO = 4.55V (falling), 4.95 (rising)UVLO(rising) = UVLO(falling) + (2uA * R1)UVLO(falling) = 1.22 * (R1 + R2) / R2

GND inside package,

<Rb>

Vgs(th): -1.4VVgs(max): +/-12V

SI8409DB:Vds(max): -30V

<R1>

- =PPVIN_SW_TBTBST (8-13V Boost Input)

Id(max): 3.7A @ 70C

add property on another page.

no XW necessary.

dual-port designs.

Max Current = 2A?

SGND shorted to

NOTE: Change R3097 to XW3095 at PVT

Vout = 15.47V<Ra>

2

1R3081330K1/16WMF-LF

402

5%

2

1R3080470K

MF-LF1/16W

402

5%

2

1 C3080

25V10%0.1UF

X5R402

2

1R3092

402

73.2K1%

MF-LF1/16W

2

1R3087

1/16WMF-LF

330K

402

5%

2

1R3094

402MF-LF

26.7K1%

1/16W2

1 C30940.33UF6.3V

402

10%

CERM-X5R

2

1R3088330K

MF-LF1/16W

402

5%

19 29 41 42

2

1 C3089100PF

CERM50V

402

5%

NO STUFF

2

1R30961%

MF-LF

15.8K

402

1/16W

2

1 C3095

CASE-D3L

20%25VPOLY-TANT

33UF-0.06OHM

2

1C3096

25V20%

X5R-CERM0603

10UF

PLACE_SIDE=BOTTOM

2

1 C309710%25V

10UF

NO STUFF

1206X7R-CERM

2

1 C30875%50V

68PF

0402CERM2

1C30852.2UF

20%10V

402X5R-CERM

4

1

32

Q3080SI8409DB

CRITICAL

BGA

2

1R30931%

49.9K

MF-LF1/16W

402

2

1R30911%

200K

MF-LF1/16W

402

2

1C3090

0603

20%25V

10UF

X5R-CERM 2

1C309110UF

X5R-CERM25V

0603

20%

21

L3095

PIMB063T-SM

3.3UH-6.5A

CRITICAL

2

1 C30885%50V

0402

10PF

CERM

27

30

34

38

21

2098

32

37

24

23

4

3

6

33

36

35

10

2

1

28

17

16

15

14

13

12

31

25

U3090

CRITICAL

QFNLT3957

2

1R30951%

MF-LF402

137K1/16W

2

1R3089

0201

05%

MF1/20W

2

1 C30990.001UF

X7R-CERM

10%50V

0402

2

1 C3093

0402X7R-CERM

10%50V

0.0033UF

2

1C309220%10V

X5R-CERM402

2.2UF

2

1 C3086

X5R-CERM402

10V

2.2UF20%

3

21

D3095PDS540XFPWRDI5

CRITICAL

28 31

21

3Q3005DFN1006H4-3

DMN32D2LFB4

28 30

21

3

Q3000DMN32D2LFB4

DFN1006H4-3

12 41 43

2

1C309820%

10UF25V

0603X5R-CERM

PLACE_SIDE=TOP

21

R3097

1/16W

402MF-LF

10

5%

45


1 2


SYNC_MASTER=CLEAN_X305 SYNC_DATE=06/24/2014

Thunderbolt Mobile Support

MIN_NECK_WIDTH=0.25 mmVOLTAGE=0V

MIN_LINE_WIDTH=0.5 mmGND_TBTBST_SGND

TBTBST_SNS2

TBTBST_VSNS

TBTBST_RT

PPBUS_G3H

PM_BATLOW_LTBT_BATLOW_LMAKE_BASE=TRUE

TBTBST_PWREN_L

TBTBST_PWREN_DIV_L

TBTBST_SS

TBT_A_HV_EN

TBT_BATLOW_L

PP3V3_S4_TBT

TBTBST_SNS1


TBTBST_BOOSTMIN_LINE_WIDTH=0.5 mm


PPVIN_SW_TBTBSTMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

TBTBST_FBX

PP15V_TBT

SMC_DELAYED_PWRGD

TBTBST_EN_UVLO

TBTBST_SHDN_DIV

TBTBST_VC

TBTBST_INTVCC

TBTBST_VC_RC

30 OF 82

30 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

45 56 57 63 65 70 72

28 30

33

28 29 46 70

70

31 32 70

w w w

. c h

i n a

f i x

. c o

m

IN

IN

OUT

IN

IN

V3P3

ISET_V3P3

OUT

THRMGND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

IN

IN

IN

OUT

BI

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

BI

IN

IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+

DPMLO-

HPD

THMPADGND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENATB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN

IN

IN

ML_LANE1P

GND1

ML_LANE0N

GND0

ML_LANE0P

ML_LANE1N

ML_LANE2N

RETURN

HPD

CONFIG1

CONFIG2

GND2

ML_LANE3P

ML_LANE3N

GND4

DP_PWR

AUX_CHP

AUX_CHN

ML_LANE2P

GND3

SHIELD PINS

SHIELD PINS

PORT B

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




(0-18.9V)

For 12V systems:

wake from Thunderbolt devices.

DP Dir

514-0876

down HPD input with

to 100K (DPv1.1a).greater than or equal

TBT: Unused

<RV3P3>

V3P3 must be S4 to support

IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

Single-fault protection

Low: 0 - 0.8V

ILIM = 40000 / RISET

Sink HPD range:

(Both C’s)

(Both C’s)(Both C’s)

TBT Dir

(0-18.9V)

TBT: TX_0

DP Dir

(Both C’s)

TBT: LSX_R2P/P2R (P/N)

DP Source must pull

High: 2.0 - 5.0V

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1

(IPU)

(IPD)

(IPD)

(IPU) below

requires two R’s per HV

Single R on ISET_V3P3 OK.

12V: See

<RHVS0><RHVS3>

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum) Nominal Min Max

TBT: TX_1

TBT: RX_0

TBT: RX_1

IV3P3 1100mA 1030mA 1200mA

3.3V/HV Power MUX

15.75V Max

Nominal Min Max

ISET_Sx with CD3210.

Thunderbolt Connector A

TBT Dir

470k R’s for ESD protectionon AC-coupled signals.

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)

2

1C3200

50V10%

0402X7R-CERM

0.01UF

28 79

28 79

2

1 C3202

0201

16V10%

X5R-CERM

0.01UF

21

R3201

1/20WMF201

5%

12

2

1 C3201

0402

50V10%

X7R-CERM

0.01UF

2

1R3294

NO_XNET_CONNECTION=TRUE

GND_VOID=TRUE

1/20W5%

201MF

1K

2

1R3295


GND_VOID=TRUE

1/20W5%

201MF

1K

2

1R32415%100K1/20W

201MF

2

1 C3286

6.3V20%

0402CERM-X5R

10UF

2

1C3285

X5R-CERM16V10%

0201

0.1UF

2

1 C3281

16V10%

0201X5R-CERM

0.1UF

2

1C328020%

6.3V

603X5R-CERM-1

22UF

2

1C3287100UF

6.3V20%

CASE-B2-SMPOLY-TANT

CRITICAL

2

1R3252

1/20WMF

5%

201

1M

2

1R3251

201

1/20W5%

MF

1M

2

1C3294

X7R

330PF

0201

10%16V 2

1 C3295

X7R

330PF

0201

10%16V

21

L3200CRITICAL

FERR-120-OHM-3A

0603

28

2

1 C32100.1UF25V10%

402X5R

2

1R3270470K

MF201

5%1/20W

GND_VOID=TRUE

2

1R3271GND_VOID=TRUE

470K

MF201

5%1/20W

21C32710.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

21C32700.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

28 79

28 79

21C32720.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

21C32730.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

2

1R3273470K

MF201

5%1/20W

GND_VOID=TRUE

2

1R3272470K

MF201

5%1/20W

GND_VOID=TRUE

7

6

18

20

19

21

17

14

12

8

9

1011

15

13321

416

5

U3210QFN

CRITICAL

CD3211A1RGP

28 30

32 65 66 67

32 45 67

2

1R3212

1/20W1%

201MF

36.5K

2

1 C3211

25V10%

402X5R

0.1UF

2

1C32200.1UF

0201

10%16V

X5R-CERM

28

33

33

28

28

28 73 79

28 73 79

28 79

28 79

21C323202010.22UF 6.3V20%

X5R21C3233

0.22UF 6.3V20%0201X5R

28 79

28 79

21C32300.1UF 10% 16V

X5R-CERM020121C3231

X5R-CERM0201

0.1UF 10% 16V

28 79

28 79

21C32780.22UF 6.3V20%

0201X5R21C3279

0.22UF 6.3V20%0201X5R

28 79

28 79

2

1R3211

1/20W1%

201MF

22.6K

TBTHV:P15V

2

1R3210

1/20W1%

201MF

22.6K

TBTHV:P15V

2

1R321422.6K

MF201

1%1/20W

TBTHV:P15V

2

1R3213TBTHV:P15V

22.6K

MF201

1%1/20W

2

1C3215

25V10%

0603X5R-CERM

4.7UF

2

1C32050.01UF

X5R-CERM0201

10%25V

GND_VOID=TRUE

2

1C32060.01UF

GND_VOID=TRUE

25V

0201X5R-CERM

10%

28

21C32744V

GND_VOID=TRUE

201CERM-X5R-10.47UF 20%

21C32752014V

GND_VOID=TRUE

CERM-X5R-10.47UF 20%

3

25

8

7 15

14

13

12 17

219

19

20

6

11

10

4

5

16 18

22

23

24

2

1

U3220

SIGNAL_MODEL=TBT_MUX

CBTL05024HVQFN24-COMBO

CRITICAL

28 32

28

28

2

1R3279

1/20W5%

201MF

470K

2

1R3278470K1/20W5%

201MF

21C32772014V0.47UF 20%

CERM-X5R-1

GND_VOID=TRUE

21C32762014V0.47UF 20%

GND_VOID=TRUE

CERM-X5R-1

S24

S22

S21

S20

S19

S18

S17

S16

S15

S14

S13

S12

B19

B10

B12

B15

B17

B9

B11

B3

B5

B2

B14 B13

B8 B7

B1

B20

B6

B4

B16

B18

J3200F-RT-TH

CRITICAL

MDP-J44

TBTHV:P12V118S0145 R3211,R32142 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

TBTHV:P12VR3210,R32132118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

Thunderbolt Connector ASYNC_MASTER=CLEAN_X305 SYNC_DATE=06/24/2014

TBT_A_D2R_C_N<1> TBT_A_CIO_SELVOLTAGE=15V

MIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM

PP3V3RHV_S4_TBTAPWR

TBTAPWRSW_ISET_V3P3

TBT_A_HV_EN

S4_PWR_EN

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

PP15V_TBTTBT_A_D2R_P<1>

TBT_A_D2R_C_P<1>

TBT_A_D2R_N<1>

DP_TBTPA_AUXCH_C_NDP_TBTPA_AUXCH_P

TBTAPWRSW_ISET_S3_RDP_TBTPA_HPD

TBT_A_LSRXTBT_A_LSTX

DP_TBTPA_DDC_DATA

TBT_A_CONFIG1_BUF

TBT_A_D2R1_AUXDDC_NTBT_A_D2R1_AUXDDC_P

TBTDP_AUXIO_ENTBT_A_DP_PWRDN

DP_TBTPA_AUXCH_N

DP_TBTPA_ML_N<1>DP_TBTPA_ML_P<1>

TBT_A_HPD

DP_A_LSX_ML_N<1>DP_A_LSX_ML_P<1>

TBT_A_CONFIG1_RC

PP3V3_S4_TBTAPWR

TBT_A_R2D_C_N<0>

TBT_A_R2D_C_N<1>TBT_A_R2D_C_P<1>

TBT_A_R2D_C_P<0>

DP_TBTPA_ML_C_N<3>DP_TBTPA_ML_C_P<3>

TBT_A_D2R_N<0>TBT_A_D2R_P<0>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<1>DP_TBTPA_ML_C_P<1>


TBTACONN_20_RC

VOLTAGE=18V

DP_TBTPA_DDC_CLK

PP3V3_S4_TBTAPWRMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

VOLTAGE=3.3V

TBTAPWRSW_ISET_S0_R

TBT_A_D2R_C_N<0>TBT_A_D2R_C_P<0>

TBT_A_R2D_N<1>

DP_A_LSX_ML_N<1>

TBT_A_R2D_P<0>

TBTACONN_1_CMIN_LINE_WIDTH=0.38 MM


TBT_A_R2D_N<0>

TBTACONN_7_CMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

MIN_NECK_WIDTH=0.20 MMVOLTAGE=15V

MIN_LINE_WIDTH=0.38 MMPP3V3RHV_S4_TBTAPWR_F

TBT_A_D2R1_AUXDDC_N

PP3V3_S5

PM_SLP_S3_R_L

DP_A_LSX_ML_P<1>

TBT_A_R2D_P<1>

TBT_A_D2R1_AUXDDC_P

DP_TBTPA_ML_P<3>

TBT_A_CONFIG1_RC

TBT_A_CONFIG2_RC

DP_TBTPA_ML_N<3>

TBT_A_HPD

<BRANCH>

<SCH_NUM>

<E4LABEL>

32 OF 118

31 OF 82

79 30 32 70

79

79 31 79

31 79

79

79

79

31

31 79

31 79

31

31

31

79

79

79

31 79

79

79

31 79

12 14 15 17 18 19 21 32 34 61 64 66

67 70 71 72 82

31 79

79

31 79

79

31

79

31

w w w

. c h

i n a

f i x

. c o

m

IN

IN

OUT

IN

IN

V3P3

ISET_V3P3

OUT

THRMGND

HV_EN

S0

EN

ISET_S0

V3P3OUT

ISET_S3

ENHVU

VHV

FAULTZ

PAD

IN

IN

IN

OUT

BI

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

BI

IN

IN

OUT

TB+

LSRX

AUX+

CA_DET

DPMLO+

DPMLO-

HPD

THMPADGND

DP+

LSTX

DP-

HPDOUT

AUX-

VDD

DP_PD

AUXIO_EN

TB_ENATB-

AUXIO+

AUXIO-

CA_DETOUT

DDC_CLK

DDC_DAT

IN

IN

IN

ML_LANE1P

GND3GND4

HPD

CONFIG2

GND2

RETURNAUX_CHN

CONFIG1

ML_LANE3N

ML_LANE3P

AUX_CHP

GND0

DP_PWR

ML_LANE0P

GND1

ML_LANE0N

ML_LANE1N

ML_LANE2N

ML_LANE2P

PORT A

SHIELD PINS

SHIELD PINS

Apple Inc.


124578

B

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6 3




to 100K (DPv1.1a).

For 12V systems:

V3P3 must be S4 to support

DP Source must pull

TBT: RX_1

down HPD input with

Thunderbolt Connector B

TBT: Unused

TBT: RX_0

Nominal Min MaxIHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

<RHVS3> <RHVS0>Single R on ISET_V3P3 OK.

requires two R’s per HVISET_Sx with CD3210.

ILIM = 40000 / RISET

below

Single-fault protection

3.3V/HV Power MUX

(IPU)

(IPD)

(IPD)

(IPU)

TBT: RX_1

TBT: LSX_A_R2P/P2R (P/N)

Sink HPD range:High: 2.0 - 5.0VLow: 0 - 0.8V

greater than or equal

TBT: LSX_R2P/P2R (P/N)

(Both C’s)

DP Dir

(0-18.9V)

TBT: TX_0

(0-18.9V)

TBT Dir

(Both C’s)

470k R’s for ESD protectionon AC-coupled signals.

(Both C’s)TBT Dir DP Dir

(Both C’s)

15.75V Max

wake from Thunderbolt devices.

Nominal Min Max

<RV3P3>

514-0876 TBT: TX_1

IV3P3 1100mA 1030mA 1200mAIHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

12V: See

2

1C3300

50V10%

0402X7R-CERM

0.01UF

28 79

28 79

2

1 C3302

16V10%

0201X5R-CERM

0.01UF

21

R3301

MF

5%

12

201

1/20W

2

1 C3301

50V10%

0402X7R-CERM

0.01UF

2

1R3394


GND_VOID=TRUE

1/20W5%

201MF

1K

2

1R3395


GND_VOID=TRUE

1/20W5%

201MF

1K

2

1R3341100K1/20W5%

201MF

2

1 C3386

6.3V20%

0402CERM-X5R

10UF

2

1C3385

16V10%

0201X5R-CERM

0.1UF

2

1 C3381

16V10%

0201

0.1UF

X5R-CERM2

1C338020%

22UF

603

6.3VX5R-CERM-12

1C3387100UF

CRITICAL

6.3V20%

CASE-B2-SMPOLY-TANT

2

1R3352

1/20W5%

201MF

1M

2

1R3351

1/20W5%

201MF

1M

2

1C3394

X7R

330PF

0201

10%16V 2

1 C3395

X7R

330PF

0201

10%16V

21

L3300

0603

FERR-120-OHM-3A

CRITICAL

28

2

1 C3310

25V10%

402X5R

0.1UF

2

1R3370470K

MF201

5%1/20W

GND_VOID=TRUE

2

1R3371470K

MF201

5%1/20W

GND_VOID=TRUE

21C33710.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

21C33700.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

28 79

28 79

21C33720.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

21C33730.22UF X5R 0201

20% 6.3V

GND_VOID=TRUE

2

1R3373470K

MF201

5%1/20W

GND_VOID=TRUE

2

1R3372470K

MF201

5%1/20W

GND_VOID=TRUE

7

6

18

20

19

21

17

14

12

8

9

1011

15

13321

416

5

U3310CRITICAL

QFNCD3211A1RGP

28 33

31 65 66 67

31 45 67

2

1R331236.5K1%1/20WMF201

2

1 C3311

25V10%

402X5R

0.1UF

2

1C33200.1UF

0201

10%16V

X5R-CERM

28

33

33

28

28

28 79

28 79

28 79

28 79

21C3332X5R 020120% 6.3V0.22UF21C3333X5R 020120% 6.3V0.22UF

28 79

28 79

21C33300201

X5R-CERM16V10%0.1UF

21C333116V10%

X5R-CERM0.1UF0201

28 79

28 79

21C33780.22UF 6.3V20%

0201X5R21C3379

0.22UF 6.3V20%0201X5R

28 79

28 79

2

1R3311TBTHV:P15V

1/20W

201MF

22.6K1%

2

1R3310

1/20W1%

201MF

TBTHV:P15V

22.6K

2

1R3314TBTHV:P15V

22.6K

MF201

1%1/20W

2

1R3313TBTHV:P15V

22.6K

MF201

1%1/20W

2

1C3315

25V10%

0603X5R-CERM

4.7UF

2

1C33050.01UF

X5R-CERM0201

10%25V

GND_VOID=TRUE

2

1C3306GND_VOID=TRUE

25V10%

0201X5R-CERM

0.01UF

28

21C33744V

GND_VOID=TRUE

201CERM-X5R-10.47UF 20%

21C33752014V

GND_VOID=TRUE

CERM-X5R-10.47UF 20%

3

25

8

7 15

14

13

12 17

219

19

20

6

11

10

4

5

16 18

22

23

24

2

1

U3320

SIGNAL_MODEL=TBT_MUX

CBTL05024

CRITICAL

HVQFN24-COMBO

28 31

28

28

2

1R3379

1/20W5%

201MF

470K

2

1R3378

1/20W5%

201MF

470K

21C3376

GND_VOID=TRUE

2014V0.47UF 20%CERM-X5R-1

21C3377

GND_VOID=TRUE

2014V0.47UF 20%CERM-X5R-1

S9

S8

S7

S6

S5

S4

S3

S23

S2

S11

S10

S1

A19

A10

A12

A15

A17

A9

A11

A3

A5

A2

A14 A13

A8 A7

A1

A20

A6

A4

A16

A18

J3200MDP-J44

CRITICAL

F-RT-TH

118S0145 TBTHV:P12VR3311,R33142 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

TBTHV:P12VR3310,R33132118S0145 RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF

SYNC_DATE=06/24/2014SYNC_MASTER=CLEAN_X305

Thunderbolt Connector B

TBTBPWRSW_ISET_S0

DP_B_LSX_ML_P<1>

TBT_B_D2R_C_N<0>

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R_C_P<0>

DP_TBTPB_ML_N<3>DP_TBTPB_ML_P<3>

TBT_B_D2R1_AUXDDC_P

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMTBTBCONN_1_C

VOLTAGE=18.9V

PP3V3RHV_S4_TBTBPWR_F

VOLTAGE=15V


TBT_B_R2D_P<0>

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MM

VOLTAGE=18.9V

TBTBCONN_7_C

TBT_B_R2D_N<0>

DP_B_LSX_ML_N<1>

TBT_B_R2D_N<1>TBT_B_R2D_P<1>

TBT_B_D2R_C_N<1>TBT_B_D2R_C_P<1>

TBT_B_D2R_P<1>TBT_B_D2R_N<1>

DP_TBTPB_ML_C_P<1>DP_TBTPB_ML_C_N<1>

TBT_B_D2R_P<0>TBT_B_D2R_N<0>

DP_TBTPB_ML_C_P<3>DP_TBTPB_ML_C_N<3>

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_P<1>TBT_B_R2D_C_N<1>

TBT_B_R2D_C_N<0>

TBT_B_CONFIG2_RC

PP3V3_S4_TBTBPWR

DP_TBTPB_AUXCH_P

TBT_B_CONFIG1_RC

DP_B_LSX_ML_P<1>DP_B_LSX_ML_N<1>

TBT_B_HPD

DP_TBTPB_ML_P<1>DP_TBTPB_ML_N<1>

TBT_B_DP_PWRDNTBTDP_AUXIO_ENTBT_B_CIO_SEL

TBT_B_D2R1_AUXDDC_PTBT_B_D2R1_AUXDDC_N

TBT_B_CONFIG1_BUF

DP_TBTPB_DDC_CLKDP_TBTPB_DDC_DATA

TBT_B_LSTXTBT_B_LSRX

DP_TBTPB_HPDTBTBPWRSW_ISET_S0_RTBTBPWRSW_ISET_S3_R

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMTBTBCONN_20_RC

VOLTAGE=18V

DP_TBTPB_AUXCH_C_NDP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_N


VOLTAGE=3.3V

PP3V3_S4_TBTBPWRMIN_NECK_WIDTH=0.20 MM

S4_PWR_EN

VOLTAGE=15V

PP3V3RHV_S4_TBTBPWRMIN_LINE_WIDTH=0.38 MMMIN_NECK_WIDTH=0.20 MM

TBTBPWRSW_ISET_V3P3

PP3V3_S5

TBT_B_HV_EN

TBTBPWRSW_ISET_S3

PP15V_TBT

PM_SLP_S3_R_L

TBT_B_CONFIG1_RC

TBT_B_HPD

<BRANCH>

<SCH_NUM>

<E4LABEL>

33 OF 118

32 OF 82

32 79

79

32 79

79

79

79

32 79

79

79

32 79

79

79

79

79

32

79

32

32 79

32 79

32

79

79

32 79

32 79

79

32

12 14 15 17 18 19 21 31 34 61 64 66

67 70 71 72 82

30 31 70

32

32

w w w

. c h

i n a

f i x

. c o

m

BI

OUT

BI

OUT

SBI

INB+

VCC

OUTA1+

OUTA1-

OUTA0+

OUTA0-

SAO

OUTB1+

OUTB1-

OUTB0-

OUTB0+

SBO

ENA

INA-

INA+

SAI

INB-

GND

THRM

ENB

PAD

BI

IN

BI

IN

IN

OUT

IN

VER 3

D

SG

VER 3

D

SG

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DDC CrossbarOn single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

NEVER SEND AUXCH THROUGH CROSSBAR!

Only necessary on dual-port hosts.

SAI/SBI = 1: INA == OUTA0, INB == OUTB0SAI/SBI = 0: INA == OUTB0, INB == OUTA0

to indicate active display interface.2.2k pull-ups are required by PCH

DP++ spec violation, should remove!

Second TBT Port HV Boost Enable

32

32

31

31

13

21

1112

1514

6

7

8

9

20

19

18

17

3

4

1

2

5

10

16

U3400QFN

CRITICAL

TS3DS10224

SIGNAL_MODEL=DDC_XBAR_MUX

12 71

12 71

12 71

12 71

2

1 C3480

402CERM10V20%0.1UF

2

1R3451

201MF

1%1/20W

2.2K

2

1R34522.2K

201MF1/20W1%

2

1R3453

MF1/20W

1%2.2K

201

2

1R3454

201MF

1%2.2K1/20W

28

30

28 32

2

1R3400100K

MF-LF402

1%1/16W

45

3Q3410

SOT563

DMN5L06VK-7

12

6Q3410

SOT563

DMN5L06VK-7

DDC CrossbarSYNC_DATE=11/16/2012SYNC_MASTER=J15_REFERENCE

TBT_B_HV_EN

TBTBST_PWREN_L

TBT_DDC_XBAR_EN_L

TBT_DDC_XBAR_EN

DP_TBTPB_DDC_DATADP_TBTPB_DDC_CLK

DP_TBTSNK0_DDC_CLK

DP_TBTPA_DDC_CLKDP_TBTPA_DDC_DATA

DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_DATADP_TBTSNK1_DDC_CLK

PP3V3_S0

<BRANCH>

<SCH_NUM>

<E4LABEL>

34 OF 118

33 OF 82

11 12 13 14 15 17 19 20 29 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

w w w

. c h

i n a

f i x

. c o

m

IN

IN

IN

IN

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

SYM_VER_2

G S

D

BI

BI

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

IN

NC

OUT

GND

VOUT

ON

VIN

IN

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE

RESET*

+-

PAD

(OD)

DLY

VREF

GND

VDD

D

SON

CAP

SYM_VER-1

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6 3




AIRPORT

3.3V SIL WLAN Switch

18.5 mOhm Typ

SLG5AP1443V

CURRENT SENSE

25.8 mOhm Max

17 mOhm Typ19 mOhm Max

Load Switch

Part

Type

R(on)

Max Current = 2A (85C)

R(on)

Type Load Switch

3.3V TI WLAN SwitchTPS22924CPart

@ 2.5V

@ 2.5V

1A PEAK

155S0367

BLUETOOTH

L USB_BT_WAKE

SEL OUTPUT

Delay = 130 ms +/- 20%

Supervisor & CLKREQ # Isolation

516S1016

H USB_BT

NOTE: Stuff non-zero value for R3557 to see which end is driving low

21

L3504FERR-120-OHM-3A

0603

2

1C3521

PLACE_NEAR=J3501.1:2.54MM

402

20%10V

0.1uF

CERM2

1C3522


0.1uF

CERM402

10V20%

13 77

13 77

11 77

11 77

21

C3531

16V10%0.1UF

0402PLACE_NEAR=J3501.5:2.54MM

X7R-CERM

21

C3530


16V10%0.1UF

0402 X7R-CERM

12 36 72 77

2

1 C35320.01UF

X7R-CERM0402

16V10%

20

11 18

2

1 C35400.1uF10V20%

402CERM2

1R3554232K1%1/16WMF-LF402

2

1R3555

MF-LF

100K1%

402

1/16W

2

1R3553100K

MF-LF402

1%1/16W

41 42 72

2

1 C3570NOSTUFF

0201

16V

0.1UF10%

X5R-CERM

21

L3570OMIT_TABLE

02010.6NH+/-0.1NH-0.85A

2

1 C3571NOSTUFF

0201

16V10%0.1UF

X5R-CERM

2

1 C3573NOSTUFF

X5R-CERM0201

16V

0.1UF10%

21

L3571

0.6NH+/-0.1NH-0.85A

OMIT_TABLE0201

2

1 C35720.1UF

X5R-CERM

NOSTUFF

16V10%

0201

2

1 C3575NOSTUFF

0.1UF

X5R-CERM16V10%

0201

21

L3573OMIT_TABLE

02010.6NH+/-0.1NH-0.85A

2

1 C3574

0201X5R-CERM16V

0.1UF10% NOSTUFF

2

1 C3577NOSTUFF

0201

16V10%

X5R-CERM

0.1UF

21

L3574

0.6NH+/-0.1NH-0.85A

OMIT_TABLE0201

2

1 C3576

X5R-CERM

0.1UFNOSTUFF

0201

10%16V

13 77

13 77

34 47

34 47

2 1

L3505

FERR-120-OHM-1.5A


0402-LF

21

3Q3510NO_XNET_CONNECTION=TRUE

DMN32D2LFB4DFN1006H4-3

13 76

13 76

2

1R3512

1/20W1%

MF201

15K

1

2

9

10 8

5

4

3

7

6

U3510PI3USB102EZLE

TQFN

SIGNAL_MODEL=MOJO_MUX_USBONLY

CRITICAL

12 21 38 41 67 69 72

2

1 C3510

6.3V10%

0201

0.1UF

CERM-X5R

39 41 43 72

B1

A1

B2

A2

C2

C1

U3550

CRITICAL

TPS22924CSP

WLAN_SW:TI

34 41 67

1

9

2

4

8

3

7

5

6

U3540

CRITICAL

TDFNSLG4AP041V

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

21

20

19

J3501SSD-X29-D1

F-RT-SM

CRITICAL

2

1R35565%

MF1/20W

0201

APCLKRQ:ISOL

0

21

R35571K

1/20WMF

5%

201

APCLKRQ:BIDIR

2

1C355510%

X7R10V

201

4700PF

WLAN_SW:SIL

1

52

8

37

U3551

WLAN_SW:SIL

TDFNSLG5AP1443V

CRITICAL

4

32

1

L3501TAM0605

CRITICAL


90-OHM-0.1A-0.7-2GHZ

4117S0201 RES, 0OHM, 0201 L3570,L3571,L3573,L3574

X87 CONNECTOR


PCIE_AP_R2D_C_PPCIE_AP_R2D_PI_P

PCIE_WAKE_L

AP_RESET_CONN_L

AP_CLKREQ_Q_L

WIFI_EVENT_L

AP_CLKREQ_L

PCIE_AP_D2R_PI_P

USB_BT_N

SMC_PME_S4_WAKE_L

PCIE_AP_R2D_PI_N

USB_BT_P

PP3V3_S4

PP3V3_S3RS4_BT_FMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_S5

AP_RESET_L

P3V3WLAN_VMON

PP3V3_WLAN_F

AP_CLKREQ_R_LPM_WLAN_EN

PM_SLP_S4_L

PP3V3_S4

USB_BT_WAKEN

USB_BT_CONN_PUSB_BT_CONN_N

PCIE_AP_R2D_P

PCIE_AP_D2R_P

PP3V3_WLAN_FMIN_LINE_WIDTH=1 mm

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=1 mm

VOLTAGE=3.3V

PP3V3_WLAN

PCIE_AP_R2D_C_N

PCIE_AP_R2D_N

PM_WLAN_CAP

PM_WLAN_EN

PP3V3_S5PP3V3_WLAN_RMIN_LINE_WIDTH=1 mm

VOLTAGE=3.3VMIN_NECK_WIDTH=0.25 mm

PP3V3_WLAN_R

PP3V3_S5

PM_WLAN_EN

PCIE_AP_D2R_PI_N

PCIE_AP_D2R_N

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_CONN_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

35 OF 118

34 OF 82

77

72

72

72 77

77

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

72

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

34 47

34 41 67

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

72 76

72 76

72 77

42 72

72 77

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

34 47

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

34 41 67

72 77

72 77

72 77

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

IN

NC

08

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

NC

08

IN

NC

RESET*

OUT

EN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLY

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FOR DESENSE IMPROVEMENT

Delay = ~55ms

Supervisor & CLKREQ# Isolation

GND_VOID

Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA

Gumstick3 Connector

APN 343S0511

OOB Isolation

GND_VOID

514S0449

41

2

1 C3702

PLACE_NEAR=L3700.1:1mm

10VX5R-CERM0201

0.1UF10%

21

L3700


CRITICAL

FERR-26-OHM-6A

0603

2

1 C3701

PLACE_NEAR=L3700.1:1mm

10VX5R-CERM0201

0.1UF10%

2

1R3742

MF

1%100K1/20W

201

2

1R3740

201

100K1/20W

MF

5%

2

1R37411%

MF1/20W

232K

201

11

2

1 C3740

CERM-X5R

10%0.1UF6.3V

0201

20

35 66

4

6

5 3

1

2

U3711

SOT89174LVC1G08

CRITICAL

2

1C3719BYPASS=U3711::5 mm

X5R-CERM

0.1UF10V10%

0201

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

21C37110.22UF 6.3V20%

GND_VOID=TRUEX6S-CERM 0201

21C371020%0.22UF 6.3V 0201

GND_VOID=TRUEX6S-CERM

11 77

11 77

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

5 71 75

35 66

41

20

18

9

8

7

63

62

61

60

6

59

58

57

56

55

54

53

52

51

505

49

48

47

46

45

44

43

42

41

40

4

39

38

37

36

35

34

33

32

31

30

3

2928

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3700F-RT-SM

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

SSD-GS3

TRUE

TRUE

TRUE

TRUE

TRUE

CRITICAL

TRUE

TRUE

TRUE

2

1R3700

MF201

1/20W1%

100K

NOSTUFF

4

6

53

1

2

U3710

74LVC1G08

CRITICAL

SOT89141

2

1 C3718BYPASS=U3710::5 mm

0.1UF10V

0201X5R-CERM

10%

1

9

2

4

8

3

7

5

6

U3740SLG4AP016V

TDFN

CRITICAL

21C37120.22UF 6.3V20% 0201X6S-CERM

GND_VOID=TRUE

21C371320% 6.3V X6S-CERM 02010.22UF

GND_VOID=TRUE

21C37140.22UF X6S-CERM6.3V20% 0201

GND_VOID=TRUE

21C3715X6S-CERM20% 02010.22UF 6.3V

GND_VOID=TRUE

21C37166.3V X6S-CERM20% 02010.22UF

GND_VOID=TRUE

21C37170.22UF 0201

GND_VOID=TRUE20% X6S-CERM6.3V

2

1R3701

1/20W

201MF

1%100K

2

1 C3722


0201

12PF5%NP0-C0G

25V2

1 C372312PF


0201

5%NP0-C0G

25V2

1 C3724

PLACE_NEAR=J3700.5:2mm25V

NP0-C0G5%12PF

0201


SSD Connector

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<0>

PCIE_SSD_R2D_P<1>

PCIE_SSD_R2D_P<2>

PCIE_SSD_R2D_N<3>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<2>

PCIE_SSD_D2R_N<0>PCIE_SSD_D2R_P<0>

PCIE_CLK100M_SSD_N

PCIE_SSD_D2R_N<1>

SMC_OOB1_D2R_L

PP3V3_S0SW_SSD

PP3V3_S0

SMC_OOB1_R2D_L

SSD_DEVSLP

P3V3SSD_VMON

SSD_CLKREQ_LSSD_PWR_FET_EN

PP3V3_S0SW_SSDPP3V42_G3H

MAKE_BASE=TRUE

SSD_PWR_FET_ENSSD_PWR_FET_EN

PCIE_SSD_D2R_P<2>

SSD_RESET_L

PP3V3_S0SW_SSD

NO_TEST=TRUENC_SSD_MFG_RSVD

PP3V3_S0

PCIE_SSD_R2D_N<0>

PCIE_CLK100M_SSD_P

PCIE_SSD_D2R_P<3>PCIE_SSD_D2R_N<3>

SMC_PWRFAIL_WARN_L

PCIE_SSD_R2D_C_P<1>

SSD_PWR_FET_EN

SMC_OOB1_R2D_CONN_L

SSD_PCIE_SEL_L

SMC_OOB1_D2R_CONN_L

SSD_CLKREQ_CONN_LPCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_R2D_C_N<0>

SSD_RESET_CONN_L

PCIE_SSD_R2D_N<2>

PCIE_SSD_R2D_P<3>

PCIE_SSD_R2D_C_N<1>

VOLTAGE=3.3V

PP3V3_S0SW_SSD_FLTMIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.15mm

<BRANCH>

<SCH_NUM>

<E4LABEL>

37 OF 118

35 OF 82

75

75

75

75

75

35 46 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

35 46 70 72 19 38 39 41 42 43 44 50 56 57 65 67 70 72

35 66 35 66

35 46 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

75

75

75

w w w

. c h

i n a

f i x

. c o

m

NCNC

NCNC

OUT

IN

OUT

BI

IN

IN

IN

OUT

IN

IN

OUT

OUT

IN

IN

SYM 1 OF 3

DEBUG_15

DEBUG_14

PWR_MODE

SENSOR_WAKE*

PCIE_WAKE*

PCIE_CLKREQ*

JTAG_SRST*

JTAG_TRST*

JTAG_TMS

JTAG_TDO

PCIE_REFCLKN

DEBUG_03

DEBUG_04

DEBUG_05

DEBUG_09PCIE_RDP0

DEBUG_06

DEBUG_00

DEBUG_01

DEBUG_02

DEBUG_07

DEBUG_08

DEBUG_10

DEBUG_11

DEBUG_12

DEBUG_13

DEBUG_16

GPIO_00

GPIO_01

GPIO_02

GPIO_03

GPIO_04

GPIO_05

GPIO_06

GPIO_07

I2C_CLK_DBG

I2C_CLK_SENSOR

I2C_DATA_DBG

I2C_DATA_SENSOR

JTAG_TCK

JTAG_TDI

MIPI_CP_CLK

PCIE_RDN0

PCIE_REFCLKP

PCIE_RST*

PCIE_TDN0

RESET*

SHUTDOWN*

UARTCTS

UARTRTS

UARTRXD

UARTTXD

XTAL_N

XTAL_P

MIPI_DM0

MIPI_DP0

MIPI_CM_CLK

PCIE_TDP0

PCIE_TESTN

MIPI_DP1

MIPI_DM1

STRAP_XTAL_FREQ

STRAP_XTAL_SEL

TEST_OUT

TEST_MODE

PCIE_TESTP

SYM 2 OF 3

DDR_CK_N0

DDR_CK_P0

DDR_CAS*

DDR_RAS*

DDR_CKE

DDR_AD00

DDR_AD01

DDR_AD02

DDR_AD03

DDR_AD04

DDR_AD05

DDR_AD06

DDR_AD07

DDR_AD08

DDR_AD09

DDR_AD10

DDR_AD11

DDR_AD12

DDR_AD13

DDR_AD14

DDR_BA0

DDR_BA1

DDR_BA2

DDR_CS*

DDR_DM0

DDR_DM1

DDR_DQ00

DDR_DQ01

DDR_DQ02

DDR_DQ03

DDR_DQ04

DDR_DQ05

DDR_DQ06

DDR_DQ07

DDR_DQ08

DDR_DQ09

DDR_DQ10

DDR_DQ11

DDR_DQ12

DDR_DQ13

DDR_DQ14

DDR_DQ15

DDR_DQS_N0

DDR_DQS_N1

DDR_DQS_P0

DDR_DQS_P1

DDR_RESET*

DDR_WE*

DDR_ZQ

SYM 3 OF 3

SR_VLXD_O

VDD_1P35A

PCIE_GND

XTAL_AVDD1P2

VDDC

VDD1P8_O

SR_VLXC_O

SR_VDD_3P3D

SR_VDD_3P3C

SR_PVSSD

SR_PVSSC

PMU_AVSS

OTP_VDD3P3

DDR_VDDIO_CK

MIPI_AGND

VDD_3P3A

DDR_VREF

VSSC

XTAL_AVSS

DDR_VDDIO

PCIE_VDD1P2

VSENSE_D

VSENSE_C

PCIE_PVDD1P2

DDR_AVDD1P8

MIPI_AVDD1P8

PLL_VDD1P8

VDD1P2_O

VDDO18

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

NCNCNCNC

NCNC

NCNCNC

NCNCNCNC

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



PD = 1.35V

L3901:1L3902:1

PU = 25MHz

(=PP3V3_S3RS0_CAMERA)

(=PP3V3_S3RS0_CAMERA)

PU on PCH page

11

37

37 72

37 72

2

1R3930NOSTUFF

100K

MF1/20W

201

5%

2

1R3932NOSTUFF

100K1/20WMF201

5%

13 18

20

2

1 C390010%0.1UF

0201CERM-X5R6.3V

2

1 C39240.1UF10%

CERM-X5R6.3V

02012

1 C3923

X5R6.3V

0201-1

1.0UF20%

2

1 C392210%0.1UF

0201CERM-X5R6.3V2

1 C392120%

X5R6.3V

0201-1

1.0UF

2

1 C391010%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.D6::2.54MM

2

1 C395110%0.1UF

0201CERM-X5R6.3V


2

1R3901100K

MF1/20W

201

5%

37

37

37 77

37 77

37 77

37 77

37 77

37 77

2

1R3906NO STUFF

100K

MF1/20W5%

201

2

1R3907100K

MF201

5%1/20W

2

1R3904

1/20W5%100K

MF201

21

L3901

PLACE_NEAR=U3900.M13:4MM

1.0UH-1.6A-55MOHM

1008

21

L39021.0UH-1.6A-55MOHM

PLACE_NEAR=U3900.K13:4MM1008

2

1 C39124.7UF6.3V20%

X5R402

BYPASS=U3900.K13::2.54MM

2

1 C3915

X5R6.3V PLACE_NEAR=U3900.M13:2.54MM4.7UF20%

402

21

L390622NH

0402

2

1 C391610%0.1UF

0201CERM-X5R6.3V

BYPASS=U3900.L7::2.54MM

2

1 C3928

X5R6.3V

402

20%4.7UF

2

1 C3926

X5R6.3V

402

20%4.7UF

PLACE_NEAR=U3900.M14:2.54MM

2

1 C39190.1UF10%6.3VCERM-X5R0201

BYPASS=U3900.J1::2.54MM

2

1 C393710%

0201

6.3V

BYPASS=U3900::5mm

CERM-X5R

0.1UF

2

1 C393510%

BYPASS=U3900::5mm

CERM-X5R6.3V

0201

0.1UF

2

1 C394010%0.1UF6.3VCERM-X5R

BYPASS=U3900::5mm

02012

1 C3942

X5R6.3V

4.7UF

402

20%

BYPASS=U3900::7mm

2

1 C3941

BYPASS=U3900.F15::2.54MM

2.2UF20%

402-LFCERM6.3V

2

1 C393910%10V

402X5R

BYPASS=U3900.G15::2.54MM

1UF

2

1 C396010%0.1UF

0201CERM-X5R6.3V

A13

A12

E14

E13

D14

D13

J12

M10

C12

C13

H12

R13

E15

G12

N12

B9

C9

A8

B8

R14

B10

A10

B7

A7

P13

P6

P8

R6

R8

P7

R7

D11

D12

F12

E12

F13

C11

R9

C15

R10

D15

N9

N10

N11

P9

P10

P11

P12

R12

L10

L11

K10

K11

J10

H10

H11

G10

G11

F10

F11

E10

E11

A15

B14

C14

B11

U3900FBGA

OMIT_TABLE

BCM15700

CRITICAL

G3

J2

R3

H3

A2

E2

A3

D2

B3

B2

C5

A5

B4

B1

C3

B5

F2

F4

F1

F3

D3

E4

E3

C2

C4

C1

L4

J3

H2

G2

H4

K2

L2

K3

R4

P1

L1

R2

J4

P2

P3

N2

P4

M2

M1

M3

N3

M4

L3

U3900

CRITICAL

FBGA

OMIT_TABLE

BCM15700

B12

B13

G8

G7

G6

G1

E5

D5

E9R5

R1

P5

D1

N1

M9

A14

K9

K8

K7

K6

K5

K1

J9

B6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

A6

A1

K12

M11

R11

B15

L9

L8

L5

L6

F9

F8

F7

F6

J11

F14

G15

F15

K14

K13

N14

M13

J15

J14

J13

H15

H14

N15

M15

M14

L15

L14

L13

L12

K15

R15

P15

P14

N13

M12

G14

D6

C8

D9

C7

C10

D7

L7

N6

N8

N7

N5

G5

N4

K4

G4

D4

A4

J1

U3900

CRITICAL

BCM15700FBGA

OMIT_TABLE

2

1 C3918

X7R-1

10%

0201

BYPASS=U3900.J1::2.54MM

16V

1000PF

2

1 C3934

X7R-1

BYPASS=U3900::3mm

0201

16V

1000PF10%

2

1 C3917

X7R-1


0201

1000PF16V10%

2

1 C3936

X7R-1

BYPASS=U3900::3mm

1000PF16V

0201

10%

2

1 C3938

X7R-10201


1000PF16V10%

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37 80

37

2

1R3910100K

MF1/20W

201

5%

NO STUFF

2

1R3911100K

MF1/20W

201

5%

21

R3912

1%

240

MF1/20W

201

2

1R39131K

MF1/20W

201

5%

2

1R39141K

MF1/20W

201

5%

37 80

21

XW3900SM

21

XW3901SM

2

1R3990100K

MF1/20W

201

5%

2

1 C3990NO STUFF

0201

6.3VCERM-X5R

0.1UF10%

2

1 C392710%0.1UF

0201CERM-X5R6.3V

2

1 C3930

X5R6.3V

1.0UF20%

0201-1

37 80

2

1 C39321.0UF6.3VX5R

20%

0201-1

2

1 C3931

X5R402

4V

10UF20%

2

1 C3933

X5R4V20%10UF

402

2

1 C3914

X5R6.3V

402

20%4.7UF

2

1 C3913

X5R6.3V

4.7UF20%

402

21

L3903220-OHM-1.4A

0603

21

L3904220-OHM-1.4A

0603

21

R3991

MF1/20W

0201

0

5%

NO STUFF

12 34 72 77

2

1 C3975


10%0.1UF

0201CERM-X5R6.3V2

1 C3974


10%0.1UF

0201CERM-X5R6.3V2

1 C3973

0201X7R-116V


1000PF10%

2

1 C3972


CERM-X5R0201

10%0.1UF6.3V2

1 C3971

X7R-1


0201

16V10%1000PF

2

1 C3970


10%

0201CERM-X5R6.3V

0.1UF

2

1R397551K

MF1/20W

201

5%

2

1R397651K

MF1/20W

201

5%

2

1R3920100K

MF1/20W

201

5%

2

1R3921100K

MF1/20W

201

5%

2

1R3934NOSTUFF

100K

MF1/20W

201

5%

2

1R39315%

201

1/20WMF

330K

2

1R39335%

201

1/20WMF

330K

2

1R39355%

201

1/20WMF

330K

2

1R3936100K

NOSTUFF

MF1/20W

201

5%

2

1R3937NOSTUFF

100K

MF1/20W

201

5%

37 80


Camera 1 of 2SYNC_DATE=06/24/2014

PP3V3_S3RS0_CAMERA

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

PP1V8_CAM

VOLTAGE=1.2VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP1V2_CAM_PCIE_VDD_FLT

GND_CAM_PVSSD

PP1V8_CAM

CAM_XTAL_SEL

TP_CAM_JTAG_TDO

TP_CAM_JTAG_TRST_L

CAMERA_CLKREQ_L

VOLTAGE=1.2V


PP1V2_CAM_PCIE_PVDD_FLT

PP1V2_CAM

CAM_RAMCFG0CAM_RAMCFG1

PP1V8_CAM

PCIE_CAMERA_R2D_N

P1V35_CAM_SRVLXD_PHASE

TP_CAM_LV_JTAG_TMSTP_CAM_LV_JTAG_TDOTP_CAM_LV_JTAG_TDITP_CAM_LV_JTAG_TCKTP_CAM_TEST_MODE2TP_CAM_TEST_MODE1TP_CAM_TEST_MODE0

TP_CAM_LV_JTAG_TRSTN

GND_CAM_PVSSC

MEM_CAM_A<14>MEM_CAM_A<13>


MEM_CAM_A<12>

MEM_CAM_BA<0>

PCIE_CLK100M_CAMERA_C_P


PP1V8_CAM

CAM_GPIO3

PP1V8_CAM

P1V2_CAM_SRVLXC_PHASE

CAM_RAMCFG2

CAM_RAMCFG0

CAM_XTAL_SEL

CAM_XTAL_FREQ

CAM_TEST_MODECAM_TEST_OUT

CAM_UARTCTSTP_CAM_UARTRTS

CAM_UARTRXDTP_CAM_UARTTXD

CAM_RAMCFG1

I2C_CAM_SMBDBG_DATI2C_CAM_SMBDBG_CLK

MIPI_CLK_NMIPI_CLK_P

GND_CAM_PVSSC

PP1V2_CAM

VOLTAGE=1.2V


PP1V8_CAM

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

MAKE_BASE=TRUE

PP1V2_CAM_XTALPCIEVDDMIN_NECK_WIDTH=0.2MM

PP1V35_CAM

PP1V35_CAMPP1V2_CAM

VOLTAGE=0.675VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMPP0V675_CAM_VREF

VOLTAGE=1.35V


PP1V35_DDR_CLK

P1V2_CAM_SRVLXC_PHASEMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

DIDT=TRUE

DIDT=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

P1V35_CAM_SRVLXD_PHASE

MEM_CAM_ZQ_S2

MEM_CAM_A<0>MEM_CAM_A<1>MEM_CAM_A<2>MEM_CAM_A<3>


MEM_CAM_A<6>MEM_CAM_A<7>MEM_CAM_A<8>


MEM_CAM_A<11>

MEM_CAM_BA<1>MEM_CAM_BA<2>

MEM_CAM_CLK_PMEM_CAM_CLK_N

MEM_CAM_DM<0>MEM_CAM_DM<1>

MEM_CAM_CKEMEM_CAM_CS_L

MEM_CAM_DQ<15>MEM_CAM_DQ<14>MEM_CAM_DQ<13>MEM_CAM_DQ<12>MEM_CAM_DQ<11>MEM_CAM_DQ<10>MEM_CAM_DQ<9>MEM_CAM_DQ<8>MEM_CAM_DQ<7>MEM_CAM_DQ<6>MEM_CAM_DQ<5>MEM_CAM_DQ<4>MEM_CAM_DQ<3>MEM_CAM_DQ<2>MEM_CAM_DQ<1>MEM_CAM_DQ<0>

TP_CAM_JTAG_TCK

I2C_CAM_SMBDBG_DAT

I2C_CAM_SMBDBG_CLK

MIPI_DATA_NMIPI_DATA_P

PCIE_CAMERA_R2D_P

PCIE_CAMERA_D2R_C_NPCIE_CAMERA_D2R_C_P

PP1V8_CAM

CAM_XTAL_FREQ

CAM_UARTCTS

CAM_UARTRXD

CLK25M_CAM_CLKPCLK25M_CAM_CLKN

PCIE_CLK100M_CAMERA_C_N

MEM_CAM_DQS_P<0>MEM_CAM_DQS_N<0>

MEM_CAM_DQS_P<1>MEM_CAM_DQS_N<1>

MEM_CAM_RAS_LMEM_CAM_WE_LMEM_CAM_CAS_LMEM_CAM_RESET_L

CAM_TEST_MODE

GND_CAM_PVSSD

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

PCIE_WAKE_L

VOLTAGE=0VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMGND_CAM_PVSSC

CAM_TEST_OUT


CAM_RAMCFG2

VOLTAGE=1.35V

PP1V35_CAMMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

GND_CAM_PVSSD

TP_CAM_JTAG_TMS

TP_CAM_JTAG_SRST_L

CAM_PCIE_WAKE_L

CAMERA_PWR_ENCAM_SENSOR_WAKE_L

CAM_DEBUG_RESET_L

CAM_PCIE_RESET_L

CAM_PWR_SEL

TP_CAM_JTAG_TDI

I2C_CAM_SDA

I2C_CAM_SCK

PP1V8_CAM

<BRANCH>

<SCH_NUM>

<E4LABEL>

39 OF 118

36 OF 82

13 47 70

36

36 37

36

36

36

36 36 37

36

36

19 36

19 36

36 37

36 37

36

36

36

36

36

36

36

36

36

36

36

36

36

36

19 36

36 37 80

36 37 80

36

37 80

36

36

36

36

36 37

36

36

36

36

36

36

36 37 80

36

36 37

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

OUT

OUT

IN

IN

IN

IN

BI

IN

IN

IN

BI

BIBI

IN

A4

A14

DQSL*

DQL1

VDD

A2

A3

A1

A0

NC

A6

ODT

RESET*

VSSQ VSS

CAS*

RAS*

BA2

BA0

BA1

DQL7

DQL4

DQL3

DQL2

DQL0

ZQ

DQU3

DQU2

DQU4

CS*

CKE

DQU7

DQU6

DQSU*

DQU0

DQSL

A13

A11

A10/AP

A8

A5

A7

A9

CK

DML

DMU

DQL5

DQL6

DQSU

DQU1

DQU5

VREFCA

VREFDQ

CK*

WE*

VDDQ

A12/BC*

NCNCNCNCNC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

SYM_VER-1

SYM_VER-1

NCNC

OUT

IN

OUT

OUT

IN

IN

IN

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



CAMERA SENSOR

remove DRAM SPD Straps

1

0

0

0

CFG 0

0 1

CFG 1

MICRON

SAMSUNG

HYNIX

VENDOR

1

0

1

1

CFG 2

A

ELPIDA

DIE REV

DRAM CFG Chart

96.2 mA peak77.2 mA nominal max

ALS

518S0892

B

NOTE: TBD PPM crystal required

36 77

36 77

13 77

13 77

21C403310%0.1UF 16V 0201X5R-CERM

21C403210%0.1UF 16V 0201X5R-CERM

21C403110%0.1UF X5R-CERM 020116V

21C403010%0.1UF X5R-CERM 020116V

13 77

13 77

36 77

36 77

21

R4009

5%

0

0201

1/20WMF

NO STUFF

21

R4010

5%

0

0201

1/20WMF

NO STUFF

21

R4008

5%

0

02011/20W

MF

21

R4007

5%

0

02011/20WMF

NO STUFF

21

R4000

MF1/20W

0201

0

5%

2

1 C400420%4V

0.47UF

201

BYPASS=U4000.H9::4mm

CERM-X5R-1 2

1 C4008

402X5R-CERM

20%2.2UF10V

BYPASS=U4000.K2::4mm

2

1 C4006

402

BYPASS=U4000.D2::4mm

10V

2.2UF20%

X5R-CERM

2

1R4012

201

1/20WMF

1%1M

NO STUFF

21

C4015NO STUFF

25V

12PF

0201

5%

CERM

21

C4014

NO STUFF

0201

25V

12PF

5%

CERM

2

1 C4009

6.3VCERM-X5R0201

0.1UF10%

2

1 C4007

6.3VCERM-X5R0201

0.1UF10%

BYPASS=U4000.R9::4mm

2

1C4013

CERM402

10V20%

0.1uF

36 72

36 72

2

1 C4005

6.3VCERM-X5R0201

0.1UF10%

36 80

36 80

36 80

36 80

2 1

L4010FERR-120-OHM-1.5A

0402-LF

2

1 C4003

402

20%4VX5R

10UF

BYPASS=U4000.B2::4mm

2

1 C4002

4V20%

402

10UF

X5R

BYPASS=U4000.A1::4mm

41 44 48 68 71 72 81

41 44 48 68 71 72 81

2

1R40221%1K

MF1/20W

201

2

1R40231%1K

MF1/20W

201

L8

L3

G9

G1

F9

E8

E2

D8

D1

B9

B1

P9

P1

M9

M1

J8

J2

G8

E1

T9

T1

B3

A9

H1

M8

H9

H2

F1

E9

D2

C9

C1

A8

A1

R9

R1

N9

N1

K8

K2

G7

D9

B2

T2

J3

K1

M7

L9

L1

J9

J1

A3

B8

A2

A7

C2

C8

C3

D7

B7

C7

G3

F3

H7

G2

H8

H3

F8

F2

F7

E3

D3

E7

L2

K9

K7

J7

K3

M3

N8

M2

R3

T8

R2

R8

P2

P8

N2

P3

T7

T3

N7

R7

L7

P7

N3 U4000FBGA

OMIT_TABLE

CRITICAL

K4B4G1646B-HYK0

4GB-DDR3-256MX16

36 80

36 80

2

1 C4011

6.3VCERM-X5R0201

0.1UF10%

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

2

1C4010

6.3VCERM-X5R

0201

0.1UF10%

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36

36 80

36 80

36 80

36 80

2

1R40201%84.5

MF1/20W

201

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

36 80

2

1R40211%82

MF1/20W

NO STUFF

201

36 80

2

1R40021K

MF1/20W

201

5%

2

1R40031K

NOSTUFF

MF1/20W

201

5%

2

1R40041%2401/20W

201MF

21

R4030CAM_WAKE:YES

MF1/20W

0201

0

5%

2

1 C4016

25V

100PF

0201

5%

C0G

2

1R4031CAM_WAKE:NO

MF1/20W

0201

05%

9

8

7

6

5

4

3

2

12

11

10

1

13

14

J4002CCR20-AK7100-1

CRITICAL

F-RT-SM

21C406110%0.1UF 16V 0201X5R-CERM

21C406210%0.1UF 16V 0201X5R-CERM

2 1

L4011FERR-120-OHM-1.5A

0402-LF

NOSTUFF

2

1 C40265%100PF

0201

25VC0G

NO STUFF

36 80

4

32

1

L4007


CRITICAL

90-OHM-0.1A-0.7-2GHZTAM0605

4

32

1

L4009


90-OHM-0.1A-0.7-2GHZTAM0605

CRITICAL

2

1 C4012

25V

NP0-C0G


5%

0201

12PF

31

42

Y4000CRITICAL

SM-3.2X2.5MM

25.000MHZ-12PF-20PPMNO STUFF

36

36

36 77

36 77

11 77

11 77

2

1R4005100K

MF1/20W

201

5%

19 76

SYNC_DATE=06/24/2014

Camera 2 of 2SYNC_MASTER=CLEAN_X305

VOLTAGE=5V

PP5V_S3RS0_ALSCAM_FMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mm

MIPI_DATA_CONN_PMIPI_DATA_N

MIPI_DATA_P

MIPI_CLK_N

MIPI_CLK_P

CLK25M_CAM_XTALN

PP5V_S3

MEM_CAM_CKE_R

MEM_CAM_WE_L

MEM_CAM_CS_L

MEM_CAM_CAS_LMEM_CAM_RAS_L

MEM_CAM_BA<0>

MEM_CAM_A<12>



MEM_CAM_DQ<13>

MEM_CAM_DQ<9>

MEM_CAM_DQS_P<1>

MEM_CAM_DQ<5>

MEM_CAM_DM<1>

MEM_CAM_DQS_P<0>

MEM_CAM_DQS_N<1>

MEM_CAM_DQ<14>MEM_CAM_DQ<15>

MEM_CAM_DQ<12>

MEM_CAM_DQ<10>MEM_CAM_DQ<11>

MEM_CAM_DQ<0>

MEM_CAM_DQ<2>MEM_CAM_DQ<3>MEM_CAM_DQ<4>

MEM_CAM_DQ<7>

MEM_CAM_DQS_N<0>

MEM_CAM_DM<0>

MEM_CAM_A<6>

MEM_CAM_A<3>

MEM_CAM_RESET_L

MEM_CAM_ZQ_DDR

MEM_CAM_A<11>

MEM_CAM_BA<1>

MEM_CAM_DQ<8>

PP5V_S0

CAM_SENSOR_WAKE_L_CONN

MEM_CAM_BA<2>


CLK25M_CAM_CLKP

CLK25M_CAM_XTALP_RCLK25M_CAM_XTALP

PCIE_CAMERA_R2D_P

PCIE_CAMERA_R2D_N

PCIE_CAMERA_D2R_P

PCIE_CAMERA_D2R_N

PCIE_CLK100M_CAMERA_C_P

PCIE_CLK100M_CAMERA_C_N

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_D2R_C_P

PCIE_CAMERA_R2D_C_N

PCIE_CLK100M_CAMERA_P

PCIE_CAMERA_D2R_C_N

PCIE_CLK100M_CAMERA_N

PP1V8_CAM

CAM_SENSOR_WAKE_L_CONN CAM_SENSOR_WAKE_L

CLK25M_CAM_CLKN

SYSCLK_CLK25M_CAMERA

MEM_CAM_DQ<6>

MEM_CAM_DQ<1>

PP1V35_CAM

PP0V675_MEM_CAM_VREFDQMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.675V

VOLTAGE=0.675VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmPP0V675_MEM_CAM_VREFCA

MEM_CAM_A<0>MEM_CAM_A<1>MEM_CAM_A<2>


PP0V675_CAM_VREF

MEM_CAM_CLK_P

MEM_CAM_ODT

MEM_CAM_CLK_N

MEM_CAM_CKE

MIPI_CLK_CONN_NMIPI_CLK_CONN_P

MIPI_DATA_CONN_N

I2C_CAM_SDA

SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SDA

I2C_CAM_SCK

<BRANCH>

<SCH_NUM>

<E4LABEL>

40 OF 118

37 OF 82

72

72 80

21 60 66 67 70 72

18 19 49 58 59 62 63 66 67 70 71 72

37 72

36

37 72 36

36 80

80

80

36 80

80

72 80

72 80

72 80

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

IN

GND

VBUS

SSTX+

SSRX-

GND

SSTX-

D+

D-

GND

SXRX+

SYM_VER-1

BI

BI

IN

OUT

IN

OUT

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GNDTHRMPAD

Apple Inc.


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REVISION

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6 3



USB/SMC Debug Mux

USB Port Power Switch

CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX

We can add protection to 5V if we want, but leaving NC for now

SEL=1 Choose USB

Left USB Port A

Place L4605 and L4615 at connector pin

SEL=0 Choose SMC

514-093413 76

13 76

13 76

13 76

21

L4605FERR-120-OHM-3A

0603

CRITICAL

21C46110201

0.1UF

16VX5R-CERM

10%

GND_VOID=TRUE

21C461016V 0201X5R-CERM

10%

0.1UFGND_VOID=TRUE

2

1C4696

CASE-B2-SM1

6.3V20%

POLY-TANT

220UF-35MOHM

CRITICAL

2

1R4600

1/16W

402MF-LF

22.1K1%

2

1R4601

1/20W

201

22.1K1%

MF

21

R4651NOSTUFF

MF1/20W

0201

0

5%

21

R4652NOSTUFF

MF1/20W

0201

0

5%

1

8

2

3

9

19

18

17

16

15

14

13

12

23

22

21

20

11

10

7

4

6

5

J4600CRITICAL

F-RT-THUSB3.0-J44-ALT

4

32

1

L4600CRITICAL

TAM060590-OHM-0.1A-0.7-2GHZ

2

1

D46010201-THICKSTNCL

ESD112-B1-02ELS

CRITICAL 2

1

D4600CRITICAL

ESD112-B1-02ELS0201-THICKSTNCL

2

1

D4610

GND_VOID=TRUE

CRITICAL

0201-THICKSTNCLESD112-B1-02ELS

2

1

D4611

GND_VOID=TRUE

CRITICAL

ESD112-B1-02ELS0201-THICKSTNCL

2

1


GND_VOID=TRUE

CRITICAL

ESD112-B1-02ELS

2

1


CRITICAL

ESD112-B1-02ELS

GND_VOID=TRUE

2

1C4695

6.3V20%

X5R

10UF

6032

1 C469120%

CERM

0.1UF10V

402

13 76

13 76

2

1C46500.1UF

CERM

20%10V

4022

1R4650100K1/16WMF-LF402

5%

41 42 76

41 42 76

41

2

1C4605

0402X7R-CERM

16V20%

0.01UF18

2

1C4690

X5R

10UF20%

6.3V

603

2

1R4690

MF-LF402

1/16W

05%

2

1C4692NOSTUFF

0.47UF10VX5R

0402

10%

1

2

9

108

5

4

3

7

6

U4650

CRITICAL

SIGNAL_MODEL=MOJO_MUX_USBONLY

PI3USB102EZLETQFN

9

7

6

3

2

5

1

8

4

U4600SON

TPS2557DRB

CRITICAL

SYNC_MASTER=J15_MLB

USB 3.0 CONNECTORSSYNC_DATE=10/31/2012


PP5V_S3_LTUSB_A_FMIN_LINE_WIDTH=0.5 mm

USB_EXTA_N

SMC_DEBUGPRT_EN_L

USB_EXTA_P

PP5V_S4

PP3V42_G3H

PM_SLP_S4_L

USB_ILIMUSB_EXTA_OC_L

SMC_DEBUGPRT_RX_LSMC_DEBUGPRT_TX_L

USB_EXTA_MUXED_P

VOLTAGE=5V


PP5V_S3_LTUSB_A_ILIM

USB_ILIM_R

USB3_EXTA_R2D_C_N

USB3_EXTA_R2D_C_P

USB_LT1_PUSB_LT1_N

USB3_EXTA_R2D_PUSB3_EXTA_R2D_N

USB3_EXTA_D2R_N

USB_EXTA_MUXED_N

USB3_EXTA_D2R_P

USB_PWR_EN

<BRANCH>

<SCH_NUM>

<E4LABEL>

46 OF 118

38 OF 82

39 51 61 66 67 68 69 70 72

19 35 39 41 42 43 44 50 56 57 65 67 70 72

12 21 34 41 67 69 72

76 76

76

76

76 76

w w w

. c h

i n a

f i x

. c o

mNCNC

NCNC

IN

OUT

OUT

SYM_VER_2

G S

D

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

INT*

ADDR

SCL

SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4

P1_5

P1_6

P1_7

GND

OUT

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

INT*

ADDR

SCL

SDA

RESET*

VCCI

VCCP

P1_1

P1_0

P1_3

P1_2

P1_4

P1_5

P1_6

P1_7

GND

VDD

OUT_1

GNDTHRM

OE

OUT_ALL#

OUT_3

OUT_2

IN_1

IN_3

IN_2

(IPD)

(IPD)

(IPD)

(IPD)

PAD

Apple Inc.


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IPD CONNECTOR

LEFT SHIFT, OPTION & CONTROL KEYS COMBINED WITH POWER BUTTON CAUSE SMC RESET# ASSERTION.

Keys ANDed with PSoC power to isolate when PSoC is not powered.

No IPD on OE input pin PP3V3_S4 (symbol error).

Keyboard Connector518S0752

Pull-up in U5110.

(Write: 0x40 Read: 0x41)311S0597

IO EXPANDER / KEYBOARD INTERFACE

(Write: 0x42 Read: 0x43)311S0597

SMC Manual Reset & Isolation

2

1 C4821

BYPASS=U4820.B3:E2:2MM

10%

0201CERM-X5R6.3V

0.1UF

2

1R485510K

MF1/20W

201

5%

2

1R4856

1/20W

201

10K

MF

5%

2

1R4857

1/20W

10K

MF201

5%

2

1R485910K

MF1/20W

201

5%

2

1R486010K

MF1/20W

201

5%

2

1R486110K

MF1/20W

201

5%

2

1R486210K

MF1/20W

201

5%

2

1R4858

1/20W

10K

MF201

5%

2

1 C4822


10%0.1UF

CERM-X5R6.3V

0201

2

1C48015%25V

0201

100PFC0G

2

1

XW4801

PLACE_NEAR=J4801:3MM

SM

21

R4890

NOSTUFF 1/16WMF-LF402

5%

0

21

R4891

NOSTUFF402

5%

MF-LF1/16W

0

2

1C48030.1uF

402

20%CERM10V

2 1

L4803

0402-LF

FERR-120-OHM-1.5A

2

1R4893

1/20W

NOSTUFF

100K5%

MF201

98

76

5

45

44

43

42

4140

4

3938

3736

3534

3332

3130

3

2928

2726

2524

2322

2120

2

1918

1716

1514

1312

1110

1

J4801502250-8041

F-RT-SM

CRITICAL

2

1C4808PLACE_NEAR=J4801.35:5mm

CERM-X5R0402

1.0UF35V10%

2

1 C4806

CER-X5R


0.1UF10%35V

02012

1 C4807


0201CER-X5R

0.1UF35V10%

67 21

R4809

5%

0

1/20WMF0201

PLACE_NEAR=C4809.1:2MM

2

1 C4809NOSTUFF

PLACE_NEAR=J4801.26:2MM0201

25V5%100PF

C0G

21

R4808

0201MF1/20W5%

041 72

42

2

1C4850

X7R-CERM

0.1UF

0402

10%16V

BYPASS=U4850.10:5:5 mm

2

1C482410%

NOSTUFF

0.01UF

0201

10VX5R-CERM

2

1R4821

MF1/20W

201

5%10K

2 1

R4824

MF1/20W 02015%

0

NOSTUFF

2

1R4840100K

1%1/16W

402MF-LF

21

3Q4840DFN1006H4-3

DMN32D2LFB4

2

1R4820

201

5%1/20WMF

100K

2

1C4834

X5R-CERM

0.01UF

NOSTUFF

10%10V

0201

2

1R4831

MF1/20W

201

5%10K

2

1R4830

1/20W

100K

MF201

5%2

1 C4830

402


6.3V

1UF10%

CERM

B4

B3

A4

A5

A2

C4

C5

D5

D4

E5

D3

E4

E3

D2

E1

D1

C2

C1

B1

C3

A1A3

E2

B5

U4830

VFBGA

PCAL6416A

2

1 C483110%0.1UF

0201


6.3VCERM-X5R 2

1 C483210%6.3V

0201CERM-X5R

0.1UF


39 41 42 72

2

1 C482010%6.3V


1UF

402CERM

2

1C4810PLACE_NEAR=J4813.5:5MM

CERM

0.1UF20%

402

10V

21

R4810

5%

MF-LF402

1/16W

1K

21

R48150

MF-LF1/16W

402

5%

21

R4814

1%1/16W

402

113

MF-LF

9

8

7

6

5

4

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

32

31

J4813

FF14A-30C-R11DL-B-3H

F-RT-SM

CRITICAL

B4

B3

A4

A5

A2

C4

C5

D5

D4

E5

D3

E4

E3

D2

E1

D1

C2

C1

B1

C3

A1A3

E2

B5

U4820

VFBGA

PCAL6416A

10

11

6

7

8

9

4

3

2

1

5

U4850SLG4AP4103

TQFN

2

1R48225%

201

1/20WMF

2.0K

2

1R48232.0K

MF1/20W

201

5%

2

1R4802

1/20W

10K5%

MF201 2

1R4801

201MF

5%10K

1/20W

2

1R485210K

MF201

5%1/20W

2

1R485310K

MF1/20W

201

5%

2

1R485410K

201

5%1/20W

MF

KEYBOARD/TRACKPAD (1 OF 2)


PP3V3_S4

SMC_ACTUATOR_EN_L

SMC_LID

SMC_ACTUATOR_EN_R_L

TPAD_NC3

TPAD_VBUS_EN

TPAD_VBUS_EN_R

GND_ACTUATORMIN_NECK_WIDTH=0.2MMVOLTAGE=0V


SMC_PME_S4_WAKE_L

GND_ACTUATOR

PPVIN_S4_TPAD

TPAD_ACTUATOR_THRMTRIP_LSMBUS_SMC_2_S3_SCL

PP5V_S4_TPAD_F

VOLTAGE=5V


SMC_ONOFF_L

I2C_IOXP_SCL

PP3V3_S4

WS_KBD9

WS_LEFT_SHIFT_KEY

WS_KBD12WS_KBD8WS_KBD17

PP3V3_S4

WS_KBD19

IOXP2_RESET_L

WS_KBD10

WS_KBD3

WS_KBD20

WS_KBD1

WS_KBD5

PP3V3_S4

WS_KBD15_C


WS_KBD4WS_KBD20WS_KBD22WS_KBD21

I2C_IOXP_SCLI2C_IOXP_SDA

TP_IOXP1_1TP_IOXP1_0

TP_IOXP1_3TP_IOXP1_2

TP_IOXP1_4

WS_KBD16NSMC_ONOFF_LIOXP1_DEBUG

PP3V3_S4

WS_LEFT_OPTION_KEYWS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KBDWS_CONTROL_KEY

SMC_TPAD_RST_L

IOXP1_INT_L

PP3V3_S4

WS_KBD15_CAPWS_KBD16_NUM

WS_KBD8WS_KBD7

WS_CONTROL_KBDWS_LEFT_OPTION_KBDWS_LEFT_SHIFT_KBD

WS_KBD23WS_KBD22

WS_KBD19

WS_KBD21

WS_KBD9WS_KBD10

WS_KBD12WS_KBD11

WS_KBD13WS_KBD14

WS_KBD17WS_KBD18

WS_KBD6WS_KBD5WS_KBD4WS_KBD3

WS_KBD15_C

WS_KBD_ONOFF_L

WS_KBD2

WS_KBD16N

I2C_IOXP_SDA

IOXP1_LED_DRV

IOXP1_RESET_L

WS_CONTROL_KBD

WS_KBD6WS_KBD7

WS_KBD18


WS_CONTROL_KEYWS_LEFT_OPTION_KEY

IOXP2_INT_L

I2C_IOXP_SCL

WS_LEFT_SHIFT_KEY

PP3V3_S4

PP3V42_G3H

PP5V_S4

USB_TPAD_N

PP3V42_G3H

PPVIN_S4_TPAD

GND_ACTUATOR

I2C_IOXP_SDATPAD_SPI_INT_LTPAD_SPI_SCLK

TPAD_SPI_MOSITPAD_SPI_MISO

PP3V3_S4

TPAD_SPI_BUS_EN

SMBUS_SMC_2_S3_SDA

USB_TPAD_P

IOXP2_INT_LTPAD_NC4

TPAD_SPI_CS_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

48 OF 118

39 OF 82

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

41 42 43 72

72

39 72

34 41 43 72

39 72

39 46 70 72

65 72

41 44 72 81

39 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

39 72

39

39 72

39 72

39 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

39 72

39 72

39 72

39 72

39 72

39 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

39

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39

39 41 42 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71

72

39

39 72

39 72

39

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

72

72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39

72

39 72

39

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39 72

39

39

39 72

39 72

39

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

38 51 61 66 67 68 69 70 72

13 72 76

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

39 46 70 72

39 72

39 72

71 72

71 72 77

71 72 77

71 72 77

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

71 72

41 44 72 81

13 72 76

39 72

71 72 77

w w w

. c h

i n a

f i x

. c o

mNC

NC

OUT

VCC+

GND

Apple Inc.


124578

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Keyboard Backlight Connector

.

516S0899

X249 Boost Voltage Sense

Trip set at 13.5V (divider set for 1.45V)

Final Filter RC TBD

X249 BOOST UVP TRIP

9

8 7

6 5

4 3

2

10

1

14

13

12

11

J4915

CRITICAL

AA07A-S010-VA1F-ST-SM

2

1R4968X249:BOOST

1/16W

402

100K5%

MF-LF

2

1 C4960

25V

X249:BOOST

10%

X5R402

0.1UF

65 2 1

R4969X249:BOOST

402

1/16W5%

MF-LF

0

2

1R4962X249:BOOST

1%

402MF-LF1/16W

1M

2 1

R4967X249:BOOST

402

10M

MF-LF

5%1/16W

5

4

1

3

2

U4960

X249:BOOST

SC70-5

CRITICAL

LMV331

2

1C4964

PLACE_NEAR=U4960.3:5MM

402

0.1UF

X5R

10%25V

X249:BOOST

2 1

R4964

1/16WMF-LF

0

5%

402


X249:BOOST

2

1R4963

402MF-LF

787K1/16W

1%

X249:BOOST

21

XW4960SM

2

1R496684.5K

1/20W

201MF

1%

2

1

R4965

201

1/20W

MF

10.2K1%


KEYBOARD/TRACKPAD (2 OF 2)


PP3V3_S4

TPAD_BOOST_DIV_F

TPAD_BOOST_UVP_REF

VOUT_TPAD_BOOST_DIV

KBDBKLT_RETURN2

VOUT_TPAD_BOOST_XW

PPVOUT_S0_KBDBKLT

KBDBKLT_RETURN1

X249_BOOST_UVPTRIP_LTPAD_BOOST_UVPTRIP_L_R

PP28V_TPAD_OUT

VOUT_TPAD_BOOST_DIV

<BRANCH>

<SCH_NUM>

<E4LABEL>

49 OF 118

40 OF 82

20 34 39 42 43 46 47 65 66 67 69 70 71 72

40

63 72

63 72

63 72

65

40

w w w

. c h

i n a

f i x

. c o

mLPC0AD3

LPC0CLK

LPC0FRAME*

LPC0AD1

LPC0AD2

AIN08

AIN07

LPC0CLKRUN*

LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX

PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119

PP4/IRQ120

C0-

WT2CCP0/PH0

WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2

SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127

PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4

PF5

T1CCP0/PJ0

T2CCP0/PJ2

T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK

SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

INBI

BI

BI

BI

IN

IN

IN

BI

OUT

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

NC

OUT

BI

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

IN

IN

IN

NC

OUT

IN

IN

OUT

OUT

BI

IN

IN

IN

IN

BI

OUT

BI

BI

NC

NC

OUT

OUT

OUT

IN

BI

OUT

IN

Apple Inc.


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6 3



(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

If SMS interrupt is not used, pull up to SMC rail.

those designated as inputs require pull-ups.

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

H10

G4

H3

H4

J3

K4

K3

L7

K7

E12

E13

E11

F11

M1

L3

C5

D5

C8

A9

B9

C9

F3

F4

N9

M9

K10

L10

N1

L4

M3

M2

L6

M6

K5

N6N5

F5

E4

D4

K6

D8

L5

J13

J12

M5

L12M13

M11

N11

N12L11

D10

G3

L13

H11

A12C11

B12

J2

J4

K9

L9

C6

C4

L1

H13

F12

C13

F13

D12

G11

H12

D11

C12

A13

B13

N3

N4

M7

N7

K8

L8

M8

N8

N2

M4

D13

E10

L2

K1

K2

A8

B8

A7

B7

H2

H1

G1

G2

B2

B1

C2

C1

A6

B6

A5

B5

A4

B4

A3

B3

F1

F2

E1

E2

U5000

OMIT_TABLE

LM4FSXAH5BBBGA

N10

M10

N13

D2

D1

D6

K13

J6

J1

D3

J10

J9

J7

F10

E9

E8

E6

D7

K12

B10

A11

A10

C10G10

B11

G13G12

A2

M12

E3C3

J11

J8

J5

H9

H5

F9

E5

D9

K11

C7

A1

U5000

OMIT_TABLE

LM4FSXAH5BBBGA

2 1

XW5000

PLACE_NEAR=U5000.A1:4MM

SM

42 50 57 72

2

1 C50140.1UF

CERM-X5R0201

10%6.3V 2

1 C50150.1UF

CERM-X5R0201

10%6.3V 2

1 C50160.1UF

CERM-X5R0201

10%6.3V 2

1 C50170.1UF

CERM-X5R0201

10%6.3V2

1 C50130.1UF

CERM-X5R0201

10%6.3V

42

2

1R50021M

MF201

5%1/20W

2

1 C50060.1UF

X5R-CERM0201

10%16V2

1 C50050.1UF

X5R-CERM0201

10%16V

2

1 C50090.1UF

X5R-CERM0201

10%16V2

1 C50080.1UF

X5R-CERM0201

10%16V

2

1 C50040.1UF

X5R-CERM0201

10%16V2

1 C50030.1UF

X5R-CERM0201

10%16V

2

1 C50070.1UF

X5R-CERM0201

10%16V

13 77

13 77

13 77

13 77

19 77

13 77

20

13

12

12 20

14

37 44 48 68 71 72 81

37 44 48 68 71 72 81

44 48 81

44 48 81

39 44 72 81

39 44 72 81

43 81

43 81

43

43

44 56 57 72 81

44 56 57 72 81

43 46

43 46

43 46

43 45

43 45

43 45

43 45

43 46

43 45

43 46

43 45

43 47

43 45

43 47

43 46

43

43

43 47

43 46

43

43 47

43 47

43 46

43 46

42 61 67

12 72 77

19 29 30 42

42

38 42 76

38 42 76

43

50 77

50 77

50 77

50 77

38

43

18 19 58 67 72

42

12 18 77

12 19 72 77

2

1 C50010.1UF

CERM-X5R0201

10%6.3V

14

42

42

42

42

49

49

63

49

49

43

34 39 43 72

39 42 43 72

42

42 43 56 57

42

12 21 67 72

12 21 34 38 67 69 72

12 67

39 42 72

20 28 42 43

42 67

12 30 43

34 42 72

43

42

61 67

19 42

21

L500130-OHM-1.7A

0402

6 42 58 75

35

43 65

35

2

1 C50111UF

X5R402

10%25V2

1 C50101UF

X5R402

10%25V 2

1 C50121UF

X5R402

10%25V

56

12 18 19 72 77

42

6 75

43

43

12 42

43

43

2

1 C50200.01UF

X5R-CERM0201

10%10V 2

1 C50211UF

CERM402

10%6.3V

2

1C50021UF

CERM402

10%6.3V

43

34 67

35

39 72

65

43

43

SMC


SMC_RUNTIME_SCI_LSMC_WAKE_SCI_L

SMC_FAN_0_CTL SMC_VCCIO_CPU_DIV2SMC_S5_PWRGD_VIN

SMC_S2_ISENSE

LPC_FRAME_L

SMC_PCH_SUSWARN_L

SMC_PCH_SUSACK_L

SMC_LRESET_LLPC_SERIRQ

LPC_PWRDWN_L

NC_SMBUS_SMC_3_SDA

PP3V3_S5_SMC_VDDA

VOLTAGE=3.3V


PP1V2_S5_SMC_VDDC

VOLTAGE=1.2V


SMC_SYS_KBDLED

SMC_FAN_1_TACH

TP_SMC_MPM5_LED_CHG

CPU_PECI_R

SMC_FAN_0_TACH

NC_HISIDE_ISENSE_OC

SMC_PECI_L

SMC_BIL_BUTTON_L

SMC_PWRFAIL_WARN_L

SMC_RX_L

S5_PWRGD

SMC_ONOFF_L

PM_SLP_S4_L

PM_WLAN_EN

PP3V42_G3H

SMC_P1V35MEM_ISENSE

SMC_SSD_ISENSESMC_CHGR_BMON_ISENSE

SMC_OTHER3V3_HI_ISENSE

SMC_TMS

SMBUS_SMC_5_G3_SCL

SMC_TCK

SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SCL

PM_CLKRUN_L

SMBUS_SMC_5_G3_SDA

SMC_DCIN_VSENSE

SMC_LCDBKLT_ISENSE

SMC_TPAD_VSENSE

CPU_PROCHOT_L

CPU_CATERR_L

PM_DSW_PWRGD

SMC_DEBUGPRT_RX_L

NC_SYS_GFX_THROTTLE_L

SMC_DELAYED_PWRGDSMC_PROCHOT

NC_SMC_SYS_LED

SPI_SMC_MOSISPI_SMC_CLK

NC_SYS_GFX_OVERTEMP

SPI_SMC_CS_L

SMC_DEBUGPRT_EN_L

PM_SYSRST_L

WIFI_EVENT_L

SMC_CLK32K

SMC_EXTAL

SMC_OOB1_D2R_L

SPI_SMC_MISO

SMC_CPUPKG_ISENSE

SMC_WAKE_LSMC_TDO

SMC_PBUS_VSENSE

SMC_OTHER5V_HI_ISENSE

SMC_RESET_L

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

SMC_CPUPKG_VSENSE

SMC_TPAD_ISENSE

SMC_TBT_ISENSE

SMC_DEBUGPRT_TX_L

SMC_PCH_CORE_ISENSE

NC_SMC_ADC16NC_SMC_ADC15

NC_SMC_ADC18

SMC_TDI

SMC_XTAL

SMC_CPUDDR_ISENSE


SMC_X87_ISENSE

SMC_LCDPANEL_ISENSE

SMC_CPU_HI_ISENSE

NC_SMBUS_SMC_4_ASF_SDANC_SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_1_S0_SDASMBUS_SMC_2_S3_SCLSMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SCL

SMC_TX_L

PM_SLP_S5_L

PM_SLP_S3_L

PM_PCH_SYS_PWROK

SMC_ADAPTER_ENNC_MEM_EVENT_L

PM_PWRBTN_L

PM_BATLOW_L

SMC_TPAD_BOOST_DISABLE_LNC_IR_RX_OUT_RCSMC_OOB1_R2D_L

SMC_DCIN_ISENSE

SMC_THRMTRIPALL_SYS_PWRGD

SMC_FAN_1_CTL

SMC_BC_ACOKG3_POWERON_L

CPU_THRMTRIP_3V3

SMC_PM_G2_EN

SMS_INT_L

NC_SMBUS_SMC_3_SCL

SMC_CPU_IMON_ISENSE

SMC_DP_HPD_L

SMC_TOPBLK_SWP_L

SMC_PME_S4_WAKE_LSMC_PME_S4_DARK_LSMC_S4_WAKESRC_EN

SMC_ACTUATOR_EN_LSMC_LID

LPC_AD<0>

LPC_AD<3>LPC_AD<2>LPC_AD<1>

LPC_CLK33M_SMC

SYS_ONEWIRENC_SYS_TDM_ONEWIRESMC_ACTUATOR_DISABLE_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

50 OF 118

41 OF 82

42

42

19 35 38 39 42 43 44 50 56 57 65 67 70 72

42 50 72

42 50 72

42

42

42 72

42 45 46 47

42

42

w w w

. c h

i n a

f i x

. c o

mIN

OUT

BI

IN

IN

IN OUT

IN OUT

IN

OUT

IN

NC

NC

OUT BI

OUT

SYM_VER_2

G S

D

SN0903049

PAD

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

VER 3

D

S G

VER 3

D

S G

Apple Inc.


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6 3



Mac Mini: 5V

NOTE: Internal pull-ups are to VIN, not V+.

From/To CPU/PCH

SMC12 PECI SUPPORT

From SMC

To SMC

(IPU)

(IPU)

Mobiles: 3.42V

SMC Crystal Circuit

MR1* and MR2* must both be low to cause manual reset.

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

SMC Reset "Button", Supervisor & AVREF Supply

Used on mobiles to support SMC reset via keyboard.

Debug Power "Buttons"

21R5170 10KMF1/20W 2015%

21R5171 100KMF1/20W 2015%

21R5173 10KMF1/20W 2015%

21R5174 100KMF1/20W 2015%

21R5177 10KMF1/20W 2015%

21R5178 10KMF1/20W 2015%

21R5179 10KMF1/20W 2015%

21R5180 10KMF1/20W 2015%

21R5185 10KMF1/20W 2015%

41 42

14 77

2

1R5115PLACE_SIDE=BOTTOM

SILK_PART=PWR_BTN

603MF-LF1/10W

OMIT

05%

6 41 58 75

41

21R5189 10KMF1/20W 2015%

21R5181 10KMF1/20W 2015%

21R5187 470KMF1/20W 2015%

21R5193 10KMF1/20W 2015%

21R5172 10KMF1/20W 2015%

2

1R5116

1/10W

OMIT

603

SILK_PART=PWR_BTN

MF-LF

PLACE_SIDE=TOP 05%

2

1R5101OMIT

SILK_PART=SMC_RST

603MF-LF1/10W

PLACE_SIDE=BOTTOM

05%

39 41 42 72

39

2

1C5101

10V

0.01UF10%

X5R-CERM0201 2

1C5125

6.3V

603X5R

10uF20%

2

1 C5126

X5R-CERM

0.01UF10%10V

0201

41 50 57 72

12 21

R5112

PLACE_NEAR=U1100.Y6:5.1mm

22

MF1/20W

201

5%

41

21R5190 100KMF1/20W 2015%

21R5175 20KMF1/20W 2015%

21R5176 20KMF1/20W 2015%

21R5186 10KMF1/20W 2015%

21R5169 100KMF1/20W 2015%

2

1R5131330

MF1/20W

201

5%

2

1R5133

0201

OMIT

NOSTUFF

NONE

NONENONE

21

R5132

MF1/20W

0201

0

5%

41

2

1R5197

1%100K

MF1/20W

201

2

1R5196

1%100K

MF1/20W

201

21R5192 100KMF1/20W 2015%

41 42

6 14 75

21R5194 100KMF1/20W 2015%

21R5195NOSTUFF 10KMF1/20W 2015%

2

3

1Q5158DFN1006-3

MMBT3904LP-7

CRITICAL

21

R513443

MF1/20W

201

5%

41 6 14 75

39 41 42 72

21

R51583.3K

MF1/20W

201

5%

21R5198 100KMF1/20W 2015%

21R5191 100KMF1/20W 2015%

2

1 C5111

CERM

5%

0201

25V

12PF

2

1 C5110

0201CERM

5%25V

12PF

21

R5110

1%1/20W

2.49K

MF201

31

42

Y51103.2X2.5MM-SM-1

CRITICAL

12.000MHZ-30PPM-10PF-85C

2

1C5120

6.3V10%

402CERM-X5R

0.47UF

2

1 C5127

NO STUFF

20%6.3V

4.7UF

402X5R

2

1R5100100K

MF1/20W

201

5%

21

R51270

5%1/16WMF-LF402

21

3Q5130CRITICAL

DFN1006H4-3DMN32D2LFB4

31

9

5

8

7

6

2

4

U5110VREF-3.3V-VDET-3.0V

DFN

CRITICAL

45

3Q5159SOT563DMN5L06VK-7

12

6Q5159SOT563

DMN5L06VK-7


SMC Shared Support

SMC_XTAL_R

SMC_EXTAL


SMC_THRMTRIP

CPU_THRMTRIP_3V3

SMC_LID

PP3V42_G3H

GND_SMC_AVSSMIN_LINE_WIDTH=0.4 mm

VOLTAGE=0VMIN_NECK_WIDTH=0.1 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3VMIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.4 mm

SMC_TPAD_RST_L SMC_RESET_L

SMC_MANUAL_RST_L

SMC_ONOFF_L

SMC_XTAL

PP1V05_S0

PM_THRMTRIP_B_L

PM_THRMTRIP_L

SMC_CLK32K

SMC_PECI_L SMC_PECI_L_R

SMC_RX_L

G3_POWERON_L

SMC_DEBUGPRT_TX_L

SMC_TMS

SMC_PME_S4_DARK_L

SMC_TDO

SMC_S5_PWRGD_VIN

SMC_DELAYED_PWRGD

SMC_S4_WAKESRC_EN

SMC_PM_G2_EN

WIFI_EVENT_L

SMC_DEBUGPRT_RX_L

SMC_ONOFF_L

SMC_TCK

SMC_TX_L

SMC_BIL_BUTTON_L

SMC_TDI

SMC_BC_ACOK

SMS_INT_L

PP1V05_S0

PP3V3_WLAN

PP3V42_G3H

PP3V3_S4

CPU_PECICPU_PECI_R

SMC_VCCIO_CPU_DIV2

CPU_THRMTRIP_3V3

SMC_ADAPTER_EN

PM_CLK32K_SUSCLK_R

PP3V42_G3H_SMC_SPVSRMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.1 mmVOLTAGE=3.42V

PP3V42_G3H

SMC_ONOFF_L

PM_THRMTRIP_L_R

SMC_THRMTRIP

CPU_PROCHOT_L

SMC_PROCHOT

<BRANCH>

<SCH_NUM>

<E4LABEL>

51 OF 118

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41

19 41

41 42

41 42

39 41 43 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

41 45 46 47

41 72

41

10 14 15 17 18 42 62 67 70 72

41

41

38 41 76

41 50 72

20 28 41 43

41

41

19 29 30 41

41 67

41 61 67

34 41 72

38 41 76

39 41 42 72

41 50 72

41

41

41

41 43 56 57

41

10 14 15 17 18 42 62 67 70 72

34 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

20 34 39 40 43 46 47 65 66 67 69 70 71 72

41

12 41

19 35 38 39

41 42

43 44

50 56

57 65

67 70

72

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NC

NC

NC

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUTIN

OUT IN

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Spare S4 IRQ

APN: 998-3029

Hall Effect pads

8

7

6

54

3

2

1

J5250SM

HALL-SENSOR-MLB-PADS-K99

OMIT_TABLE

2

1 C5250

50V10%

0402X7R-CERM

0.001UF

21

R5250

1/20W5%

0201MF

0 41

12 30 41 43

21

R5283

1/20W5%

201MF

1K

34 39 41 43 72

34 39 41 43 72

12 30 41 43

12

2

1R5282

1/20W5%

201MF

100K

34 39 41 43 72

2

1R52595%1/20W

201MF

100K

41

21

R5230SMC_SUSACK:YES

1/20W5%

201MF

0

12 21

R5231

1/20W5%

201MF

0

SMC_SUSACK:YES

41

41 12

J52501607-6811 SUBASSY,PCBA HALL EFFECT,K99 CRITICAL

SMC Project Support

PCH_SUSWARN_L

NC_SMBUS_SMC_3_SDA

NC_SMBUS_SMC_4_ASF_SDAMAKE_BASE=TRUE NO_TEST=TRUENC_SMBUS_SMC_3_SCL

NO_TEST=TRUEMAKE_BASE=TRUE

SMC_PCH_SUSWARN_L

SMC_DP_HPD_L

SMC_DCIN_VSENSEMAKE_BASE=TRUE

SMC_PCH_SUSACK_L

NC_SMC_ADC15

SMC_S2_ISENSE

SMC_TPAD_VSENSEMAKE_BASE=TRUE

SMC_TPAD_BOOST_DISABLE_LMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_SMC_ADC16

NO_TEST=TRUENC_SMC_ADC15MAKE_BASE=TRUE

SMC_CPU_IMON_ISENSEMAKE_BASE=TRUE

SMC_OTHER5V_HI_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_CPUDDR_ISENSE

SMC_P1V35MEM_ISENSEMAKE_BASE=TRUE


SMC_LCDPANEL_ISENSE

SMC_CHGR_BMON_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_SSD_ISENSE

SMC_TPAD_ISENSEMAKE_BASE=TRUE

SMC_CPUPKG_ISENSEMAKE_BASE=TRUE

NC_HISIDE_ISENSE_OC

SMC_BC_ACOK SMC_BC_ACOKMAKE_BASE=TRUENC_HISIDE_ISENSE_OC

NO_TEST=TRUEMAKE_BASE=TRUE

NC_IR_RX_OUT_RC

SMC_CPU_IMON_ISENSE

SMC_PCH_CORE_ISENSE

MAKE_BASE=TRUESMC_S2_ISENSE

SMC_LCDBKLT_ISENSEMAKE_BASE=TRUE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_DCIN_VSENSE

SMC_CPUPKG_ISENSE

SMC_CHGR_BMON_ISENSE

SMC_PME_S4_DARK_L

SMC_PBUS_VSENSEMAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

SMC_PME_S4_WAKE_L

NC_SMC_ADC16

PCH_SUSACK_L

PCH_STRP_TOPBLK_SWP_LSMC_TOPBLK_SWP_L

MAKE_BASE=TRUE NO_TEST=TRUENC_SMC_SYS_LED

PP3V42_G3HSMC_LID_R

PP3V3_S4

SMC_LCDBKLT_ISENSE


SMC_SSD_ISENSE

MAKE_BASE=TRUESMC_DCIN_ISENSE

SMC_OTHER3V3_HI_ISENSEMAKE_BASE=TRUE

NC_SYS_GFX_THROTTLE_LNO_TEST=TRUEMAKE_BASE=TRUE

SMC_P1V35MEM_ISENSE

SMC_TPAD_ISENSE

SMC_CPU_HI_ISENSEMAKE_BASE=TRUESMC_CPU_HI_ISENSE

SMC_CPUPKG_VSENSEMAKE_BASE=TRUE

SMC_LID

MAKE_BASE=TRUEPM_BATLOW_L

MAKE_BASE=TRUESMC_PME_S4_WAKE_L

PP3V3_S4

PM_BATLOW_L

SMC_TPAD_BOOST_DISABLE_L

NC_SMBUS_SMC_4_ASF_SDA

SMC_TBT_ISENSE

SMC_CPUDDR_ISENSE

SMC_CPUPKG_VSENSE

NO_TEST=TRUEMAKE_BASE=TRUENC_SMC_ADC18

SMC_LCDPANEL_ISENSEMAKE_BASE=TRUE

NC_IR_RX_OUT_RCNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_SYS_GFX_OVERTEMP

NC_MEM_EVENT_L

NC_SMC_SYS_LED

NC_SYS_TDM_ONEWIRENO_TEST=TRUEMAKE_BASE=TRUE

NC_MEM_EVENT_LMAKE_BASE=TRUE NO_TEST=TRUE

SMC_PME_S4_DARK_L

NC_SMBUS_SMC_3_SDAMAKE_BASE=TRUE NO_TEST=TRUE

NC_SMBUS_SMC_3_SCL

NC_SMC_ADC18

SMC_PCH_CORE_ISENSEMAKE_BASE=TRUE

NC_SYS_GFX_OVERTEMP

NC_SYS_GFX_THROTTLE_L

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUESMC_PME_S4_DARK_L

NC_SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCLMAKE_BASE=TRUE NO_TEST=TRUE

SMC_TBT_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_X87_ISENSESMC_X87_ISENSE

SMC_TPAD_VSENSE

<BRANCH>

<SCH_NUM>

<E4LABEL>

52 OF 118

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41 43

41 43 81

41 43 45

41 43

41 43 47

41 43 46

41 43 65

41 43

41 43

41 43 46

41 43 45

41 43 47

41 43 46

41 43 45

41 43 47

41 43 45

41 43 46

41 43 46

41 43 46

41 43

41 42 43 56 57 41 42 43 56 57

41 43

41 43

41 43 46

41 43 46

41 43 47

41 43 47

41 43 45

41 43 45

41 43 45

41 43 46

41 43 45

20 28 41 42 43

41 43 45

41 43

41 43

19 35 38 39 41 42 44

50 56 57 65 67

70 72

72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

41 43 47

41 43 45

41 43 46

41 43 45

41 43 45

41 43

41 43 46

41 43 46

41 43 45 41 43 45

41 43 46

39 41 42 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

41 43 65

41 43

41 43 46

41 43 47

41 43 46

41 43

41 43 47

41 43

41 43

41 43

41 43

41 43

41 43

20 28 41 42 43

41 43 81

41 43 81

41 43

41 43 46

41 43

41 43

41 43

20 28 41 42 43

41 43 41 43

41 43 46

41 43 47 41 43 47

41 43 46

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SMC "3" SMBUS CONNECTIONS

(Write: 0x98 Read: 0x99)

PCH SMBus "0" Connections

ISL6258 - U7100

SMC

SMC "0" SMBus Connections

U5000

Lynx Point

U1100

(MASTER)

(WRITE: 0xCC READ: 0xCD)

HDMI Redriver (on RIO)J9510 -> U9700


Lynx Point

SMLink 1 is slave port to

(MASTER)

(MASTER)

U5000

SMC

U1100

(MASTER)


SMC

(MASTER)

U5000

CPU/DDR3/PCH/AIRFLOW TEMP


EMC1414-A: U5870

U5000

(MASTER)


J7050


Battery

Battery Charger

Unused

U5000

(MASTER)

SMC


SMC

(MASTER)

U5000

Unused

PCH "SMLink 0" Connections

PCH "SMLink 1" Connections

access PCH & CPU via PECI.


U1100

Lynx Point


XDP Connectors

J1800 & J1850


ALS

J4002

(MASTER)

EMC1412-A: U5860

L&R Fin Stack Temp

J4801

Trackpad

NOTE: SMC RMT bus remains powered and may be active in S3 state


SMC


J8300

eDP Connector

(WRITE: 0X92 READ: 0X93)

TMP105: U5823

X87 TEMP

2

1R53805%

201MF

2.0K1/20W

2

1R53815%

201

1/20WMF

2.0K

2

1R5370

1/20W

1K5%

201MF

2

1R53715%

201

1/20WMF

1K

2

1 R53515%1/16W

402MF-LF

2.0K

2

1R53505%

402

1/16WMF-LF

2.0K

2

1R53105%

8.2K

MF-LF402

1/16W

2

1R53115%8.2K

MF-LF402

1/16W

2

1R53215%

201

1/20WMF

8.2K

NO STUFF

2

1R53205%

201

1/20WMF

8.2K

NO STUFF

21

R53235%0

0201

1/20WMF

21

R53225%0

0201

1/20WMF

2

1R53015%1K1/16WMF-LF4022

1R53005%1K

402

1/16WMF-LF

2

1R53615%

201

1/20WMF

1K

2

1R53605%

201

1/20WMF

1K

SYNC_DATE=11/26/2012SYNC_MASTER=CHANG_J45

SMBus Connections

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SCLMAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDAMAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_2_S3_SDA

PP3V3_S3


SMBUS_SMC_0_S0_SCL

PP3V3_S0

SMBUS_SMC_0_S0_SDA

SMBUS_PCH_DATA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_PCH_CLK

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUESML_PCH_1_CLK

MAKE_BASE=TRUESML_PCH_0_CLK

SML_PCH_0_DATAMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUESML_PCH_1_DATA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_5_G3_SCL

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PP3V42_G3H

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCL

PP3V3_S0

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

PP3V3_S0

PP3V3_S0

PP3V3_S0

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SDA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA


MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUESMBUS_PCH_CLK

MAKE_BASE=TRUESMBUS_PCH_DATA

SMBUS_SMC_2_S3_SDAMAKE_BASE=TRUE

<BRANCH>

<SCH_NUM>

<E4LABEL>

53 OF 118

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41 44 48 81

41 44 48 81

41 44 48 81

37 41 44 48 68 71

72 81

39 41 44 72 81

13 20 21 46 47 66 69 70 72

39 41 44 72 81

37 41 44 48 68 71 72 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

37 41 44 48 68 71

72 81

13 18 44 69 71 72 77

37 41 44 48 68 71

72 81

37 41 44 48 68 71

72 81

13 18 44 69 71 72 77

39 41 44 72 81

13 77

13 77

13 77

41 44 56 57 72 81

41 44 56

57 72 81

13 77

37 41 44 48 68 71

72 81

41 44 56 57 72 81

41 44 48 81

41 44 56 57 72 81

41 44 56 57 72 81

41 44 56 57 72 81

19 35 38 39 41 42 43 50 56 57 65 67 70 72

41 44 56 57 72 81

41 44 56 57 72 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

41 44 48 81

41 44 48 81

41 44 48 81

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

39 41 44 72 81

41 44 48 81

13 18 44 69 71 72 77

13 18 44 69 71 72 77

37 41 44 48 68 71

72 81

37 41 44 48 68 71 72 81

37 41 44 48 68 71 72 81

37 41 44

48 68 71 72 81

39 41 44 72 81

13 18 44 69 71 72 77

13 18 44 69 71 72 77

39 41 44

72 81

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INOUTIN

OUT

OUT

V+

REFIN+

IN- OUT

GND

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNELOUT

IN

OUT OUTIN-

IN+ REF

V+

GND

OUTIN-

IN+ REF

V+

GND

D

S

G

G

S

DP-CH

N-CH

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SMC_ADC13

SMC Key IO5R

DC-In Voltage Sense Enable & Filter

From charger

CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER DC-IN (AMON) Current Sense Filter

EDP Current:5A

Gain:100x

OTHERS (5V) High Side Current Sense / Filter

SMC Key IO3R

SMC_ADC9

SMC_ADC8

SMC_ADC7IPBR

EDP Current:4.6A

SMC Key ID0RSMC_ADC4

Divider set for Vin max of 13.98VRTHEVENIN = 4508 Ohms

divider when in S0.

PBUS Voltage Sense Enable & Filter

SMC Key IC0R

Power Drop across R5400 at EDP becomes 1.21W

OTHERS (3.3V) High Side Current Sense / Filter

Gain:100x

EDP Current:5A

SMC_ADC3divider when SUS present.

Enables PBUS VSense

SMC Key VP0RSMC KEY VD0R

RTHEVENIN = 4567 Ohms

SMC_ADC5

Divider set for Vin max of 22.32V

Enables DC-In VSense

COMPUTING High Side Current Sense / Filter

EDP Current:21.6A

Gain:50x

57 41 43 57

2

1 C5403PLACE_NEAR=U5000.B5:5MM

0.22UF

0201

20%6.3VX5R

21

R54034.53K

PLACE_NEAR=U5000.B5:5MM

1%1/20WMF201

41 43

21

R5433PLACE_NEAR=U5000.A5:5MM

1%

4.53K

MF1/20W

201

2

1 C5433PLACE_NEAR=U5000.A5:5MM

0201

6.3VX5R

0.22UF20%

41 43

3

1

6

4

5

2

U5400INA213SC70

CRITICAL

2

1 C5401

20%0.1UF

402

10VCERM

2

1 C5431

402

0.1UF20%

CERM10V

4

3

2

1

R54000612

CRITICAL

1%

0.003

TFT1.5W

4

3

2

1

R54300612-3

0.005

MF

1%

CRITICAL

1W

41 43

2

1 C54210.022UF10%6.3V

PLACE_NEAR=U5000.A4:5MMX5R-CERM0201

21

R5423

1/20WMF

45.3K

1%


201

21

R5441PLACE_NEAR=U5000.B3:5MM

201

1/20WMF

1%

45.3K

2

1 C5441PLACE_NEAR=U5000.B3:5MM

0201

2200PF

X7R-CERM10V10%

2

1R5402

1%100K

1/16WMF-LF402

31 32 67

41 43

2

1R540119.1K

1%

MF1/20W

201


2

1 C5404

6.3V20%0.22UF

X5R0201


2

1R5404

MF1/20W

201


1%5.90K

4

1

5

2

3

6

Q5400

SOT-963

CRITICAL

NTUD3169CZ

2

1R5405

1/16WMF-LF402

100K1%

41 43

2

1R5412

1/16W1%

402MF-LF

100K

12 66 67

2

1R5413

MF201

30.9K1%

1/20WPLACE_NEAR=U5000.F1:5MM

2

1 C5414

X5R0201

PLACE_NEAR=U5000.F1:5MM

0.22UF20%6.3V

2

1R5414

201

PLACE_NEAR=U5000.F1:5MMMF

1/20W1%

5.36K

2

1R5411

1/16W

402MF-LF

1%100K

2

1R5409

402

20K1/16WMF-LF

5%


2

1R5439

402

20K


5%1/16WMF-LF

41 43

2

1 C5426

20%

X5R0201

6.3V

0.22UF

PLACE_NEAR=U5000.C2:5MM

21

R5426

201MF

4.53K

1%1/20W


2

1R5429

402

20K


MF-LF1/16W5%

2

1 C5422

10VCERM

20%0.1UF

402

4

3

2

1

R54200612-3

1W

CRITICAL

1%

MF

0.005

3

1

6

4

5

2

U5430INA214

CRITICAL

SC70

3

1

6

4

5

2

U5420INA214

CRITICAL

SC70

4

1

5

2

3

6

Q5410SOT963

DMC31D5UDJ

High Side Voltage and Current Sensing


PPVIN_S5_HS_COMPUTING_ISNS

SMC_DCIN_VSENSE

GND_SMC_AVSS

PM_SLP_S3_R_L

SMC_PBUS_VSENSE

ISNS_HS_OTHER5V_N

ISNS_HS_OTHER5V_P

HS_OTHER3V3_IOUTISNS_HS_OTHER3V3_N

ISNS_HS_OTHER3V3_P

PP3V3_S0

ISNS_HS_COMPUTING_P

PPBUS_G3H

ISNS_HS_COMPUTING_N SMC_CPU_HI_ISENSE

PBUS_S0_VSENSE

PPBUS_G3H

GND_SMC_AVSS

PBUSVSENS_EN_L

HS_COMPUTING_IOUT

PBUSVSENS_EN_L_DIV

GND_SMC_AVSS

SMC_DCIN_ISENSECHGR_AMON

GND_SMC_AVSS

SMC_CHGR_BMON_ISENSECHGR_BMON

GND_SMC_AVSS

PPVIN_S5_HS_OTHER5V_ISNS

PPBUS_G3H

GND_SMC_AVSS

PPVIN_S5_HS_OTHER3V3_ISNS

PPBUS_G3H


PP3V3_S0

PP3V3_S0

HS_OTHER5V_IOUT

DCINVSENS_EN_L

PM_SLP_SUS_L

PDCINVSENS_EN_L_DIV

PPDCIN_G3H_ISOL

DCIN_S5_VSENSE

GND_SMC_AVSS


<BRANCH>

<SCH_NUM>

<E4LABEL>

54 OF 118

45 OF 82

58 59 60 62 70

41 42 45 46 47

82

82

82

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

82

30 45 56 57 63 65 70 72

82

30 45 56 57 63 65 70 72

41 42 45 46 47

41 42 45 46 47 41 42 45 46 47

41 42 45 46 47

61 70

30 45 56 57 63 65 70 72

41 42 45 46 47

61 70

30 45 56 57 63 65 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

56 57 70

41 42 45 46 47

w w w

. c h

i n a

f i x

. c o

m

OUT

V-

V++

-

V-

V++

-OUT

V-

V++

-

IN

IN

IN

IN

IN

IN

V-

V++

-

IN

OUT

OUT

OUT

GND

OUT

VIN+ VIN-

V+

IN

V-

V++

-

OUT

OUT

OUT

V-

V++

-

OUT

IN

IN

OUT

Apple Inc.


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REVISION

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6 3



SMC_AD2ITPC

IC2CSMC_ADC14

TRACKPAD CURRENT SENSE

CPU Vcore Voltage Sense / Filter

GAIN: 165.56X

Gain:137.77x

VTPC

Sense Resistor R7640 0.001 Ohm on PCH regulator page

EDP CURRENT: 5A

GAIN: 333X

VC0C

SMC_ADC23

IC1C

EDP CURRENT: 0.94 A

Max VOut: 3.3V at 95.8AScale: 29.03A / V

CPU PKG Load Side Current Sense / Filter

IC0CSMC_ADC1

GAIN: 274X

EDP CURRENT: 5A

Sense Resistor 0.005 Ohm

SSD CURRENT SENSE

IHDCSMC_ADC6

GAIN:136.6X

Individual Sense R is 0.75mOhm

(Effective Sense R is 0.25mOhm due to summing of the 3 phases)EDP: 95A TDP :45A

SMC_ADC19

PCH CORE CURRENT SENSE

SMC_ADC10

IM0C

SMC_ADC0

EDP CURRENT:8AIHSC

SENSE RESISTOR 0.010 OHM DDR3L 1.35V DRAM ONLY CURRENT SENSE / FILTER

TBT Router CURRENT SENSE

TRACK PAD VOLTAGE SENSE

SMC_ADC21

CPU Load Side (IMON) Current Sensor

Vsense: 52.2 mV, Range: 5 A

Gain: 24.9x, EDP: 2.61 A (Transient)

Rsense: 0.02 (R5510)

RTHEVENIN = 4494 Ohms

Divider set for Vin max of 33.3V

Gain: 1000uA/V * 24.9kOhm = 24.9x

41 43 21

R5577

1%

4.53K

MF1/20W

201

PLACE_NEAR=U5000.B6:7mm

2

1 C5577

0201

0.22UF20%6.3VX5R

PLACE_NEAR=U5000.B6:5mm

21

R55737.32K

1%

MF-LF1/16W

402

21

R5576

MF-LF

1%

402

1/16W


1M

2

1R55751M1%1/16WMF-LF402

21

R5574

1/16W1%

7.32K

MF-LF402

5

2

4

3

1

U5560OPA333DCKG4SC70-5

2

1 C5560

10VX7R-CERM

20%

0402

0.1UF

2

1 C5540

20%6.3VX5R

0201

PLACE_NEAR=U5000.B4:5MM0.22UF

21

R5564


201

1%

MF1/20W

4.53K

2

1 C55580.1UF

402

20%

CERM10V

5

2

4

3

1

U5540

SC70-5OPA333DCKG4

21

R55631M

1%

MF-LF1/16W

402


2

1R55621M1%1/16W


402MF-LF

21

R5504

402

MF-LF

1%

1/16W

6.04K

21

R5561

402

1%

1/16W

MF-LF

6.04K41 43

2

1 C5501

0201X5R6.3V20%

PLACE_NEAR=U5000.E1:5MM

0.22UF SENSOR_NONPROD:Y

21

R5506

1%

MF201


1/20W

4.53K

SENSOR_NONPROD:Y

2

1 C5550SENSOR_NONPROD:Y

20%

0402

0.1UF10V


X7R-CERM

5

2

4

3

1

U5550

SC70-5

OPA333DCKG4

CRITICAL

SENSOR_NONPROD:Y

21

R5555


732K

SENSOR_NONPROD:Y

1/16W1%

402MF-LF

21

R5503

1/16W1%

MF-LF402

3.57K

SENSOR_NONPROD:Y

2

1R5554SENSOR_NONPROD:Y

402

1/16W

732K1%

MF-LF


21

R5507

MF-LF

SENSOR_NONPROD:Y

1/16W1%

402

3.57K

21

R5505PLACE_NEAR=R7310.3:5MM

0.5%1/16W

SENSOR_NONPROD:Y

402


5.23K

MF

59 82

21



SENSOR_NONPROD:Y

5.23K

1/16WMF402

0.5%

21

R5508SENSOR_NONPROD:Y

5.23K

PLACE_NEAR=R7320.3:5MM

0.5%

402

1/16WMF


21

R5570

1/16WNO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y

0.5%

402

5.23K

MF


21



SENSOR_NONPROD:Y

1/16WMF402

0.5%

5.23K

59 82

59 82

59 82

59 82

21

R5572

MF402


5.23K

0.5%1/16W


SENSOR_NONPROD:Y

59 82

2

1 C55000.22UF

X5R

20%

0201

6.3V


21

R5502

MF


1/20W

4.53K

1%

201

2

1 C5551

402

CERM10V20%0.1UF

5

2

4

3

1

U5500

SC70-5OPA333DCKG4

21

R5501

1/20WMF

1%

1M

201


2

1R5553

201

1/20WMF

1M1%

21

R5551

201MF

1/20W

3.65K

1%

21

R5552

201

3.65K

1/20WMF

1%

4

3

2

1R5559

1206-1MF

1%1/2W

0.010

CRITICAL

21

R5530


MF-LF1/16W5%

402

058

4

3

2

1R5560

0612

1%

MF1W

CRITICAL0.003

43

21

R5549

MF1W1%

0.005

CRITICAL

0612-3

41 43

41 43

2

1 C5530


NOSTUFF

0.22UF20%6.3VX5R0201

41 43

2

1C5510

BYPASS=U5510.5::5MM

20%10V

402CERM

0.1UF

43

5 1

2

U5510SOT23-5INA139

CRITICAL

46 65

70

2

1R5511

1%24.9K

402MF-LF1/16W

2

1C55110.1UF

20%

402CERM10V

BYPASS=U5511.5::5MM

5

2

1

4

3

U5511CRITICAL

SOT-23

OPA340NA

39 70 72

2

1 C5514

PLACE_NEAR=U5000.F2:5MM0201

X5R

6.3V

0.22UF20%

41 43 21

R5514PLACE_NEAR=U5000.F2:5MM

4.53K

1/20W

1%

MF

201

2

1R5581

1/20W

4.99K1%

MF201

2

1R5580

MF

45.3K

1/20W1%

201

2

1 C5580PLACE_NEAR=U5000.A7:10MM

0.22UF20%6.3VX6S-CERM0201

41 43

5

2

4

3

1

U5590

SC70-5OPA333DCKG4

41 43

2

1 C55910.22UF

0201X5R

6.3V20%

PLACE_NEAR=U5000.H2:5MM

21

R55954.53K

1%

PLACE_NEAR=U5000.H2:7MM

1/20W

MF201

2

1 C5590

10V

CERM

20%

402

0.1UF

21

R5594

MF-LF

1%1/16W

1M


402

2

1R5593

1/16W

402


1%

1M

MF-LF

21

R5591

MF

3.0K

0201

1/20W0.1%

21

R55923.0K

MF0201

0.1%1/20W

62 82

62 82

21

R551810K

201

1%1/20WMF

2

1R55191%1/20W

10K

MF201

43

21

R55101%1WTF

0612

0.02

PLACE_NEAR=U5510.3:3MM PLACE_NEAR=U5510.4:3MM

CRITICAL

41 43 21

R55204.53K

1%

MF201

1/20W


2

1 C5520PLACE_NEAR=U5000.E2:5MM

0201

6.3VX5R

20%0.22UF

21

XW5520

PLACE_NEAR=R7310.2:5 MM

SM

SYNC_MASTER=CLEAN_X305_PEG

Load Side Voltage and Current Sensing


GND_SMC_AVSS

ISNS_TPAD_P

PPBUS_S4_TPAD PPVIN_S4_TPAD

SMC_TPAD_VSENSE

PP3V3_S4

PP3V3_S4

ISNS_TPAD_N

ISNS_TBT_R_NISNS_TBT_N

ISNS_SSD_IOUT

PP3V3_S4

ISNS_1V35_MEM_R_N

ISENSE_P1V35MEM_IOUT

PP3V3_S3

CPUVR_ISNS_N

PP1V35_S3

ISNS_PCH_R_P

ISNS_PCH_IOUT

ISNS_PCH_R_N

PPVCC_S0_CPU

CPUVR_IMON

SMC_TBT_ISENSE

ISNS_TBT_R_P

ISNS_1V35_MEM_P

ISNS_1V35_MEM_N

GND_SMC_AVSS

SMC_P1V35MEM_ISENSE

GND_SMC_AVSS

PP1V35_S3_MEM

CPUVR_ISNS3_N

SMC_SSD_ISENSE

PP3V3_S0

ISNS_SSD_R_N

ISNS_SSD_P

PP3V3_S0SW_SSD_R

ISNS_SSD_N

PP3V3_S0SW_SSD

GND_SMC_AVSS

PP3V3_S0

CPUVR_ISNS1_P

CPUVR_ISNS2_P

SMC_CPUPKG_ISENSE

CPUVR_ISNS_P

CPUVR_ISUM_R_N

CPUVR_ISUM_IOUT

CPUVR_ISNS2_N

CPUVR_ISNS1_N

ISNS_TBT_P

GND_SMC_AVSS

SMC_CPUPKG_VSENSE

GND_SMC_AVSS

ISNS_SSD_R_P

CPUVR_ISUM_R_PCPUVR_ISNS3_P

P1V05S0_CS_N

P1V05S0_CS_P

CPUVSENSE_IN

PP3V3_S0

SMC_PCH_CORE_ISENSE

ISNS_1V35_MEM_R_P

PP3V3_S4_TBT

GND_SMC_AVSS

ISNS_TBT_IOUT

PPBUS_S4_TPAD

PP3V3_S4

GND_SMC_AVSS

SMC_TPAD_ISENSE_R

SMC_CPU_IMON_ISENSE

SMC_TPAD_ISENSE

GND_SMC_AVSS

ISNS_TPAD_IOUT_FDBK

ISNS_TPAD_IOUT_BUF

<BRANCH>

<SCH_NUM>

<E4LABEL>

55 OF 118

46 OF 82

41 42 45 46 47

82

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47

65 66 67 69

70 71 72

82

82

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

82

13 20 21 44 47 66 69 70 72

21 60 66 70 72

82

82

6 8 10 59 70 72

82

82

41 42 45 46 47

41 42 45 46 47

22 23 24 25 26 70 78

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

82

82

66 70

82

35 70 72

41 42 45 46 47

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

82

82

82

41 42 45 46 47

41 42 45 46 47

82

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

82

28 29 30 70

41 42 45 46 47

46 65 70

20 34 39 40 42 43 46 47

65 66 67 69 70 71

72

41 42 45 46 47

41 42 45 46 47

w w w

. c h

i n a

f i x

. c o

mOUTIN-

IN+ REF

V+

GND

IN

V-

V++

-

IN

OUTIN-

IN+ REF

V+

GND

V-

V++

-

V-

V++

-

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN


Apple Inc.


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LCD BKLT Current Sense

EDP Current: 0.75A

LCD PANEL CURRENT SENSE

ILDCSMC_ADC12

IC3CSMC_ADC11

Gain: 316x IBLC

Sense Resistor 0.010 Ohm

EDP Current: 820mA

Sense Resistor 0.005 OhmEDP Current: 1.06A

.

ICMCSMC_ADC20

GAIN: 332X

GAIN: 100X

SMC_ADC17

GAIN: 100X

SMC_ADC22IAPC

EDP CURRENT: 1.0A

S2 CAMERA CONTROLLER CURRENT SENSE

GAIN: 822X

EDP CURRENT: 4.2A

X87 AIRPORT CURRENT SENSE

CPU DDR CURRENT SENSE

2


10V

402CERM

0.1UF20%

21

R5684

SENSOR_NONPROD:Y

1M

1/20W

MF

1%

201


21

R5681SENSOR_NONPROD:Y

MF1/20W

1%

201

3.16K

21

R56823.16K

MF1/20W

1%

201SENSOR_NONPROD:Y

2

1R56831%1M1/20W

MF201


SENSOR_NONPROD:Y

3

1

6

4

5

2

U5670

SENSOR_NONPROD:Y

SC70INA214

2


0.1UF

CERM402

20%10V

68 82

5

2

4

3

1

U5682SC70-5OPA333DCKG4

SENSOR_NONPROD:Y

68 82

2

1 C5601

0201X5R

PLACE_NEAR=U5000.G1:5MM

0.22UF

SENSOR_NONPROD:Y

20%6.3V

2


10V20%

402CERM

0.1UF

21

R5601

SENSOR_NONPROD:Y

4.53K

MF

PLACE_NEAR=U5000.G1:7MM

1%1/20W

201

3

1

6

4

5

2

U5601SC70

INA214

SENSOR_NONPROD:Y

2


20%6.3V

X5R0201

0.22UFPLACE_NEAR=U5000.B8:7MM

21

R5634

201

4.53K

MF

1%

SENSOR_NONPROD:Y

1/20W


2


10%

0201CERM-X5R6.3V

0.1UF

5

2

4

3

1

U5630SC70-5OPA333DCKG4

SENSOR_NONPROD:Y

21

R5633

1% SENSOR_NONPROD:Y1/20W

MF201

NO_XNET_CONNECTION=TRUE510K

21

R5630620

201MF

SENSOR_NONPROD:Y

1/20W

1%

21

R5631

1/20W

201

SENSOR_NONPROD:Y1%

620

MF

2

1R5632


MF1/20W

1%

201

510K

SENSOR_NONPROD:Y

2

1 C5681


0.22UF20%

0201

6.3V

X5R

SENSOR_NONPROD:Y

2

1 C5671

0201

SENSOR_NONPROD:Y


0.22UF20%6.3V

X5R

21

R5671PLACE_NEAR=U5000.C1:7MM

SENSOR_NONPROD:Y

4.53K

MF

1%1/20W

201

21

R5685

MF


1/20W

1%

SENSOR_NONPROD:Y

4.53K

201

21

R56003.01K

SENSOR_NONPROD:Y1%1/20W

201MF

21

R5670

1/20W

1%

MF201

3.01K SENSOR_NONPROD:Y

21

R5677

402

0

5%MF-LF 1/16W

S2_PWR:S0

21

R5676

402

0 S2_PWR:S3

MF-LF 1/16W5%

2

1R56721%SENSOR_NONPROD:Y1/20W

MF

1M


201

21

R5673NO_XNET_CONNECTION=TRUE

SENSOR_NONPROD:Y1/20W

1M

MF

1%

201

5

2

4

3

1

U5600OPA333DCKG4SC70-5

SENSOR_NONPROD:Y

2

1 C56000.22UF20%

X5RPLACE_NEAR=U5000.B7:7MM

SENSOR_NONPROD:Y

0201

6.3V

2

1 C5603

0201

10%0.1UF

CERM-X5R6.3V

SENSOR_NONPROD:Y

21

R5674PLACE_NEAR=U5000.H1:7MM

4.53K

SENSOR_NONPROD:Y

1%

MF1/20W

201

63 82

63 82

41 43

41 43

41 43

41 43

41 43

4

3

2

1R5675

1/2W

1206-1MF

1%

CRITICAL

0.010

66 82

66 82

43

21

R5635

0612-3

0.0051%1W

CRITICAL

MF

Debug SensorsSYNC_MASTER=CLEAN_X305 SYNC_DATE=01/14/2014

RES,MTL FILM,100K,5,1/20W,0201,SMD,LF117S0008 5 SENSOR_NONPROD:NC5601,C5631,C5600,C5681,C5671

ISNS_AIRPORTN

ISNS_AIRPORTP

PP3V3_WLAN_F

PP3V3_WLAN_R

PP3V3_S4

ISNS_CPUDDR_N

ISNS_CPUDDR_P

PP3V3_S3

ISNS_CPU_DDR_IOUT

ISNS_AIRPORT_IOUT

ISNS_AIRPORT_R_N

ISNS_CPU_DDR_R_P

ISNS_LCD_PANEL_P

ISNS_LCD_PANEL_N

PP3V3_S0

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

GND_SMC_AVSS

ISNS_S2_R_P

PP3V3_S3RS0_CAMERA

VOLTAGE=3.3V


PP3V3_S3RS0_CAMERA_R

ISNS_S2N

ISNS_S2P

GND_SMC_AVSS

LCDBKLT_IOUT

SMC_LCDPANEL_ISENSE

PP3V3_S0

SMC_X87_ISENSE

PP3V3_S3

SMC_S2_ISENSE

ISNS_AIRPORT_R_P

ISNS_S2_R_N

ISNS_S2_OUT

SMC_LCDBKLT_ISENSE

SMC_CPUDDR_ISENSE

PP3V3_S3

ISNS_CPU_DDR_R_N

GND_SMC_AVSS

PP3V3_S0

LCD_PANEL_IOUT

GND_SMC_AVSS

GND_SMC_AVSS

47 OF 82

56 OF 118

<E4LABEL>

<SCH_NUM>

<BRANCH>

34

34

20 34 39 40 42 43 46 65 66 67 69 70 71 72

13 20 21 44 46 47 66 69 70 72

82

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

41 42 45 46 47

82

13 36 70

41 42 45 46 47

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 66

67 68 70 72 82

13 20 21 44 46 47 66 69 70 72

82

82

13 20 21 44 46 47 66 69 70 72

82

41 42 45 46 47

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

41 42 45 46 47

41 42 45 46 47

w w w

. c h

i n a

f i x

. c o

mBI

DP1 THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLKGND

ALERT*

DP2/DN3

DN2/DP3

BI

BI

NC

THERM*/ADDR

ALERT*

GND

VDD

DN

DP

SMDATA

SMCLKTHRMPAD

BI

BI

GND

V+

ADD0

ALERTSCL

SDA

BI

BI

Apple Inc.


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6 3



X87 PROXIMITY

Placement note:

WRITE ADDRESS: 0X92

READ ADDRESS: 0X93

CLOSE TO THE LEFT FIN STACK

LEFT FIN STACK TEMPERATURE

PLACE U5823 ON BOTTOM NEAR X87 CONN

TBT DIE

DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

CPU PROXIMITY TEMPERATURE

DDR3 PROXIMITY TEMPERATURE

THSP

Placement note:PLACE Q5804 ON TOP SIDE UNDER PCH

PLACE U5870 ON TOP SIDE UNDER CPU

PLACE Q5802 ON TOP SIDE

Placement note:

CLOSE TO BOARD EDGE

TM0P

AIRFLOW PROXIMITY TEMPERATURE Ta0P

TP0PWrite Address: 0x98Read Address: 0x99

Placement note:

TC0P

TW0P

Read Address: 0x99Write Address: 0x98

Placement note:PLACE Q5803 ON TOP SIDE NEAR DDR3

PCH PROXIMITY TEMPERATURE

LEFT FIN STACK/RIGHT FIN STACK

Th2H

PLACE U5860 ON TOP SIDE RIGHT FIN STACK TEMPERATURE Th1H

PLACE Q5803 ON BOTTOM SIDE NEAR RIGHT FIN STACK

Placement note:

Placement note:

Use GND pin B1 on U2800 for N leg

2

1R5872

1/16W5%

402MF-LF

10K

2

1R5871

1/16W5%

402MF-LF

10K

2

3

1Q5804CRITICAL

BC846BMXXHSOT732-3

2

1R5851

1/16W5%

402MF-LF

10K

2

1R585210K

MF-LF402

5%1/16W

2

1 C5850

X7R-CERM

0.1UF

0402

20%10V

21

R585047

402

5%

MF-LF1/16W

2

3

1

Q5802CRITICAL

BC846BMXXHSOT732-3

2

1C5871

CERM402

10%50V

PLACE_NEAR=U5870.3:5mmPLACE_NEAR=U5870.2:5mm


0.0022uF

28 48 82

21

XW5820SM

PLACE_NEAR=U2800.AC6:2mm 2

1R582010K

402

5%1/16W

NOSTUFFPLACE_SIDE=TOP

MF-LF

2

3

1Q5806CRITICAL

BC846BMXXHSOT732-3

1

11

7

9

10

6

4

2

5

3 8

U5870EMC1414-A-AIA

DFN

41 44 48 81

41 44 48 81

2

1 C58230.1uF20%10VCERM402

2

1R582210K

402

1/16W5%

MF-LF

1

9

4

7

8

5

2

36

U5860

CRITICAL

EMC1412-ATQFN

2

3

1Q5803CRITICAL

BC846BMXXHSOT732-3 2

1C5852



0.0022uF

CERM402

10%50V

37 41 44 68 71 72 81

37 41 44 68 71 72 81

5

6

1

2

3

4

U5823HPA00330AI

PLACE_SIDE=BOTTOM

SOT563

PLACE_NEAR=J3501:5MM

CRITICAL

41 44 48 81

41 44 48 81

2

1 C5870

10VX7R-CERM

0.1UF

0402

20%

21

R587047

MF-LF402

5%1/16W

2

1C58900.0022uF

CERM402

10%50V



SYNC_MASTER=CHANG_J45 SYNC_DATE=11/26/2012

Thermal Sensors

FINTHMSNS_D_N

FINTHMSNS_D_P FINTHMSNS_THM_L

FINTHMSNS_ALERT_L

CPUTHMSNS_D2_P

PP3V3_S0MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_S0_CPUTHMSNS_R

DDR3THMSNS_D1_N

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

PP3V3_S0

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

TBT_THERMDP

TBT_THERMDN

DDR3THMSNS_D1_P

TBT_THERMDPMAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mmPP3V3_S0_FINTHMSNS_R

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

CPUTHMSNS_D2_N

X87THMSNS_A0

PP3V3_S0

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

<BRANCH>

<SCH_NUM>

<E4LABEL>

58 OF 118

48 OF 82

82

82

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

82

82

28 48 82

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

w w w

. c h

i n a

f i x

. c o

m

IN

OUT

IN

NC

NC

NC

NC

NC NC

OUT

VER 1

S D

G

VER 1

S D

G

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6 3



518S0769

Left Fan Right Fan

518S0769

2

1R605047K5%

1/16W

402MF-LF

21

R6055

5%1/16W

47K

402MF-LF

2

1R6060

MF-LF402

5%1/16W

47K

21

R6065

1/16W5%

402MF-LF

47K

2

1R6051100K

201MF

1/20W5%

2

1R6061

201MF

100K5%

1/20W

41

41

41

5

4

3

2

1

6

7

J6050FF14A-5C-R11DL-B-3H

CRITICAL

F-RT-SM

5

4

3

2

1

6

7

J6060FF14A-5C-R11DL-B-3H

F-RT-SM

CRITICAL

41

21

R60710

NOSTUFF402

1/16WMF-LF

5%

21

R6072

MF-LF1/16W

NOSTUFF

0

5%

402

4

5

3

Q6060DMN5L06VK-7SOT563

1

2



Fan ConnectorsSYNC_MASTER=J15_MLB

SMC_FAN_0_TACH

PP3V3_S3_FAN_CTL

FAN_LT_TACH

PP5V_S0

SMC_FAN_0_CTL FAN_RT_PWM

PP3V3_S3_FAN_CTL

SMC_FAN_1_CTL

PP3V3_S0PP3V3_S0

SMC_FAN_1_TACH

PP3V3_S0

FAN_RT_TACH

PP3V3_S0

PP5V_S0

FAN_LT_PWM

<BRANCH>

<SCH_NUM>

<E4LABEL>

60 OF 118

49 OF 82

49 71

72

18 19 37 49 58 59 62 63 66 67 70 71 72

72

49 71

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

18 19 37 49 58 59 62 63 66 67 70 71 72

72

w w w

. c h

i n a

f i x

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m

BI

IN

IN

IN

OUT

BI

BI

BI

BI

OUTOUT

VCC

D

B

A Y

OE*C

GND

CS*

DI(IO0)

THRM_PAD

CLK

WP*(IO2)

HOLD*(IO3)

DO(IO1)

VCC

GND

OUT

OUT

BI

BI

BI

BI

IN

IN

BI

Apple Inc.


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REVISION

BRANCH

6 3



IO3(SWCLK)

SMC12 Master

SPI ROM Slave

IO1

IO0

SPI ROM

SPI+SWD SAM Connector

(SWDIO)

Sam Card ROM Slave

NOTE: If HOLD* is asserted

in normal and Dual-IO modes.

SPI Frequency: 50MHz for CPU, 20MHz for SMC.Quad-IO Mode (Mode 0 & 3) supported.

IO2

516S00024

(SPI_IO<1>)

(SPI_IO<0>)

0HOM WERE ADDED FOR R6118&R6119 AS PLACEHOLDER.OVER/UNDER-SHOOT WAS OBSERVED ON IO2 AND IO3.

SPI Bus Series Termination

Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)

ROM will ignore SPI cycles

in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.

PCH Master

FINAL VALUE NEEDS TO BE TUNED.

2

1R6126

0201

SAMCONN

PLACE_NEAR=J6100.3:5MM

MF1/20W5%0

21

R6122

1/20WMF

PLACE_NEAR=U6100.5:12MM1%

33

201

21

R6112

5%

11

201

1/20WMF

PLACE_NEAR=U1100.AH1:50MM13 77

2

1R6127


5%1/20WMF0201

0

SAMCONN

2

1R6128SAMCONN


5%

MF0201

01/20W

41 77

41 77

41 77

41 77

21

R6117

0201

0

MF1/20W5%

NOSTUFF

PLACE_NEAR=U5000.K10:12MM

21

R6115

0201

PLACE_NEAR=U5000.N9:12MM

0

MF1/20W5%

NOSTUFF

21

R6116

0201

0

MF1/20W5%

NOSTUFF

PLACE_NEAR=U5000.L10:12MM

21

R6114

0201

0

MF1/20W5%

PLACE_NEAR=U5000.M9:12MM

NOSTUFF

21

R6113

5%

11

201

1/20WMF

PLACE_NEAR=U1100.AH3:50MM

21

R6130

1/20WMF

33

201

1%PLACE_NEAR=U6100.3:12MM

21

R6131

1/20WMF201

1%

33PLACE_NEAR=U6100.7:12MM

13 77

13 77

41 42 72

14 50 72

41 42 72

9

8 7

6 5

4 3

2

16 15

14 13

12 11

10

1

J6100

SAMCONN

M-ST-SMDF40PC-12DP-0.4V-51

CRITICAL

41 42 57 72

2

1R6132SAMCONN

0201

1/20WMF

5%0


2

1R6133

0201

SAMCONN


5%

MF1/20W

0

2

1C6100

0201X5R-CERM

16V10%

0.1UF

BYPASS=U6100::3mm

2

1 C6101

0201

BYPASS=U6101::3mm

10%16VX5R-CERM

0.1UF

78

1

4

6

5

3

2

U610174LVC1G99

SOT833

CRITICALPLACE_NEAR=U6100.1:12MM

3

8

9

7

4

2

5

1

6

U6100

WSON

OMIT_TABLE

W25Q64FVZPIG64MBIT

CRITICAL

50 77

50 77

50 77

50 77

50 77

50 77

21

R6118

5%

11

201

1/20WMF

PLACE_NEAR=U1100.AJ4:50MM

21

R6119

5%

11

201

1/20WMF

PLACE_NEAR=U1100.AJ2:50MM

21

R6110

201

5%1/20WMF

11PLACE_NEAR=U1100.AJ7:50MM

13 77

21

R6111

5%

11

201

1/20WMF

PLACE_NEAR=U1100.AJ11:50MM13 77

21

R6123

1/20WMF


201

3313 77

21

R6120

1/20WMF


201

1%

33

2

1R6125


5%0

MF0201

1/20W

SAMCONN

21

R612133

1/20WMF


201

SYNC_MASTER=CLEAN_X305_PEG SYNC_DATE=02/18/2014

SPI Debug Connector

SPI_CS0_R_L

SPI_CLK

SPI_MOSI SPI_MLB_IO0_MOSI

SPI_CS0_L

SPI_MLB_IO1_MISO

SPI_MLB_IO2_WP_LSPI_IO2_R

SPI_IO3_R SPI_MLB_IO3_HOLD_L

SPI_MISO_R

SPI_IO<3>

PP3V42_G3H

SPI_ALT_CLK

SPI_MLB_IO1_MISO

SPI_IO<2>

SPI_CLK_R

SPI_MISO

SPI_MLB_CLK

PP3V3_SUS

SPI_MLBROM_CS_L

SPI_MOSI_R

SPI_SMC_CS_L

SPI_SMC_MISO

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_ALT_IO2_WP_L

SPI_ALT_CS_L

SPI_SMC_CLK

SPI_SMC_MOSI

SPI_ALT_IO1_MISOSPI_ALT_IO0_MOSISPI_ALT_CLK

SPI_ALT_IO2_WP_L

SMC_TCK

SPIROM_USE_MLBSPI_ALT_CS_L

SPI_ALT_IO3_HOLD_LSPI_MLB_IO2_WP_L

SPI_MLB_IO0_MOSI

SPI_MLB_IO3_HOLD_L

SPI_ALT_IO1_MISO

SPIROM_USE_MLBSPI_MLB_CS_L

SPI_ALT_IO0_MOSI

SMC_RESET_LSMC_TMS

SPI_ALT_IO3_HOLD_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

61 OF 118

50 OF 82

77

77

77

77

19 35 38 39 41 42 43 44 56 57 65 67 70 72

50 72 77

50 77

50 77

11 12 13 14 15 17 64 66 67 70

50 72 77

50 72 77

50 72 77

50 72 77

50 72 77

50 72 77

50 72 77

50 77 50 77

50 77

50 77

50 72 77

14 50 72

50 77

50 72 77

50 77

w w w

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i n a

f i x

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mANALOGSYM 1 OF 2

AGND

AGND

AGND

AGND

HPGND

HPGND

HPGND

HSGND

PLLGND

VA_PLL

VA

VA_REF

VA_HP

SENSE_A1

SENSE_A2

HPOUT_L

HPOUT_R

HS3

HS4

HS4_REF

SENSE_B2

SENSE_B1

SENSE_D

SENSE_C

HS3_REF

HSIN+

HSIN-

LINEOUT1_L-

LINEOUT1_L+

LINEOUT1_R+

LINEOUT1_R-

LINEOUT2_L-

LINEOUT2_L+

LINEOUT2_R-

LINEOUT2_R+

LINEOUT3_R+

LINEOUT3_L+

LINEOUT3_R-

LINEOUT4_L+

LINEOUT4_L-

LINEOUT4_R+

LINEOUT4_R-

LINEOUT3_L-

VREF_ADC

VCOM

FLYN

FLYN

FLYP

VHP_FILT-

VREF_DAC

LINEIN_L+

LINEIN_R-

LINEIN_R+

LINEIN_L-

MICBIAS2_R

MICBIAS2_L

MICBIAS1_R

MICBIAS1_L

MICIN1_L+

MICIN2_L-

MICIN1_L-

MICIN1_R+

MICIN2_L+

MICIN2_R+

MICIN2_R-

HSBIAS_IN

HSBIAS

HSBIAS_REF

HSBIAS_FILT

MICIN1_R-

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NR/FB

NC

IN

EN

GND

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

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6 3



PLACE XW6201 NEAR 5V SOURCE

4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2456

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

RT. SUBWOOFER AMP. SIG. SOURCE

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

AUDIO CODEC, ANALOG BLOCKSAPPLE P/N 353S4080

H13

N12

A11

M12

H12

A1

A9

N13

L3

M3

D11

E11

D12

C11

A2

N4

M4

N5

M5

N7

M7

N8

M8

L4

L5

L7

L8

K13

L11

K11

K12

J12

J13

H11

J11

G12

G13

F13

G11

F11

F12

E12

E13

N9

M9

N10

M10

N6

M6

D13

M13

L12

N11

L13

B12

C12

B13

C13

A13

A12

C10

C8

A10

A8

B11

B10

L10

L9

L6

M11

U6201CS4208-CRZR

VFBGA

2

1C62120.1UF

0402

10%

X7R-CERM16V

BYPASS=U6201.A1:A2:5 MM

2

1C6216

BYPASS=U6201.N13:M11:5 mm

0402

16V

0.1UF10%

X7R-CERM

2

1C6215

BYPASS=U6201.H12:H13:5 mm

10UF

16V20%

CRITICAL

TANT-POLY0805-LLP-1

21

C6219

20%

CRITICAL

4VX5R

15UF

0402

53 82

53 82

53 82

53 82

53 82

53 82

53 82

53 82

2

1C6210CRITICAL

0603-LLP

1UF-10OHM

25VTANT

20%2

1 C6211

TANT-POLY

20%16V

CRITICAL

10UF

0805-LLP-1

2

1C6222CRITICAL

0402

20%4VX5R

15UF

BYPASS=U6201.A8:B10:5 mm

2

1 C6221

0402X5R-CERM10V20%4.7UF

21

C6220

X5R402

25V10%

1UF

21

R62062.21K

MF

1%1/20W

201

21

C6224

40210%

X5R25V

1UF

21

C6225

10%25VX5R402

1UF

21

XW6201SM

21

R62002.2K

1/20WNOSTUFF 5%

201MF

21

L6200FERR-22-OHM-1A-0.055OHM

0201

2

1 C6201

X5R402

10V10%1UF

1

3

5

6

2

4

U6200SON

CRITICAL

TPS71745

21

XW6200SM

2

1 C6203

0201-1

10V20%1.0UF

X5R-CERM

CRITICAL

2

1C6218

0402

0.1UF

16VX7R-CERM

BYPASS=U6201.H12:L10:5 mm

10%

55

55

55

55

55

55

55

54 82

54 82

2

1 C621710UF20%

TANT-POLY16V

0805-LLP-1

55

55

2

1C6202

25V

0.01UF

0201X5R-CERM

CRITICAL

10%

2

1C62140.1UF

16V10%

X7R-CERM0402

2

1 C6213CRITICAL

10UF20%10VX5R-CERM0402-1

21

L6201

0402

CRITICAL

120-OHM-25%-1.3A

21

C6226

16V

0201

0.1UF10%

X5R-CERM

2

1 C6200

0402

16V

0.1UF

X7R-CERM

10%

21

R6207

5%

22K

MF1/20W

201

AUDIO:CODEC, ANALOGSYNC_MASTER=JOE_J45 SYNC_DATE=07/30/2013

PP4V5_AUDIO_ANALOG

VREF_DAC


MIN_NECK_WIDTH=0.07MM AUD_CH_HS_GNDMIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.3MM

HS_MIC_P

HS_MIC_NMIN_NECK_WIDTH=0.07MMMIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.07MM AUD_US_HS_GNDMIN_LINE_WIDTH=0.5MM


PP4V5_AUDIO_ANALOG

VOLTAGE=4.5VMIN_NECK_WIDTH=0.15MM

CODEC_MICIN2

TP_AUD_CODEC_MICBIAS2_R

MIN_NECK_WIDTH=0.07MM AUD_HP_PORT_LMIN_LINE_WIDTH=0.3MM

PP5V_S4

GND_AUDIO_CODEC

4V5_NR

GND_AUDIO_CODEC

GND_AUDIO_CODEC

GND_AUDIO_CODEC


VOLTAGE=0V

MIN_NECK_WIDTH=0.07MM AUD_HP_PORT_RMIN_LINE_WIDTH=0.3MM

GND_AUDIO_CODEC

AUD_HSBIAS_FILT

NO_TEST=TRUE NC_AUD_LO4_LNNO_TEST=TRUE NC_AUD_LO4_LP

AUD_LO3_R_N

AUD_LO3_L_P

GND_AUDIO_CODEC

CODEC_VCOM

NO_TEST=TRUE NC_AUD_LO4_RP

AUD_LO3_R_P

AUD_LO3_L_N

AUD_LO2_L_P

MIN_LINE_WIDTH=0.4MM AUD_HP_PORT_REFUSMIN_NECK_WIDTH=0.07MM

CODEC_VREF_ADC

GND_AUDIO_CODEC

NO_TEST=TRUE NC_AUD_LO4_RN

AUD_LO2_R_N

AUD_LO2_R_P

AUD_LO2_L_N

MIN_NECK_WIDTH=0.06MMMIN_LINE_WIDTH=0.3MMCODEC_HS_MIC_P

AUD_TIPDET_2

AUD_TIPDET_1

PP3V3_S0PP3V3_S0_AUDIO_ANALOGMIN_LINE_WIDTH=0.4 MM


VHP_FILTNMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.07MM

CODEC_FLYPMIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.07MM

CODEC_FLYNMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.07MM

GND_AUDIO_CODEC

TP_AUD_CODEC_MICBIAS1_L

TP_AUD_CODEC_MICBIAS1_R

TP_AUD_CODEC_MICBIAS2_L

GND_AUDIO_CODEC

AUD_HSBIAS_IN

AUD_HSBIAS_REF

AUD_HSBIAS

4V5_REG_IN

VOLTAGE=5VMIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MM

4V5_REG_EN

PM_SLP_S3_BUF_L

PP3V3_S0

VOLTAGE=5VMIN_NECK_WIDTH=0.20MM

PP5V_S4_AUDIO_XWMIN_LINE_WIDTH=0.60MM

MIN_LINE_WIDTH=0.4MM AUD_HP_PORT_REFCHMIN_NECK_WIDTH=0.07MM

NO_TEST=TRUE NC_AUD_LO1_LNNO_TEST=TRUE NC_AUD_LO1_LP

GND_AUDIO_CODEC

NO_TEST=TRUE NC_AUD_LO1_RP

NO_TEST=TRUE NC_AUD_LO1_RN

MIN_NECK_WIDTH=0.06MMCODEC_HS_MIC_N MIN_LINE_WIDTH=0.3MM

AUD_TYPEDET

<BRANCH>

<SCH_NUM>

<E4LABEL>

62 OF 118

51 OF 82

51

51 38 39 61 66 67 68 69 70 72

51 55

51 55

51 55

51 55

51 55

51 55

51 55

82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

51 55

51 55

66 67 69 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

51 55

82

w w w

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i n a

f i x

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mDIGITALSYM 2 OF 2

VD

VL_HD

VL_IF

VL_SP

VL_DM

NC

NC

NC

NC

NC

NC

NC

NC

NC

DMIC_SCL3

DMIC_SDA3

DMIC_SCL2

DMIC_SDA2

DMIC_SCL1

DMIC_SDA1

DMIC_SCL0

DMIC_SDA0

SPDIF_OUT

SPDIF_IN

SCL

SDA

SDIN_B

SDOUT_B

LRCK_B

SCLK_B

MCLK_B

RST*

SDO3

SDO2

SDO1

SDO0

GPIO0

GPIO1

GPIO5

GPIO4

GPIO3

GPO0

SYNC

BCLK

SDI0

GPO1

SDI1

SCLK_A

MCLK_A

LRCK_A

SDOUT_A

SDIN_A

GPIO2

DGND

LGND

LGND

LGND

LGND

LGND

PP

OUT

IN

OUT

IN

IN

IN

OUT

OUT

IN

OUT

PP

PP

PP

PP

OUT

IN

IN

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APPLE P/N 353S4080AUDIO CODEC, DIGITAL BLOCKS

A7

G1

E1

K1

J2

E2

G2

G3

B8

A3

B1

C3

C2

D2

A4

B3

C1

D1

C6

B6

B2

B7

D3

H8

H7

H6

G8

G7

G6

F8

F7

F6

A6

A5

B5

B4

K3

J3

F3

E3

F1

B9

C9

C7

C5

C4

H1

H2

H3

K2

M2

N1

N3

L2

L1

M1

N2

J1

F2

U6201CS4208-CRZR

VFBGA

21

R6302SHORT

402

OMIT

21

R6323100K

201

5%

MF1/20W

2

1R6325

201MF

5%100K

1/20W

1

PP6305P3MMSM

PLACE_NEAR=U6201.D1:5 mm

54

21

L6300FERR-22-OHM-1A-0.055OHM

0201

11 77

11 77

11 52 77

11 52 77

21

R6331

201MF

5%

22

1/20W

2

1C630510UF20%

0402-1X5R-CERM10V

2

1 C6302

10%0.1UF

0402

16VX7R-CERM

BYPASS=U6201.E1:F1:5 mm

2

1C6306

0402-1X5R-CERM10V20%10UF

2

1 C6307

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U6201.A7:E3:5 mm2

1 C6303

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U6201.G1:F1:5 mm

2

1C63004.7UF20%4V

402X5R-1

2

1 C6304

10%0.1UF

0201CERM-X5R6.3V

BYPASS=U6201.K1:K3:5 mm

11 52 77

21

R6330

1/16W

402

5%

33

MF-LF

55

21

R633275

402MF-LF1/16W1%

55 72

52 55 72

2

1 C6301

10%0.1UF

BYPASS=U6201.J2:J1:5 mmX7R-CERM0402

16V

53

2

1R6324

201MF

5%100K

1/20W

21

R6322NOSTUFF

MF201

1/20W5%

100K

1

PP6302

PLACE_NEAR=U6201.F2:5 mm

P3MMSM

1

PP6301P3MMSM

PLACE_NEAR=U6201.N3:5 mm

1

PP6303P3MMSM

PLACE_NEAR=U6201.E2:5 mm

1

PP6304P3MMSM

PLACE_NEAR=U6201.D2:5 mm

54

55 72

55 72

AUDIO:CODEC, DIGITALSYNC_MASTER=JOE_J45 SYNC_DATE=07/30/2013

PP3V3_S0

PD_CS4208_GPIO1

SPKRCONN_L_ID

CS4208_HDA_SDOUT0_R

MIN_NECK_WIDTH=0.07MMVOLTAGE=1.5V

PP1V5_S0_AUDIO_DIGMIN_LINE_WIDTH=0.6 MM

GPIO0_SPKR_SHUTDOWN

NO_TEST=TRUENC_CS4208_LRCLKA

NO_TEST=TRUENC_CS4208_SDOUTA

NO_TEST=TRUENC_CS4208_LRCLKB

DMIC_SDA3

DMIC_CLK3

NO_TEST=TRUENC_CS4208_SCLKB

DMIC_CLK3_R

PP3V3_S0

PP3V3_S0

HDA_SYNC

HDA_SDOUT

CS4208_HDA_SDOUT0_R

HDA_BIT_CLK

CS4208_SPDIF_IN

PP1V5_S0

DMIC_SDA3

TP_CS4208_HDA_SDOUT1

NO_TEST=TRUENC_CS4208_MCLKB

NO_TEST=TRUENC_CS4208_SCLKA

NO_TEST=TRUENC_CS4208_SDOUTB

NO_TEST=TRUE NC_DMIC_CLK1


SPDIF_OUT_JACKCS4208_SPDIF_OUT


HDA_RST_L

NO_TEST=TRUENC_CS4208_MCLKA

HDA_SDIN0

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

NO_TEST=TRUENC_CS4208_GPO1

DFET_OPENCH

DFET_OPENUSSPKRCONN_R_ID

NO_TEST=TRUENC_CS4208_GPO0

<BRANCH>

<SCH_NUM>

<E4LABEL>

63 OF 118

52 OF 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

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52 77

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 52 77

11 52 77

52 77

11 52 77

11 12 13 15 17 19 64 67 69 70 72

52 55 72

w w w

. c h

i n a

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VDD

EDGEGND

GAINSD*

OUT+

OUT-IN-

IN+

OUT

OUT

VDD

EDGEGND

GAINSD*

OUT+

OUT-IN-

IN+

OUT

OUT

IN

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN-

IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

IN-

IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

IN

IN

IN

IN

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6 3



1ST ORDER FC (SUB) = NOM 9 HZ1ST ORDER FC (L&R) = NOM 569 HZGAIN = +3 DBAPN: 353S2888 & 353S2958

C6411 USING 0603 PAKAGE IS FOR DFM TO PROTECT U6410 (CSP)

C6441 USING 0603 PAKAGE IS FOR DFM TO PROTECT U6440 (CSP)

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

21

L6430CRITICAL

0402

FERR-1000-OHM

21

C6443

16V

0.22UF

CRITICAL

CERM402

10%

21

C6444

16VCERM402

10%

0.22UF

CRITICAL

21

C64340.22UF

10%

402CERM

CRITICAL

16V

21

C6433CRITICAL

CERM402

0.22UF

10%16V

C2

A2

C3

B3

B1

A1

C1

A3

B2

U6430

CRITICAL

WLCSPSSM2375

55 72 82

55 72 82

2

1 C6431

0201X5R-CERM16V10%0.1UF

BYPASS=U6430.C2:C1:5 mm

C2

A2

C3

B3

B1

A1

C1

A3

B2

U6440SSM2375WLCSP

CRITICAL55 72 82

55 72 82

2

1 C6441

603-1X7R50V10%0.1UF

BYPASS=U6440.C2:C1:5 mm

2

1C642247UF

TANT-POLY6.3V20%

CASE-A4

CRITICAL

2

1C643220%

TANT6.3V

CASE-AL1

100UF

CRITICAL

2

1C6442CRITICAL

CASE-AL1TANT6.3V20%

100UF

2

1 C6436

X7R-CERM

4700PF

50V

0402

10%

2

1 C6446

X7R-CERM50V

0402

10%4700PF

2

1R6400

5%

MF-LF

100K

402

1/16W

21

L6401FERR-1000-OHM

0402

CRITICAL

51 82

52

21

L6411

0402

CRITICAL

FERR-1000-OHM

55 72 82

2

1 C6411

603-1X7R

BYPASS=U6410.A1:A2:5 mm

50V10%0.1UF

2

1 C6421

X5R-CERM16V10%0.1UF

0201

BYPASS=U6420.A1:A2:5 mm

21

L6421

CRITICAL

FERR-1000-OHM

0402

51 82

55 72 82

2

1C6412

CASE-A4TANT-POLY

CRITICAL

47UF20%

6.3V

21

L6410FERR-1000-OHM

0402

CRITICAL

51 82

21

L6420

0402

CRITICAL

FERR-1000-OHM

51 82 21

C6423CRITICAL

10%

0402X7R-CERM

50V

0.01UF

21

C64240.01UF

X7R-CERM

10%50V

CRITICAL

0402

21

C6414

0402

0.01UF

10%50V

X7R-CERM

CRITICAL

21

C6413

X7R-CERM

0.01UF

CRITICAL

0402

50V10%

55 72 82

55 72 82

C2

A1

A2

B1

C1

B2

A3

B3

C3

U6410MAX98300

CRITICAL

WLP

2

1R6410100K

1/16W

402MF-LF

5%

C2

A1

A2

B1

C1

B2

A3

B3

C3

U6420WLP

MAX98300

CRITICAL

2

1R6420100K

1/16W5%

402MF-LF

51 82

51 82

21

L6441CRITICAL

FERR-1000-OHM

0402

21

L6440FERR-1000-OHM

CRITICAL

0402

51 82 21

L6431

0402

CRITICAL

FERR-1000-OHM

51 82

SYNC_DATE=07/30/2013SYNC_MASTER=JOE_J45

AUDIO: SPEAKER AMP

SPKR_SHUTDOWN

PP5V_S0_AUDIO_AMP_L

PP5V_S0_AUDIO_AMP_L

SPKRCONN_L_OUT_P


SPKRCONN_L_OUT_NMIN_LINE_WIDTH=0.40 MMMIN_NECK_WIDTH=0.10 MM

SPKR_SHUTDOWN


SPKRCONN_SR_OUT_P

SPKRCONN_SR_OUT_NMIN_LINE_WIDTH=0.40 MM


NO_TEST=TRUESPKRAMP_RIN_P

SPKR_SHUTDOWN

PP5V_S0_AUDIO_AMP_R

SPKR_L_GAIN

NO_TEST=TRUESPKRAMP_RIN_N

NO_TEST=TRUESPKRAMP_LIN_N

AUD_SPKRAMP_LSUBIN_P

AUD_SPKRAMP_LSUBIN_N

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

SPKRAMP_LIN_P

GPIO0_SPKR_SHUTDOWN

AUD_SPKRAMP_RSUBIN_N

PP5V_S0_AUDIO_AMP_R


SPKRCONN_SL_OUT_P

RSUBIN_PNO_TEST=TRUE

MIN_LINE_WIDTH=0.40 MMSPKRCONN_R_OUT_N


MIN_LINE_WIDTH=0.40 MMSPKRCONN_R_OUT_P


MIN_LINE_WIDTH=0.40 MMMIN_NECK_WIDTH=0.10 MMSPKRCONN_SL_OUT_N

AUD_SPKRAMP_RIN_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_LIN_N

AUD_SPKRAMP_RSUBIN_P

RSUBIN_N

NO_TEST=TRUE

LSUBIN_NNO_TEST=TRUE

LSUBIN_PNO_TEST=TRUE

AUD_LO2_L_N

AUD_LO2_R_P

SPKR_R_GAIN

AUD_LO2_R_N

AUD_LO3_R_P

AUD_LO3_R_N

AUD_LO3_L_P

AUD_LO3_L_N

AUD_LO2_L_P

SPKR_SHUTDOWN

RSUB_GAIN

LSUB_GAIN

<BRANCH>

<SCH_NUM>

<E4LABEL>

64 OF 118

53 OF 82

53

53 71

53 71

53

82

53

53 71

82

82

82

82

82

82

82

53 71

82

82

82

82

53

w w w

. c h

i n a

f i x

. c o

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OUT IN

IN

IN

OUT

OUT

OUT

OUT

IN

PSEL

CP

GND

OUT2

OUT1

VDD

PSEL

CP

GND

OUT2

OUT1

VDD

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(SEE RADAR # 6210118)

R/C6550 FILTER TO ADDRESS OUT-OF-BANDNOISE ISSUE SEEN ON EARLY HEADSETS

51 82

51 82

2

1R6556

201

100K1/20W

MF

5%

21

R6550

402MF-LF1/16W

2.2K

5%

2

1 C6558

C0G

5%

0201

25V

CRITICAL

27PF

21

R6559

1/16WMF-LF

5%

2.2K

402

55 82

55 82

2

1 C65011000PF25V5%

0402NP0-C0G

52

54 55

54 55

54 55

54 55

52

2

1 C6502

25VNP0-C0G

1000PF5%

0402

2

1R6520

402

1/16WMF-LF

10K5%

2

1 C6542

BYPASS=U6501.B2::3MM

0.1UF10%

X5R-CERM16V

02012

1 C65301.0UF

CERM-X5R0402

10%35V

2

1 C6550CRITICAL

X7R-CERM

10%10V

0201

3300PF

2

1 C65430.01UF


10VX5R-CERM0201

10%

B2

C2

A2

A1

B1

C1

U6500TAIC3027A0YFFR

WCSP

B2

C2

A2

A1

B1

C1

U6501WCSP

TAIC3027A0YFFR

2

1 C6563BYPASS=U6500.B2::3MM

10%

0201X5R-CERM10V

0.01UF2

1 C6562


0201

16V

0.1UF10%

X5R-CERM2

1 C6560

35V10%

0402CERM-X5R

1.0UF

2

1R6521

5%10K

MF-LF1/16W

402

AUDIO: JACKSYNC_DATE=06/24/2014SYNC_MASTER=CLEAN_X305

DFET_OPENCH

DFET_OPENUS

DFET_CPO1

MIN_NECK_WIDTH=0.06MMMIN_LINE_WIDTH=0.2MMAUD_HS_MIC_P


AUD_HS_MIC_NMIN_LINE_WIDTH=0.2MM

HS_MIC_P

HS_MIC_N

AUD_CONN_SLEEVE_XWAUD_CONN_SLEEVE_XW

AUD_CONN_RING2_XWAUD_CONN_RING2_XWDFET_CPO2

<BRANCH>

<SCH_NUM>

<E4LABEL>

65 OF 118

54 OF 82

w w w

. c h

i n a

f i x

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IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

NC

GND

VDD

AUDIO GND

SHELL

VIN

MIC

DET2

DET1

1RTN

2RTN

R.AUDIO

AUDIO GND

PINS

POFOPERATING VOLTAGE 3.3

AUDIO

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HIGH = FG, LOW = MERRY

HIGH = FG, LOW = MERRY

OTHER CODEC GPIO LINES

HIGH = DFETs OPEN

0X09 (9)

0X04 (4)

0X03 (3)

0X02 (2)

0X04 (4)

VOLUME

TWEETERS

PIN COMPLEX

CODEC OUTPUT SIGNAL PATHS

VREF

3.3V

CODEC GPIO0

CODEC GPIO0

0X1C (28)DMIC 2

2.7V0X18 (24)0X07 (7)

PIN COMPLEX

0X02 (2)

0X03 (3) APN: 518S0672

SPEAKER CONNECTOR

INPUT

HP=80HZ

CODEC INPUT SIGNAL PATHS

HP/HS OUT N/A

N/A

FUNCTION MUTE CONTROLCONVERTER

0X10 (16)

FUNCTION

SPDIF OUT

CONVERTER

N/A

0X12 (18)

0X13 (19)

0X21 (33)

GPIO3

INPUTGPIO2

0X09 (9) 3.3V

0X1C (28)

0X0E (14)APN: 518S0769

2-MIC CONNECTOR

GPIO4 OUTPUT

RIGHT SPEAKER ID

LEFT SPEAKER ID

HEADSET MIC

DMIC 1

SUB

APN: 514-0875

DFET CONTROL

6

5

4

3

2

1

8

7

J6602M-RT-SM

78171-6006

CRITICAL

6

5

4

3

2

1

8

7

J6603M-RT-SM

CRITICAL

78171-6006

53 72 82

53 72 82

53 72 82

52 72

53 72 82

52 72

53 72 82

53 72 82

53 72 82

53 72 82

52 72

52 72

21

R6680

402

OMIT

SHORT

51

51

54 82

54 82

51

51

51

51

51

21

L6606

0201

FERR-470-OHM

CRITICAL

21

L6605CRITICAL

120-OHM-25%-1.3A

0402

21

L6607FERR-470-OHM

CRITICAL

0201

21

L6604

0402

CRITICAL

120-OHM-25%-1.3A

51

51

21

L6608

0201

CRITICAL

FERR-470-OHM

2

1C6600

10V

1UF

402-1X5R

10%2

1 C6601

6.3VCERM-X5R0201

0.1UF10%

2

1R6601

5%

402

10K

1/16WMF-LF

21

XW6600PLACE_NEAR=J6600.3:2.54mm

SM

21

XW6602SM

PLACE_NEAR=J6600.5:2.54mm

21

XW6601SM

21

XW6603SM

5

4

3

2

1

6

7

J6601F-RT-SM

FF14A-5C-R11DL-B-3H

2

1

DZ6607CRITICAL

SOD882ESDALC5-1BM2

2

1

DZ6602SOD882

CRITICAL

ESDALC5-1BM2

2

1

DZ6606CRITICAL

SOD882ESDALC5-1BM2

2

1

DZ6604CRITICAL

ESDALC5-1BM2SOD882

2

1

DZ6601ESDALC5-1BM2

SOD882

CRITICAL

2

1

DZ6603SOD882

CRITICAL

ESDALC5-1BM2

2

1

DZ6605ESDALC5-1BM2

CRITICAL

SOD882

52

2

1C6608

25V

100PF5%

0201C0G

21

L6611

0402

CRITICAL

120-OHM-25%-1.3A

21

L6612

0402

CRITICAL

120-OHM-25%-1.3A

21

L6613

0402

CRITICAL

120-OHM-25%-1.3A

21

L6614CRITICAL

0402

120-OHM-25%-1.3A

2

1 C6607

0201

25V

100PF5%

C0G

2

1C6602

25V

0201

5%100PF

C0G

2

1C6605100PF5%

0201

25VC0G

2

1C6606

25V

100PF5%

0201C0G2

1C66045%25V

0201

100PF

C0G

2

1 C6603

25V

100PF5%

0201C0G

9

8

7

6

5

4

3

2

15

14

13

12

11

10

1

J6600

F-RT-THAUDIO-SPDIF-J44

2

1

R66032.2K5%

201

1/20WMF

2

1

R6602

201MF1/20W5%2.2K


AUDIO: JACK TRANSLATORS

AUD_TIPDET_1

SPDIF_OUT_JACK

AUD_HS_MIC_N

AUD_US_HS_GND

AUD_HP_PORT_REFCH

SPKRCONN_L_OUT_N

SPKRCONN_SL_OUT_N

SPKRCONN_SL_OUT_P

SPKRCONN_R_ID

SPKRCONN_SR_OUT_P

SPKRCONN_L_OUT_P

SPKRCONN_L_ID

AUD_TYPEDET

PP3V3_S0

DMIC_SDA3

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

SPKRCONN_SR_OUT_N

AUD_CH_HS_GND

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.5MMAUD_CONN_SLEEVE_XW

DMIC_SDA2

DMIC_CLK3


AUD_CONN_SLEEVE


AUD_CONN_RING2

AUD_TIPDET_2

GND_AUDIO_CODEC

AUD_HP_PORT_R

AUD_HP_PORT_L

AUD_HP_PORT_REFUS

AUD_HS_MIC_P

MIN_LINE_WIDTH=0.5MMAUD_CONN_RING2_XW



AUD_CONN_HP_LEFTMIN_LINE_WIDTH=0.3MM


AUD_CONN_HP_RIGHT

AUD_CONN_TIPDET_1

AUD_CONN_TYPEDET

PP3V3_S0

AUD_CONN_TIPDET_2

<BRANCH>

<SCH_NUM>

<E4LABEL>

66 OF 118

55 OF 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

54

72

51

54

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 68 70 72 82

w w w

. c h

i n a

f i x

. c o

mVCC

EXT INT

NC GND

NC

POS

NEG

SYS_DETECT

SDA

POS

POS

POS

SCL

NEG

NEG

NEG

VER 1

NCNC

BI

NC

G

D

S

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

IN

Y

B

A

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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



NOTE: R7097 can be replacedby SHORT at PVT

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

Vout = 3.425V

send transients onto ADAPTER_SENSE when AC is

1-Wire OverVoltage Protection

6.8V Zener

The chassis ground will otherwise float and can

<Ra>

Input impedance of 22.1K meetssparkitecture requirements

518S0508

connected.

for D2 design only

518-0376

MagSafe DC Power Jack

blocking the leakage path and 22.1K can be

BATTERY CONNECTOR

When input voltage is 2V the FET will be off

<Rb>

Vout = 1.25V * (1 + Ra / Rb)



properly detected.

When input voltage is at 16V+, FET willconduct and power charger and 3.42V reg

300MA MAX OUTPUT

(Switcher limit)

APN:353S3733

21

F7005CRITICAL

0603

6AMP-32V-0.0095OHM

2

1 C7005NOSTUFF

0.01UF

50VCERM0603

20%

1

3

42

5

U7000

CRITICAL

SC70-5MAX9940

2

1C705010%25VX5R

0.1UF

4022

1C7060

402

1UF16V10%

X5R

21

3

D7050CRITICAL

RCLAMP2402B

SC-75

2

1R70505%

MF-LF

10K

402

1/16W

2

1 C7095

C0G

22PF

50V

0201

5%

2

1R7096

201

1/20WMF

200K1%

2

1 C709910UF

X5R-CERM0402-1

10V20%

2

1R7095

201MF

1%348K

1/20W

21

R7005

805

1/8W

10

MF-LF

5%

21

R7020

805

1%

47

1/3WMF

3

2

1

D7005BAT30CWFILM

SOT-323

CRITICAL

21

L7095

DP418C-SM

CRITICAL

33UH-20%-0.39A-0.435OHM2

1C7094

10V10%

402CERM

0.22UF

20 9

19 8

18 7

17 6

16 5

15 4

14 3

13 2

12 1

22 11

21 10

J7050BAT-J5F-ST-TH

CRITICAL

6

5

4

3

2

1

J7000

CRITICAL

M-RT-SMWTB-PWR-M82

41

2

1R7029

402

1/16W

2.0K

MF-LF

5%

5A

5

4

1

Q7010

POWERPAK

SI5419DU

2

1R7010100K

MF201

1/20W5%

2

1R701222.1K1%

MF1/20W

201

K

A

D7010CDZ6.8B

SM

2

1C7091NOSTUFF

0603X5R-CERM

10%35V

4.7UF

2

1C7090NOSTUFF

4.7UF

X5R-CERM35V10%

06032

1C7092

0603X5R-CERM

35V10%

4.7UF

2

1C7093

0603

4.7UF10%35V

X5R-CERM 2

1C7096

X5R-CERM

4.7UF

0603

35V10%

2

1C70974.7UF

10%35V

X5R-CERM0603

2

1 C7012

0402

25V10%0.047UF

X7R

21

R701110K

MF1/20W

201

5%

6

9

48

7

5

1

3

2

U7090

CRITICAL

DFNLT3470AED

2

1 C7008

20%

402CERM

PLACEMENT_NOTE=PLACE NEAR U7100 and U700110V

0.1UF

41 42 43 57

4

5

3

1

2

U7001

CRITICAL

TC7SZ08FEAPESOT665

2

1C70000.1UF

CERM402

20%10V

21

R7001

MF1/20W

0201

0

5%

2

1C7001NOSTUFF

NONE

402NONENONE

OMIT

2

1R700249.9K

NOSTUFF

1%

MF1/20W

2012

1 C709810UF20%

0402-1X5R-CERM10V

2

1R709705%

MF-LF402

1/16W


DC-In & Battery Connectors

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=20V

PP20V_DCIN_CONN_R

DCIN_ISOL_GATE

PPBUS_G3HMIN_LINE_WIDTH=0.4 mmPPVIN_G3H_P3V42G3H


P3V42G3H_SHDN_L

SMBUS_SMC_5_G3_SCL

PPVBAT_G3H_CONN

SMBUS_SMC_5_G3_SDA

SYS_DETECT_L

SMC_BC_ACOK_VCC

DCIN_ISOL_GATE_R

TP_TDM_ONEWIRE_MPM

PP3V42_G3H

SYS_ONEWIRE

SMC_BC_ACOK

ADAPTER_SENSE

PPDCIN_G3H_ISOL

PP20V_DCIN_FUSE

VOLTAGE=20V

MIN_LINE_WIDTH=1MMMIN_NECK_WIDTH=0.20MM

PPDCIN_G3H

PPBUS_G3H_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=18.5V


SWITCH_NODE=TRUEDIDT=TRUE


P3V42G3H_SW

DIDT=TRUEP3V42G3H_BOOST

PP3V42_G3H

P3V42G3H_BIAS

P3V42G3H_FB

<BRANCH>

<SCH_NUM>

<E4LABEL>

70 OF 118

56 OF 82

30 45 57 63 65 70 72

41 44 57 72 81

57 72

41 44 57 72 81

72

19 35 38 39 41 42

43 44 50

56 57 65

67 70 72

72

45 57 70

72

57 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

IN

BI

OUT

AMON

BMON

ACOK

LGATE

PHASE

BOOT

SGATE

AGATE

CSIP

CSIN

DCIN

VNEG

CSOP

CSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATE

ICOMP

VCOMP

ACIN

SDA

VFRQ

CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

D

S

GIN

NC

SW

BOOSTVIN

BIAS

SHDN*

GND

NC

FB

PADTHRM

NC

NCNCNC

G G

S D SD

D

S

G

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Sparkitecture impedance is set by R7112 in D2

(CHGR_DCIN)

Vout = 1.25V * (1 + Ra / Rb)

f = 400 kHz

(CHGR_AGATE)

Inrush Limiter

(CHGR_SGATE)

Max Current = 8A

(L7130 limit)

NOTE: MIRROR C7190

Reverse-Current Protection

For Erp Lot6 spec

Vout = 5.50V

(Switcher limit)100MA MAX OUTPUT

<Ra>

AND C7191

NOTE: MIRROR C7198AND C7199

<Rb>

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V

152S1466

(CHGR_CSO_N)

30mA max load

FROM ADAPTER

(OD)

353S2392

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

(AGND)

36V/V

TO/FROM BATTERY

20V/V

(GND)

(PPVBAT_G3H_CHGR_R)

(CHGR_CSO_P)

TO SYSTEM

2

1 C71420.1UF50V10%

0402X5R-CERM

2

1 C7116470PF

CERM0402

10%50V

2

1R7116

1/16W

3.01K

MF-LF402

1%

2

1C7115220PF

X7R-CERM0402

10%50V

2

1R7115330K

MF-LF402

5%1/16W

2

1C71021UF

X5R402

10%10V

2

1 C7100

X5R

10%10V

402-1

1UF

21

R71014.7

MF-LF402

1/16W5%

2

1C7157

X7R-CERM

10%0.01UF

0402

16V2

1C71560.1UF

X7R-CERM0402

10%16V

21

XW7100SM


2

1C71011UF

X5R402

10%10V 2

1 C7121

0402X5R-CERM

10%50V

0.1UF

2

1C71220.1UF

50V10%

0402X5R-CERM

2

1 C7120

X5R-CERM

0.047UF

0402

10%10V

2

1 C7125

CERM

0.22UF10%10V

402

PLACE_NEAR=U7100.25:2mm

21

R7122

5%1/16W

10

402MF-LF

21

R7121

402MF-LF

5%

10

1/16W

21R7151 2.2MF-LF 4025% 1/16W

21R7152 0MF-LF 4025% 1/16W

45

45

41 44 56 72 81

41 44 56 72 81

2

1C71110.01UF

X7R-CERM0402

10%16V

2

1 C71501UF

X5R402

10%16V

2

1C71260.001UF

X7R-CERM0402

10%50V

41 42 43 56

3

4

1

2R7120

0612

1W

CRITICAL

MF-LF

0.0200.5%

2

1 C71370.001UF

X7R-CERM0402

10%50V

2

1 C7145

0402X7R-CERM

0.001UF10%50V

8

12

4

20

19

7

24

29

1326

10

11

23

22

21

5

2

18

17

28

276

25

15

16

9

1

14

3

U7100

CRITICAL

ISL6259

TQFN

2

1R7102NO STUFF

1/16W

100K

MF-LF402

5%

67

32

1

4

5

Q7155CRITICAL

SI7137DPSO-8

3

2

1

D7105CRITICAL

SOT-323BAT30CWFILM

2

1R71121K

MF-LF402

1%1/16W

321

4

5

Q7130NTMFS4C06N

CRITICAL

DFN

2

1C714068UF20%16VPOLY-TANTCASE-D2E-SM

CRITICAL

21

R710520

MF-LF402

1/16W5%

2

1 C7135CRITICAL

1UF

X5R603

10%35V 2

1 C7136CRITICAL

1UF

X5R603

10%35V

2

1C7155

603-1

1UF

X5R

10%25V

21

R71000

MF-LF402

5%1/16W

41 42

50

72

2

1 C71850.1UF

402X5R

10%25V

2

1 R7185470K

MF-LF402

1%1/16W

2

1R7186332K

MF-LF402

1%1/16W

2

1R718162K1/16WMF-LF402

5%

2

1R7180

402

100K

MF-LF

5%1/16W

21

F7141

0603

CRITICAL

8AMP-32V-0.006OHM

21

F71408AMP-32V-0.006OHM

CRITICAL

0603

4 3

2 1

R71500.005

CRITICAL

0612-3

1WMF

1%

21

L7130

PIME173T-SM

4.7UH-20%-14.5A-9MOHM

CRITICAL

2

1C7130

TANT-POLY

10UF

CASE-D2-SM

20%35V

CRITICAL

2

1C7131

CASE-D2-SMTANT-POLY

20%35V

CRITICAL

10UF2

1C7132CRITICAL

10UF

CASE-D2-SM

20%35VTANT-POLY 2

1C7133CRITICAL

10UF20%35V

CASE-D2-SMTANT-POLY 2

1C7134CRITICAL

10UF

TANT-POLY

20%35V

CASE-D2-SM

2

1R71421K5%

402MF-LF1/16W

2

1R7195681K1/20W

MF201

1%2

1 C7198

10V

CRITICAL

10UF20%

X5R-CERM0402-1

PLACE_SIDE=TOP

2

1R7196

1/20W

200K

MF201

1%

2

1C7194

402

10VCERM

0.22UF10%

21

L719533UH-20%-0.39A-0.435OHM

CRITICAL

DP418C-SM

2

1 C7195

C0G0201

22PF50V5%

2

1C71904.7UF

35VX5R-CERM

PLACE_SIDE=TOP

10%

0603

6

9

48

7

5

1

3

2

U7190LT3470A

CRITICAL

DFN

21

R7190NOSTUFF

1/16W5% 402MF-LF

0

2

1 C7199CRITICAL

10UF20%10VX5R-CERM

PLACE_SIDE=BOTTOM0402-1

2

1C71050.22UF

X5R-CERM0603-1

10%50V

2

1R7110130K

MF-LF402

1%1/16W

2

1R711140.2K

MF-LF402

1%1/16W

2

1 C7180NOSTUFF

NONE

NONE

603

OMIT

NONE

25 14

36

10

9 78

Q7180IRF9395TRPBF

CRITICAL

DIRECTFET-MC

2

1C71914.7UFPLACE_SIDE=BOTTOM

35V10%

X5R-CERM0603

321

4

5

Q7135NTMFS4C10NDFN

CRITICAL

PBus Supply & Battery ChargerSYNC_MASTER=CLEAN_X305 SYNC_DATE=01/15/2014

P5V1_SWMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmSWITCH_NODE=TRUEDIDT=TRUE

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

PPVBAT_G3H_CONN

PP5V1_CHGR_VDDMIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.2 mm

VOLTAGE=5.1V

CHGR_CSO_N

SMC_BC_ACOKCHGR_BMON

CHGR_VCOMP_R

CHGR_ICOMP

SMC_RESET_L

CHGR_AMON

CHGR_VCOMP

SMBUS_SMC_5_G3_SCL

CHGR_VFRQ

CHGR_RST_L

CHGR_VNEG

CHGR_ICOMP_RC

SMBUS_SMC_5_G3_SDA

CHGR_VNEG_R

CHGR_CELL

CHGR_ACIN

CHGR_CSO_P

PPDCIN_G3H_ISOL


CHGR_AGATE_DIV

VOLTAGE=12.6V

PPVBAT_G3H_CHGR_RMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 MM

CHGR_CSO_R_N

CHGR_CSO_R_P

GND_CHGR_AGND

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmCHGR_DCIN_D_R

CHGR_DCIN

PP5V1_CHGR_VDDP

P5V1_BOOSTDIDT=TRUE

MIN_LINE_WIDTH=0.6 mmPPDCIN_G3H_INRUSH

VOLTAGE=20VMIN_NECK_WIDTH=0.25 mm

CHGR_SGATE_DIVMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.25 mm P5V1_FB

CHGR_CSI_R_N

CHGR_CSI_R_P

CHGR_CSI_N

PPDCIN_G3H

CHGR_BGATE

CHGR_SGATECHGR_AGATE

GATE_NODE=TRUE DIDT=TRUECHGR_LGATEMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm


PPVBAT_G3H_CHGR_REG

VOLTAGE=12.6V

PPBUS_G3H

CHGR_CSI_P

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmPP5V1_CHGR_VDDP

VOLTAGE=5.1V

DIDT=TRUECHGR_BOOTCHGR_UGATE GATE_NODE=TRUE DIDT=TRUE


PPDCIN_G3H_CHGRMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=20V

GND_CHGR_AGND

VOLTAGE=0V


CHGR_DCIN

CHGR_DCIN_D_R


CHGR_PHASE

SWITCH_NODE=TRUEDIDT=TRUE

PP3V42_G3H

<BRANCH>

<SCH_NUM>

<E4LABEL>

71 OF 118

57 OF 82

56 72

81

81

45 56 70

82

82

57

57 57

57

82

82

81

56 70 72

30 45 56 63 65 70 72

81

57

57

57

57

19 35 38 39 41 42 43 44 50 56 65 67 70 72

w w w

. c h

i n a

f i x

. c o

m

BI

IN

OUT

IN

OUT

ISEN3

ISEN2

ISEN1

IMON

ISUMN

ISUMP

FB2

FB

RTN

COMP

SCLK

ALERT*

SDA

NTC

VINVDD

FCCM

PWM1

PWM2

PWM3

DRSEL

PGOOD

THRM

VR_ON

PROG3

NC

NC

NC

NC

PROG2

SLOPE

VR_HOT*

PROG1

PAD

OUT

OUT

NC

NCNC

OUT

OUT

OUT

NC

IN

IN

IN

IN

OUT

IN

IN

IN

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(CPU_VCCSENSE_N)

(GND)

(CPUVR_ISUMP)

8 75

8 75

8 75

18 19 41 67 72

6 41 42 75

2

1R7279


54.91%

MF1/20W

201 2

1R72801%110

MF1/20W

201

PLACE_NEAR=U7200.30:2mm1

4

17

16

33

29

30

32

13

23

22

2026

27

28

2

5

24

21

19

9

15

14

10

11

12

3

18

8

7

25

6

31

U7200ISL95826AHRZ-_S2378

LLP

CRITICAL19

59

59

59

59

21

R7224

1%1/16W

0402

2.49M

MF

21

R7202

1/16WMF-LF

10

402

5%

2

1C72020.22UF

PLACE_NEAR=U7200.17:2mmX7R25V10%

0402

21

R7201

1/16WMF-LF402

1

5%

2

1 C7201

402-1

PLACE_NEAR=U7200.16:2mm 1UF10%10VX5R

59

59

59

2

1 C7210

0201

20%6.3VX6S-CERM

0.22UF

2

1 C72110.22UF

X6S-CERM0201

6.3V20%

2

1 C72120.22UF

X6S-CERM0201

6.3V20%

59

2

1C72130.1UF

6.3V10%

CERM-X5R0201

2

1R72204.02K1%

MF1/20W

2012

1R7221

201

1%154K

MF1/20W

46

2

1R723093.1K

201

1/20WMF

1%

2

1C7230

10V

0201

1500PF10%

X7R

59

2

1C7214NO_XNET_CONNECTION=TRUE

220PF

X7R-CERM

10%

201

25V

21

R7215

201

845

1%MF1/20W

21

C7215

X7R-CERM

2700PF

10V20110%

21

C7216

02015%25V NP0-C0G

39PF

8 75

9 75

2

1 C7260

X7R16V10%330PF

02012

1 C7261

X7R0201

16V10%330PF

2

1C7240

X7R-CERM

10%1800PF

0201

25V

2 1

C7242

0201C0G

5%25V


100PF

2

1C7241

C0G

5%25V

0201

18PF


2

1R7240


365K1%

MF1/20W

201

2 1

R72421K

1%

MF1/20W

201

21

R7243

MF1/20W

0201

0

5%

21

R7235

201MF

9.31K

1%1/20W

2

1R7236

201

95.3K1%

MF1/20W

2

1

R7237100KOHM0201

21

R7250NO_XNET_CONNECTION=TRUE

NO STUFF201

2K

1/20WMF

1%

2

1 C7250

X7R0201

10%16V

330PF

NO STUFF

21

R72412.87K

1%

MF1/20W

201

21

R7210

1/20W1%

487

MF201

2

1R7223102K

MF

1%1/20W

201 2

1R72229.31K

201

1%

MF1/20W

2

1C7231

C0G

5%47PF

25V

0201

2

1 C7279

0402

16V

0.01UF

X7R-CERM

10%

CPU VR12.5 VCC Regulator IC


CPUVR_ISUMN

CPUVR_ISEN2

CPUVR_ISUMP

CPU_VIDSCLKCPU_VIDALERT_LCPU_VIDSOUT

CPUVR_COMP

CPUVR_FB2CPUVR_FB

CPUVR_IMON

CPUVR_ISEN3

PPVCCIO_S0_CPUCPUVR_NTC

CPUVR_PROG2

CPUVR_ISEN1

CPU_VCCSENSE_N

CPUVR_COMP_RC

CPUVR_ISUMN_R

CPUVR_ISUMN_RC

CPU_VCCSENSE_P_R

CPUVR_SLOPE

CPUVR_PROG3

ALL_SYS_PWRGD

CPU_VCCSENSE_P

CPUVR_PWM1


CPU_VCCSENSE_P_RC

CPUVR_PGOOD

CPUVR_PWM3CPUVR_PWM2

CPUVR_FCCM

CPUVR_DRSEL

PP5V_S0

CPUVR_FB_RC

PPVIN_S0_CPUVR_VINMIN_LINE_WIDTH=0.3 mm


PP5V_S0_CPUVR_VDDMIN_NECK_WIDTH=0.2 mmVOLTAGE=5V


CPU_PROCHOT_L

CPUVR_PROG1

CPUVR_NTC_R

<BRANCH>

<SCH_NUM>

<E4LABEL>

72 OF 118

58 OF 82

5 6 8 10 18

45 59 60 62 70 18 19 37 49 59 62 63 66 67 70 71 72

w w w

. c h

i n a

f i x

. c o

mIN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

NC

NC

NC

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*NC

NC

NC

NC

IN

NC

NC

NC

NC

PWM

VCIN

VDRV

CGND

NC

VIN

VSWH

PGND

BOOT

DISB*

GL

GH

PHASE

ZCD_EN*

THWN*

IN

IN

OUTOUT

OUTOUT

OUT OUT

Apple Inc.


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REVISION

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6 3



152S1538

Additonal Input Bulk CapsTHESE TWO CAPS ARE FOR EMC

Vout = 1.85V max95A max outputf = 450 kHz

THESE TWO CAPS ARE FOR EMC

152S1538

353S3836

PHASE 1

PHASE 3

PHASE 2

353S3836

353S3836

152S1538

THESE TWO CAPS ARE FOR EMC

2

1 C7372

20%16V

CASE-D2E-SMPOLY-TANT

68UF

CRITICAL

2

1 C7371

20%16VPOLY-TANTCASE-D2E-SM

68UF

CRITICAL

2

1 C7370CRITICAL


68UF20%16V

2

1 C7319

0402X7R-CERM50V10%0.001UF

2

1 C7318

X7R-CERM50V

0402

10%0.001UF

2

1 C7317

16VX6S-CERM0402

10%1UF

2

1 C7316

0603

NOSTUFFCRITICAL

16VX6S-CERM

20%10UF

2

1 C7315

0603

20%16VX6S-CERM

10UF

CRITICALNOSTUFF

43

21

R7310

0612-1

1W

0.000751%

MF

CRITICAL

2

1R7314


1/20WMF201

1%3.9

2

1 C7314

POLY-TANTCASE-D2E-SM

20%16V

68UF

CRITICAL

2

1 C7313CRITICAL


20%16V

68UF

21

L73100.36UH-20%-36A-0.00108OHM

CRITICAL

PIMS103T-SM

2

1R7312

603MF-LF1/10W

2.25%

NOSTUFF

2

1 C73120.001UF

NOSTUFF

50V10%

X7R-CERM0402

58

58 59

2

1 C7373

20%16V


68UF

CRITICAL

2

1R731610K1/20WMF201

1%

NO_XNET_CONNECTION=TRUE2

1R7315

201NO_XNET_CONNECTION=TRUE

1/20W

1K1%

MF

58

58 59

58 59

21

R7317


201MF

1%1/20W

10K

2

1 C73290.001UF10%50V

0402X7R-CERM

58 59

2

1 C7328

10%50V

0.001UF

X7R-CERM0402

2

1 C7327

16V

1UF10%

0402X6S-CERM

2

1R7324


1/20WMF201

1%3.9

2

1 C7326

20%

0603

16VX6S-CERM

CRITICALNOSTUFF

10UF

2

1 C7325

X6S-CERM

20%

CRITICALNOSTUFF

10UF

16V

0603

2

1 C7324CRITICAL

68UF

16V20%


2

1 C7323

POLY-TANT16V

68UF

CASE-D2E-SM

20%

CRITICAL

21

L73200.36UH-20%-36A-0.00108OHM

CRITICAL

PIMS103T-SM

2

1 C7322

0402

50V10%

NOSTUFF

0.001UF

X7R-CERM

2

1R73261%

MF201

1/20W

10K


1R7325

1/20WMF201

1K1%


2

1R7322

2.2

MF-LF1/10W

603

5%

NOSTUFF

58

2

1 C7339

X7R-CERM

10%0.001UF

50V

0402

58 59

2

1 C7338

0402X7R-CERM50V10%0.001UF

2

1 C7337

X6S-CERM

1UF

0402

16V10%

2

1R7334


3.91%

201MF1/20W

2

1 C7336

16V20%

NOSTUFFCRITICAL

10UF

0603X6S-CERM2

1 C733510UF

X6S-CERM16V

NOSTUFFCRITICAL

0603

20%

2

1 C7334CRITICAL

68UF


16V20%

2

1 C7333CRITICAL


16V

68UF20%

21

L7330

PIMS103T-SM

CRITICAL

0.36UH-20%-36A-0.00108OHM

2

1 C73320.001UF

50V10%

X7R-CERM0402

NOSTUFF

2

1R7336

201

1%

MF

10K1/20W


1R7335

1/20WMF

1%

201

1K


2

1R7332

1/10W

603MF-LF

5%2.2

NOSTUFF

58

58 59

58

58 59

1

43

35

34

33

32

31

30

29

15

42

14

13

12

11

10

9

3

2

38

40

7

25

24

23

22

21

20

19

18

28

27

26

17

16

8

36

6

39

41

375

4 U7310PQFN

CRITICAL

FDMF6808N1 2

R7311

1/16W

402

0

MF-LF

5%

21

C73110.22UF

402CERM16V10%

2

1C7310

0402X6S-CERM

10%16V

1UF

1

43

35

34

33

32

31

30

29

15

42

14

13

12

11

10

9

3

2

38

40

7

25

24

23

22

21

20

19

18

28

27

26

17

16

8

36

6

39

41

375

4 U7320FDMF6808N

PQFN

CRITICAL

2

1C7320

0402X6S-CERM

10%16V

1UF

1 2

R7321

402

0

1/16WMF-LF

5%

21

C7321

402

0.22UF

CERM16V10%

58 59

2

1C73301UF

16V10%

X6S-CERM0402

1

43

35

34

33

32

31

30

29

15

42

14

13

12

11

10

9

3

2

38

40

7

25

24

23

22

21

20

19

18

28

27

26

17

16

8

36

6

39

41

375

4 U7330

CRITICAL

PQFNFDMF6808N

1 2

R7331

402

5%

MF-LF1/16W

0

21

C7331

10%16VCERM

0.22UF

402

58

58 59

4 3

2 1

R7320

0612-1

CRITICAL

0.00075

1W1%

MF

43

21

R7330

0612-1MF1W

CRITICAL

0.000751%

2

1 C737668UF

CRITICAL


16V20%

2

1 C7375CRITICAL

68UF

CASE-D2E-SMPOLY-TANT16V20%

2

1 C7374CRITICAL


68UF20%16V

2

1 C7377

16V

SMTANT

15UF20%

CRITICAL

2

1 C7378

SMTANT

15UF20%16V

CRITICAL

2

1 C7379

SMTANT

15UF20%16V

CRITICAL

2

1 C7380

SMTANT

15UF20%16V

CRITICAL

21

R7318

201MF

1%1/20W


10K

21

R7327

NO_XNET_CONNECTION=TRUE1%

10K

201

1/20WMF

21

R7328


10K

201

1/20WMF

21

R7337


10K

201

1/20WMF

21

R7338

MF1/20W

201

10K

1% NO_XNET_CONNECTION=TRUE

2

1 C7381CRITICAL


68UF20%16V 2

1 C7382CRITICAL


68UF20%16V 2

1 C7383CRITICAL


68UF20%16V 2

1 C7384

16V20%68UF


CRITICAL

46 59 82 46 82

46 59 82 46 82

46 82 46 59 82

SYNC_MASTER=J15_MLB

CPU VR12.5 VCC Power StageSYNC_DATE=10/31/2012

CPUVR_ISUMN

CPUVR_ISNS3_P

PPVCC_S0_CPU_PH3

VOLTAGE=1.8V


VOLTAGE=1.8V

PPVCC_S0_CPU_PH2


CPUVR_ISNS2_NCPUVR_ISNS2_P

CPUVR_ISEN1

CPUVR_ISUMN

PPVCC_S0_CPU_PH1

VOLTAGE=1.8V


CPUVR_ISNS1_P

CPUVR_PHASE1

DIDT=TRUE

SWITCH_NODE=TRUE


CPUVR_PH2_SNUB

DIDT=TRUE


CPUVR_PHASE3

SWITCH_NODE=TRUE

DIDT=TRUE


CPUVR_BOOT2_RCMIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_BOOT3

DIDT=TRUEMIN_NECK_WIDTH=0.2 MM


CPUVR_BOOT1

MIN_NECK_WIDTH=0.2 MMDIDT=TRUE


CPUVR_BOOT3_RC



MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMDIDT=TRUE

CPUVR_BOOT1_RC

CPUVR_PH3_SNUB

DIDT=TRUE

CPUVR_PH1_SNUB

DIDT=TRUE

CPUVR_BOOT2MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUVR_ISEN3

CPUVR_ISNS2_N

CPUVR_ISNS1_N

CPUVR_ISNS3_N

CPUVR_ISNS1_N

CPUVR_FCCM

CPUVR_ISUMP

CPUVR_PWM2

PP5V_S0

CPUVR_FCCM

CPUVR_FCCM

CPUVR_PWM3

PP5V_S0

CPUVR_ISNS2_NCPUVR_PWM1

PP5V_S0

CPUVR_PHASE1_K

CPUVR_PHASE2_K

CPUVR_PHASE3_K

CPUVR_ISNS3_N

CPUVR_ISNS1_N

CPUVR_ISUMN

CPUVR_ISUMP

CPUVR_ISUMP

CPUVR_ISEN2

CPUVR_ISNS3_N

PPVCC_S0_CPU

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=1.5 MMCPUVR_PHASE2



<BRANCH>

<SCH_NUM>

<E4LABEL>

73 OF 118

59 OF 82

46 59 82

46 59 82

46 59 82

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

46 59 82

18 19 37 49 58 59 62 63 66 67

70 71 72

46 59 82

6 8 10 46 70 72

45 58 60 62 70

w w w

. c h

i n a

f i x

. c o

m

IN

V5IN

REFIN

S5

VREF

S3

MODE

TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

INVSW

PGND

TGR

TG

BG

VIN

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6 3




C7460, C7461, C7462, C7463 close to memory

NOTE:MIRROR C7460, C7462 and C7461, C7463

152S0905

(DDRREG_LL)

(DDRREG_VDDQSNS)

(DDRREG_DRVL)

10mA max load

DDR3L (1V35 S3) REGULATOR

18A max output

Vout = 1.35V

(Q7335 limit)

f = 400 kHz

(DDRREG_DRVH)(VTT Enable)

(VDDQ/VTTREF Enable)

2

1C7400BYPASS=U7400.12:10:5MM

10VX5R-CERM

10UF20%

0402-1

2

1C743068UF

CRITICAL

20%


16V 2

1C743168UF

CRITICAL


20%16V

21

C7425

X5R402

10%

0.1UF

25V

2

1 C743310%0.001UF

X7R-CERM0402

50V

2

1C7440CRITICAL

TANTCASE-B4-SM

20%2V

270UF

21

L7430

PCMB103T

CRITICAL

0.68UH-18A-3.3MOHM

2

1C7441270UF

CASE-B4-SM

20%

CRITICAL

TANT2V 2

1 C744510UF

0402

4VX6S

20%2

1 C74460.001UF

0402

10%50VX7R-CERM

67

1

5

4

3

6

2

9

1512

18

21

13

16

17

8

20

10

19

7

11

14U7400TPS51916

QFN

CRITICAL 67

21

XW7460PLACE_NEAR=C7461.1:3mm

SM

2

1

XW7400SM 2

1C7450

CERM10V10%

0.22UF

402

BYPASS=U7400.5:7:5mm

2

1C746020%

10UF

0402X6S

PLACE_SIDE=TOP

4V


21 71

2

1C74150.1UF

X7R-CERM0402

10%16V

2

1 C7461

0402

PLACE_SIDE=TOP


10UF20%

X6S4V

2

1R7417

1/16W1%

402MF-LF

200K

2

1R741519.6K

MF-LF1/16W1%

402

2

1R741660.4K

402

1%1/16WMF-LF 2

1 C7416

X7R-CERM

0.01UF

0402

10%16V

2

1C7401

X5R-CERM

10UF

BYPASS=U7400.2:10:5MM

10V20%

0402-1

8

7

6

1

4

3

9

5

Q7430SON5X6

CSD58872Q5D

CRITICAL

2

1R741852.3K

MF-LF402

1%1/16W

2

1C7435CRITICAL

15UF

SM

20%

TANT16V

2

1C7462

PLACE_SIDE=BOTTOM

X6S0402

10UF4V20%

2

1C746310UF

20%4VX6S

PLACE_SIDE=BOTTOM

0402

2

1 C744720%

0402X6S

10UF4V

21

R740110

1%1/20WMF201

2

1 C7432

0402

25V

1UF

X5R

10%2

1 C7434

0402

25VX5R

10%1UF

21R7425

05%

1/16WMF-LF402


1.35V DDR3L SUPPLYSYNC_DATE=01/15/2014

DDRREG_VBST


DIDT=TRUEGATE_NODE=TRUEDDRREG_DRVL


SWITCH_NODE=TRUE DIDT=TRUEDDRREG_LL



DDRREG_VBST_R


PP1V35_S3

DIDT=TRUEDDRREG_DRVH MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mmGATE_NODE=TRUE

PPVTT_S0_DDR

DDRREG_TRIPDDRREG_VTTSNS

DDRREG_EN

DDRREG_MODE

DDRREG_PGOOD


DDRREG_VSWSWITCH_NODE=TRUEDIDT=TRUE

MEMVTT_EN

DDRREG_VDDQSNS


PP1V35_S3

PP5V_S3


PPVTTDDR_S3

VOLTAGE=0VMIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.6 mmGND_DDRREG_SGND

DDRREG_FB

DDRREG_1V8_VREF

<BRANCH>

<SCH_NUM>

<E4LABEL>

74 OF 118

60 OF 82

21 46 60 66 70 72

21 46 60 66 70 72

21 37 66 67 70 72

45 58 59 62 70

70 72

w w w

. c h

i n a

f i x

. c o

m

OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1

SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2

CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

IN

OUT

VSW

PGND

TGR

TG

BG

VIN

G2

S2

D1

S1/D2

G1

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6 3







11A MAX OUTPUT 152S0754

F = 400 KHZ

VOUT = 3.3V

F = 400 KHZ

VOUT = 5.0V

(P5VP3V3_VREF2) (P5VP3V3_VREF2)

VOUT = 5V

10A MAX OUTPUT

100MA MAX OUTPUT2

1C75001UF

X5R603-1

10%25V

21

L75601.0UH-22APCMC063T-SM

CRITICAL

2

1C75640.1UF

10%

X5R25V

402

2

1 C7590

10VX5R-CERM0402-1

20%10UF

2

1 C7524

402X5R25V10%0.1UF

2

1C755220%

POLY-TANT6.3V

330UF

CRITICAL

CASE-D3L-SM2

1C7550

0402-1X5R-CERM

10V20%

10UF

CRITICAL

2

1 C7581

0402

25V10%1UF

X5R

2

1 C750320%

X5R-CERM

2.2UF10V

402

2

1 C7505

0402-1

10V

10UF

X5R-CERM

20%

2

1R7506

402

1%249K1/16WMF-LF

67

2

1

XW7561

PLACE_NEAR=L7560.2:3MM

SM

2

1C75010.22UF

10V10%

CERM402

2

1R7560

MF-LF402

1/16W1%

23.2K

2

1R7561

1/16W1%

402MF-LF

10K

2

1R7520

1/16W1%

402MF-LF

40.2K

2

1R7521

1/16WMF-LF

1%

402

10K

2

1C7580


16V20%

68UF

CRITICAL

21

C75880.15UF

10V10%

X5R402

2

1

XW7560SM


21

C7518

10%10VX5R402

0.15UF

21

R7547

402

3.24K

MF-LF

1%1/16W

2

1R7556

1/16W1%

402MF-LF

4.75K2

1

XW7520SM


2

1

XW7521SM


2

1R753612.1K

402

1%1/16WMF-LF

2

1R753710K

MF-LF402

1%1/16W

2

1C7537

0402

15PF5%50V

CERM

2

1C7592330UF

POLY-TANTCASE-D3L-SM

20%6.3V

CRITICAL

2

1R753920.0K1/16W

1%

402MF-LF

2

1 C7539

0402CER

47PF5%50V

2

1R753812.1K

MF-LF402

1%1/16W

67

2

1C7599

0402

50V10%

X7R-CERM

NO STUFF

0.0033UF

2

1R7599

1/10WMF-LF

15%

603

NO STUFF

2

1R75985%

NO STUFF

1/10W

603MF-LF

10

2

1C757210%50V

0402X7R-CERM

0.001UF

2

1 C75830.001UF

X7R-CERM0402

10%50V

2

1 C75700.001UF50V10%

0402X7R-CERM

2

1 C7571

0402X7R-CERM50V10%0.001UF

29

22

13

23

169

2631

2

33

2532

19

6

3

205

14

11

28

214

12

2730

241

187

178

1510

U7501QFN

TPS51980

CRITICAL

2

1C7542


CRITICAL

20%16V

68UF

2

1C7582

CASE-D2E-SM

16V20%

POLY-TANT

68UF

CRITICAL

41 42 67

21

R75461K

1%

402MF-LF1/16W

2

1R7516

402

1%

MF-LF1/16W

4.02K

2

1 C7541

0402X5R

10%25V

1UF

67

41 67

2

1 C7598

X7R-CERM

10%

NO STUFF

0.001UF50V

0402

2

1

XW7500PLACE_NEAR=U7501.28:1MM

SM

8

7

6

1

4

3

9

5

Q7520SON5X6

CRITICAL

CSD58872Q5D

2

1R7500

0201MF

05%

1/20W

SKIP_5V3V3:AUDIBLE

2

1R7501

MF1/20W

0201

5%0

SKIP_5V3V3:INAUDIBLE

2

1C7553

6.3V

CASE-B2-SM

20%

POLY-TANT

150UF-0.035OHMCRITICAL

2

1C7554

150UF-0.035OHM

20%6.3V

POLY-TANTCASE-B2-SM

CRITICAL

2

1C759320%

6.3V

CRITICAL

POLY-TANT

150UF-0.035OHM

CASE-B2-SM

2

1

L7520PCMB103T-SM

CRITICAL

2.2UH-20%-13A-9MOHM

2

1 C7536

402CERM

10%100V

4700PF

2

1C7538

100V

4700PF10%

CERM402

2

1C7594

POLY-TANTCASE-B2-SM

CRITICAL

6.3V20%

150UF-0.035OHM2

1 C7555

NO STUFF

150UF-0.035OHM6.3V20%

POLY-TANTCASE-B2-SM

CRITICAL

2

1C7585CRITICAL

SM

15UF20%16V

TANT2

1C7584

SM

16VTANT

20%15UF

CRITICAL

2

1C7543CRITICAL

16V

SM

20%

TANT

15UF2

1C7544


16V20%

68UF

CRITICAL

2

1C7551CRITICAL

20%10UF

10VX5R-CERM

0402-1

2

1 C7591

X5R-CERM0402-1

20%10UF10V

2

1R752210

402MF-LF

5%1/16W


2

1R756210

402MF-LF1/16W5%


21

R75641

1/16W

402MF-LF

5%

21

R7545

402MF-LF1/16W5%

1

2

1 C7540

0402

25VX5R

1UF10%

2

1 C7586

0402

1UF

X5R

10%25V

7

6

5

10

8

19

4

3

2

Q7560

DFN8

CRITICAL

NTMFD4951NF


5V / 3.3V Power Supply

PP5V_S5

SWITCH_NODE=TRUEP3V3S5_LL

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

GATE_NODE=TRUE


MIN_NECK_WIDTH=0.2 MMDIDT=TRUE GATE_NODE=TRUEP3V3S5_DRVH




DIDT=TRUEP3V3S5_VBST_R


P5VP3V3_VREF2

GND_5V3V3_AGND

VOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM

DIDT=TRUE MIN_LINE_WIDTH=0.6 MMP3V3S5_DRVL

P3V3S5_SNUBRMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MMDIDT=TRUE

PP3V3_S5

DIDT=TRUEP3V3S5_CSP2_R

P3V3S5_CSN2

SMC_PM_G2_EN

DIDT=TRUESWITCH_NODE=TRUEP5VS4_LL


P5VS4_VBST_RDIDT=TRUE


P5VS4_COMP1

P5VS4_SNUBRMIN_LINE_WIDTH=0.6 MM



P5VS4_VSW

PP5V_S4

DIDT=TRUE


P3V3S5_VBST



GATE_NODE=TRUE DIDT=TRUEP5VS4_DRVH

P5VP3V3_SKIPSEL

P5VS4_PGOOD

GATE_NODE=TRUE DIDT=TRUEP5VS4_DRVL


P5VS4_EN

P3V3S5_VFB2_R

S5_PWRGD

PP5V_S4

P5VS4_COMP1_R

P3V3S5_EN

P5VS4_VFB1_R

P5VS4_CSP1_RDIDT=TRUE

P3V3S5_COMP2_R

P3V3S5_CSP2

P5VP3V3_VREG3

DIDT=TRUE


P5VS4_VBST


P5VS4_CSP1

P3V3S5_VFB2P3V3S5_COMP2

P3V3S5_RF

P5VS4_CSN1

P5VS4_VFB1

75 OF 118

<E4LABEL>

<SCH_NUM>

61 OF 82

<BRANCH>

66 70 72

45 70

12 14 15 17 18 19 21 31 32 34

64 66 67 70 71

72 82

38 39 51 61 66 67 68 69 70 72

38 39 51 61 66 67 68 69 70 72

45 70

w w w

. c h

i n a

f i x

. c o

m

OUT

IN BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC PVCC

GND PGND

EN

FB

OUT

OUT

G2

S2

D1

S1/D2

G1

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6 3



<Rb> <Rb>

f = 300 kHz

1V05 S0 REGULATOR

(PCHVCCIOS0_VO)

(PCHVCCIOS0_OCSET)

12A MAX OUTPUT

Vout = 1.05V

Vout = 0.5V * (1 + Ra / Rb)

<Ra><Ra>

OCP = 14.4AOCP = R7641 x 8.5uA / R7640

152S0955

376S00043

(P1V05S0_LL)


2

1R7644

402MF-LF

3.01K1%1/16W


67

67

2

1C7602

X5R-CERM

2.2UF

BYPASS=Q9800.13:1:5mm

10V20%

402 2

1R7603

1/16W

0

MF-LF

5%

NO STUFF

402

21

XW7600


SM

8

13

11

4

2

14

10

9

16

7

15

1

5

6

3 12

U7600ISL95870

CRITICAL

UTQFN

2

1R7601

402MF-LF

2.21/16W

5%2

1 C7601

0402-1X5R-CERM

10UF20%10V

BYPASS=Q9800.14:16:5mm2

1 C76301UF

402

10%

X5R16V

2 1

C7640

10%

X7R-CERM50V

0402

0.0018UF

2

1C7623

25V5%

1000PF

CERM0402

PLACE_NEAR=L7630.2:1.5mm

2

1C7620CRITICAL

68UF


20%16V 2

1C762168UF

CRITICAL


20%16V 2

1 C7622


1000PF

0402

5%

CERM25V

2

1C7648

2V20%270UF

CRITICAL

TANTCASE-B4-SM

34

12

R7640CRITICAL

0.001

MF-10612

1%1W

2

1C7649CRITICAL

270UF

TANTCASE-B4-SM

20%2V

2

1R76300

MF-LF603

5%1/10W

2

1C7604

CERM50V5%

0402

10PF

21

XW7601PLACE_NEAR=U1100.AJ12:1MM

SM

21

XW7602PLACE_NEAR=U1100.AK14:1MM

SM

2

1R7642

201MF

1%1/20W

1.37K

2

1R7641

201

1/20WMF

1%1.37K2

1 C7605

CERM50V5%

0402

10PF

21

L7630

PCMC063T-SM

CRITICAL

0.68UH-25A-5.5MOHM

46 62 82

46 62 82

2

1 C7624


10%1UF25VX5R0402

2

1 C7625

X5R0402


1UF10%25V

7

6

5

10

8

19

4

3

2

Q7630NTMFD4951NF

DFN8

CRITICAL

2

1 C7603

0402

10%16V

0.047UF

X7R-CERM

2

1R76452.74K

MF-LF402

1%1/16W

2

1R7605

1/16W

2.74K

MF-LF402

1%

2

1R76043.01K

402

1%1/16WMF-LF



1V05V POWER SUPPLY

DIDT=TRUE

P1V05S0_BOOT_RCMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm



P1V05S0_LL



DIDT=TRUE

P1V05S0_VBST

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

P1V05S0_DRVHMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P1V05S0_OCSET

PP5V_S0

P1V05S0_DRVL

DIDT=TRUEGATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

P1V05S0_CS_N

P1V05S0_CS_N MAKE_BASE=TRUE

P1V05S0_CS_P MAKE_BASE=TRUE

P1V05S0_VO

P1V05S0_SREF

P1V05S0_PGOOD

P1V05S0_FB

P1V05S0_RTN

VOLTAGE=0VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmP1V05S0_AGND

P1V05S0_SENSE_PPP1V05_S0

P1V05S0_EN

PP1V05_S0

P1V05S0_SENSE_N


PP1V05_S0_REG_R

VOLTAGE=1.05V


P1V05S0_FSEL

P1V05S0_CS_P

PP5V_S0_P1V05S0_VCC

VOLTAGE=5V


<BRANCH>

<SCH_NUM>

<E4LABEL>

76 OF 118

62 OF 82

45 58 59 60 70

18 19 37 49 58 59 63 66 67 70 71 72

46 62 82

46 62 82

82 10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42

62 67 70

72

82

w w w

. c h

i n a

f i x

. c o

m

GND_SW

GND_SW

SW2

FB2

KEYB1

KEYB2

SDA

SCL

PWM_KEYB

EN

SENSE_OUT

FB

THRM

GNDA

GNDD

GND_SW2

SD

VSENSE_N

VSENSE_P

SW

ISET_KEYB

GD

VDDA

VDDD

SW

PAD

IN

IN

OUT

OUT

IN

IN

OUT

BI

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6 3




PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

Page Notes

(PPBUS_S0_BKLT_PWR_F)

(PPBUS_S0_BKLT_PWR_R)

(IPU)

C7723, C7724 SHOULD BE PLACED MIRROREDC7720, C7721 SHOULD BE PLACED MIRRORED

371S0572152S1701

BKLT:PROD - Stuffs 0 ohm series R for production

BKLT:ENG - Stuffs 10.2 ohm series R for engineering builds

BOM options provided by this page:

- =PP5V_S0_KBDLED (5V Keyboard Backlight Input)

- =PP5V_S0_BKLTCTRL (5V Backlight Driver Input)

Power aliases required by this page:

- =PPVIN_S0_LCDBKLT (9-12.6V LCD Backlight Input)

(IPU)

353S4160

152S1527

10

9

5 18

25

2

1

6

19

16

11

15

12

14

13

20

3

22

24

23 7

4

8

21

17

U7701LLP

LP8548B1SQ_-04

CRITICAL

21

F7700CRITICAL

3AMP-32V-467

603-HF

21

L7710

DEM8030C-SM

22UH-20%-2.4A-0.105OHM

CRITICAL

21

L7720CRITICAL

10UH-20%-1.4A-0.17OHM

PST041H-CDH46D14-SM

2

1R770180.6K

201

1%

MF1/20W

2

1 C7700

16V10%1000PF

X7R-10201

2

1R7702

MF-LF402

1%1/16W

63.4K

4

3

6

5

2

1

Q7706CRITICAL

FDC638APZ_SBMS001SSOT6-HF

2

1 C77220.1UF

X5R-CERM0201

10%16V2

1 C77212.2UF

603

10%

X5R-CERM25V 2

1 C77250.001UF

X7R-CERM0402

10%50V

21

R77470

MF0201

5%1/20W

2

1 C774733PF

NPO-C0G0201

5%25V

NO STUFF

21

R77420

MF0201

5%1/20W

2

1C77401UF

X5R402-2

10%10V 2

1 C77411UF

X5R402-2

10%10V

2

1R77401M

MF201

5%1/20W

21

R772310.2

TF402

0.1%1/16W

BKLT:ENG

21

XW7700SM

2

1 C77120.1UF

X5R402

10%25V

12 71 72

41

2

1 C77010.001UF

CERM50V10%

402

NOSTUFF 2

1 C77104.7UF

X6S-CERM0603

10%25V 2

1 C7711

X6S-CERM0603

10%25V

4.7UF

2

1R774131.6K

MF201

1%1/20W

KA

D7720CRITICAL

RB160M-60G

SOD-123

2

1 C77231.0UF

X7R0805

10%50V 2

1 C77241.0UF

X7R0805

10%50V2

1 C77202.2UF

603

10%25VX5R-CERM

2

1 C7742NO STUFF

33PF

NPO-C0G0201

5%25V

2

1

XW7720PLACE_NEAR=D7720.K:2MM

SM

43

21

R77000.025

MTL0612

1%1W

47 82

47 82

21

R7724BKLT:ENG

TF402

0.1%1/16W

10.2

2

1R7709150K

MF-LF402

1%1/16W

2

1R770818.2K

1%

MF-LF402

1/16W

KA

D7701

DFLS2100

CRITICAL

POWERDI-123


321

4

5

Q7701


CRITICAL

PWRPK-1212-8SI7812DN

2

1R77030

MF-LF402

5%1/16W

21

R77580

MF 02015%1/20W

2

1R77612.4K

MF201

5%1/20W

2

1R77602.4K

MF201

5%1/20W

21

R77800

MF02015%

1/20W12 71

21

R77830

MF-LF402

5%1/16W

2

1R77440

MF-LF402

5%1/16W

2

1R77430

402

5%1/16WMF-LF

2

1 C77261.0UF

X7R0805

10%50V 2

1 C77271.0UF

X7R0805

10%50V

68 71 72

68 72

21

R77570

MF 02015%1/20W68 71 72

2

1 C7717

PLACE_NEAR=D7701.K:5MM

100V

1000PF10%

X7R-CERM0603

2

1 C7715


100V10%

1210-1X7R

2.2UF

CRITICAL

2

1 C7716CRITICAL


100V

1210-1

10%2.2UF

X7R 2

1 C7718


CRITICAL

2.2UF

X7R1210-1

10%100V 2

1 C7719


CRITICAL

2.2UF

X7R1210-1

10%100V

RES,MTL FILM,0 OHM,1A MAX,0402,SMD2 BKLT:PRODR7723,R7724116S0004


LCD/KBD Backlight Driver


MIN_LINE_WIDTH=2 MM


PPBUS_SW_BKL

EDP_IG_BKL_ON

BKLT_SD

BKLT_SENSE_OUT

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMVOLTAGE=5V

PP5V_S0_BKLT_VDDA

GND_BKLT_SGND

I2C_BKLT_SCL

KBDBKLT_RETURN2MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MM

GND_BKLT_SGND

VOLTAGE=12.6V

MIN_LINE_WIDTH=2 MMMIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_FUSED

PP5V_S0


KBDBKLT_RETURN1

MIN_NECK_WIDTH=0.25 MMDIDT=TRUE

BKL_FET_CNTL_RMIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.25 MMVOLTAGE=12.6V

MIN_LINE_WIDTH=2 MMPPBUS_SW_LCDBKLT_PWRPPBUS_G3H

BKLT_KEYB1

SMC_SYS_KBDLED

PP5V_S0

GND_BKLT_SGND

BKLT_ISET_KEYB


BKL_FET_CNTLMIN_LINE_WIDTH=0.6 MM

PP5V_S0_KBDLED_RMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=5V

EDP_IG_BKL_PWM LCD_BKLT_PWM_R

PPVOUT_S0_KBDBKLT

VOLTAGE=40V


BKLT_KEYB2

BKLT_PWM_KEYB

I2C_BKLT_SDA

BKLT_SCL

BKLT_SDA

MIN_NECK_WIDTH=0.2 MMVOLTAGE=0V

MIN_LINE_WIDTH=0.4 MMGND_BKLT_SGND

BKLT_EN_R

PP5V_S0

VOLTAGE=5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM PP5V_S0_BKLT_VDDD

LCDBKLT_EN_L

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

PPBUS_S0_LCDBKLT_PWR_SWMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=2 MM

DIDT=TRUESWITCH_NODE=TRUEVOLTAGE=45V

DIDT=TRUE

BKL_SWMIN_LINE_WIDTH=2 mmMIN_NECK_WIDTH=0.25 mm

BKL_FB

DIDT=TRUE

KBDBKLT_SWMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MM

PPVOUT_BKLT_FB2

VOLTAGE=40V


VOLTAGE=55V

MIN_LINE_WIDTH=0.5 MMPPVOUT_S0_LCDBKLTMIN_NECK_WIDTH=0.25 MM

<BRANCH>

<SCH_NUM>

<E4LABEL>

77 OF 118

63 OF 82

70

63

40 72 63

18 19 37 49 58 59 62 63 66 67 70 71 72

40 72

30 45 56 57 65 70 72

18 19 37 49 58 59 62 63 66 67 70 71 72

63

40 72

63

18 19 37 49 58 59 62 63 66 67 70 71 72

68 72

w w w

. c h

i n a

f i x

. c o

m

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND THRM_PAD

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

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6 3



Freq = 1.6MHZ

<Ra>

Max Current = 1.5A

Vout = 0.8V * (1 + Ra / Rb)

Lynx Point-H requires JTAG pull-ups to be powered at 1.05V in SUS.

70mA is required to support pull-ups. Alternative is strong voltage

1.5V S0 Regulator

dividers (200/100) to 3.3V SUS, which burns 100mW in all S-states.

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

<Rb>

Vout = 1.05VMax Current = 0.35A

1.05V SUS LDO

Vout = 1.508V66 67

1

6

9

4 5

3

8

7

2

U7810

CRITICAL

ISL8009BDFN

2

1 C7850

0402-1X5R-CERM10V20%10UF

CRITICAL

21

L7870

PCMB042T-IHLP1616BZ

2.2UH-3A

CRITICAL

2

1R7881

MF-LF402

1%1/16W

113K

2

1C787627PF

CERM

5%50V

0402-1 2

1R7880

MF-LF402

1%100K1/16W

2

1 C7871

X5R-CERM

20%6.3V

0805-1

47UF

CRITICAL

67

2

1 C7841XDP_PCH

2.2UF

X5R402

10%6.3V

7

1

2

6

5

3

4

U7840TPS720105

SON

XDP_PCHCRITICAL

2

1C7840XDP_PCH

1UF

CERM402

10%6.3V

2

1 C7851CRITICAL

20%10UF

0402-1

10VX5R-CERM


Misc Power SuppliesSYNC_MASTER=CLEAN_X305

P1V5S0_PGOOD

P3V3S0_P1V5_S0_EN

PP1V05_SUSPP3V3_SUS

PP3V3_S5


P1V5S0_SW



P1V5S0_FB

PP1V5_S0

<BRANCH>

<SCH_NUM>

<E4LABEL>

78 OF 118

64 OF 82

18 70 11 12 13 14 15 17 50 66 67 70

12 14 15 17 18 19 21 31 32 34 61 66 67 70 71 72 82

11 12 13 15 17 19 52 67 69 70 72

w w w

. c h

i n a

f i x

. c o

m

VCC

A*

B

CLR*

Q

REXT_CEXT

CEXT

GND

S

D

G

N-CHN

P-CHN

G

S

D

IN

G

SYM_VER_1

D

S

IN

IN

ISEN

EN/MODE

VIN

FB

AGNDPGND

COMP

VG

DR

VCC

NC

VIN1 OUT1

OUT2

DV_DT

EN_UVLO

OUT3

BFET

EPAD ILIM

VIN3

VIN2

IN

BI

D S

G

SYM_VER_2

G S

D

SG

D

P-CHN

G

S

D

S

D

G

N-CHN

SG

D

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6 3



EFUSE


RC Value not Final


X249 POWERX249_BOOST_MODESYSTEM STATE

RC Value set for 100ms

0 V

Hi-Z

0 V

X

X

PBUS

0 V

0 V

X

X

Hi-Z

Hi-Z

0 V

0 V

1.8 V

0 V (OFF)

0 V

0 V

28 V (BOOST)

BOOST OUTPUT

0 V (OFF) 0 V

PBUS

28 V

S4, S3, S0

S4, S3, S0

S4, S3, S0

G3H, S5

SYSTEM STATE

PBUS ONLY CONTROL INPUTS

S4, S3, S0

S4, S3, S0

G3H, S5

Hi-Z

0 V

X

X

3.3 V

0 V

S4, S3, S0

S4, S3, S0

X

Hi-Z

0 V

X

X 0 V

0 V (OFF)

X249 POWERTPAD_ACTUATOR_THRMTRIP_L

Hi-Z

X

TPAD_ACTUATOR_THRMTRIP_L

0 V 0 V (OFF)

0 V

(Open-Drain)

=X249_BOOST_EN(PM_SLP_S*_L)

SMC_ACTUATOR_DISABLE_L


0 V

BOOST CONTROL INPUTS (X249:BOOST BOM OPTION)

(Open-Drain)

(Open-Drain)

2

1R7912X249:BOOST

5%1/16WMF-LF

75K

402

2 1

R7913X249:BOOST

5%

402MF-LF

130K

1/16W

A2

B2

D2

D1

C1 C2

B1

A1

U7930

X249:BOOST

CRITICAL

BGASN74LVC1G123

2

1C793010%10V

1UF

X6S-CERM0402

X249:BOOST

2

1R7934X249:BOOST

1/16W

402

51.1K

MF-LF

1%

2

1C7934

402

1UF10%10VX5R

X249:BOOST

1

2

6

Q7904NTUD3169CZ

X249:BOOSTCRITICAL

SOT-963

4

5

3

Q7904

X249:BOOSTCRITICAL

NTUD3169CZSOT-963

2

1R7914

402MF-LF

200K1%

1/16W

X249:BOOST

2

1C7935

X249:BOOST

X7R-CERM

0.01UF10%

0402

16V

2 1

R7970

5%

402MF-LF

33K

1/16W

2

1C797110%

X5R402

16V

0.033UF

2

1C797010%16V

X7R-CERM

0.01UF

0402

40

K

AD7935SOD-523

BAT54XV2T1

X249:BOOST

2

1R7999X249:BOOST

5%

402

1M1/16WMF-LF

21

R793920.0K

402

1/16WMF-LF

1%

X249:BOOST

2

1

3

Q7909SOT23

CRITICAL

SI2308BDS-GE3

X249:BOOST

2

1R7915X249:BOOST

5%0

402

1/16WMF-LF

31 32 66 67

2 1

C7931X249:BOOST

10%

0.1UF

0402X7R-CERM

16V

21

R7916X249:BOOST

402

20.0K

MF-LF1/16W1%

2 1

R7919

5%

0

402MF-LF1/16W

NO STUFF

2 1

R7918X249:BOOST

5%

0

402MF-LF1/16W

2

1C7909

PLACE_NEAR=D7900.K:4mm

CERM-X5R0402

1.0UF35V10%

X249:BOOST

2 1

R7917

1/16WMF-LF402

5%

X249:BOOST

0

41 43

2

1R7923

1/20W5%0

0201MF

2

1C7908X249:BOOST

10%35V

1.0UF

0402CERM-X5R


2

1C79791.0UF

0402CERM-X5R

35V10%

2

1C797810%

0402CERM-X5R

1.0UF35V

10 4

1

3

9

6

5

2

7

8

U7900LM3017LE

CRITICAL

VQFN

X249:BOOST

2

1

R7964


10K5%

1/16WMF-LF

402 2

1R7965100K


1%1/16W

402MF-LF

2

1R7963

MF-LF


5%15K

1/16W

402

2

1 C7960


5%

NP0-C0G

NOSTUFF

25V

0402

1000PF

5

4

3

11

8

7

6

10

2

1

9

U7960TPS2592ZADRC

QFN

CRITICAL

2

1

XW7900SM


2

1 C7902X249:BOOST

0.1UF16V

0402X7R-CERM

10%

39 72

21

R7911X249:BOOST

5%

0

MF02011/20W

2

1C7903X249:BOOST

10%10V

0402

1UF

X6S-CERM

2

1C7900X249:BOOST

20%10UF

25V

0603X5R-CERM 2

1C790120%

X5R-CERM25V

0603

10UF

X249:BOOST

41

21

R7900

MF1/4W1%

0.5

CRITICAL

X249:BOOST

0805

32

1

4

5

Q7900

X249:BOOSTCRITICAL

3.3X3.3-QFN

CSD16340Q3

2

1C7904

X249:BOOST10%16V

0201

470PF

X5R-X7R-CERM

21

R7905

1%

X249:BOOST

201MF

1/20W

90.9K

2

1C790510%

X5R6.3V

0201

0.015UF

X249:BOOST

2

1 C792210%

0201

1000PF16V

X249:BOOST

X7R-1

2

1R7904

201MF1/20W1%

X249:BOOST

20K

2

1R7903X249:BOOST

1/20W

422K1%

MF201

2

1 C7910

35V

CRITICAL

20%

TANT-POLYCASE-D-1

X249:BOOST

33UF2

1 C791133UF

X249:BOOST

TANT-POLYCASE-D-1

CRITICAL

35V20%

2

1 C7912

X249:BOOST

20%35V

CRITICAL

CASE-D-1TANT-POLY

33UF2

1 C7913

35V20%

X249:BOOSTCRITICAL

33UF

TANT-POLYCASE-D-1

KA

D7900

X249:BOOSTCRITICAL

DFLS260

POWERDI-123

2

1 C7914

X249:BOOSTCRITICAL

33UF

CASE-D-1

35V20%

TANT-POLY

21

L7900CRITICAL

100UH-20%-0.4A-1.854OHM

X249:BOOST

PST041H-SM

21

3Q7972DMN32D2LFB4

DFN1006H4-3

CRITICAL

2

1R79725%

402

1/16WMF-LF

47K

32

1

4

5

Q7979PWRPK-1212-8SI7121DN

CRITICAL

2

1R79065%1/20WMF

100K

201

X249:BOOST

KA

D7970

PMEG6030EP

CRITICAL

SOD128

4

5

3

Q7902NTUD3169CZ

CRITICAL

SOT-963

X249:BOOST

K

A

D7922BAT54XV2T1

X249:BOOST

SOD-523

2

1R79765%

201

1/20WMF

100K

2

1R7908X249:BOOST

201

1/20WMF

1%34.8K

2

1R7909

201

1/20WMF

1%28.7K

X249:BOOST

1

2

6

Q7902SOT-963

NTUD3169CZ

CRITICALX249:BOOST

2

1R79260

402

1/16WMF-LF

5%

2

1R79225%0

MF-LF402

1/16W

32

1

4

5

Q7905

X249:BOOSTCRITICAL

SI7121DNPWRPK-1212-8

X249 Boost Power SupplySYNC_MASTER=CLEAN_X305 SYNC_DATE=05/30/2014

PVIN_S4_TPAD_SS

PPVIN_X249_BOOST_ISNS


PPVCC_X249_BOOSTMIN_LINE_WIDTH=0.6 MM

VOLTAGE=6VMIN_NECK_WIDTH=0.2 MM


PVIN_S4_TPAD_EN

X249_BOOST_RESET_L

S4_PWR_EN

X249_BOOST_COFET_EN_SOURCE


MIN_LINE_WIDTH=0.3 MMP3V3R3V42_X249_COFET_EN

X249_BOOST_COFET_EN_L

X249_BOOST_COFET_EN_IN

X249_BOOST_RC_EN

X249_BOOST_EN_L

PP3V3_S4

PPVIN_X249_BOOST_SW


PP3V3_S4

X249_BOOST_UVPTRIP_L

SMC_TPAD_BOOST_DISABLE_L

X249_BOOST_EN_DIV

X249_BOOST_COMP_RC

X249_BOOST_COFET_GATE_R

PVIN_S4_TPAD_EN_L

PP3V3_S4

PP3V42_G3H

X249_BOOST_COFET_EN_RC

X249_BOOST_SW

DIDT=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

X249_BOOST_COFET_EN


PP28V_TPAD_OUT

VOLTAGE=29V

X249_BOOST_COFET_GATE

X249_BOOST_DRDIDT=TRUE

X249_BOOST_VG

X249_BOOST_COMP

VOLTAGE=0V

GND_X249_BOOST_AGNDMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

X249_BOOST_ISEN

X249_BOOST_FB

PPBUS_S4_TPAD

EFUSE_DVDT

EFUSE_UVLO

TPAD_ACTUATOR_THRMTRIP_L

X249_BOOST_MODE

PPBUS_G3H


VOLTAGE=12.9V

PPVIN_S4_TPAD_D



PPVIN_S4_TPAD_EFUSE

EFUSE_ILIM

<BRANCH>

<SCH_NUM>

<E4LABEL>

79 OF 118

65 OF 82

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69

70 71 72

20 34 39 40 42 43

46 47

65 66 67

69 70

71 72

19 35 38 39 41 42 43 44 50 56 57 67 70 72

40 46 70 30 45 56 57 63 70 72

w w w

. c h

i n a

f i x

. c o

mIN

DS

G

IN

DS

G

DS

G

IN

IN

S

G

D

DS

GIN

S

G

D

GND

VOUT

ON

VIN

IN

SYM_VER_2

G S

D

SYM_VER_2

G S

D

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

IN

OUT

OUT

GND

VDD

D

SON

CAP

Apple Inc.


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D

A

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



1.35V S3/S0 FET

1.3 A (EDP)

2.8 A (EDP)

1.1 A (EDP)

26 mOhm @1.8V

P-TYPE 8V/5V

SiA427

LOADING

P-TYPE 8V/5V

CHANNEL

MOSFET

5 A (EDP)

SI7615DN

5.0V S0 FET

3.3V S0 SSD FET

LOADING

SiA427

CHANNEL

5.5 MOHM @4.5V

P-TYPE 20V/12VP-TYPE 8V/5V

SiA427

RDS(ON)

MOSFET

3.3V S3 FET

LOADING

RDS(ON)

CHANNEL

SI7615DN

RDS(ON)

26 mOhm @1.8V

P-TYPE 8V/5VCHANNEL

SiA427MOSFET

LOADING

26 mOhm @1.8V

RDS(ON)

3.3V SUS FET

3.3V SUS FET

CHANNEL

5.0V S0 FET

MOSFET

P-TYPE 20V/12V

3.3V S0 SSD FET

MOSFET

LOADING

RDS(ON)

0.5 A (EDP)

RDS(ON)

5V S3 FET

26 mOhm @1.8V

MOSFET

3.3V S3 FET

5V S3 FET

CHANNEL

0.3 A (EDP)

APN 353S2741

3.3V S0 Switch

TPS22924C

U8030

25.8 mOhm Max18.5 mOhm Typ

Load SwitchType

R(on)@ 2.5V

Part

Max Current = 2A

LOADING

3.3V S4 FET

5.5 mOhm @4.5V

376S0945

EDP is per X305 Power Budget rev?? 3.3V S4 FET

CHANNEL

RDS(ON)

LOADING

Integ. MOSFET

9.6 mOhm

N-TYPE

SLG5AP1438V

4.8 A (EDP)

1.35V S3/S0 FET

Slew rate :

0.8V/ms = 19.75nF

21

C80100.01UF

X7R-CERM16V10%

0402

2

1C80110.033UF

X5R402

16V10%

21

R801039K

402MF-LF1/16W5%

2

1R80125%

47K1/16WMF-LF

402

67

74

3

1

Q8010SIA413DJ

SC70-6L

CRITICAL

31 32 65 67

2

1R80025%

402

1/16W

MF-LF

220K

21

R8000

MF-LF

5%

47K

1/16W

402

2

1C80090.033UF

10%16VX5R402

74

3

1

Q8000SIA413DJ

CRITICAL

SC70-6L

21

C80000.01UF

10%16V

X7R-CERM0402

2

1C802110%

402

16V

X5R

0.033UF

74

3

1

Q8020SIA413DJ

CRITICAL

SC70-6L

21

C8020

0402

10%

0.01UF

16VX7R-CERM

2

1R80225%

402

MF-LF

100K1/16W

21

R8020

5%1/16WMF-LF402

12K

12 45 67

67

2

1R80625%

270K1/16WMF-LF

402

21

R80606.2K

5%1/16W

402MF-LF

2

1C80610.12UF

402

10%10.0V

CERM-X5R

21

C80600.47UF

0402

10V10%

X5R

32

1

4

5

Q8060CRITICAL

PWRPK-1212-8SI7615DN

74

3

1

Q8050CRITICAL

SIA427DJSC70-6L

2

1C805110%

0.033UF16VX5R402

21

R8050

1/16W5%

MF-LF

5.1K

402

2

1R80525%

200K1/16WMF-LF

402

21

C80500.01UF

10%16V

X7R-CERM0402

67

21

C80700.01UF

0402X7R-CERM

16V10%

32

1

4

5

Q8070CRITICAL


SI7615DNPWRPK-1212-8

2

1C807110%

X5R402

16V

0.033UF

21

R8070

5%

MF-LF

33K

402

1/16W

2

1R80725%

47K1/16WMF-LF

402

B1

A1

B2

A2

C2

C1

U8030TPS22924

CRITICAL

CSP

2

1C8030

6.3V

1UF

X5R402

10%

64 67

21

3Q8012DMN32D2LFB4

DFN1006H4-3

21

3Q8072DFN1006H4-3

DMN32D2LFB4

21

R8073SSD_PWR_EN:GPIO

5%

0

0201 1/20W MF

21

R8074

5%

0

1/20W MF

SSD_PWR_EN:S0

0201

12

6Q8002

SOT563

DMN5L06VK-7

45

3Q8002

DMN5L06VK-7SOT563

12

6Q8052

SOT563DMN5L06VK-7

45

3Q8052

DMN5L06VK-7SOT563

21

2

1C8002

402

16V

X7R

10%

0.018UF

2

1C8001

402

20%

10V

CERM

0.1UF

4 3

2 1

R8005

MF-1

SENSOR_NONPROD_R

1W1%

0612

0.002

47 82

47 82

1

52

8

37

U8001

CRITICAL

TDFN

SLG5AP1438V


Power FETsSYNC_DATE=02/18/2014

PP1V35_S3

CPUVDDQ_EN

PP5V_S5

P1V35CPU_SLEW_CTL

P5VS0_EN

P5V0S0_EN_L

PM_SLP_SUS_L

SSD_PWR_FET_EN

P5VS3_ENP5VS3_EN_L

S4_PWR_EN

P3V3SUS_EN_L

P3V3S4_EN_L

PP3V3_S5PP3V3_S0SW_SSD_RPP3V3_S5

PP3V3_S0

P3V3S0_P1V5_S0_EN

PP3V3_S5

PP5V_S4

PP3V3_S5

PP5V_S4

PP3V3_S3

PP5V_S0

P3V3_SSD_SSP3V3_SSD_EN_LP3V3S3_SS

P3V3S3_S4

P5V0S0_SS

PP5V_S3

PP3V3_S4

PP3V3_SUS

P3V3SUS_SS

P3V3S3_EN

PP3V3_S5

PM_SLP_S3_BUF_L

SSD_PWR_EN

P5VS3_SS

P3V3S3_EN_L

PP1V35_S3RS0_CPUDDR

ISNS_CPUDDR_N

ISNS_CPUDDR_P

PP1V35_S3RS0_FET

<BRANCH>

<SCH_NUM>

<E4LABEL>

80 OF 118

66 OF 82

21 46 60 70 72

61 70 72

35

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

46 70 12 14 15 17 18 19 21 31 32 34 61 64

66 67 70 71 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

67 68 70 72 82 12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72

82

38 39 51 61 66 67 68 69 70 72

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

38 39 51 61 66 67 68 69 70 72

13 20 21 44 46 47 69 70 72

18 19 37 49 58 59 62 63 67 70 71 72

21 37 60 67 70 72

20 34 39 40 42 43 46 47 65 67 69 70 71 72

11 12 13 14 15 17 50 64 67 70

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

51 67 69 72

13 18

6 8 10 21 67 70 82 70

w w w

. c h

i n a

f i x

. c o

m

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

NC

NC

Q3

Q2

Q4

Q1

OUT

IN

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

OUT

IN OUT

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND THRM_PAD

OUTIN

OUT

OUT

OUT

IN NC

NC

OUT

OUT

OUT

OUT

SYM_VER_2

G S

D

SYM_VER_2

G S

D

OUT

OUT

OUT

G

D

S

OUTIN

OUT

OUT

IN

VER 3

D

SG

VER 3

D

SG

IN

IN

Apple Inc.


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BRANCH

6 3



CHGR VFRQ GenerationVFRQ Low: Fix Frequency

P1V5S0_PGOOD from U7810

1V5 S0 "PGOOD" Delay

V3MON: 0.572V-0.630V

Thresholds:

0

0

1

Battery Off (G3Hot)

Deep Sleep (dS5)

Battery Off (G3HotAC) toggle 3Hz

10

0

0

1

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (dS5AC)

State

Deep Sleep (dS4AC)

Deep Sleep (dS4)

SMC_ADAPTER_EN

1

SMC_PM_G2_ENABLE

X

0 1

1

1

1

1

1

1

0

1

Mobile System Power State Table

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

1

1

1

1

SMC_S4_WAKESRC_EN

1 0

0

PM_SLP_SUS_L

1

1

1

1

PM_SLP_S5_L

1

0

0

0

0

0

PM_SLP_S4_L

0

0

PM_SLP_S3_L

0

0

1

0

0

0

0

0

1V05_VMON divider0.716V @1.02V

P5V_VMON divider

353S2310(IPU)

0.717V @1.31V

3.16V @4.5V

(For development only)

S0 ENABLE

3V3 Divider:1.07V

S5 Rail Enables & PGOOD

VBEon: 0.58~0.7V1V5 Divider:0.75~0.85V

S3 ENABLE

SMC-->PM_DSW_PWRGD

S5_PWRGD-->SMC

PM_RSMRST_L goes to U1100.C21

353S2809

(PM_SLP_S3_BUF_L)

5.0V Divider:1.07V

1V35_VMON divider

PM_SLP_S4_L:100K pull down in PCH page

U8130 Sense input

No stuff C8131, 12ms

S4 Power Enable

CPUVCORE ENABLE

3.3V SUS Detect

NOTE: S4 term is guaranteed by S4 pull-up on open-drain AP_PWR_EN signal."WLAN" = ("S4" && "AP_PWR_EN" && ("AC" || "S0"))

WLAN Enable Generation

PM_SLP_S3_L:100K pull down in PCH page

PM_SLP_S5_L:100K pull down on PCH page

Min delay time

threhold is 3.07V

VFRQ High: Variable Frequency

Power State Debug LEDs

Vgs:0.7V~1.0V Unused PGOOD signals

S0 Rail PGOOD (BJT Version)PM_SLP_SUS_L: 100K pull down on PCH page

3.3V SUS Enable

Vbe 0.7V max @2mA

Vce(sat) 0.1V max @1mA

Q1 Vth 0.7~1V @Id 250uA

S0 Rail PGOOD Circuitry (ISL Version in development)

keep R8171 DDRCPU 1.35V only

V4MON: 0.572V-0.630V

V2MON: 2.815V-3.099VVDD: 2.734V-3.010V

60 67

66 67

2

1R81120

MF-LF

PLACE_NEAR=Q8012.1:6mm

5%

402

1/16W

2

1 C8112NO STUFF

10%

CERM-X5R402

6.3V


0.47UF

18 19 41 58 67 72

31 32 45 67

62 67

2

1R81115%

402

1/16WMF-LF

5.1K


2

1 C81100.47UF

CERM-X5R402

10%6.3V


12 21 34 38 41 67 69 72

2

1R8185


5%1/16WMF-LF402

130K

2

1 C8185

402

6.3V10%0.82UF

X5R


2

1R8131

1/16W

402

5%100K

MF-LF

57

12 21 41 72

31 32 65 66 67

2

1R8167

402MF-LF1/16W

5%10K

18 19 41 58 67 72

2

1R8157

402MF-LF1/16W

5%100

21

R8169

1/16W

100

MF-LF 4025%

21

R8162330

402

5%

S0PGOOD_ISL

MF-LF1/16W

62

2

1R8156150K

1/16WMF-LF402

1%

21

R8153

5%

MF-LF1/16W

1K

402

2

1R8151

1%1/16WMF-LF402

54.9K

2

1R8152

MF-LF

15.0K

402

1%1/16W

3

2

8

46

1

7

5

Q8150

CRITICAL

DFN2015H4-8

ASMCC0179

21

R81541K

MF-LF1/16W5%

402

21

R8155

5%

402MF-LF1/16W

1K

31 32 65 66 67

12 41

6

5 1

3

2

4

U8130TPS3808G33DBVRG4

CRITICAL

SOT23-6

2

1 C8131

402CERM50V20%

NO STUFF

0.001UF

2

1R8133

5%

402

1/16WMF-LF

100K

2

1C8130BYPASS=U8130.6:2:2.3mm

0.1uF20%

CERM402

10V

21

R8168100

4021/16W5% MF-LF64

21

R8178

MF-LF

5%

402

100

1/16W

64 66 67

12 72 77

41 42 61 67

2

1 C81420.0033UF10%50VX7R-CERM


NO STUFF

0402

21

R8140

402MF-LF1/16W5%


10061 67

41 61

67

2

1R8141

MF-LF

5%

402

100K

1/16W


72

6

5

3

9

8

1

4

U8160

TDFN

ISL88042IRTEZ

S0PGOOD_ISL

CRITICAL

2

1R8172

1/16W

402

6.04K

MF-LF

1%

S0PGOOD_ISL

2

1R8173

1/16W

S0PGOOD_ISL

MF-LF

1%

402

15.0K

2

1R8170

S0PGOOD_ISL

10K1%

MF-LF402

1/16W

2

1R8171

S0PGOOD_ISL

12.4K1%

1/16W

402

MF-LF

2

1R8160

1%

S0PGOOD_ISL

1/16W

MF-LF

402

6.04K

2

1R8161

1/16W

MF-LF

1%

402

15.0K

S0PGOOD_ISL

12 45 66 67 12 45 66 67

31 32 65 66 67

2

1 C8113

402CERM-X5R

10%6.3V

0.47UF

PLACE_NEAR=Q8052.2:6MM

NO STUFF

2

1R8113

402

5%

PLACE_NEAR=Q8052.2:6MM

0

MF-LF1/16W

66 67

31 32 45 67

41 42

4

6

5 3

1

2

U8170

SOT89174LVC1G32

2

1C8170

BYPASS=U8170.6:3:2.3mm

0.1uF20%10VCERM402

2

1 C8114NO STUFF

0.47UF10%6.3VCERM-X5R402


2

1R8114

1/20WMF

3.3K

201PLACE_NEAR=J4801.17:10MM

5%

39

2

1C8160

S0PGOOD_ISL


0402

10V20%

X7R-CERM

0.1UF

K

AD8190DBGLED

SILK_PART=S5_ONPLACE_SIDE=BOTTOMLTQH9G-SMGREEN-56MCD-2MA-2.65V

K

AD8191

SILK_PART=S4_ON

DBGLED

PLACE_SIDE=BOTTOM

GREEN-56MCD-2MA-2.65VLTQH9G-SM

K

AD8193

SILK_PART=S0_ONPLACE_SIDE=BOTTOM

DBGLED


K

AD8192DBGLED

PLACE_SIDE=BOTTOMSILK_PART=S3_ON


2

1R819020K5%

201

1/20WMF

DBGLED

2

1R819120K1/20WMF201

5%

DBGLED

2

1R819220K5%1/20W

201

DBGLED

MF2

1R819320K

DBGLED

1/20W

201MF

5%

2 1

R8194DBGLED

0

402

PLACE_SIDE=BOTTOM

MF-LF1/16W5%

2

1R8158

1%15.0K

402

1/16WMF-LF

2

1R81597.15K

402

1%1/16WMF-LF

2

1R81865%20K1/16WMF-LF402

64 66 67

2

1 C8186

CERM

10%6.3V

402

0.68UF

2

1 C8187

CERM

10%6.3V

402


0.68UF

NO STUFF

2

1R81870

402

5%

MF-LF1/16W


66 67

2

1 C8174

X5R402

6.3V10%2.2UF


2

1R8174

402

1/16WMF-LF

43K5%


61 67

21

3Q8131DMN32D2LFB4

DFN1006H4-3

21

3Q8191DMN32D2LFB4

DFN1006H4-3

DBGLED

21

R8175

MF-LF

5%1/16W

240

402

21

R8138820

402MF-LF1/16W5%


5

4

1

2

3

U8180

SC70-HFMC74VHC1G08

12 45 66 67

41 42

61

67

2

1R8180100K

NO STUFF

402MF-LF1/16W5%

K

AD8185SOD-523

BAT54XV2T1


K

AD8174


SOD-523

BAT54XV2T1

2

1C818020%10V

CERM402

0.1uF

BYPASS=U8180.5:3:2.3mm

18 19 41 58 67 72

1

2

6

Q8151CRITICAL

DMB53D0UVSOT-563

2

1R8136

1/16W

402

23.7K1%

MF-LF

4

3

5Q8151CRITICAL

DMB53D0UVSOT-563

2

1C8134

X5R402

2.2UF10%

6.3V

2

1R8135

402

1/16WMF-LF

1%54.9K

2

1R813461.9K

MF-LF1/16W

1%

402

21

R8137

1/16W5%

402MF-LF

100

2

1R8139

MF-LF402

1/16W

2.0K1%

34 41 67

2

1R8125

MF1/20W

201

330K5%

34 41 67

51 66 67 69 72

2

1

C8161

10V

0.1UF20%

PLACE_NEAR=U8160.2:4mmS0PGOOD_ISL

0402X7R-CERM

21

R8195

PLACE_NEAR=U8160.2:4mm402

5%

10

1/16W

S0PGOOD_ISL

MF-LF

21

R8196S0PGOOD_ISL

1/16W

402

MF-LF 10


5%

2

1C8162


0402

NOSTUFF

20%

X7R-CERM10V

0.1UF

2

1C81630.1UF


20%

X7R-CERM0402

10V

NOSTUFF

2

1R8197

402

100K

1/16W5%

MF-LF

NOSTUFFPLACE_NEAR=U8160.1:4MM

31 32 65 66 67

60 67 21

R8120DDRREG_PGD:Y

100

402MF-LF5% 1/16W

45

3Q8190

SOT563

DMN5L06VK-7

DBGLED

12

6Q8190

DMN5L06VK-7SOT563

DBGLED

60 67

2

1R8165

1/16WMF-LF

5%

402

470K2

1R8166DDRREG_PGD:N

470K

201

5%1/20WMF

61

Power Control 1/ENABLESYNC_DATE=05/30/2014SYNC_MASTER=CLEAN_X305

VMON_3V3_DIV

PP3V3_S0_VMON_P2

VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

VMON_Q2_BASE

PP5V_S0

PP1V35_S3RS0_CPUDDR

PP1V35_S3RS0_CPUDDR

PM_SLP_S3_L

PM_WLAN_EN

DDRREG_PGOOD

PP5V_S4

P5VS4_PGOOD

PM_SLP_S4_L

DBGLED_S3_D

S4_PWR_EN

DBGLED_S4_D

DDRREG_PGOOD

PP1V5_S0

PP3V3_S0_VMON_P7


VOLTAGE=3.3V

ALL_SYS_PWRGD

PP3V3_S5

PP3V3_SUS

PP3V3_S5

PM_SLP_S3_BUF_L

P5VS0_EN

PM_SLP_SUS_L

PP3V3_S5

P5VS4_EN_D

P5VS4_EN

MAKE_BASE=TRUEP3V3S0_P1V5_S0_EN

MAKE_BASE=TRUEP1V05S0_EN

PM_SLP_S3_R_L

PP3V3_S5

P3V3S0_P1V5_S0_EN

P1V05S0_EN

SMC_S4_WAKESRC_EN

PM_SLP_SUS_L

P3V3S0_P1V5_S0_EN

P5VS3_EN

DDRREG_EN

PP3V3_S5

VMON_5V_DIV

DBGLED_S0

PP3V3_SUS

P1V05_EN_D

S4_PWR_EN

VMON_Q4_BASE

PM_SLP_S5_L

P3V3S3_EN

DBGLED_S3

PM_RSMRST_L

ALL_SYS_PWRGD

PP3V42_G3H

S5_PWRGD

CHGR_VFRQ

TP_SUS_PGOOD_MR_L

SMC_PM_G2_EN

P3V3S5_EN

VMON_Q3_BASE

PM_SLP_S3_BUF_L

TPAD_VBUS_EN_R

PM_SLP_S3_R_L

DELAY_1V5S0_PGD

PM_P1V5_PGD_DIV

PM_1V5_PGD_L_R

PM_1V5_PGD_L

DBGLED_S0_D

PM_SLP_S3_R_L

MAKE_BASE=TRUEPM_SLP_S3_R_L

MAKE_BASE=TRUEP3V3S5_ENSMC_PM_G2_EN

MAKE_BASE=TRUE

PM_SLP_SUS_LMAKE_BASE=TRUE

S5_PWRGDMAKE_BASE=TRUE

ALL_SYS_PWRGDMAKE_BASE=TRUE

P5VS0_ENMAKE_BASE=TRUE

S0PGD_C

ALL_SYS_PWRGD

PM_WLAN_ENMAKE_BASE=TRUE

PP3V3_S4

MAKE_BASE=TRUEDDRREG_EN

P5VS3_ENMAKE_BASE=TRUE

MAKE_BASE=TRUEP3V3S3_EN

MAKE_BASE=TRUE

P5VS4_EN

P1V5S0_PGOOD

PP3V3_S5_DBGLEDMIN_LINE_WIDTH=0.5 MM


P1V05_VID_VMON

PP3V3_S0

PP1V05_S0

ALL_SYS_PWRGD_R

VMON_MRP5V_DIV_VMON

PP5V_S0

DBGLED_S4DBGLED_S5 S4_PWR_EN

PP3V3_S0

PP3V3_S0

SUS_PGOOD_CT

P1V05S0_PGOOD

PP5V_S3

PP3V42_G3H

ALL_SYS_PWRGD

S0PGD_BJT_GND_R

PP3V3_S5

P1V5_DIV_VMON

PM_SLP_S3_BUF_L

VMON_MR

PP3V3_S0_VMON_P7

MAKE_BASE=TRUES4_PWR_EN

S4_PWR_ENS4_PWR_EN

PM_SLP_S4_L

<BRANCH>

<SCH_NUM>

<E4LABEL>

81 OF 118

67 OF 82

18 19 37 49 58 59 62 63 66 67 70 71 72

6 8 10 21 66 67 70

82

6 8 10 21 66 67 70 82

38 39 51 61 66 68 69 70 72

12 21 34 38 41 67 69 72

31 32 65 66 67

11 12

13

15

17

19

52

64

69

70 72

67

12 14 15 17 18 19 21 31 32 34 61 64 66

67 70 71 72 82

11 12 13 14 15 17 50 64 66 67 70

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

64 66 67

62 67

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

11 12 13 14 15 17 50 64 66 67 70

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

41 61 67

51 66 67 69 72

31 32 45 67

61 67

18 19 41 58 67 72

66 67

18 19 41 58 67 72

20 34 39 40 42 43 46 47 65 66 69 70 71 72

60 67

66 67

66 67

61 67

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

10 14 15 17 18 42 62 70 72

67

18 19 37 49

58 59 62 63 66 67 70 71 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12

13

14

15

17

19

20

29

33

35

44

45

46

47

48

49

51

52

55

66

67

68 70 72 82

21 37 60 66 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70

72

12 14 15 17 18 19 21 31 32 34 61 64 66

67 70 71 72

82

51 66 67 69 72

w w w

. c h

i n a

f i x

. c o

mIN

IN

IN

IN

IN

IN

IN

IN

BI

BI

NC

OUT

OUT

OUT

OUT

VIN

ONGND

VOUT

IN

BI

IN

BI

IN

D SG

D SG

IN

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

GND

VDD

D

SON

CAP

Apple Inc.


124578

B

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8 7 6 5 4 3

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A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



GND_VOID

GND_VOID

GND_VOID

LCD PANEL INTERFACE (eDP)

GND_VOID

GND_VOID

GND_VOID

GND_VOID

U8310

19 mOhm Max

2.5 A Max

Part

Type

R(on) 66 mOhm Typ

90 mOhm Max

Load Switch

0.5A Max

TPS22904

LCD Panel HPD & AUX strapping

U8300

GND_VOID

Part

Type

17 mOhm Typ

518S0829

Current

@ 3.6V

TCON 3V3 <30mA

3.3V TCON Switch

Current

@100mA

R(on)

Load Switch

SLG5AP1443V

2

1C8301

0402X7R-CERM

16V10%

0.1UF

21

L8300

0805

FERR-220-OHM

CRITICAL

2

1C8302

X7R-CERM50V10%

0402

0.001UF

2

1 C8311

X7R-CERM16V10%

0402

0.1UF

2

1 C8312

6.3V

603

20%

X5R

10UF

21C8321TRUE

TRUE

16VX5R-CERM 020110%0.1UF

21C83200201

16V

TRUE

0.1UFTRUE

X5R-CERM10%

5 71 75

5 71 75

21C8323TRUE

TRUE

16V10%0201X5R-CERM0.1UF

21C8322TRUE

TRUE

10%0.1UF 16V0201X5R-CERM

5 71 75

5 71 75

21C8325TRUE

16V10%X5R-CERM0.1UF

TRUE

0201

21C832410%

0201TRUE

TRUE

16V0.1UF X5R-CERM

5 71 75

5 71 75

21C832716V

TRUE

TRUE

X5R-CERM 02010.1UF 10%

21C8326TRUE

TRUE

10% 16VX5R-CERM0.1UF 0201

5 71 75

5 71 75

21C83290201

16V0.1UF 10%X5R-CERM

21C832816V10%

0201X5R-CERM0.1UF5 71 75

5 71 75

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J8300

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

F-RT-SM20525-130E-01

CRITICAL

2

1C83001000PF

100VX7R

0603

10%

68 72

21R83005% 1/20WMF0201020

2

1R8302

1/20W5%

201MF

1M

NOSTUFF

2

1R8303

1/20W5%

201MF

1M

NOSTUFF

2

1R8301

1/20W5%

201MF

1M

21

R8313TRUE

1/20W5%

201MF

1M

21

R8314TRUE

1/20W5%

201MF

1M

21

R8315TRUE

1/20W5%

201MF

1M

21

R8316TRUE

1/20W5%

201MF

1M

21

R8312TRUE

5%1/20W

201MF

1M

21

R8317TRUE

1/20W5%

201MF

1M

21

R8318TRUE

1/20W5%

201MF

1M

21

R83111M

TRUE

1/20W5%

201MF

47 82

47 82

2

1 C8350

0201NP0-C0G

12PF5%

25V2

1 C8351

25V0201

5%12PFNP0-C0G 2

1 C83525%12PF

25V0201NP0-C0G 2

1 C8353

0201

12PF5%

25V

NP0-C0G 2

1 C8354

0201

12PF5%

25V

NP0-C0G 2

1 C8355

0201NP0-C0G

25V

5%12PF

43

21

R8320

SENSOR_NONPROD_RCRITICAL0.025

MTL1W1%

0612

2

1 C83081.0UF20%

0201-1X5R

6.3V

2

1 C83040.1UF

CERM-X5R0201BYPASS=J8300.5::5MM

NOSTUFF

6.3V10%

21

R831926.1K

1%1/20W

201MF

2

1 C83191.0UF

X5R-CERM0201

6.3V10%

21

R8305

1%

11K

201MF

1/20W

A2A1

B1

B2

U8310CSP

TPS22904

CRITICAL

2

1 C8305

0201X5R-CERM

1.0UF6.3V10%

2

1R8380

MF201

2.0K5%

1/20W

2

1R83812.0K

5%1/20W

MF201

37 41 44 48 71 72 81

37 41 44 48 71 72 81

2

1 C8309

10VX5R-CERM0201

10%0.1UF

2

1 C83134700PF10%10V

201X7R

63 71 72

63 71 72

63 72

45

3

Q8302SSM6N37FEAPE

SOT563

12

6

Q8302SSM6N37FEAPE

SOT563

12 68 71 72

2

1R8350NOSTUFF

100K

MF201

5%1/20W

2

1R8351

1/20WMF

100K

201

5%

4

32

1

FL8300

3.25-OHM-0.1A-2.4GHZTAM0605-4SM

TRUETRUETRUE

CRITICAL

TRUE

4

32

1

FL8301TRUETRUE

3.25-OHM-0.1A-2.4GHZ

TRUE

CRITICAL

TAM0605-4SM

TRUE

4

32

1

FL8302TRUE

3.25-OHM-0.1A-2.4GHZ

CRITICAL

TRUETRUETRUE

TAM0605-4SM

4

32

1

FL8303

3.25-OHM-0.1A-2.4GHZ

CRITICAL

TRUETRUETRUE

TAM0605-4SM

TRUE

2

1R83108.06K1/20W

201MFPLACE_NEAR=D8310.K:2mm

1%

K A

D8310SM-201

RB521ZS-30PLACE_NEAR=U8310.B1:6mm

KA

D8308

RB521ZS-30PLACE_NEAR=U8300.2:6mm

SM-2012

1R8308


6.04K1%1/20W

201MF

1

52

8

37

U8300SLG5AP1443V

TDFN

CRITICAL

2

1 C8356

25V

5%12PFNP0-C0G0201 2

1 C83575%

25V

12PF

0201NP0-C0G 2

1 C83585%12PFNP0-C0G

25V0201

2

1 C830312PFNP0-C0G020125V

5%


2

1 C8306

100V

0402CERM

12PF2%

eDP Display Connector


DP_INT_ML_P<0>

DP_INT_AUX_N

LCD_IRQ_LLCD_HPD_CONN

LCD_BKLT_PWM_RI2C_TCON_SDA_RI2C_TCON_SCL_RPP3V3_S0_EDP_SW

I2C_BKLT_SCLI2C_BKLT_SDA

I2C_TCON_SDA_R

PP3V3_S0_EDP_SW

I2C_TCON_SCL_R

PP3V3_S0_EDP_SWVOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

LCD_PWR_3V3_RC

PP3V3_S0

LCD_PWR_5V_RCEDP_IG_PANEL_PWR

PPVOUT_S0_LCDBKLT

PP5VR3V3_SW_LCDMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V

DP_INT_ML_N<3>

DP_INT_ML_F_N<0>

DP_INT_ML_F_P<0>

LCD_HPD

DP_INT_ML_P<3>

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=5V

PP5VR3V3_SW_LCD_UFPP5VR3V3_SW_LCD_ISNSVOLTAGE=5VMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mm

DP_INT_ML_C_N<3>

DP_INT_ML_C_N<1> DP_INT_ML_N<1>

DP_INT_ML_C_P<2>

LCD_PWR_5V_D

DP_INT_ML_C_P<0>

DP_INT_ML_F_P<3>

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

DP_INT_ML_C_N<0>

DP_INT_ML_P<2>

DP_INT_ML_N<2>

DP_INT_ML_P<3>

ISNS_LCD_PANEL_P

EDP_IG_PANEL_PWR

LCD_PWR_3V3_D

PP3V3_S0_EDP_SW

DP_INT_AUX_N

DP_INT_AUX_P LCD_HPD_CONN

DP_INT_ML_F_N<3>

DP_INT_ML_N<3>

ISNS_LCD_PANEL_N

PP3V3_S0_EDP_SW

LCD_IRQ_L

PP3V3_S0_EDP_SW

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL DP_INT_ML_F_P<2>

DP_INT_ML_F_N<1>

DP_INT_ML_P<2>

DP_INT_AUXCH_C_P

PP5V_S4

DP_INT_AUXCH_C_N

DP_INT_ML_P<1>

DP_INT_ML_N<0>

DP_INT_ML_F_P<1>

DP_INT_AUX_P

DP_INT_ML_N<2>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<2> DP_INT_ML_F_N<2>

DP_INT_ML_C_P<1>

VOLTAGE=5V

PP5V_FETCAP_LCDMIN_NECK_WIDTH=0.1 mmMIN_LINE_WIDTH=0.25 mm

DP_INT_ML_P<0>

<BRANCH>

<SCH_NUM>

<E4LABEL>

83 OF 118

68 OF 82

68 72 75

68 72 75

68 72

68

68

68

68

68

68

68

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52

55 66 67 70 72 82

63 72

72

68 72 75

75

75

68 72 75

68 72 75

75

68 72 75

68 72 75

68 72 75

68 72 75

68 72 75

68 72 75

12 68 71 72

68

68 72 75

68 72 75 68 72

75

68 72 75

68

68 72

68

75

75

68 72 75

38 39 51 61 66 67 69 70 72

68 72 75

68 72 75

75

68 72 75

68 72 75 75

68 72 75

w w w

. c h

i n a

f i x

. c o

mIN

IN

BI

BIIN

IN

OUT

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN

IN

IN

TP

TP

TP

TP

TP

TP

IN

BI

OUT

IN

OUT

OUT

IN

IN

IN

BI

Apple Inc.


124578

B

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D

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



518S0829

Wire-to-Board (Micro-coax) Connector

516S00052

Board-to-Board (Flex) Connector

71 72 75

71 72 75

13 72 76

13 72 76 13 76

13 76

13 72 76

13 72 76

9

8

7

6

5

41

40

4

39

38

37

36

35

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9500

CRITICAL

20525-130E-01

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

F-RT-SM

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

71 72 75

71 72 75

71 72 75

71 72 75

13 20 72 77

13 20 72 77

13 20 72 77

13 20 72 77

5 71 72 75

5 71 72 75

1BP9501


BEAD-PROBE

SM

1BP9502BEAD-PROBE

SM


1BP9505 SM


BEAD-PROBE

1BP9506 SM


BEAD-PROBE

1BP9503BEAD-PROBE

SM


1BP9504 SM

BEAD-PROBE


21C95010.1UF

GND_VOID=TRUE

10% X5R-CERM16V 0201

21C95020.1UF

GND_VOID=TRUE

020116V X5R-CERM10%

2

1C95100.1uF

402

10V20%

CERM

2

1 C9511

CERM

0.1uF

402

20%10V9

8 7

6 5

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J9510DF40HC-3.0-40DS-0.4V-51

F-ST-SM

CRITICAL

12 71 72

12 71 72

18 72

13 18 72

20 72

12 20 71 72

12 21 34 38 41 67 72

51 66 67 72

13 18 44 71 72 77

13 18 44 71 72 77

RIO Connectors

SYNC_DATE=01/14/2014SYNC_MASTER=CLEAN_X305G

RIO_SDCONN_STATE_CHANGE_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

HDMI_DDC_CLK

PM_SLP_S4_L

PM_SLP_S3_BUF_L

PP1V5_S0

HDMI_HPD

USB3_EXTB_D2R_P

USB3_EXTB_D2R_N

HDMI_DATA_N<2>

HDMI_DDC_DATA

PP5V_S4

USB_EXTB_OC_L

SD_PWR_EN

PP5V_S4

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S4

USB3_SD_D2R_P

USB3_SD_D2R_N

USB_EXTB_P

USB_EXTB_N

USB3_SD_R2D_C_N

USB3_EXTB_R2D_C_P

USB3_EXTB_R2D_C_N

USB3_SD_R2D_C_P

HDMI_CLK_N

USB3_EXTB_R2D_N

USB3_EXTB_R2D_P

HDMI_CLK_P

HDMI_DATA_P<1>

HDMI_DATA_P<2>

HDMI_DATA_N<1>

HDMI_DATA_N<0>

HDMI_DATA_P<0>

<BRANCH>

<SCH_NUM>

<E4LABEL>

95 OF 118

69 OF 82

11 12 13 15 17 19 52 64 67 70 72

38 39 51 61 66 67 68 69 70 72 38 39 51 61 66 67 68 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

20 34 39 40 42 43 46 47 65 66 67 70 71 72

72 76

72 76

w w w

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Apple Inc.


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BRANCH

6 3



1.5V/1.35V/1.05V/VCORE/BKLT Rails3.3V RailsG3H/5V Rails TBT RAILS


Power Aliases

MAKE_BASE=TRUEVOLTAGE=1.05V

PP1V05_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

PP1V05_S0

PP1V05_S0PP1V05_S0PP1V05_S0PP1V05_S0

VOLTAGE=1.05VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

PP1V05_SUSMIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

PP3V3_S4


PP3V42_G3H

MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MMMAKE_BASE=TRUE

PP3V3_S3

PPBUS_G3H

PP3V3_S5

PP3V3_S4

PP3V3_S4

PP3V3_S4PP3V3_S4

MAKE_BASE=TRUE

PP3V3_S4MIN_NECK_WIDTH=0.1 MM

VOLTAGE=3.3VMIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MMPP3V3_S5

PP3V3_S5

PP3V3_S3

PP3V3_S3

PP3V3_S3

PP3V3_S3PP3V3_S3

PP3V3_S3PP3V3_S3PP3V3_S3

PP3V3_SUSPP3V3_SUS

PP3V3_SUS

PP3V3_SUSPP3V3_SUSPP3V3_SUSPP3V3_SUSPP3V3_SUSPP3V3_SUSPP3V3_SUS

PP3V3_S4

PP3V3_S4

PP3V3_S4PP3V3_S4

PP3V3_S4

VOLTAGE=3.3VPP3V3_SUS

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

PP3V3_S5

PP3V3_S5

PP3V3_S5PP3V3_S5

PP3V3_S5

PP3V3_S5PP3V3_S5

PP3V3_S5PP3V3_S5

PP3V3_S5

PPBUS_S4_TPADVOLTAGE=28VMAKE_BASE=TRUE


PPBUS_S4_TPAD

PPBUS_S4_TPAD

PP3V3_S0PP3V3_S0

PP1V05_S0

PP1V05_S0PP1V05_S0

PP1V05_SUS

PP1V35_S3RS0_CPUDDR

PP3V3_S5

PP1V35_S3RS0_CPUDDR

PPBUS_S4_TPAD

PP1V05_S0

PP1V05_S0

PP1V05_S0

MIN_NECK_WIDTH=0.15 MMMIN_LINE_WIDTH=0.4 MMPP3V3_TBTLC

VOLTAGE=3.3VMAKE_BASE=TRUE

PP3V3_TBTLC

PP1V5_S0

PPVTTDDR_S3

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP5V_S5

PPDCIN_G3H




PP5V_S4

PP3V42_G3H

PPDCIN_G3H_ISOLPPDCIN_G3H_ISOL

PPDCIN_G3H


VOLTAGE=12.8VMIN_LINE_WIDTH=0.6 MMPPVIN_S5_HS_COMPUTING_ISNSMIN_NECK_WIDTH=0.25 MM MAKE_BASE=TRUE

PPVIN_S5_HS_COMPUTING_ISNS MAKE_BASE=TRUEVOLTAGE=1.35V

PP1V35_S3RS0_CPUDDRMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

PP1V35_S3_MEM

PP1V5_S0

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 MMVOLTAGE=1.8VMIN_LINE_WIDTH=0.6 MM

PPVCC_S0_CPU

PP1V05_S0

PPBUS_G3H

PP3V3_TBTLC

PPVIN_S5_HS_COMPUTING_ISNSPPVIN_S5_HS_COMPUTING_ISNS

PPVCC_S0_CPU

MIN_LINE_WIDTH=2 MMMAKE_BASE=TRUEVOLTAGE=12.6V


PPBUS_SW_BKL

VOLTAGE=15VPP15V_TBTMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP5V_S0

PPVCC_S0_CPU

PP3V3_S0SW_SSD_R

MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.1 MM

PP3V3_S4_TBT

PP3V3_S0SW_SSD

PP3V3_S3RS0_CAMERA

PP3V3_S3RS0_CAMERAMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_S3RS0_CAMERA

PP15V_TBTPP15V_TBT

PP1V5_S0

MIN_LINE_WIDTH=0.3 MMMAKE_BASE=TRUE

PPVTTDDR_S3MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0.675V

PP1V5_S0PP1V5_S0

PP3V3_S5

PP3V3_S0


PP3V3_S0PP3V3_S0

PP1V5_S0

PP1V05_S0

PP1V05_S0PP1V05_S0

VOLTAGE=12.8VPPVIN_SW_TBTBST

PP1V5_S0


MIN_LINE_WIDTH=0.5 MMPP3V3_S0SW_SSDMIN_NECK_WIDTH=0.2 MM


PP3V3_S0SW_SSD_RMAKE_BASE=TRUEVOLTAGE=3.3V

PP3V3_S0

PP3V3_S4_TBT

PPBUS_SW_BKL

PP15V_TBT

PPBUS_G3HPPBUS_G3H

PP1V5_S0

PPBUS_G3H

PP3V3_S5

PPVCC_S0_CPU

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MMPPVIN_S5_HS_OTHER3V3_ISNS


VOLTAGE=12.8VMIN_LINE_WIDTH=0.6 MMMAKE_BASE=TRUE

PPVIN_S5_HS_OTHER5V_ISNSMIN_NECK_WIDTH=0.25 MM

PP3V3_S0

PP3V3_S0

PP3V42_G3H

PP3V42_G3HPP3V42_G3H

PP1V05_S0PP1V05_S0

PP1V05_S0

PPBUS_G3H

PPBUS_G3H

VOLTAGE=20VMAKE_BASE=TRUE

PPDCIN_G3H_ISOLMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MM

PP5V_S4

PP5V_S0

PP5V_S0PP5V_S0PP5V_S0PP5V_S0

PP5V_S0PP5V_S0

PP5V_S0PP5V_S0

PP5V_S0

VOLTAGE=5VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MMPP5V_S0

PP5V_S4

PP5V_S4

PPVRTC_G3H

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S0

PP3V3_S5



PPBUS_G3HMIN_LINE_WIDTH=0.6 MM

PP3V42_G3H

PP3V3_S0

PP3V3_S0

PP3V3_S0MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.075 MM

PP3V3_S0PP3V3_S0PP3V3_S0PP3V3_S0

PP3V3_S0

PP3V3_S0PP3V3_S0


PP3V42_G3H

PP3V42_G3H

VOLTAGE=20VMAKE_BASE=TRUE

PPDCIN_G3HMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MM

PPVIN_S4_TPAD

PPVIN_S4_TPADMAKE_BASE=TRUEMIN_NECK_WIDTH=0.25 MMVOLTAGE=28V

PPVIN_S4_TPADMIN_LINE_WIDTH=0.6 MM


PP3V42_G3HMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM

PPDCIN_G3H_ISOL


PP5V_S4PP5V_S4

PP5V_S4

PP5V_S3PP5V_S3

PP5V_S3

PP5V_S0

PP5V_S4

MAKE_BASE=TRUEVOLTAGE=5V

MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.5 MMPP5V_S5PPVRTC_G3H


PP5V_S4MIN_LINE_WIDTH=0.5 MM


PP5V_S5

MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42VMIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PPVRTC_G3H


PPBUS_G3H

PP3V3_S5PP1V35_S3_MEMPP1V35_S3_MEM

PP1V35_S3

PP5V_S3MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MMPP5V_S3


PP1V35_S3

PP1V35_S3_MEM

PP1V35_S3PP1V35_S3




PP1V35_S3RS0_FET

PP3V3_S5

PP3V3_S5

PP1V35_S3RS0_CPUDDR

PPVTT_S0_DDRMAKE_BASE=TRUEVOLTAGE=0.675V

MIN_NECK_WIDTH=0.17 mmMIN_LINE_WIDTH=0.4 mmPPVTT_S0_DDR

PPVTT_S0_DDRPPVTT_S0_DDRPPVTT_S0_DDR


PP1V5_S0MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

PP1V5_S0

PP1V5_S0

PP1V35_S3RS0_FET

MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.35VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.17 MM

PP1V35_S3_MEM


PP1V35_S3MIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.17 MMPP1V35_S3

PP3V42_G3H



GNDMIN_LINE_WIDTH=0.6 MM

<BRANCH>

<SCH_NUM>

<E4LABEL>

100 OF 118

70 OF 82

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

18 64 70

18 64 70

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

45 61 70

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

13 20 21 44 46 47 66 69 70 72

30 45 56 57 63 65 70 72

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70

71 72 82

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

12 14 15 17 18 19 21 31 32 34 61 64 66 67

70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72

82

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

13 20 21 44 46 47 66 69 70 72

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66

67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67 70

11 12 13 14 15 17 50 64 66 67

70

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

11 12 13 14 15 17 50 64 66 67 70

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34

61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

46 65 70

46 65 70

46 65 70

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 66 67 68 70 72 82

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

6 8 10 21 66 67 70 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

6 8 10 21 66 67 70 82

46 65 70

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

19 20 28 29 70

19 20 28 29 70

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 14 15 17 19 20 29 33 35 44

45 46 47 48 49 51 52 55 66

67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

61 66 70 72

56 57 70 72

45 58 59 60

62 70

45 61 70

45 61 70

38 39 51 61 66 67 68 69 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

45 56 57 70

45 56 57 70

56 57 70 72

45 61 70

45 58 59 60 62 70

45 58 59 60 62 70

6 8 10 21 66 67 70 82

22 23 24 25 26 46 70 78

11 12 13 15 17 19 52 64 67 69 70 72

6 8 10 46 59 70 72

10 14 15 17 18 42 62 67 70 72

30 45 56 57 63 65 70 72

19 20 28 29 70

45 58 59 60 62 70

45 58 59 60 62 70

6 8 10 46 59 70 72

63 70

30 31 32 70

18 19 37 49 58 59 62 63 66 67 70 71 72

6 8 10 46 59 70 72

46 66 70

28 29 30 46 70

35 46 70 72

13 36 47 70

13 36 47 70

13 36 47 70

30 31 32 70

30 31 32 70

11 12 13 15 17 19 52 64 67 69 70 72

60 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

12 14 15 17 18 19 21 31 32 34

61 64 66 67 70 71 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 15 17 19 52 64 67 69 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

30

11 12 13 15 17 19 52 64 67 69 70 72

35 46 70 72

46 66 70

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 66 67 68 70 72 82

28 29 30 46 70

30 31 32 70

30 45 56 57 63 65 70 72

30 45 56 57 63 65 70 72

11 12 13 15 17 19 52 64 67 69 70 72

30 45 56 57 63 65 70 72

12 14 15 17 18 19 21 31

32 34 61 64 66 67 70 71 72

82

6 8 10 46 59 70 72

45 61 70

45 61 70

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

10 14 15 17 18 42 62 67 70 72

30 45 56 57 63 65 70 72

30 45 56 57 63 65 70 72

45 56 57 70

38 39 51 61 66 67 68 69 70 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

18 19 37 49 58 59 62 63 66 67 70 71 72

38 39 51 61 66 67 68 69 70 72

38 39 51 61 66 67 68 69 70 72

11 12 15 19

70

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33

35

44

45

46

47

48

49

51

52

55

66

67

68

70

72

82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33 35 44 45 46

47 48 49 51 52 55 66 67 68 70 72 82

11 12 13 14 15 17 19 20 29 33

35 44 45 46 47 48 49 51

52

55 66 67 68 70 72 82

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

19 35 38 39

41 42

43 44

50 56

57 65

67 70

72

39 46 70 72

39 46 70 72

39 46 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

45 56 57 70

19 35 38 39 41 42 43 44 50 56 57 65 67 70

72

38 39 51 61 66 67 68 69 70 72

38 39 51 61 66 67 68 69 70 72

38 39 51 61 66 67 68 69 70 72

21 37 60 66 67 70 72

21 37 60 66 67 70 72

21 37 60 66

67 70

72

18 19 37 49

58 59

62 63

66 67

70 71

72

38 39 51 61

66 67

68 69

70 72

61 66 70 72

11 12 15 19 70

38 39 51 61 66 67 68 69 70 72

61 66 70 72

11 12 15 19 70

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

30 45 56 57

63 65

70 72

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

22 23 24 25 26 46 70 78

22 23 24 25 26 46 70 78

21 46 60 66 70 72

21 37 60 66 67 70 72

21 37 60 66 67 70 72

21 46 60 66 70 72

21 46 60 66 70 72

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

66 70

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72 82

6 8 10 21 66 67 70 82

21 27 60 70 72

21 27 60 70 72

21 27 60 70 72

21 27 60 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

11 12 13 15 17 19 52 64 67 69 70 72

22 23 24 25 26 46 70 78

21 46 60 66 70 72

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

w w w

. c h

i n a

f i x

. c o

mOUT

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

OUT

OUT

Apple Inc.


124578

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SHEET


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REVISION

BRANCH

6 3



Unused PCH PCIE LanesNO_TESTMAKE_BASE

Thunderbolt Signals Through PEG

J9510 RIO FLEX CONN

VOLTAGE MAKE_BASE

CPU signals

Display Aliases

MAKE_BASE

Unused TPAD SPI

EDP CABLE

Unused signals

Unused PEG Lanes

SSD Signals Through PEG

21

XWA202SM

21

XWA203SM

5 28 75

5 28 75

5 28 75

5 28 75

21

RA201

1/20W

0

MF

5%

0201

21

RA202NOSTUFF

0

5%1/20WMF0201

2 1

RA298100K

1/20W

201

1%

MF

2 1

RA296

1%1/20W

100K

MF201

2 1

RA299

1%

201

100K

1/20WMF

2 1

RA297

201

100K

1/20WMF

1%

2 1

RA294100K

MF

1%1/20W

2012 1

RA295100K

1/20W1%

MF201

5 35 75

5 35 75

5 35 75

5 35 75

I1490

Signal AliasesSYNC_DATE=10/31/2012SYNC_MASTER=J15_MLB

DPMUX_UC_IRQPEG_CLKREQ_L

SDCONN_OC_LLPCPLUS_GPIO

SMBUS_PCH_CLK

=PEG_R2D_C_P<15..12>MAKE_BASE=TRUETP_PEG_D2RN<15..12>

MAKE_BASE=TRUEPCIE_TBT_R2D_C_N<3..0>

=PEG_D2R_P<7..4>

=PEG_R2D_C_P<7..4>

=PEG_D2R_P<11..8>

=PEG_R2D_C_N<15..12>MAKE_BASE=TRUETP_PEG_R2D_CN<15..12>

PP3V3_S5



PP3V3_S3_FAN_CTL

PP3V3_S4

PP3V3_S3_FAN_CTL

HDMITBTMUX_SEL_TBTENET_LOW_PWR_PCHENET_CLKREQ_L

AUD_I2C_INT_LAUD_IP_PERIPHERAL_DETAUD_IPHS_SWITCH_EN_PCHENET_MEDIA_SENSE_RDIVDP_TBT_SELFW_PME_LWOL_ENFW_PWR_EN_PCHMEM_VDD_SEL_1V5_LBT_PWRRST_L

TBT_GO2SX_BIDIR

TP_DP_IG_C_MLN<3..0>

DP_TBTSNK1_DDC_CLK

TP_DP_IG_A_MLN<3..0>

DP_TBTSNK0_DDC_CLKDP_TBTSNK0_DDC_CLKMAKE_BASE=TRUE


PCIE_SSD_D2R_P<3..0>MAKE_BASE=TRUE

PCIE_SSD_R2D_C_N<3..0>MAKE_BASE=TRUE

TP_DP_IG_B_MLP<3..0>

DP_INT_AUXCH_C_N

PCIE_TBT_D2R_N<3..0>MAKE_BASE=TRUE

PCIE_SSD_D2R_N<3..0>MAKE_BASE=TRUEPCIE_SSD_R2D_C_P<3..0>MAKE_BASE=TRUE

=PEG_R2D_C_P<3..0>

=PEG_D2R_N<3..0>

=PEG_D2R_P<3..0>



I2C_BKLT_SCLMAKE_BASE=TRUE

I2C_BKLT_SDAMAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

I2C_BKLT_SDA

I2C_BKLT_SCL

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

TPAD_SPI_INT_LTRUE

TRUETPAD_SPI_CS_L

TPAD_SPI_MOSITRUE

TRUETPAD_SPI_SCLK

TPAD_SPI_MISOTRUE

TPAD_SPI_BUS_ENTRUE

TPAD_SPI_BUS_EN

TPAD_SPI_SCLK

TPAD_SPI_CS_L

TPAD_SPI_MISOTPAD_SPI_INT_L

TPAD_SPI_MOSI

DP_TBTSNK0_ML_C_P<3..0>MAKE_BASE=TRUE

HDMI_CLK_N

DP_TBTSNK1_DDC_DATAMAKE_BASE=TRUE

EDP_IG_PANEL_PWR

EDP_IG_BKL_ON

DP_TBTSNK0_HPD

TP_DP_IG_C_MLP<3..0>MAKE_BASE=TRUEDP_TBTSNK1_HPD

DP_INT_AUXCH_C_NMAKE_BASE=TRUE

PP5V_S0_AUDIO_AMP_R

VOLTAGE=5V


MIN_NECK_WIDTH=0.2MMVOLTAGE=5V

MIN_LINE_WIDTH=0.4MMPP5V_S0_AUDIO_AMP_L

PP5V_S0

HDMI_DDC_CLK


EDP_IG_BKL_PWM


DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_HPD

DP_TBTSNK1_DDC_DATA

TP_DP_IG_B_MLN<3..0>


HDMI_DATA_N<0..2>MAKE_BASE=TRUE

MAKE_BASE=TRUEHDMI_CLK_N

DP_TBTSNK1_AUXCH_C_NMAKE_BASE=TRUE

DP_TBTSNK1_DDC_CLKMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_INT_AUXCH_C_P

MAKE_BASE=TRUEDP_TBTSNK0_ML_C_N<3..0>

MAKE_BASE=TRUEDP_TBTSNK0_DDC_DATA

DP_TBTSNK0_AUXCH_C_NMAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_PMAKE_BASE=TRUE

DP_TBTSNK1_ML_C_N<3..0>MAKE_BASE=TRUE

MAKE_BASE=TRUEDP_TBTSNK1_ML_C_P<3..0>

MAKE_BASE=TRUEDP_TBTSNK1_AUXCH_C_P

DP_INT_ML_C_P<3..0>MAKE_BASE=TRUE

EDP_IG_PANEL_PWRMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_INT_ML_C_N<3..0>

MAKE_BASE=TRUEEDP_IG_BKL_PWM

MAKE_BASE=TRUEDP_TBTSNK0_HPD

EDP_IG_BKL_ONMAKE_BASE=TRUE

0.675V TRUE PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFDQ_A0.675V TRUEPP0V75_S3_MEM_VREFDQ_A

MAKE_BASE=TRUEHDMI_DDC_CLK

HDMI_DDC_DATAMAKE_BASE=TRUE

HDMI_DDC_DATA

MAKE_BASE=TRUEHDMI_DATA_P<0..2>

TP_DP_IG_D_MLN<2..0>

HDMI_CLK_P

TP_DP_IG_D_MLP<2..0>

HDMI_HPDHDMI_HPDMAKE_BASE=TRUE

0.675V TRUE PP0V75_S3_MEM_VREFCA



MEMVTT_ENMAKE_BASE=TRUEMEMVTT_EN

SMBUS_PCH_DATA

DP_INT_AUXCH_C_P

TP_DP_IG_A_MLP<3..0>

PP3V3_S4

SMBUS_PCH_DATA

SMBUS_PCH_CLK

HDMI_CLK_PMAKE_BASE=TRUE =PEG_D2R_N<15..12>

=PEG_D2R_P<15..12>

=PEG_R2D_C_N<7..4>

=PEG_D2R_N<7..4>

=PEG_R2D_C_N<3..0>

=PEG_R2D_C_P<11..8>

=PEG_R2D_C_N<11..8>

=PEG_D2R_N<11..8>

MAKE_BASE=TRUEPCIE_TBT_R2D_C_P<3..0>

TP_PEG_D2RP<7..4>MAKE_BASE=TRUE

MAKE_BASE=TRUETP_PEG_D2RN<7..4>

MAKE_BASE=TRUETP_PEG_R2D_CP<7..4>

MAKE_BASE=TRUETP_PEG_R2D_CN<7..4>

NC_PCIE_SSD_D2RP<3..0>TRUETRUE

NC_PCIE_SSD_R2D_CP<3..0>TRUETRUE

NC_PCIE_SSD_R2D_CN<3..0>TRUETRUE

NC_PCIE_SSD_D2RN<3..0>TRUETRUE

=PCIE_SSD_R2D_C_P<3..0>

=PCIE_SSD_R2D_C_N<3..0>

=PCIE_SSD_D2R_N<3..0>

=PCIE_SSD_D2R_P<3..0>

MAKE_BASE=TRUETP_PEG_R2D_CP<15..12>

MAKE_BASE=TRUETP_PEG_D2RP<15..12>

PCIE_TBT_D2R_P<3..0>MAKE_BASE=TRUE

<BRANCH>

<SCH_NUM>

<E4LABEL>

102 OF 118

71 OF 82

14

11

12

14

13 18 44 69 71 72 77

5

5

5

5

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 72 82

49 71

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

49 71

28

12

11

12

12

12

11

11

14

14

14

14

12

14

12 33 71

12 33 71 12 33 71

12 28 71 75

5 68 71 75

22 25 26 71 75

22 23 24 25 26 71 75 78

63 68 71 72

63 68 71 72

37 41 44 48 68 71 72 81

37 41 44 48 68 71 72 81

63 68 71 72

63 68 71 72

37 41 44 48 68 71 72 81

37 41 44 48 68 71 72 81

39 71 72

39 71 72 77

39 71 72 77

39 71 72 77

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39 71 72

39 71 72 77

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5 28 75

5 69 71 72 75

12 33 71

12 68 71 72

12 63 71 72

12 28 71

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18 19 37 49 58 59 62 63 66 67 70 72

12 69 71 72

12 28 71 75

12 63 71

12 28 71 75

12 33 71

12 28 71

12 33 71

12 28 71 75

69 72 75

5 69 71 72 75

12 28 71 75

12 33 71

5 68 71 75

5 28 75

12 33 71

12 28 71 75

12 28 71 75

5 28 75

5 28 75

12 28 71 75

5 68 75

12 68 71 72

5 68 75

12 63 71

12 28 71

12 63 71 72

22 25 26 71 75

22 23 24 71 75 78 22 23 24 71 75 78

12 69 71 72

12 69 71 72 12 69 71 72

69 72 75

5

5 69 71 72 75

5

12 20 69 71 72 12 20 69 71 72

22 23 24 25 26 71 75 78

22 23 24 25 26 71 75 78

22 23 24 25 26 71 75 78

21 60 71 21 60 71

13 18 44 69 71 72 77

5 68 71 75

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

13 18 44 69 71 72 77

13 18 44 69 71 72 77

5 69 71 72 75

5

5

13

13

13

13

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2X

2X

4X

4X

J4801 - ipd flex

J6100 - spiFUNC_TEST

J4002 - Camera

J4813 - keyboard

J8300 - eDP

3X

16X

J9500 - rio coax

J9510 - rio flex

5X

3X

10X

J6050 - left fan

J5150 - hall effect

J3501 - airport

J6601 - mic

J6602 - L speaker

J6603 - R speaker

2X

J4915 - kbd bklt

J6060 - right fan

5X

3X

3X

5X

19X

2X GND

J7000 - DC PWR

J7050 - battery

8X

8X

2X

2X

2X

2X

FUNC_TEST

4X

4X

Power Rails

FUNC_TESTXDP

FUNC_TESTPower Sequence


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TRUE WIFI_EVENT_L

TRUE USB3_EXTB_R2D_P

TRUE CAM_SENSOR_WAKE_L_CONNTRUE MIPI_DATA_CONN_N

PCIE_CLK100M_AP_CONN_NTRUE

TRUE PP3V3_S3RS4_BT_F

WS_CONTROL_KBDTRUE

TRUE CPU_CFG<3>TRUE PM_SYSRST_L

TRUE PM_RSMRST_L

TRUE PM_PCH_PWROK

TRUE XDP_PCH_TDO

PP3V3_S5_AVREF_SMCTRUE

TRUE SMBUS_SMC_5_G3_SDASMBUS_SMC_5_G3_SCLTRUE

TRUE PP20V_DCIN_FUSETRUE ADAPTER_SENSE

SPKRCONN_SR_OUT_PTRUE

TRUE SPKRCONN_SR_OUT_NTRUE SPKRCONN_R_OUT_PTRUE SPKRCONN_R_OUT_NTRUE SPKRCONN_R_ID

TRUE SPKRCONN_SL_OUT_P

TRUE DMIC_SDA2

WS_LEFT_OPTION_KBDTRUE

TRUE WS_KBD_ONOFF_L

TRUE WS_KBD8TRUE WS_KBD9

TRUE WS_KBD7

WS_KBD3TRUE

WS_KBD23TRUE

TRUE WS_KBD22

TRUE WS_KBD20

TRUE WS_KBD19

TRUE WS_KBD17WS_KBD18TRUE

TRUE WS_KBD16_NUMTRUE WS_KBD15_CAP

WS_KBD14TRUE

WS_KBD12TRUE

WS_KBD11TRUE


TRUE PP3V42_G3H

USB_BT_CONN_PTRUE

TRUE PCIE_AP_D2R_PI_N

TRUE PPVOUT_S0_KBDBKLTTRUE KBDBKLT_RETURN2

TRUE WS_LEFT_SHIFT_KBD

PPVTT_S0_DDRTRUE

TRUE PP1V35_S3TRUE PP1V5_S0

XDP_CPU_TMSTRUE

XDP_PCH_TDITRUE

XDP_PCH_TMSTRUE

XDP_CPUPCH_TRST_LTRUE

XDP_CPU_TDOTRUE

XDP_CPU_TDITRUE

XDP_PCH_TCKTRUE

TRUE XDP_CPU_TCK

TRUE PM_DSW_PWRGD

TRUE ALL_SYS_PWRGD

TRUE PM_PCH_SYS_PWROK

TRUE PLT_RESET_L

TRUE EDP_IG_PANEL_PWR

TRUE SMC_ONOFF_L

TRUE PCIE_AP_R2D_P

TRUE PP3V3_WLAN

TRUE MIPI_DATA_CONN_P

TRUE SMC_LID_R

TRUE FAN_LT_PWM

TRUE PP5V_S0

TRUE SMBUS_SMC_0_S0_SDA

PP5V_S3RS0_ALSCAM_FTRUE

TRUE I2C_CAM_SDATRUE I2C_CAM_SCK

TRUE HDMI_DATA_N<2>

HDMI_DATA_P<2>TRUE

USB3_EXTB_D2R_PTRUE

TRUE USB3_EXTB_D2R_N

USB_EXTB_NTRUE

TRUE USB_EXTB_P

HDMI_DATA_P<0>TRUE

TRUE HDMI_DATA_N<1>

TRUE HDMI_CLK_N

TRUE HDMI_DATA_N<0>

PP3V3_S4TRUE

TRUE KBDBKLT_RETURN1

TRUE EDP_IG_BKL_ON

TRUE DMIC_SDA3

TRUE DMIC_CLK3

TRUE SPKRCONN_SL_OUT_NTRUE SPKRCONN_L_OUT_PTRUE SPKRCONN_L_OUT_NTRUE SPKRCONN_L_ID

TRUE XDP_CPU_PRDY_L

XDP_CPU_PREQ_LTRUE

TRUE PPVBAT_G3H_CONN

TRUE PCIE_WAKE_L

TRUE PP1V05_S0

TRUE PP3V42_G3H

FAN_RT_PWMTRUE

TRUE PP3V3_S0

USB3_SD_D2R_NTRUEUSB3_SD_D2R_PTRUE

TRUE MIPI_CLK_CONN_PTRUE MIPI_CLK_CONN_N

FAN_LT_TACHTRUE

SYS_DETECT_LTRUE

AP_CLKREQ_Q_LTRUE

TRUE PP5V_S3

TRUE PP3V42_G3H


WS_KBD4TRUE

TRUE PP3V3_S0SW_SSDTRUE PPVTTDDR_S3

PPVCC_S0_CPUTRUE

PPDCIN_G3HTRUE

PPBUS_G3HTRUE

TRUE PP5V_S5

TRUE PP3V3_S5

PM_SLP_S3_LTRUE

TRUE PCIE_AP_R2D_N

TRUE FAN_RT_TACH

TRUE WS_KBD13

WS_KBD2TRUE

TRUE WS_KBD21

USB3_SD_R2D_C_PTRUE

HDMI_DATA_P<1>TRUE

TRUE HDMI_CLK_P

SMBUS_SMC_0_S0_SCLTRUE

PP5V_S0TRUE

PP3V3_S3TRUEPP3V3_S4TRUE

TRUE USB_EXTB_OC_L

SMBUS_PCH_DATATRUEPM_SLP_S3_BUF_LTRUE

RIO_SDCONN_STATE_CHANGE_LTRUE

PP5V_S4TRUE

PM_SLP_S4_LTRUE

SMBUS_PCH_CLKTRUE

HDMI_HPDTRUE

HDMI_DDC_DATATRUE

HDMI_DDC_CLKTRUE

TRUE SD_PWR_EN

TRUE PP3V3_S0TRUE PP3V3_S3

TRUE PP5V_S0

DP_INT_ML_P<3>TRUE

TRUE PPVOUT_S0_LCDBKLTTRUE PP5VR3V3_SW_LCDTRUE I2C_BKLT_SCL

I2C_BKLT_SDATRUE

TRUE LCD_BKLT_PWM_RSMBUS_SMC_0_S0_SDATRUE

TRUE SMBUS_SMC_0_S0_SCL

TRUE LCD_HPD_CONN

DP_INT_ML_P<2>TRUE

DP_INT_ML_P<1>TRUE

TRUE DP_INT_ML_P<0>TRUE DP_INT_ML_N<3>

DP_INT_ML_N<1>TRUE

TRUE DP_INT_ML_N<2>

DP_INT_ML_N<0>TRUE

DP_INT_AUX_PTRUE

DP_INT_AUX_NTRUE

TRUE PCIE_CLK100M_AP_CONN_P

TRUE USB_BT_CONN_N

TRUE PCIE_AP_D2R_PI_PSMC_RESET_LTRUE

TRUE SPI_ALT_IO1_MISO

TRUE SMC_TCK

SPI_ALT_CS_LTRUESPI_ALT_IO0_MOSITRUE

SPIROM_USE_MLBTRUE

SMC_TMSTRUE

PP3V42_G3HTRUE

TPAD_SPI_CS_LTRUE

TPAD_SPI_INT_LTRUE

TRUE TPAD_VBUS_EN

GND_ACTUATORTRUE

TRUE PP3V3_S4TRUE PP5V_S4

TRUE PPVIN_S4_TPAD

IOXP2_INT_LTRUE

SMC_PME_S4_WAKE_LTRUE

USB_TPAD_PTRUE

TPAD_SPI_BUS_ENTRUE

I2C_IOXP_SCLTRUE

USB_TPAD_NTRUE

SPI_ALT_IO1_HOLD_LTRUE

SPI_ALT_IO2_WP_LTRUE

TPAD_SPI_MOSITRUETPAD_SPI_MISOTRUETPAD_SPI_SCLKTRUE

I2C_IOXP_SDATRUE

TPAD_ACTUATOR_THRMTRIP_LTRUE

SMC_ACTUATOR_EN_LTRUE

TRUE SMC_LIDSMBUS_SMC_2_S3_SDATRUE

SMBUS_SMC_2_S3_SCLTRUE

AP_RESET_CONN_LTRUE

SPI_ALT_CLKTRUE

LCD_IRQ_LTRUE

TRUE USB3_EXTB_R2D_N

USB3_SD_R2D_C_NTRUE

TRUE GND

TRUE GND

GNDTRUE

GNDTRUE

GNDTRUE

TRUE GND

TRUE GND

GNDTRUE

TRUE GND

TRUE GND

GNDTRUE

GNDTRUE

TRUE GND

GNDTRUE

GNDTRUE

GNDTRUE

TRUE GND

GNDTRUE

<BRANCH>

<SCH_NUM>

<E4LABEL>

104 OF 118

72 OF 82

34 41 42

69 76

37

37 80

34 77

34

39

6 18 75

12 19 41 77

12 67 77

12 19 77

11 18

41 42

41 44 56 57 81

41 44 56 57 81

56

56

53 55 82

53 55 82

53 55 82

53 55 82

52 55

53 55 82

55

39

39

39

39

39

39

39

39

39

39

39

39

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39

39

39

39

39

39

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

34 76

34 77

40 63

40 63

39

21 27 60 70

21 46 60 66 70

11 12 13 15 17 19 52 64 67 69 70

6 18 75

11 18

11 18

6 18 75

6 18 75

6 18 75

11 18

6 18 75

12 41 77

18 19 41 58 67

12 18 19 41 77

12 18 20 21

12 68 71

39 41 42

34 77

34 42

37 80

43

49

18 19 37 49 58 59 62 63 66 67 70 71 72

37 41 44 48 68 71 72 81

37

36 37

36 37

69 71 75

69 71 75

13 69 76

13 69 76

13 69 76

13 69 76

69 71 75

69 71 75

5 69 71 75

69 71 75

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

40 63

12 63 71

52 55

52 55

53 55 82

53 55 82

53 55 82

52 55

6 18 75

6 18 75

56 57

12 34 36 77

10 14 15 17 18 42 62 67 70

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

49

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

13 20 69 77

13 20 69 77

37 80

37 80

49

56

34

21 37 60 66 67 70

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

39

39

39

35 46 70

60 70

6 8 10 46 59 70

56 57 70

30 45 56 57 63 65 70

61 66 70

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 82

12 21 41 67

34 77

49

39

39

39

13 20 69 77

69 71 75

5 69 71 75

37 41 44 48 68 71 72 81

18 19 37 49 58 59 62 63 66 67 70 71 72

13 20 21 44 46 47 66 69 70 72

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

18 69

13 18 44 69 71 77

51 66 67 69

20 69

38 39 51 61 66 67 68 69 70 72

12 21 34 38 41 67 69

13 18 44 69 71 77

12 20 69 71

12 69 71

12 69 71

13 18 69

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68 70 72 82

13 20 21 44 46 47 66 69 70 72

18 19 37 49 58 59 62 63 66 67 70 71 72

68 75

63 68

68

63 68 71

63 68 71

63 68

37 41 44 48 68 71 72 81

37 41 44 48 68 71 72 81

68

68 75

68 75

68 75

68 75

68 75

68 75

68 75

68 75

68 75

34 77

34 76

34 77 41 42 50 57

50 77

41 42 50

50 77

50 77

14 50

41 42 50

19 35 38 39 41 42 43 44 50 56 57 65 67 70 72

39 71 77

39 71

39

39

20 34 39 40 42 43 46 47 65 66 67 69 70 71 72

38 39 51 61 66 67 68 69 70 72

39 46 70

39

34 39 41 43

13 39 76

39 71

39

13 39 76

50 77

39 71 77

39 71 77

39 71 77

39

39 65

39 41

39 41 42 43

39 41 44 81

39 41 44 81

34

50 77

68

69 76

13 20 69 77

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PLACEABLE BEAD-PROBES FOR TBTMAKE_BASE

PCHNO_TEST NO_TEST

NC NO_TESTs

ThunderboltMAKE_BASE

1 BPA532SM BEAD-PROBE NO_XNET_CONNECTION=TRUE

1 BPA531BEAD-PROBESM NO_XNET_CONNECTION=TRUE

I1975

I1976

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NC & No Test

NC_HDA_SDIN1NC_HDA_SDIN2NC_HDA_SDIN3

NC_CLINK_CLKNC_CLINK_DATA TRUE TRUE NC_CLINK_DATA

TRUE NC_CLINK_RESET_LTRUE

TRUE TRUE NC_LPC_CLK33M_LPCPLUS_RNC_LPC_CLK33M_LPCPLUS_RNC_CLINK_RESET_L

NC_LPC_DREQ0_L

NC_PCI_CLK33M_OUT2TRUETRUENC_PCI_CLK33M_OUT2NC_PCI_PME_LNC_ITPXDP_CLK100MP

TRUE TRUE NC_ITPXDP_CLK100MN

TRUETRUE NC_USB_IRPNC_USB_IRNTRUETRUE

NC_USB_PSOCP TRUE TRUE NC_USB_PSOCP

TRUETRUE NC_USB_EXTDPTRUE TRUE NC_USB_EXTDN

TRUE TRUE NC_USB_7N

TRUE NC_USB_WLANPTRUE

TRUE PCIE_TBT_R2D_P<3..0>PCIE_TBT_R2D_N<3..0>TRUEPCIE_TBT_D2R_C_P<3..0>TRUE

NC_SATA_ODD_R2D_CP

TRUETRUE NC_PCIE_ENET_R2D_CP

TRUE NC_PCIE_ENET_D2RNTRUE

TRUETRUE NC_DP_TBTSRC_ML_CN<3..0>TP_DP_TBTSRC_ML_CP<3..0>

NC_SATA_A_D2RN

NC_SATA_A_R2D_CN

NC_USB3_EXTC_R2D_CN

NC_SATA_A_R2D_CPNC_SATA_B_D2RNNC_SATA_B_D2RP

NC_SATA_B_R2D_CPNC_SATA_B_R2D_CN

NC_ITPXDP_CLK100MN

NC_USB_WLANP

NC_SATA_F_D2RN

TBT_A_D2R_N<1>TBT_A_D2R_P<1>

NC_USB3_SPARE_D2RPNC_USB3_SPARE_R2D_CNNC_USB3_SPARE_R2D_CPNC_USB3_EXTC_D2RN

NC_USB3_EXTC_R2D_CP

NC_USB3_EXTD_D2RPNC_USB3_EXTD_D2RN

NC_USB3_EXTD_R2D_CNNC_USB3_EXTD_R2D_CP

NC_PCIE_ENET_D2RNNC_PCIE_ENET_D2RP

NC_PCIE_ENET_R2D_CP

TP_DP_TBTSRC_ML_CN<3..0>NC_DP_TBTSRC_AUXCH_CPNC_DP_TBTSRC_AUXCH_CN

NC_TBT_XTAL25OUT

NC_SMC_INTERFACE_2

NC_SATA_D_R2D_CN

NC_SATA_F_D2RPTRUE TRUE

TRUE TRUE NC_PCIE_CLK100M_SWN

TRUE DMI_N2S_N<3..1>

TRUE DMI_S2N_N<3..1>TRUE DMI_S2N_P<3..1>

PCIE_TBT_D2R_C_N<3..0>TRUE

NC_DP_TBTSRC_ML_CP<3..0>TRUETRUE

TRUE TRUE NC_DP_TBTSRC_AUXCH_CP

TRUETRUE NC_USB3_EXTD_R2D_CN

TRUE TRUE NC_USB3_SPARE_R2D_CN

NC_PCH_GPIO64_CLKOUTFLEX0TRUETRUE

NC_USB3_EXTC_D2RNTRUE TRUE

TRUE TRUE NC_DP_TBTSRC_AUXCH_CN

NC_SATA_ODD_D2RPTRUE TRUE

NC_SATA_D_D2RNTRUE TRUE

NC_SATA_F_R2D_CNTRUETRUE

TRUETRUE NC_USB_WLANNTRUE NC_USB_SDPTRUE

TRUE NC_HDA_SDIN1TRUE

NC_LPC_DREQ0_LTRUE TRUE

TRUE TRUE NC_CLINK_CLK

NC_USB_SMCPTRUETRUENC_USB_SMCNTRUE TRUE

TRUETRUE NC_SATA_B_R2D_CP

TRUETRUE NC_SATA_B_D2RNNC_SATA_A_R2D_CPTRUETRUE

TRUETRUE NC_USB3_EXTD_R2D_CP

TRUE TRUE NC_USB3_EXTC_R2D_CN

NC_SATA_A_R2D_CNTRUETRUE

NC_SATA_A_D2RNTRUETRUE

TRUE TRUE NC_HDA_SDIN2

NC_TBT_XTAL25OUTTRUETRUE

NC_SMC_INTERFACE_2TRUE TRUE

NC_USB3_SPARE_D2RPTRUE TRUE

NC_USB3_EXTC_D2RP

NC_ITPXDP_CLK100MPTRUETRUE

NC_USB_SMCNNC_USB_SMCP

NC_PCIE_CLK100M_SWPTRUETRUE

TRUE TRUE NC_PCIE_CLK100M_PEGBP

TRUE TRUE NC_PCIE_CLK100M_ENETPTRUETRUE NC_PCIE_CLK100M_ENETN

TRUETRUE NC_USB_4PTRUE NC_USB_4NTRUE

NC_SATA_D_D2RP

NC_SATA_F_R2D_CPTRUETRUE

NC_PCI_PME_LTRUETRUE

NC_HDA_SDIN3TRUE TRUE

NC_SATA_D_D2RN

TRUETRUE NC_PCIE_ENET_D2RP

NC_USB_6PNC_USB_6N

NC_USB_WLANN

NC_USB_SDN

NC_USB_EXTCN

NC_SATA_F_R2D_CPNC_SATA_F_R2D_CNNC_SATA_F_D2RP

TRUETRUE NC_SATA_D_D2RP

NC_PCIE_ENET_R2D_CNTRUETRUE

NC_SATA_A_D2RP

NC_SATA_ODD_D2RN

TRUE TRUE NC_USB3_EXTD_D2RN

NC_USB3_SPARE_D2RN

NC_SATA_A_D2RPTRUETRUE

NC_SATA_B_D2RPTRUE TRUE

TRUE NC_SATA_ODD_D2RNTRUE

NC_SATA_ODD_R2D_CNTRUE TRUE

TRUE TRUE NC_SATA_ODD_R2D_CP

NC_SATA_D_R2D_CNTRUE TRUE

TRUE TRUE NC_SATA_F_D2RN

NC_USB_4N


TRUE TRUE NC_USB3_EXTC_R2D_CP

NC_USB3_SPARE_R2D_CPTRUE TRUE

TRUE TRUE NC_PCIE_CLK100M_ENETSDP



NC_PCH_GPIO65_CLKOUTFLEX1TRUE TRUE

TRUE NC_USB_EXTCNTRUE

TRUE TRUE NC_USB_EXTCPTRUETRUE NC_USB_SDN

TRUE NC_USB_6NTRUE

NC_USB_IRNNC_USB_IRP

TRUE TRUE NC_USB_PSOCN

NC_USB_4P

NC_PCH_GPIO65_CLKOUTFLEX1NC_PCH_GPIO64_CLKOUTFLEX0

NC_PCIE_CLK100M_SWP

NC_USB_PSOCNNC_USB_EXTDPNC_USB_EXTDNNC_USB_7P TRUE TRUE NC_USB_7P


NC_PCIE_CLK100M_ENETNNC_PCIE_CLK100M_ENETPNC_PCIE_CLK100M_PEGBN

NC_PCIE_CLK100M_ENETSDPNC_PCIE_CLK100M_ENETSDN

TRUETRUE NC_USB3_EXTD_D2RP

TRUE TRUE NC_USB3_EXTC_D2RP

NC_DP_IG_D_AUXCHN

NC_PCIE_CLK100M_PE5PTRUE TRUE NC_PCIE_CLK100M_PE5N

TRUE NC_DP_IG_D_AUXCHNTRUE

NC_PCIE_CLK100M_PE5NNC_PCIE_CLK100M_GPUPNC_PCIE_CLK100M_GPUN

NC_DP_IG_D_AUXCHP

NC_USB3_SPARE_D2RNTRUE TRUE

TRUETRUE NC_PCIE_CLK100M_GPUN

NC_SATA_B_R2D_CNTRUETRUE

TRUE TRUE NC_SATA_D_R2D_CP

TRUE TRUE NC_USB_6PNC_USB_7N

NC_DP_IG_D_AUXCHPTRUE TRUE

NC_USB_SDP

NC_USB_EXTCP

NC_SATA_D_R2D_CP

NC_SATA_ODD_R2D_CNNC_SATA_ODD_D2RP

NC_PCIE_CLK100M_SWNNC_PCIE_CLK100M_PEGBP

TRUETRUE NC_PCIE_CLK100M_PEGBN

TRUE TRUE NC_PCIE_CLK100M_ENETSDNTRUE TRUE NC_PCIE_CLK100M_PE5P

TRUETRUE NC_PCIE_CLK100M_GPUP

TRUE DMI_N2S_P<3..1>

TRUE NC_PCI_CLK33M_OUT3TRUENC_PCI_CLK33M_OUT3

NC_PCIE_ENET_R2D_CN

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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD





TABLE_SPACING_RULE_ITEM


TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM



TABLE_PHYSICAL_ASSIGNMENT_ITEM


LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD



















AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD





PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD


































X425 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

Stackup-Defined Spacing Rules

Inner dielectric is 0.053 mm nominal.Note: Outer dielectric is 0.058 mm nominal,

10 MM=DEFAULT =DEFAULTY =DEFAULT* =DEFAULTSTANDARD

40_OHM_SE TOP,BOTTOM Y 0.095 MM0.145 MM

0.116 MM0.116 MMY45_OHM_SE TOP,BOTTOM

=45_OHM_SE 10 MM=45_OHM_SE* Y 0 MM 0 MMDEFAULT

0.165 MMTOP,BOTTOM37_OHM_SE Y 0.095 MM

=STANDARD=STANDARD=STANDARD37_OHM_SE Y* 0.118 MM 0.090 MM

=STANDARD =STANDARD =STANDARD* Y40_OHM_SE 0.102 MM 0.090 MM

0.083 MM 0.083 MM45_OHM_SE =STANDARD =STANDARDY* =STANDARD

0.066 MMY =STANDARD=STANDARD=STANDARD*50_OHM_SE 0.066 MM

YTOP,BOTTOM50_OHM_SE 0.095 MM0.095 MM

Y 0.095 MMTOP,BOTTOM27P4_OHM_SE 0.265 MM

=STANDARD =STANDARD* Y 0.1 MM =STANDARD27P4_OHM_SE 0.186 MM

=STANDARD =STANDARD =STANDARDN* =STANDARD72_OHM_DIFF =STANDARD

0.120 MMYISL3,ISL4,ISL9,ISL1072_OHM_DIFF 0.120 MM0.105 MM 0.105 MM

0.105 MM0.105 MM 0.120 MM72_OHM_DIFF Y 0.120 MMISL2,ISL11

Y 0.146 MM 0.120 MM0.120 MMTOP,BOTTOM72_OHM_DIFF 0.146 MM

=STANDARD=STANDARD =STANDARD* N80_OHM_DIFF =STANDARD =STANDARD

0.120 MM 0.120 MMY80_OHM_DIFF 0.092 MMISL3,ISL4,ISL9,ISL10 0.092 MM

0.155 MMY80_OHM_DIFF TOP,BOTTOM 0.125 MM 0.155 MM0.125 MM

0.125 MMTOP,BOTTOM85_OHM_DIFF 0.125 MMY 0.105 MM 0.105 MM

TOP,BOTTOM90_OHM_DIFF Y 0.101 MM 0.101 MM 0.180 MM0.180 MM

0.071MM 0.071MMY* 0.075MM 0.126MMP65_BGA

0.053 MM ?ISL3,ISL4,ISL9,ISL101x_DIELECTRIC

ISL3,ISL4,ISL9,ISL10 0.120 MM0.120 MM85_OHM_DIFF Y 0.080 MM 0.080 MM

YISL2,ISL11 0.120 MM 0.120 MM85_OHM_DIFF 0.080 MM 0.080 MM

90_OHM_DIFF N* =STANDARD =STANDARD=STANDARD=STANDARD =STANDARD

YISL3,ISL4,ISL9,ISL1090_OHM_DIFF 0.078 MM0.078 MM 0.200 MM0.200 MM

0.200 MMY90_OHM_DIFF ISL2,ISL11 0.078 MM 0.078 MM 0.200 MM

* =STANDARDN =STANDARD85_OHM_DIFF =STANDARD=STANDARD =STANDARD

0.120 MM80_OHM_DIFF YISL2,ISL11 0.120 MM0.092 MM 0.092 MM

?1:1_SPACING 0.1 MM*

P072_SPACE 0.071 MM* ?

BGA_P2MM * 0.2 MM ?

BGA_P1MM 0.1 MM ?*

P65BGA* * P075_SPACE

1X_DIELECTRIC 0.101 MM ?ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

P65_BGAP65BGA*

P075_SPACE 0.075 MM ?*

1x_DIELECTRIC TOP,BOTTOM ?0.058 MM

P072_SPACE** BGA

=STANDARD1:1_DIFFPAIR Y* =STANDARD 0.1 MM0.1 MM=STANDARD

=DEFAULT*STANDARD ?

0.1 MM*DEFAULT ?

MMNO_TYPE,BGA,P65BGA 16.2TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

SYNC_DATE=12/10/2012SYNC_MASTER=SIDLE_J45

PCB Rule Definitions

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TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM







TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM


















PEG - SSD & TBT

DIGITAL VIDEO SIGNAL CONSTRAINTS

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

SPACINGELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE

DP AUX NET PROPERTIESCPU Net Properties

PHYSICAL

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

Some signals require 27.4-ohm single-ended impedance.

SOURCE: IVB PLATFORM DG , Tables 205-207

Spacing Rule Sets

CPU Signal Constraints

SPACING

NET_TYPE

Most CPU signals with impedance requirements are 50-ohm single-ended.


DP / HDMI NET PROPERTIES

I125

I126

I130

I132

I133

I134

I135

I136

I140

I141

I150

I151

I152

I153

I154

I155

I156

I157

I158

I159

I166

I167

I170

I171

I210

I211

I212

I213

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

I249

I250

I251

I252

I253

I254

I255

I256

CPU_8MIL ?* 8 MIL

CPU_COMP 20 MIL* ?

DMICLK2N2S ?=10X_DIELECTRICTOP,BOTTOM

DMI_N2S DMI_TXRX*DMI_S2N

25 MILCPU_VCCSENSE * ?

=2:1_SPACING ?*CPU_ITP

* ?=6X_DIELECTRICDMICLK2N2S

*CPU_AGTL =STANDARD ?

DMI_TXRX ?=10X_DIELECTRICTOP,BOTTOM

=50_OHM_SECPU_50S =50_OHM_SE =50_OHM_SE=50_OHM_SE =STANDARD* =STANDARD

=45_OHM_SE=45_OHM_SECPU_45S =STANDARD* =45_OHM_SE =45_OHM_SE =STANDARD

DMI_TXRX ?=6X_DIELECTRIC*

?=6X_DIELECTRICDMICLK2S2N TOP,BOTTOMDMICLK2S2N * ?=3X_DIELECTRIC

=27P4_OHM_SE=27P4_OHM_SECPU_27P4S =27P4_OHM_SE* 7 MIL=27P4_OHM_SE 7 MIL

CPU_85D =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF

* ?DMI_2SAME =3X_DIELECTRIC

DMI_TXRXDMI_N2S *DMI_S2N

* DMI_2SAME=SAMEDMI_*

DMICLK2OTHER * ?=4X_DIELECTRIC

=7x_DIELECTRIC ?*HDMICLK_2CLK HDMICLK_2CLK ?=10x_DIELECTRICTOP,BOTTOM

HDMICLK_2DP TOP,BOTTOM ?=6x_DIELECTRIC

=4x_DIELECTRICTOP,BOTTOM ?DP_2SAME

DP_2OTHER ?=6x_DIELECTRICTOP,BOTTOM

=7x_DIELECTRIC*HDMICLK_2OTHER ?

DISPLAYPORT DP_2SAME*=SAME

*DISPLAYPORT DP_2OTHER*

HDMI_CLK * * HDMICLK_2OTHER

HDMI_CLK HDMICLK_2DP*DISPLAYPORT

*CLK_*HDMI_CLK HDMICLK_2CLK

HDMICLK_2OTHER =10x_DIELECTRICTOP,BOTTOM ?

=4x_DIELECTRICHDMICLK_2DP ?*

=4x_DIELECTRIC ?DP_2OTHER *

=3x_DIELECTRIC ?*DP_2SAME

=85_OHM_DIFF=85_OHM_DIFF*DP_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF

DMICLK2OTHER TOP,BOTTOM =4X_DIELECTRIC ?

DMI_2SAME ?=4X_DIELECTRICTOP,BOTTOM

CPU_AGTL TOP,BOTTOM ?=2x_DIELECTRIC

CPU_VID 0.457 MM ?*

CPU_VREF 12 MIL* ?

* ?PEG3_2SAME =4X_DIELECTRIC

* ?PEG3_2OTHER =5X_DIELECTRIC

PEG_D2R * PEG_TXRXPEG_R2D

*PEG_* PEG_2OTHER*

PEG3_2CLK * =8X_DIELECTRIC ?

*PEG_* =SAME PEG_2SAME

*PEG3_TXRX =8X_DIELECTRIC ?

* DMICLK2OTHER*CLK_DMI

*PEG3_* PEG3_2CLKCLK_*

PEG3_2SAMEPEG3_* =SAME *

PEG3_TXRX TOP,BOTTOM ?=12X_DIELECTRIC

*PEG3_D2RPEG3_R2D PEG3_TXRX

*PEG3_* PEG3_2OTHER*

PEG_2CLK*PEG_* CLK_*

?TOP,BOTTOM =10X_DIELECTRICPEG_TXRX

DMI_S2N * DMICLK2S2NCLK_DMI

CLK_DMI * DMICLK2N2SDMI_N2S

?PEG_2SAME =4X_DIELECTRICTOP,BOTTOM

?=6X_DIELECTRICPEG_2OTHER TOP,BOTTOM

=80_OHM_DIFFPEG_80D =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

?PEG_2SAME =3X_DIELECTRIC*

PEG_TXRX * =6X_DIELECTRIC ?

?PEG_2OTHER * =4X_DIELECTRIC

* ?PEG_2CLK =7X_DIELECTRIC

?=12X_DIELECTRICPEG3_2CLK TOP,BOTTOM

TOP,BOTTOM ?PEG3_2OTHER =8X_DIELECTRIC

TOP,BOTTOM ?PEG3_2SAME =6X_DIELECTRIC

PEG_2CLK ?TOP,BOTTOM =10X_DIELECTRIC


CPU ConstraintsSYNC_MASTER=CLEAN_X305_PEG

CPU_MEM_VREF MEM_12MIL CPU_DIMMA_VREFDQ

CPU_AGTL PM_MEM_PWRGDPM_MEM_PWRGD CPU_45S

CPU_45S PM_SYNCCPU_AGTLPM_SYNC

CPU_VCCSENSE CPU_VCCSENSECPU_27P4S CPU_VCCSENSE_N

CPU_27P4S CPU_COMPCPU_SM_RCOMP CPU_SM_RCOMP<2..0>CPU_VIDSOUTCPU_VID CPU_VIDCPU_45S

CPU_45S CPU_VIDSCLKCPU_VID CPU_VID

DISPLAYPORTDP_85DDP_INT_IG_AUX DP_INT_AUXCH_C_P

DP_85D DISPLAYPORT DP_INT_ML_F_N<3..0>

CPU_PROCHOT_LCPU_AGTLCPU_45SCPU_PROCHOT_L

XDP_BDRESET_L XDP_DBRESET_LCPU_ITPCPU_45S

CPU_ITP XDP_BPM_L<3..0>CPU_45SXDP_BPM

DISPLAYPORTDP_85D DP_INT_AUXCH_C_NDP_INT_IG_AUX

XDP_BPM_L<7..4>CPU_ITPCPU_45SXDP_BPM_L

DP_85D DISPLAYPORT DP_INT_ML_N<3..0>DP_85D DISPLAYPORT DP_INT_ML_P<3..0>

DP_85D DISPLAYPORT DP_INT_ML_F_P<3..0>

CPU_PECICPU_PECI CPU_VIDCPU_45S

XDP_CPU_TMSXDP_TMS CPU_ITPCPU_45S

XDP_TCK XDP_CPU_TCKCPU_ITPCPU_45S

CPU_45SPM_THRMTRIP_L PM_THRMTRIP_LCPU_8MIL

DP_85D DP_TBTSNK1_ML_N<3..0>DISPLAYPORT

DP_TBTSNK0_AUXCH_PTBTSNK0_AUXCH DP_85D

DP_85DTBTSNK0_AUXCH DP_TBTSNK0_AUXCH_NDP_TBTSNK0_AUXCH_C_PDP_85DDP_TBTSNK0_AUXCH_C_NDP_85D

DP_85DTBTSNK1_AUXCH DP_TBTSNK1_AUXCH_PDP_TBTSNK1_AUXCH_NTBTSNK1_AUXCH DP_85D

DP_85D DISPLAYPORT DP_TBTSNK1_ML_P<3..0>DP_TBT_ML1 DP_85D DISPLAYPORT DP_TBTSNK1_ML_C_N<3..0>

CPU_CLK135_PLL CPU_85D CPU_CLK135M_DPLLREF_PCLK_PCIE

CLK_PCIE CPU_CLK135M_DPLLSS_PCPU_85DCPU_CLK135_PLL

DMI_CLK100M_CPU_PDMI_CLK CPU_85D CLK_DMI

FDI_CSYNC CPU_50S FDI_CSYNCCPU_AGTL

CPU_PWRGDCPU_AGTLCPU_45SCPU_PWRGD

XDP_CPU_PREQ_LXDP_PREQ_L CPU_ITPCPU_45S

CPU_COMP CPU_EDP_RCOMPCPU_27P4SCPU_EDP_COMP

XDP_CPU_TDICPU_ITPXDP_TDI CPU_45S

CPU_85D PCIE_TBT_R2D_C_P<3..0>PEG_R2D

CPU_85D PEG_R2D PCIE_TBT_R2D_C_N<3..0>

CPU_85D PCIE_TBT_D2R_P<3..0>PEG_D2R_TBT PEG_D2R

DMI_S2N_N<3:0>DMI_S2N CPU_85D DMI_S2N

CPU_CFG<19..0>CPU_CFG CPU_ITPCPU_45S

XDP_TDO XDP_CPU_TDOCPU_ITPCPU_45S

XDP_CLK_PCH CLK_PCIE NC_ITPXDP_CLK100MNCLK_PCIE_85D

XDP_CLK_PCH NC_ITPXDP_CLK100MPCLK_PCIECLK_PCIE_85D

XDP_TRST_L CPU_ITPCPU_45S XDP_CPUPCH_TRST_L

CPU_85DCPU_CLK135_PLL CLK_PCIE CPU_CLK135M_DPLLREF_N

CPU_85D PEG_R2DPEG_R2D_TBT PCIE_TBT_R2D_N<3..0>

CPU_27P4S CPU_PEG_RCOMPCPU_PEG_COMP CPU_COMP

DMI_N2S CPU_85D DMI_N2S_N<3:0>DMI_N2S

CPU_85D CLK_DMI DMI_CLK100M_CPU_NDMI_CLK

CLK_PCIE CPU_CLK135M_DPLLSS_NCPU_85DCPU_CLK135_PLL

CPU_85DPEG_R2D_TBT PCIE_TBT_R2D_P<3..0>PEG_R2D

CPU_85D PEG_D2R PCIE_TBT_D2R_C_P<3..0>CPU_85D PEG_D2R PCIE_TBT_D2R_C_N<3..0>

PEG_D2RCPU_85D PCIE_TBT_D2R_N<3..0>PEG_D2R_TBT

HDMI_DATA_P<2..0>DP_85DHDMI_DATA DISPLAYPORT

DP_TBTSNK1_AUXCH_C_PDP_85D

HDMI_CLK DP_85D HDMI_CLK HDMI_CLK_N

DP_TBTSNK0_ML_N<3..0>DISPLAYPORTDP_85D

DP_TBTSNK1_AUXCH_C_NDP_85D

DP_85D HDMI_CLKHDMI_CLK HDMI_CLK_PDP_85DHDMI_DATA DISPLAYPORT HDMI_DATA_N<2..0>

DP_TBT_ML1 DISPLAYPORTDP_85D DP_TBTSNK1_ML_C_P<3..0>

DISPLAYPORTDP_85D DP_TBTSNK0_ML_P<3..0>DP_TBT_ML0 DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_N<3..0>DP_TBT_ML0 DP_85D DISPLAYPORT DP_TBTSNK0_ML_C_P<3..0>

XDP_PRDY_L CPU_45S CPU_ITP XDP_CPU_PRDY_L

CPU_CATERR_LCPU_CATERR_L CPU_AGTLCPU_45S

FDI_INT CPU_50S FDI_INTCPU_AGTL

DMI_N2S CPU_85D DMI_N2S_P<3:0>DMI_N2S

CPU_85D DMI_S2NDMI_S2N DMI_S2N_P<3:0>

DP_INT_ML_P<3..0>DP_85D DISPLAYPORT

DISPLAYPORT DP_INT_ML_C_P<3..0>DP_INT_IG_ML DP_85D

DISPLAYPORT DP_INT_AUX_PDP_85DDP_INT_IG_AUX

DISPLAYPORT DP_INT_ML_N<3..0>DP_85D

DISPLAYPORT DP_INT_ML_C_N<3..0>DP_85DDP_INT_IG_ML

DP_85D DISPLAYPORT DP_INT_AUX_NDP_INT_IG_AUX

PCIE_SSD_R2D_N<3..0>PEG3_R2DCPU_85D

PCIE_SSD_R2D_P<3..0>PEG3_R2DCPU_85D

PCIE_R2D_SSD PCIE_SSD_R2D_C_N<3..0>PEG3_R2DCPU_85D

PCIE_R2D_SSD PCIE_SSD_R2D_C_P<3..0>PEG3_R2DCPU_85D

PCIE_D2R_SSD PCIE_SSD_D2R_N<3..0>PEG3_D2RCPU_85D

PCIE_D2R_SSD PCIE_SSD_D2R_P<3..0>CPU_85D PEG3_D2R

CPU_DIMMB_VREFDQMEM_12MILCPU_MEM_VREF

MEM_PWRCPU_MEM_VREF PP0V75_S3_MEM_VREFCACPU_VREF PP0V75_S3_MEM_VREFDQ_BCPU_MEM_VREF

CPU_MEM_VREF PP0V75_S3_MEM_VREFDQ_AMEM_PWR

MEM_PWRCPU_MEM_VREF PP0V75_S3_MEM_VREFCA

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE_PCPU_VCCSENSE

CPU_VID CPU_45S CPU_VIDALERT_LCPU_VID

<BRANCH>

<SCH_NUM>

<E4LABEL>

111 OF 118

75 OF 82

7 22

6 12 21

6 12

9 58

6

8 58

8 58

5 68 71

68

6 41 42 58

6 18 19

6 18

5 68 71

6 18

68 72 75

68 72 75

68

6 14 42

6 18 72

6 18 72

6 14 42

28

28

28

12 28 71

12 28 71

28

28

28

5 28 71

6 11

6 11

6 11

5 12

6 14 18

6 18 72

5

6 18 72

5 28 71

5 28 71

5 28 71

5 12 73

6 18 72

6 18 72

11 73

11 73

6 18 72

6 11

28 73

5

5 12 73

6 11

6 11

28 73

28 73

28 73

5 28 71

69 71 72

12 28 71

5 69 71 72

28

12 28 71

5 69 71 72

69 71 72

5 28 71

28

5 28 71

5 28 71

6 18 72

6 41

5 12

5 12 73

5 12 73

68 72 75

5 68 71

68 72

68 72 75

5 68 71

68 72

35

35

5 35 71

5 35 71

5 35 71

5 35 71

7 22

22 23 24 25 26 71 75 78

22 25 26 71

22 23 24 71 78

22 23 24 25 26 71 75 78

8 58

8 58

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m

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SATA Interface Constraints

PCH Net PropertiesNET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

NOTE: Latest Intel DG calls out 50ohms SE for sys clocks

SPACINGPHYSICAL

PHYSICAL

NET_TYPE

Clock Net PropertiesELECTRICAL_CONSTRAINT_SET

NOTE: 25MHz system clocks very sensitive to noise.

System Clock Signal Constraints

USB 2.0 Interface Constraints

USB 3.0 INTERFACE CONSTRAINTS

I213

I220

I221

I222

I223

I228

I229

I230

I231

I238

I239

I244

I245

I248

I249

I250

I251

I253

I254

I255

I256

I259

I260

I261

I262

I263

I264

I265

I266

I267

I268

I271

I272

I273

I274

I281

I282

I283

I284

I285

I286

I287

I288

I290

I291

I292

I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

=4X_DIELECTRIC ?BT_WAKE *

?*USB =4X_DIELECTRIC

?*USB_RBIAS =6X_DIELECTRIC

*USB3_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF

=10X_DIELECTRICTOP,BOTTOM ?SATA_TXRX

=6X_DIELECTRIC ?SATA_2OTHER TOP,BOTTOM

=6X_DIELECTRICUSB ?TOP,BOTTOM

TOP,BOTTOM ?=10X_DIELECTRICUSB_RBIAS

TOP,BOTTOM ?BT_WAKE =6X_DIELECTRIC

USB3_2SAME =3X_DIELECTRIC* ?

=6X_DIELECTRICUSB3_TXRX * ?

?=6X_DIELECTRICTOP,BOTTOMUSB3_2OTHER

TOP,BOTTOM ?USB3_TXRX =10X_DIELECTRIC

* =STANDARD=STANDARDCLK_SLOW_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE

* =STANDARDCLK_25M_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD=45_OHM_SE

USB3_2SAME=SAME *USB3_*

USB3_R2D USB3_D2R * USB3_TXRX

* *USB3_* USB3_2OTHER

TOP,BOTTOM ?=4x_DIELECTRICUSB3_2SAME

=5x_DIELECTRICCLK_25M * ?

=4x_DIELECTRICCLK_SLOW * ?

* =37_OHM_SE =37_OHM_SE=37_OHM_SE =37_OHM_SESATA_37SE =37_OHM_SE=37_OHM_SE

SATA_RCOMP =10X_DIELECTRICTOP,BOTTOM ?

* SATA_2OTHER*SATA_*

?*SATA_2SAME =3X_DIELECTRIC

=SAMESATA_* SATA_2SAME*

=6X_DIELECTRICSATA_RCOMP ?*

SATA_2OTHER ?* =4X_DIELECTRIC

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFFUSB_85D * =85_OHM_DIFF

=STANDARD =STANDARD* =STANDARD=STANDARD =STANDARD =STANDARDPCH_USB_RBIAS

?*SATA_TXRX =6X_DIELECTRIC

* =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFFSATA_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

SATA_TXRXSATA_R2D *SATA_D2R

*SATA_45SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE

=4x_DIELECTRICTOP,BOTTOMSATA_2SAME ?

* ?=4X_DIELECTRICUSB3_2OTHER

PCH Constraints 1SYNC_DATE=12/10/2012SYNC_MASTER=SIDLE_J45

USB3_EXTA_R2D_C_PUSB3_R2DUSB_85D

USB_85D USB3_R2D USB3_EXTA_R2D_C_NUSB_85D USB3_D2RUSB3_EXTB_RX USB3_EXTB_D2R_P

USB3_EXTB_RX USB3_D2RUSB_85D USB3_EXTB_D2R_N

NC_USB3_EXTD_R2D_CNUSB3_R2DUSB_85D

USB_85D USB3_R2DUSB3_EXTA_TX USB3_EXTA_R2D_P

NC_USB_SDPUSB_NC USBUSB_85D

SYSCLK_CLK32K_RTCSYSCLK_CLK32K_RTC CLK_SLOWCLK_SLOW_45S

SYSCLK_CLK25M_SBSYSCLK_CLK25M_SB CLK_25MCLK_25M_45SSYSCLK_CLK25M_SB_RCLK_25MCLK_25M_45S

CLK_25M SYSCLK_CLK25M_CAMERASYSCLK_CLK25M_CAM CLK_25M_45S

NC_USB3 USB3_D2R NC_USB3_EXTD_D2RNUSB_85D

USB_85DUSB_NC USB NC_USB_6P

SYSCLK_CLK25M_TBT_RCLK_25MCLK_25M_45S

USB3_EXTB_TX USB3_EXTB_R2D_NUSB3_R2DUSB_85D

USB3_EXTA_RX USB_85D USB3_D2R USB3_EXTA_D2R_N

SYSCLK_CLK25M_TBT CLK_25M SYSCLK_CLK25M_TBTCLK_25M_45S

USB_85D USB3_EXTA_D2R_C_PUSB3_D2R

USB_85D USB3_R2D USB3_EXTB_R2D_C_N

USB_85DUSB3_EXTA_TX USB3_EXTA_R2D_NUSB3_R2D

USB_85D USB3_D2R USB3_EXTA_D2R_C_N

USB3_R2D NC_USB3_EXTD_R2D_CPUSB_85D

USB_85DNC_USB3 USB3_D2R NC_USB3_EXTD_D2RPUSB_85D USB3_R2D NC_USB3_EXTC_R2D_CN

USB3_R2D NC_USB3_EXTC_R2D_CPUSB_85D

USB_85D NC_USB3_EXTC_D2RNUSB3_D2RNC_USB3

USB_85DNC_USB3 USB3_D2R NC_USB3_EXTC_D2RP

USB_85D USB3_R2D USB3_EXTB_R2D_C_P

USB_85D USB3_D2R USB3_EXTB_D2R_C_P

USB3_EXTA_D2R_PUSB3_D2RUSB_85DUSB3_EXTA_RX

USB_BT USB USB_BT_PUSB_85D

USBUSB_85DUSB_NC NC_USB_EXTDN

USB_85D USB NC_USB_7NUSB_NC

PCH_USB_RBIAS PCH_USB_RBIAS USB_RBIAS PCH_USB_RBIAS

USB_85DUSB_NC USB NC_USB_IRP

USB_85DUSB_NC USB NC_USB_EXTDP

USB_85DUSB3_EXTB_TX USB3_R2D USB3_EXTB_R2D_PUSB3_D2R USB3_EXTB_D2R_C_NUSB_85D

USBUSB_85D USB_BT_CONN_NUSB USB_BT_CONN_PUSB_85D

USB_85D USBUSB_BT USB_BT_N

USB_85D USBUSB_SMC NC_USB_SMCN

NC_USB_EXTCNUSBUSB_85DUSB_NC

NC_USB_SMCPUSBUSB_SMC USB_85D

USBUSB_NC NC_USB_SDNUSB_85D

NC_SATA_A_D2RPSATA_85D SATA_D2R

NC_SATA_A_R2D_CPSATA_85D SATA_R2D

NC_SATA_B_D2RPSATA_D2RSATA_85D

NC_SATA_B_R2D_CNSATA_R2DSATA_85D

NC_SATA_A_D2RNSATA_85D SATA_D2R

NC_SATA_A_R2D_CNSATA_85D SATA_R2D

USB_EXTA USB_85D USB_EXTA_PUSBUSB_EXTA_NUSBUSB_EXTA USB_85D

CPU_45S SMC_DEBUGPRT_RX_LCPU_ITPSMC_DEBUGPRT_TX_LCPU_45S CPU_ITP

USB_EXTA USB_85D USB_EXTA_MUXED_NUSB

NC_SATA_B_R2D_CPSATA_R2DSATA_85D

USB_EXTA USB_LT1_NUSBUSB_85D

NC_SATA_B_D2RNSATA_D2RSATA_85D

SATA_RCOMP PCH_SATA_RCOMPSATA_45SEPCH_SATA_RCOMP

USB_EXTA USB_85D USB_EXTA_MUXED_PUSB

USB_EXTA USB_LT1_PUSBUSB_85D

USBUSB_NC NC_USB_EXTCPUSB_85D

USBUSB_85DUSB_NC NC_USB_IRN

USB_EXTB_PUSBUSB_85DUSB_EXTB

USB_EXTB USB_85D USB USB_EXTB_N

USB_85DUSB_NC USB NC_USB_7PNC_USB_6NUSB_85D USBUSB_NC

USB_85D USB USB_TPAD_NUSB_TPAD

USB_TPAD_PUSB_TPAD USBUSB_85D

USBUSB_85D USB_TPAD_R_NUSB_85D USB USB_TPAD_R_P

<BRANCH>

<SCH_NUM>

<E4LABEL>

112 OF 118

76 OF 82

13 38

13 38

13 69 72

13 69 72

13 73

38

13 73

11 19

11 19

11

19 37

13 73

13 73

28

69 72

13 38

19 28

13 69

38

13 73

13 73

13 73

13 73

13 73

13 73

13 69

13 38

13 34

13 73

13 73

13

13 73

13 73

69 72

34 72

34 72

13 34

73

13 73

73

13 73

11 73

11 73

11 73

11 73

11 73

11 73

13 38

13 38

38 41 42

38 41 42

38

11 73

38

11 73

11

38

38

13 73

13 73

13 69 72

13 69 72

13 73

13 73

13 39 72

13 39 72

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mMINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET



Apple Inc.


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HD Audio Interface Constraints

SPI Interface Constraints

PCH Single Net Constraints

PCI-Express

PCH Net PropertiesLPC Bus ConstraintsPCH Net Properties


SMBus Interface Constraints

SPACING

NET_TYPE

PHYSICAL

NET_TYPE

PHYSICAL SPACINGELECTRICAL_CONSTRAINT_SET

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I275

I276

I281

I282

I293

I298

I299

I300

I303

I304

I307

I308

I313

I314

I315

I316

I317

I318

I319

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I341

I342

I343

I344

I353

I354

I358

I359

I363

I364

I368

I369

I370

I371

I372

I373

I374

I375

I376

I377

I380

I381

I382

I383

I386

I387

I390

I391

I392

I395

8 MIL*CLK_LPC ?

=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARD=45_OHM_SECLK_LPC_45S =45_OHM_SE

=45_OHM_SE =STANDARD* =STANDARDLPC_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE

=STANDARD=45_OHM_SE* =STANDARD=45_OHM_SE =45_OHM_SE =45_OHM_SESMB_45S

?=2x_DIELECTRIC*SMB

LPC ?* 6 MIL

=10X_DIELECTRIC ?TOP,BOTTOMPCIE_TXRX

?PCH_SE =3x_DIELECTRICTOP,BOTTOM

TOP,BOTTOM =4X_DIELECTRIC ?PCIE_2SAME

=6X_DIELECTRICPCIE_2OTHER ?TOP,BOTTOM

=10X_DIELECTRICTOP,BOTTOM ?PCIECLK_2OTHER

=10X_DIELECTRICPCIE_2CLK ?TOP,BOTTOM

=45_OHM_SE=45_OHM_SE=45_OHM_SEPCH_45S =STANDARD=STANDARD* =45_OHM_SE

PCH_SE * ?=2x_DIELECTRIC

PCIE_2SAME ?* =2X_DIELECTRIC

=85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFFCLK_PCIE_85D =85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF=85_OHM_DIFFPCIE_85D =85_OHM_DIFF =85_OHM_DIFF

PCIE_TXRX * ?=6X_DIELECTRIC

=7X_DIELECTRIC* ?PCIECLK_2OTHER

PCIE_2CLK * =7X_DIELECTRIC ?

* ?PCIE_2OTHER =4X_DIELECTRIC

=SAME *PCIE_* PCIE_2SAME

PCIE_D2R *PCIE_R2D PCIE_TXRX

PCIECLK_2OTHERCLK_PCIE **

PCIE_2CLKPCIE_* *CLK_*

* *PCIE_* PCIE_2OTHER

=3x_DIELECTRIC ?SPI3X *

=2x_DIELECTRIC* ?HDA

=45_OHM_SE =45_OHM_SESPI_45S =45_OHM_SE =45_OHM_SE =STANDARD* =STANDARD

8 MIL*SPI ?


PCH Constraints 2

=45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD=45_OHM_SE =STANDARD*HDA_45S

SMBUS_PCH_CLK SMB SMBUS_PCH_CLKSMB_45S

TPAD_SPI_MOSISPI_45S SPISPI_TPAD

PCH_SEPCH_45S PM_PWRBTN_LPCH_PM_NET

HDAHDA_SDIN0 HDA_45S HDA_SDIN0

CLK_PCIEPCIE_CLK100M_PCH PCIE_CLK100M_PCH_PCLK_PCIE_85D

PCH_PM_NET PCH_SEPCH_45S PCH_RCIN_L

HDAHDA_45S HDA_BIT_CLK_R

USB3_SD_R2D_C_NUSB3_85D USB3_R2DUSB3_SD_R2D

USB3_D2RUSB3_85DUSB3_SD_D2R USB3_SD_D2R_PUSB3_SD_D2R_NUSB3_D2RUSB3_85DUSB3_SD_D2R

PCIE_D2RPCIE_AP_D2R PCIE_85D PCIE_AP_D2R_N

PCH_45S PCH_SE PM_PCH_PWROKPCH_PM_NET

PCIE_R2DPCIE_85D PCIE_AP_R2D_PI_P

PCIE_CLK100M_S2 CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_CAMERA_NCLK_PCIE_85D CLK_PCIE PCIE_CLK100M_CAMERA_PPCIE_CLK100M_S2

CLK_PCIE_85DPCIE_CLK100M_FW PCIE_CLK100M_SSD_PCLK_PCIE

PCIE_CLK100M_AP CLK_PCIE PCIE_CLK100M_AP_NPCIE_85D

PCIE_CLK100M_AP_CONN_NCLK_PCIEPCIE_85D

PCIE_CLK100M_AP PCIE_85D CLK_PCIE PCIE_CLK100M_AP_P

CLK_PCIE_85D CLK_PCIE PCIE_CLK100M_SSD_N

CLK_PCIECLK_PCIE_85D PCIE_CLK100M_CAMERA_C_PCLK_PCIECLK_PCIE_85D PCIE_CLK100M_CAMERA_C_N

HDAHDA_45S HDA_BIT_CLKHDA_BIT_CLK

PCH_SE PCH_INTRUDER_LPCH_45SPCH_PM_NET

PCH_SE PCH_INTVRMEN_LPCH_45SPCH_PM_NET

PCIE_CLK100M_AP_CONN_PCLK_PCIEPCIE_85D

PCH_SE PCH_DSWVRMENPCH_PM_NET PCH_45S

HDAHDA_45S HDA_RST_R_LHDAHDA_RST_L HDA_45S HDA_RST_L

PCIE_85D PCIE_R2D PCIE_AP_R2D_PI_N

PCIE_85D PCIE_R2D PCIE_AP_R2D_C_N

PCH_SE PM_SYSRST_LPCH_45SPCH_PM_NET

PCH_SE PM_RSMRST_LPCH_45SPCH_PM_NET

PCH_PM_NET PCH_45S PCH_SE PCH_SRTCRST_L

CLK_PCIEPCIE_85DPCIE_CLK100M_ENET PCIE_CLK100M_SD_N

PCIE_D2RPCIE_AP_D2R PCIE_85D PCIE_AP_D2R_P

PCIE_85D PCIE_R2D PCIE_AP_R2D_C_P

HDA_45S HDA HDA_SYNC_R

SMB SML_PCH_1_DATASMBUS_PCH_1_DATA SMB_45S

PCIE_CAMERA_D2R_C_PPCIE_D2RPCIE_85D

PCIE_R2DPCIE_85D PCIE_CAMERA_R2D_C_PPCIE_CAMERA_R2D PCIE_CAMERA_R2D_NPCIE_R2DPCIE_85D

PCIE_D2RPCIE_85D PCIE_AP_D2R_PI_PPCIE_AP_D2R_PI_NPCIE_D2RPCIE_85D

PCIE_CAMERA_D2R_PPCIE_85DPCIE_CAMERA_D2R PCIE_D2R

CLK_PCIEPCIE_CLK100M PCH_CLK33M_PCIINCPU_45S

CLK_PCIEPCIE_CLK100M PCH_CLK14P3M_REFCLKCPU_45S

CLK_PCIEPCIE_CLK100M_PCH PCIE_CLK100M_PCH_NCLK_PCIE_85D

CLK_PCIEPCIE_CLK100M_TBT PCIE_CLK100M_TBT_NCLK_PCIE_85D

CLK_PCIE PCIE_CLK100M_SD_PPCIE_85DPCIE_CLK100M_ENET

CLK_PCIE PCH_CLK100M_SATA_NPCIE_CLK100M_SATA PCIE_85D

CLK_PCIEPCIE_CLK100M_SATA PCIE_85D PCH_CLK100M_SATA_PCLK_PCIEPCIE_CLK100M_DOT PCH_CLK96M_DOT_NCLK_PCIE_85D

CLK_PCIEPCIE_CLK100M_DOT PCH_CLK96M_DOT_PCLK_PCIE_85D

CLK_PCIEPCIE_CLK100M_TBT PCIE_CLK100M_TBT_PCLK_PCIE_85D

CLK_PCIEPCIE_CLK100M PCH_CLK33M_PCIOUTCPU_45S

CLK_LPC NC_LPC_CLK33M_LPCPLUS_RCLK_LPC_45S

CLK_LPCPCH_LPC_CLK0 LPC_CLK33M_SMCCLK_LPC_45S

CLK_LPC LPC_CLK33M_SMC_RCLK_LPC_45S

PCIE_D2RPCIE_85D PCIE_CAMERA_D2R_C_N

PCIE_CAMERA_D2R_NPCIE_85DPCIE_CAMERA_D2R PCIE_D2R

PCIE_R2DPCIE_85D PCIE_CAMERA_R2D_C_N

PCIE_CAMERA_R2D PCIE_R2DPCIE_85D PCIE_CAMERA_R2D_P

LPCLPC_AD LPC_45S LPC_AD<3..0>

SPISPI_45S SPI_MOSI_RSPI_MLB

SPISPI_45S SPI_MOSISPI_MLB

HDA_SYNC HDAHDA_45S HDA_SYNC

USB3_SD_R2D USB3_85D USB3_R2D USB3_SD_R2D_C_P

HDA_45S HDA HDA_SDOUT_R

SPI_MLB SPI_45S SPI SPI_MISO_R

PCH_45S PCH_SE PM_DSW_PWRGDPCH_PM_NET

PCH_SE PM_PCH_SYS_PWROKPCH_45SPCH_PM_NET

PM_PCH_PWROKPCH_45S PCH_SEPCH_PM_NET

SPI_MLB SPI_45S SPI SPI_MISO

SPI_45S SPISPI_TPAD TPAD_SPI_MISOSPI_45SSPI_TPAD_CS TPAD_SPI_CS_LSPI

TPAD_SPI_SCLKSPI_45SSPI_TPAD SPI

PCIE_AP_R2D PCIE_R2DPCIE_85D PCIE_AP_R2D_NPCIE_AP_R2D PCIE_85D PCIE_R2D PCIE_AP_R2D_P

SPI_45S SPI3X SPI_SMC_CS_LSPI_MLB

SPI3X SPI_ALT_IO1_MISOSPI_MLB SPI_45S

SPI3X SPI_MLB_IO1_MISOSPI_45SSPI_MLB

SPI3X SPI_SMC_MISOSPI_MLB SPI_45S

SPI3X SPI_ALT_IO0_MOSISPI_MLB SPI_45S

SPI3X SPI_MLB_IO0_MOSISPI_45SSPI_MLB

SPI3XSPI_MLB SPI_SMC_MOSISPI_45S

SPI3X SPI_IO<2>SPI_45SSPI_MLB_IO2

SPI3XSPI_MLB_IO2 SPI_MLB_IO2_WP_LSPI_45S

SPI3X SPI_ALT_IO2_WP_LSPI_MLB_IO2 SPI_45S

SPI3X SPI_IO<3>SPI_MLB_IO3 SPI_45S

SPI3XSPI_MLB_IO3 SPI_45S SPI_MLB_IO3_HOLD_LSPI3XSPI_MLB_IO3 SPI_ALT_IO3_HOLD_LSPI_45S

SPI_MLB SPI_45S SPI SPI_CLK_R

PCH_PM_NET PM_THRMTRIP_L_RPCH_SEPCH_45S

PCH_PCIE_WAKE PCH_SEPCH_45S PCIE_WAKE_L

SPI3X SPI_ALT_CLKSPI_MLB SPI_45S

SPI_MLB SPI3X SPI_MLB_CLKSPI_45S

SPI_45S SPI3XSPI_MLB SPI_MLB_CS_LSPI_45S SPI SPI_CS0_R_LSPI_MLB

SPI_45S SPI SPI_CS0_LSPI_MLB

SPI_MLB SPI_45S SPI3X SPI_ALT_CS_L

SPI_MLB SPI3X SPI_SMC_CLKSPI_45S

SPI_MLB SPI_45S SPI SPI_CLK

SMBSMB_45SSMBUS_PCH_1_CLK SML_PCH_1_CLKSML_PCH_0_DATASMBUS_PCH_0_DATA SMB_45S SMB

SMBSMB_45S SML_PCH_0_CLKSMBUS_PCH_0_CLK

SMB SMBUS_PCH_DATASMB_45SSMBUS_PCH_DATA

LPC_FRAME_L LPCLPC_45S LPC_FRAME_L

HDAHDA_45SHDA_SDIN0_R CS4208_HDA_SDOUT0_RHDA_SDOUT HDA_45S HDA HDA_SDOUT

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Memory to GND Spacing

Memory to Power Spacing

DDR3 (Memory Down):

SOURCE: Double checked with Doc#486985 Chief River SFF Platform DG: Memory Down

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

NET_TYPE

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.

SOURCE: Need to re-confirm CRW DG for memory down (Intel not yet provided)

Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

Spacing Rule Sets

PHYSICAL SPACING

Memory Net PropertiesELECTRICAL_CONSTRAINT_SET

Memory Bus Constraints

Memory Bus Spacing Group Assignments

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].

DQ signals should be matched within 0.508mm of associated DQS pair

I101

I103

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I109

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I111

I112

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MEM_2OTHER* *MEM_*_DATA_*

* * MEM_2OTHERMEM_*_DQS_*

* MEM_2OTHER*MEM_CMD

* MEM_DQS2OWNDATAMEM_A_DQS_7 MEM_A_DATA_7

MEM_B_DQS_1 MEM_DQS2OWNDATA*MEM_B_DATA_1

* MEM_DQS2OWNDATAMEM_B_DQS_3 MEM_B_DATA_3

*MEM_B_DQS_5 MEM_B_DATA_5 MEM_DQS2OWNDATA


*MEM_CLK MEM_CLK MEM_CLK2CLK

*MEM_CTRL MEM_CMD2CTRLMEM_CMD

TOP,BOTTOMMEM_2OTHER ?=10x_DIELECTRIC

MEM_2GND TOP,BOTTOM ?=4x_DIELECTRIC

TOP,BOTTOMMEM_2PWR ?=4x_DIELECTRIC

MEM_CMD2CTRL TOP,BOTTOM ?=5x_DIELECTRIC

MEM_DQS2OWNDATA TOP,BOTTOM ?=5x_DIELECTRIC

=37_OHM_SE=37_OHM_SE =STANDARD* =STANDARD=37_OHM_SE =37_OHM_SEMEM_37S

=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFFMEM_72D * =72_OHM_DIFF =72_OHM_DIFF

=45_OHM_SEMEM_45S =45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARD

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF*MEM_85D =85_OHM_DIFF

=40_OHM_SE =STANDARD=40_OHM_SE =40_OHM_SE =40_OHM_SEMEM_40S =STANDARD*

?=2x_DIELECTRIC*MEM_2GND

MEM_2OTHER =6x_DIELECTRIC ?*

*MEM_CLK * MEM_2OTHER

MEM_DQS2OWNDATA*MEM_A_DATA_3MEM_A_DQS_3

?=8x_DIELECTRICTOP,BOTTOMMEM_CLK2CLK

=5x_DIELECTRICTOP,BOTTOM ?MEM_CTRL2CTRL

=5x_DIELECTRICTOP,BOTTOM ?MEM_DATA2SELF

MEM_CLK2CLK * ?=4x_DIELECTRIC

MEM_DQS2OWNDATAMEM_A_DATA_0 *MEM_A_DQS_0

TOP,BOTTOMMEM_CMD2CMD ?=5x_DIELECTRIC

*MEM_CTRL * MEM_2OTHER



*MEM_A_DQS_5 MEM_A_DATA_5 MEM_DQS2OWNDATA

* MEM_DQS2OWNDATAMEM_A_DQS_4 MEM_A_DATA_4

MEM_A_DQS_6 * MEM_DQS2OWNDATAMEM_A_DATA_6

MEM_DQS2OWNDATA*MEM_B_DQS_0 MEM_B_DATA_0

MEM_B_DATA_2 * MEM_DQS2OWNDATAMEM_B_DQS_2

*MEM_B_DQS_4 MEM_B_DATA_4 MEM_DQS2OWNDATA


*MEM_CMDMEM_CMD MEM_CMD2CMD

MEM_DATA2SELF=SAMEMEM_*_DATA_* *

MEM_2OTHERMEM*MEM_*MEM_*

MEM_PWR MEM_* * MEM_2PWR

* *MEM_PWR DEFAULT

GND *MEM_* MEM_2GND

=2x_DIELECTRICMEM_CMD2CTRL ?*

MEM_CMD2CMD * ?=2x_DIELECTRIC

=2x_DIELECTRIC ?*MEM_CTRL2CTRL

=4x_DIELECTRIC ?MEM_2OTHERMEM *

?=2x_DIELECTRICMEM_DQS2OWNDATA *

MEM_DATA2SELF =2x_DIELECTRIC* ?

=2x_DIELECTRIC* ?MEM_2PWR

MEM_CTRL2CTRL*MEM_CTRLMEM_CTRL

?=8x_DIELECTRICTOP,BOTTOMMEM_2OTHERMEM

Memory ConstraintsSYNC_MASTER=SIDLE_J45 SYNC_DATE=12/10/2012

MEM_A_DQS_2 MEM_A_DQS_N<2>MEM_A_DQS2 MEM_85D

MEM_A_DQS4 MEM_A_DQS_4 MEM_A_DQS_N<4>MEM_85D

MEM_A_DQS_7MEM_A_DQS7 MEM_A_DQS_N<7>MEM_85D

MEM_B_DATA_1 MEM_B_DQ<15..8>MEM_B_DATA_1MEM_45S

MEM_B_DATA_2 MEM_B_DATA_2 MEM_B_DQ<23..16>MEM_45S

MEM_45S MEM_B_DATA_4MEM_B_DATA_4 MEM_B_DQ<39..32>MEM_B_DATA_5MEM_B_DATA_5 MEM_B_DQ<47..40>MEM_45S

MEM_A_DQS_0 MEM_A_DQS_P<0>MEM_A_DQS0 MEM_85D


MEM_CMDMEM_40S MEM_B_A<15..0>MEM_B_CMD

MEM_40SMEM_B_CMD MEM_CMD MEM_B_BA<2..0>

MEM_45S MEM_B_DQ<7..0>MEM_B_DATA_0MEM_B_DATA_0

MEM_72D MEM_CLK MEM_A_CLK_P<0>MEM_A_CLK0

MEM_72D MEM_CLK MEM_A_CLK_N<0>MEM_A_CLK0

MEM_72D MEM_CLK MEM_A_CLK_P<1>MEM_A_CLK1

MEM_40S MEM_CTRL MEM_A_CKE<0>MEM_A_CNTL0

MEM_CTRLMEM_40S MEM_A_CS_L<0>MEM_A_CNTL0

MEM_CMDMEM_40S MEM_A_A<15..0>MEM_A_CMD

MEM_CTRL MEM_A_ODT<1>MEM_A_CNTL1 MEM_40S

MEM_CTRLMEM_40S MEM_A_ODT<0>MEM_A_CNTL0

MEM_A_BA<2..0>MEM_40S MEM_CMDMEM_A_CMD

MEM_A_CNTL1 MEM_CTRLMEM_40S MEM_A_CS_L<1>

MEM_B_DQS_2MEM_B_DQS2 MEM_B_DQS_N<2>MEM_85D

MEM_B_DQS_4MEM_B_DQS4 MEM_B_DQS_P<4>MEM_85D




MEM_A_DQS_3MEM_A_DQS3 MEM_85D MEM_A_DQS_N<3>

MEM_A_CNTL1 MEM_CTRLMEM_40S MEM_A_CKE<1>

MEM_CLKMEM_72D MEM_B_CLK_P<0>MEM_B_CLK0


MEM_B_DQS6 MEM_B_DQS_6 MEM_B_DQS_N<6>MEM_85D

MEM_B_DQS6 MEM_B_DQS_6 MEM_B_DQS_P<6>MEM_85D

MEM_B_DQS3 MEM_B_DQS_N<3>MEM_B_DQS_3MEM_85D




MEM_B_DQS0 MEM_B_DQS_0 MEM_B_DQS_N<0>MEM_85D



MEM_CTRLMEM_B_CNTL0 MEM_40S MEM_B_CS_L<0>

MEM_CTRLMEM_40S MEM_B_ODT<0>MEM_B_CNTL0

MEM_B_CLK1 MEM_CLKMEM_72D MEM_B_CLK_P<1>MEM_72DMEM_B_CLK0 MEM_B_CLK_N<0>MEM_CLK

MEM_72D MEM_CLK MEM_A_CLK_N<1>MEM_A_CLK1


MEM_A_DQS_P<4>MEM_A_DQS_4MEM_A_DQS4 MEM_85D

MEM_A_DATA_4MEM_A_DATA_4 MEM_A_DQ<39..32>MEM_45S


MEM_A_DATA_7 MEM_A_DQ<63..56>MEM_A_DATA_7 MEM_45S


MEM_A_DQS_3 MEM_A_DQS_P<3>MEM_85DMEM_A_DQS3

MEM_A_DQS5 MEM_A_DQS_5 MEM_A_DQS_N<5>MEM_85D

MEM_A_DQS_6MEM_A_DQS6 MEM_A_DQS_P<6>MEM_85D

MEM_B_DQ<55..48>MEM_B_DATA_6 MEM_B_DATA_6MEM_45S

MEM_B_DATA_7 MEM_B_DATA_7 MEM_B_DQ<63..56>MEM_45S



MEM_PWR PP1V35_S3_MEM

PP0V75_S3_MEM_VREFDQ_AMEM_PWR


MEM_CMD MEM_A_CAS_LMEM_A_CMD MEM_40S

MEM_A_RAS_LMEM_CMDMEM_A_CMD MEM_40S

MEM_CMDMEM_A_CMD MEM_A_WE_LMEM_40S






MEM_A_DQS_2MEM_A_DQS2 MEM_A_DQS_P<2>MEM_85D


MEM_CTRLMEM_B_CNTL1 MEM_40S MEM_B_CS_L<1>

MEM_40SMEM_B_CMD MEM_CMD MEM_B_RAS_LMEM_40SMEM_B_CMD MEM_CMD MEM_B_CAS_LMEM_40S MEM_CMDMEM_B_CMD MEM_B_WE_L

MEM_45SMEM_B_DATA_3 MEM_B_DQ<31..24>MEM_B_DATA_3

MEM_CTRLMEM_B_CNTL1 MEM_40S MEM_B_ODT<1>

MEM_CTRLMEM_B_CNTL1 MEM_40S MEM_B_CKE<1>MEM_B_CNTL0 MEM_40S MEM_CTRL MEM_B_CKE<0>MEM_B_CLK1 MEM_72D MEM_CLK MEM_B_CLK_N<1>

MEM_PWR PP0V75_S3_MEM_VREFCA

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Only used on dual-port hosts.


NET_TYPE

PHYSICAL SPACING

Thunderbolt IC Net Properties

Only used on hosts supporting Thunderbolt video-in

SPACING

Thunderbolt SPI Signal Constraints

TBT_DP Interface Constraints

NET_TYPE

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

Thunderbolt/DP Connector Signal Constraints

DisplayPort Signal ConstraintsNOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET PHYSICAL

Thunderbolt/DP Net Properties

I308

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I341

I342

I343

SYNC_MASTER=SIDLE_J45 SYNC_DATE=12/10/2012

Thunderbolt Constraints

=4X_DIELECTRIC* ?TBTDP_2OTHER

TBTDP_TXRX ?* =6X_DIELECTRIC

?TBTDP_2SAME * =3X_DIELECTRIC

?* =2x_DIELECTRICTBT_SPI

TBTDP_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF* =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

TBTDP_TXRXTBTDP_D2RTBTDP_R2D *

TBTDP_2OTHERTBTDP_* **

=6X_DIELECTRIC ?TOP,BOTTOMTBTDP_2OTHER

=85_OHM_DIFF=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF* =85_OHM_DIFF =85_OHM_DIFFTBTDP_85D

TOP,BOTTOMTBTDP_2SAME ?=4x_DIELECTRIC

TBTDP_* =SAME * TBTDP_2SAME

=10X_DIELECTRICTBTDP_TXRX TOP,BOTTOM ?

=45_OHM_SE =45_OHM_SE=45_OHM_SE=45_OHM_SETBT_SPI_45S * =STANDARD=STANDARDTBTDP_R2D TBT_A_R2D_N<1..0>TBT_A_R2D TBTDP_85D

TBT_A_R2D TBT_A_R2D_P<1..0>TBTDP_R2DTBTDP_85D

DP_85D DP_TBTPA_AUXCH_PTBT_A_AUXCH

DP_85D DP_TBTPA_AUXCH_C_NTBT_A_AUXCH

TBTDP_85D TBTDP_D2R TBT_A_D2R_P<0>TBT_A_D2R0

TBTDP_85D TBT_A_D2R_C_N<0>TBT_A_D2R0 TBTDP_D2R

DP_TBTPA_ML_N<3>DISPLAYPORTDP_85DDP_TBTPA_ML

DP_85D DISPLAYPORTDP_TBTPA_ML DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_N<1>DISPLAYPORTDP_85DDP_A_LSX_ML

TBTDP_R2D TBT_A_R2D_C_N<1..0>TBT_A_R2D TBTDP_85D

DP_TBTPA_ML_P<1>DISPLAYPORTDP_85DDP_A_LSX_MLDP_TBTPA_ML_N<1>DP_85D DISPLAYPORTDP_A_LSX_MLDP_A_LSX_ML_P<1>DP_85D DISPLAYPORTDP_A_LSX_ML

DP_TBTPA_ML_C_P<1>DP_85D DISPLAYPORTDP_A_LSX_ML

TBTDP_R2D TBT_A_R2D_C_P<1..0>TBT_A_R2D TBTDP_85D

DP_85D DISPLAYPORTDP_TBTPA_ML DP_TBTPA_ML_C_P<3>

TBTDP_D2RTBTDP_85D TBT_A_D2R_C_P<1>TBT_A_D2R1

DP_85D DP_TBTPA_AUXCH_C_PTBT_A_AUXCH

TBTDP_D2R TBT_A_D2R1_AUXDDC_NTBTDP_85DTBT_A_D2R1

TBTDP_D2R TBT_A_D2R1_AUXDDC_PTBT_A_D2R1 TBTDP_85D

TBTDP_D2R TBT_A_D2R_N<1>TBT_A_D2R1 TBTDP_85D

TBTDP_D2RTBTDP_85D TBT_A_D2R_C_N<1>TBT_A_D2R1

DISPLAYPORT DP_TBTSRC_ML_C_P<3..0>DP_85DDP_TBTSRC_ML_C_N<3..0>DISPLAYPORTDP_85DDP_TBTSRC_AUXCH_C_PDISPLAYPORTDP_85D

DISPLAYPORT DP_TBTSRC_AUXCH_C_NDP_85D

TBT_SPI TBT_SPI_CLKTBT_SPI_CLK TBT_SPI_45STBT_SPI_MOSITBT_SPI_MOSI TBT_SPITBT_SPI_45S

TBT_SPI TBT_SPI_CS_LTBT_SPI_CS_L TBT_SPI_45S

TBT_SPI_MISOTBT_SPI_MISO TBT_SPITBT_SPI_45S

TBT_A_D2R_P<1>TBTDP_D2RTBTDP_85DTBT_A_D2R1

TBTDP_85D TBTDP_D2R TBT_A_D2R_N<0>TBT_A_D2R0

TBT_A_D2R_C_P<0>TBTDP_D2RTBTDP_85DTBT_A_D2R0

DP_85D DISPLAYPORT DP_A_LSX_ML_N<1>DP_A_LSX_ML

DP_TBTPB_ML_C_N<1>DISPLAYPORTDP_85DDP_B_LSX_MLDP_TBTPB_ML_P<1>DISPLAYPORTDP_85DDP_B_LSX_MLDP_TBTPB_ML_N<1>DISPLAYPORTDP_85DDP_B_LSX_MLDP_B_LSX_ML_P<1>DISPLAYPORTDP_85DDP_B_LSX_MLDP_B_LSX_ML_N<1>DISPLAYPORTDP_85DDP_B_LSX_ML

DP_TBTPB_ML DP_TBTPB_ML_C_P<3>DISPLAYPORTDP_85D

DP_TBTPB_ML DP_TBTPB_ML_C_N<3>DISPLAYPORTDP_85D

DP_TBTPB_ML DP_TBTPB_ML_P<3>DISPLAYPORTDP_85D

TBT_B_D2R0 TBT_B_D2R_C_P<0>TBTDP_85D TBTDP_D2R

DP_TBTPB_ML DP_TBTPB_ML_N<3>DISPLAYPORTDP_85D

TBT_B_D2R0 TBT_B_D2R_P<0>TBTDP_D2RTBTDP_85D

TBT_B_D2R0 TBT_B_D2R_N<0>TBTDP_D2RTBTDP_85D

TBT_B_D2R1 TBT_B_D2R_C_N<1>TBTDP_85D TBTDP_D2R

TBT_B_D2R1 TBT_B_D2R_C_P<1>TBTDP_85D TBTDP_D2R

TBT_B_R2D TBT_B_R2D_C_N<1..0>TBTDP_R2DTBTDP_85D

TBT_B_D2R1 TBT_B_D2R_P<1>TBTDP_D2RTBTDP_85D

TBT_B_D2R1 TBT_B_D2R_N<1>TBTDP_D2RTBTDP_85D

TBT_B_D2R1 TBT_B_D2R1_AUXDDC_PTBTDP_85D TBTDP_D2R

TBT_B_D2R1 TBT_B_D2R1_AUXDDC_NTBTDP_85D TBTDP_D2R

TBT_B_AUXCH DP_TBTPB_AUXCH_C_PDP_85D

TBT_B_AUXCH DP_TBTPB_AUXCH_C_NDP_85D

TBT_B_AUXCH DP_TBTPB_AUXCH_PDP_85D

TBT_B_AUXCH DP_TBTPB_AUXCH_NDP_85D

DP_TBTPB_ML_C_P<1>DISPLAYPORTDP_85DDP_B_LSX_ML

TBT_B_R2D TBT_B_R2D_P<1..0>TBTDP_R2DTBTDP_85D

TBT_B_D2R0 TBT_B_D2R_C_N<0>TBTDP_85D TBTDP_D2R

TBT_B_R2D TBT_B_R2D_N<1..0>TBTDP_R2DTBTDP_85D

TBT_B_R2D TBT_B_R2D_C_P<1..0>TBTDP_R2DTBTDP_85D

DP_85D DP_TBTPA_AUXCH_NTBT_A_AUXCH

DISPLAYPORTDP_85DDP_TBTPA_ML DP_TBTPA_ML_P<3>

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Memory Bus Constraints

NET_TYPE

PHYSICAL SPACING

Memory to GND Spacing

Memory to Power Spacing

Spacing Rule Sets


MIPI Interface Constraints

Memory Bus Spacing Group Assignments

Camera Net Properties

I101

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Camera ConstraintsSYNC_MASTER=SIDLE_J45 SYNC_DATE=12/10/2012

S2_MEM_DQS1 S2_DQS2OWNDATAS2_MEM_DATA1 *

S2MEM_2OTHER * ?=6x_DIELECTRIC

?*S2MEM_2GND =2x_DIELECTRIC

MIPI_2OTHER ?* =4X_DIELECTRIC

MIPI_2CLK * =6X_DIELECTRIC ?

MIPICLK_2OTHER * =7X_DIELECTRIC ?

* * MIPI_2OTHERMIPI_DATA

* MIPI_2CLKCLK_MIPIMIPI_DATA

*CLK_MIPI * MIPICLK_2OTHER

=45_OHM_SE =STANDARD=45_OHM_SE =STANDARD=45_OHM_SE*S2_MEM_45S =45_OHM_SE

* =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFFS2_MEM_85D

*MIPI_85D =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

GND S2MEM_2GNDS2_MEM_* *

S2_2OTHERMEM*S2_MEM_*S2_MEM_*

S2_MEM_CTRL S2_MEM_CTRL S2_CTRL2CTRL*

S2_MEM_CMD S2_CMD2CMDS2_MEM_CMD *

S2_MEM_CLK * S2MEM_2OTHER*

S2MEM_2OTHERS2_MEM_CTRL * *

S2MEM_2OTHER**S2_MEM_CMD

S2_MEM_DQS0 S2_DQS2OWNDATAS2_MEM_DATA0 *

S2_MEM_PWR ** DEFAULT

S2MEM_2PWRS2_MEM_*S2_MEM_PWR *

=SAME * S2_DATA2SELFS2_MEM_DATA*

S2MEM_2OTHERS2_MEM_DATA* * *

S2_MEM_DQS* ** S2MEM_2OTHER

S2_MEM_CMD S2_MEM_CTRL S2_CMD2CTRL*

=2x_DIELECTRICS2_DATA2SELF ?*

?* =2x_DIELECTRICS2MEM_2PWR

=2x_DIELECTRIC ?*S2_DQS2OWNDATA

S2_2OTHERMEM =4x_DIELECTRIC* ?

* ?S2_CMD2CTRL =2x_DIELECTRIC

?*S2_CTRL2CTRL =2x_DIELECTRIC

=2x_DIELECTRIC ?*S2_CMD2CMD

=4x_DIELECTRICTOP,BOTTOM ?S2_CTRL2CTRL

S2MEM_2GND TOP,BOTTOM =4x_DIELECTRIC ?

S2_2OTHERMEM ?=6x_DIELECTRICTOP,BOTTOM

=4x_DIELECTRICTOP,BOTTOM ?S2_CMD2CMD

TOP,BOTTOM ?S2_DQS2OWNDATA =4x_DIELECTRIC

TOP,BOTTOM =4x_DIELECTRIC ?S2_DATA2SELF

MIPI_2OTHER TOP,BOTTOM ?=6X_DIELECTRIC

TOP,BOTTOM ?=8X_DIELECTRICMIPI_2CLK

?TOP,BOTTOM =10X_DIELECTRICMIPICLK_2OTHER

TOP,BOTTOM ?S2_CMD2CTRL =4x_DIELECTRIC

=4x_DIELECTRICS2MEM_2PWR ?TOP,BOTTOM

S2MEM_2OTHER ?=10x_DIELECTRICTOP,BOTTOM

MIPI_DATA_S2 MIPI_DATA MIPI_DATA_PMIPI_85DMIPI_DATA_NMIPI_DATAMIPI_DATA_S2 MIPI_85DMIPI_DATA_CONN_PMIPI_DATAMIPI_85DMIPI_DATA_CONN_NMIPI_DATAMIPI_85D

S2_MEM_85D S2_MEM_DQS1S2_MEM_DQS1 MEM_CAM_DQS_P<1>

S2_MEM_DATA1S2_MEM_45SS2_MEM_DATA_1 MEM_CAM_DQ<15..8>

PP0V675_MEM_CAM_VREFCAS2_MEM_PWR

CLK_MIPI MIPI_CLK_NMIPI_CLK_S2 MIPI_85D

MEM_CAM_BA<2>S2_MEM_45SS2_MEM_CMD S2_MEM_CMD

S2_MEM_CMDS2_MEM_CMD S2_MEM_45S MEM_CAM_BA<0>

S2_MEM_45S S2_MEM_CTRLS2_MEM_CNTL MEM_CAM_CS_L

S2_MEM_CLK S2_MEM_85D S2_MEM_CLK MEM_CAM_CLK_N

MIPI_CLK_PCLK_MIPIMIPI_CLK_S2 MIPI_85D

S2_MEM_CTRLS2_MEM_45SS2_MEM_CMD MEM_CAM_RAS_L

S2_MEM_CTRL MEM_CAM_CKES2_MEM_45SS2_MEM_CNTL

S2_MEM_45S S2_MEM_CTRLS2_MEM_CMD MEM_CAM_CAS_LS2_MEM_CTRLS2_MEM_45S MEM_CAM_ODT

S2_MEM_CLK S2_MEM_CLKS2_MEM_85D MEM_CAM_CLK_P

MIPI_CLK_CONN_NMIPI_85D CLK_MIPI

S2_MEM_CMD MEM_CAM_BA<1>S2_MEM_CMD S2_MEM_45S

PP0V675_CAM_VREFS2_MEM_PWR

S2_MEM_CMDS2_MEM_A S2_MEM_45S MEM_CAM_A<14..0>

MEM_CAM_DQS_P<0>S2_MEM_DQS0 S2_MEM_85D S2_MEM_DQS0

CLK_MIPI MIPI_CLK_CONN_PMIPI_85D

PP0V675_MEM_CAM_VREFDQS2_MEM_PWR

S2_MEM_PWR PP1V35_CAM

S2_MEM_DATA0S2_MEM_45SS2_MEM_DATA_0 MEM_CAM_DQ<7..0>

S2_MEM_85D S2_MEM_DQS1S2_MEM_DQS1 MEM_CAM_DQS_N<1>

S2_MEM_CMDS2_MEM_45S MEM_CAM_WE_LS2_MEM_CMD

S2_MEM_DATA0S2_MEM_DATA_0 S2_MEM_45S MEM_CAM_DM<0>

S2_MEM_DQS0S2_MEM_85DS2_MEM_DQS0 MEM_CAM_DQS_N<0>

S2_MEM_45SS2_MEM_DATA_1 S2_MEM_DATA1 MEM_CAM_DM<1>

<BRANCH>

<SCH_NUM>

<E4LABEL>

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80 OF 82

36 37

36 37

37 72

37 72

36 37

36 37

37

36 37

36 37

36 37

36 37

36 37

36 37

36 37

36 37

36 37

37

36 37

37 72

36 37

36 37

36 37

36 37

37 72

37

36 37

36 37

36 37

36 37

36 37

36 37

36 37

w w w

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SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET SPACING

SPACING

SMBus Charger Net Properties

NET_TYPE

PHYSICAL

PHYSICAL

NET_TYPE

SYNC_DATE=12/10/2012SYNC_MASTER=SIDLE_J45

SMC Constraints

CHGR_CSO_N1TO1_DIFFPAIR

CHGR_CSO_PCHGR_CSO 1TO1_DIFFPAIR

CHGR_CSI_PCHGR_CSI 1TO1_DIFFPAIRCHGR_CSI_N1TO1_DIFFPAIR

SMBUS_SMC_5_g3_SCLSMBUS_SMC_5_SCL SMBSMB_45S

SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA SMBSMB_45S

SMBUS_SMC_2_S3_SDASMBSMBUS_SMC_2_S3_SDA SMB_45S

SMB SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL SMB_45S

NC_SMBUS_SMC_3_SDASMBUS_SMC_3_SDA SMBSMB_45S

NC_SMBUS_SMC_3_SCLSMBUS_SMC_3_SCL SMBSMB_45S

SMBUS_SMC_5_G3_SDASMBUS_SMC_5_SDA SMBSMB_45S

SMBUS_SMC_1_S0_SDA SMB SMBUS_SMC_1_S0_SDASMB_45S

SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SCLSMBSMB_45S

SMBUS_SMC_2_S3_SCLSMBSMBUS_SMC_2_S3_SCL SMB_45S

<BRANCH>

<SCH_NUM>

<E4LABEL>

117 OF 118

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57

57

41 44 56 57 72

37 41 44 48 68 71 72

39 41 44 72

37 41 44 48 68 71 72

41 43

41 43

41 44 56 57 72

41 44 48

41 44 48

39 41 44 72

w w w

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6 3
















OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE







TABLE_SPACING_ASSIGNMENT_ITEMLINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD










TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD















X425 Specific Net Properties

SPACING

X425 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

DIFFERENTIAL_PAIR

DIFFERENTIAL_PAIR

NET_TYPE

PHYSICAL

NET_TYPE

PHYSICAL SPACING

I357

I358

I359

I360

I361

I362

I405

I406

I407

I408

I419

I420

I421

I422

I423

I424

I425

I426

I432

I436

I440

I441

I442

I445

I446

I447

I448

I449

I450

I451

I452

I453

I454

I455

I456

I457

I458

I459

I460

I461

I462

I463

I480

I481

I482

I483

I484

I485

I486

I487

I488

I489

I490

I491

I492

I493

I494

I495

I498

I499

I502

I503

I510

I511

I514

I515

I516

I517

I518

I519

I520

I521

I522

I523

I524

I525

I526

I527

I528

I529

I530

I531

I532

I533

MEM_85D 100 MIL0.09 MM*

500 MILUSB_85D TOP 0.1 MM

0.090 MMDP_85D ISL9 0.075 MM

0.090 MMPCIE_85D ISL10 0.075 MM

0.090 MMUSB3_85D ISL10 0.075 MM

CLK_PCIE SB_POWER * PWR_P2MM

MEM_37S 100 MIL0.09 MM*

GND_P2MMCPU_COMP *GND

=2X_DIELECTRIC ?*AUDIO

*1TO1_DIFFPAIR 1:1_DIFFPAIR

100 MILMEM_40S 0.09 MM*

=2X_DIELECTRICTHERM * ?

GND_P2MMUSB GND *

100 MIL0.09 MM*MEM_72D

PWR_P2MM * 10000.20 MM

10000.20 MM*GND_P2MM

* GND_P2MMGND SATA_*

=2X_DIELECTRIC* ?SENSE

=45_OHM_SE=45_OHM_SE=45_OHM_SETHERM_1TO1_45S * =1:1_DIFFPAIR=1:1_DIFFPAIR =1:1_DIFFPAIR

SATA_* PWR_P2MM*SB_POWER

USB SB_POWER * PWR_P2MM

PCIE_85D 0.09 MM* 10 MM

0.1 MMTOPUSB3_85D 500 MIL

100 MIL0.23 MMBOTTOMCPU_27P4S

GND_P2MMGND *PCIE_*

*GNDCLK_PCIE GND_P2MM

=45_OHM_SE 0.2 MMTHERM_45S_CPUVRISNS1 =45_OHM_SE=45_OHM_SE=1:1_DIFFPAIR 0.2 MM*

=1:1_DIFFPAIR =1:1_DIFFPAIR=1:1_DIFFPAIRDIFFPAIR =1:1_DIFFPAIR*

=STANDARD* ?GND

GND_P2MMCPU_VCCSENSE *GND

=1:1_DIFFPAIR =1:1_DIFFPAIR=45_OHM_SE=45_OHM_SE=45_OHM_SESENSE_1TO1_45S =1:1_DIFFPAIR*

10 MM=1:1_DIFFPAIR 0.1 MM 0.1 MM 0.1 MM*AUDIODIFF 0.1 MM

SYNC_MASTER=SIDLE_J45

Project Specific ConstraintsSYNC_DATE=12/10/2012

=1:1_DIFFPAIR=50_OHM_SE=50_OHM_SE=50_OHM_SETHERM_1TO1_50S * =1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR=50_OHM_SESENSE_1TO1_50S =50_OHM_SE* =1:1_DIFFPAIR =1:1_DIFFPAIR=50_OHM_SE

SENSE_1TO1_45S SENSESENSE_DIFFPAIR ISNS_LCD_PANEL_N

SENSE_1TO1_45S SENSESENSE_DIFFPAIR ISNS_LCD_PANEL_N

SENSE_1TO1_45S SENSESENSE_DIFFPAIR ISNS_LCD_PANEL_P

SENSE_1TO1_45S SENSESENSE_DIFFPAIR ISNS_LCD_PANEL_P

CHGR_CSI_R_PAUDIODIFFAUDIO_DIFFPAIR AUDIO

ISNS_S2_PSENSE_1TO1_45SSENSE_DIFFPAIR SENSE

ISNS_HS_OTHER5V_PSENSE_1TO1_45S SENSESENSE_DIFFPAIR

SENSE_DIFFPAIR THERMTHERM_1TO1_45S DDR3THMSNS_D1_N

THERM_1TO1_45S THERMSENSE_DIFFPAIR CPUTHMSNS_D2_PCPUTHMSNS_D2_NSENSE_DIFFPAIR THERMTHERM_1TO1_45S

ISNS_PCH_R_PSENSE_1TO1_45S SENSEISNS_PCH_R_NSENSE_1TO1_45S SENSEISNS_TPAD_PSENSE_1TO1_45S SENSESENSE_DIFFPAIRISNS_TPAD_NSENSE_DIFFPAIR SENSE_1TO1_45S SENSE

SENSE_1TO1_45S ISNS_HS_COMPUTING_NSENSESENSE_DIFFPAIR

AUDIO_DIFFPAIR AUDIODIFFPAIR AUD_MIC_IN1_R_N

AUD_MIC_IN1_L_PDIFFPAIR AUDIOAUDIO_DIFFPAIR

DIFFPAIR AUD_CONN_HS_MIC_PAUDIO

DIFFPAIR AUD_CONN_HS_MIC_NAUDIO

AUDIODIFF AUD_LO3_R_PAUDIO_DIFFPAIR AUDIO

AUDIODIFFAUDIO_DIFFPAIR AUD_LO3_L_NAUDIO

DIFFPAIR AUDIO HS_MIC_NDIFFPAIR HS_MIC_PAUDIO

AUD_HS_MIC_NDIFFPAIR AUDIO

AUDIO AUD_SPKRAMP_LIN_NAUDIODIFF

AUDIODIFF AUDIO SPKRAMP_RIN_P

AUDIO_DIFFPAIR AUDIO SPKRCONN_SL_OUT_PDIFFPAIR

SPKRCONN_SR_OUT_NDIFFPAIR AUDIOAUDIO_DIFFPAIR

THERMTHERM_1TO1_45SSENSE_DIFFPAIR ISNS_CPUDDR_N

AUDIODIFF AUDIO AUD_LO3_R_NAUDIO_DIFFPAIR

AUDIODIFFAUDIO_DIFFPAIR AUD_LO3_L_PAUDIO

AUDIO_DIFFPAIR DIFFPAIR SPKRCONN_SL_OUT_NAUDIO

AUDIO_DIFFPAIR AUD_LO2_R_NAUDIOAUDIODIFF

AUD_SPKRAMP_RSUBIN_NAUDIOAUDIODIFF

AUDIOAUDIODIFF AUD_SPKRAMP_LSUBIN_P

RSUBIN_PAUDIOAUDIODIFF

SPKRAMP_LIN_PAUDIOAUDIODIFF

AUDIOAUDIODIFF AUD_SPKRAMP_RIN_PAUDIODIFFAUDIO_DIFFPAIR AUD_LO2_L_NAUDIO

SB_POWER PP3V3_S5PP3V3_S0SB_POWER

CHGR_CSO_R_PAUDIODIFFAUDIO_DIFFPAIR AUDIO

AUDIOAUDIODIFF AUD_SPKRAMP_LSUBIN_N

AUDIODIFF SPKRAMP_RIN_NAUDIO

CHGR_CSI_R_NAUDIODIFF AUDIO

AUD_SPKRAMP_RSUBIN_PAUDIOAUDIODIFF

AUDIO_DIFFPAIR DIFFPAIR AUD_MIC_IN1_R_PAUDIO

AUDIO_DIFFPAIR SPKRCONN_R_OUT_NAUDIODIFFPAIR

AUDIO_DIFFPAIR SPKRCONN_SR_OUT_PAUDIODIFFPAIR

PP1V35_S3RS0_CPUDDRSB_POWER

SENSE_1TO1_45S ISNS_S2_NSENSESENSE_DIFFPAIR

CODEC_HS_MIC_PDIFFPAIRAUDIO_DIFFPAIR AUDIO

AUDIO_DIFFPAIR CODEC_HS_MIC_NDIFFPAIR AUDIO

SENSE_1TO1_45S ISNS_S2_R_PSENSE_DIFFPAIR SENSE

AUDIO_DIFFPAIR AUD_LO2_R_PAUDIODIFF AUDIO

AUD_MIC_IN1_L_NDIFFPAIR AUDIO

DIFFPAIR AUD_HS_MIC_PAUDIO

DIFFPAIRAUDIO_DIFFPAIR AUDIO SPKRCONN_R_OUT_PDIFFPAIR SPKRCONN_L_OUT_NAUDIOAUDIO_DIFFPAIR

LSUBIN_NAUDIODIFF AUDIO

AUDIO_DIFFPAIR DIFFPAIR SPKRCONN_L_OUT_PAUDIO

AUDIO RSUBIN_NAUDIODIFFLSUBIN_PAUDIOAUDIODIFF

AUDIODIFF AUD_LO2_L_PAUDIO_DIFFPAIR AUDIO

THERM_1TO1_45S THERM ISNS_CPU_DDR_R_NTHERM_1TO1_45S THERM ISNS_CPU_DDR_R_P

CHGR_CSO_R_NAUDIODIFF AUDIO

SENSE_1TO1_45S ISNS_S2_R_NSENSE_DIFFPAIR SENSE

THERM GFXIMVP_ISNS1_NTHERM_1TO1_45SSENSE_DIFFPAIR

THERMSENSE_DIFFPAIR ISNS_CPUDDR_PTHERM_1TO1_45S

THERM_1TO1_45SSENSE_DIFFPAIR THERM P1V05_GPU_PEX_IOVDD_SNS_N

CPUVR_ISNS3THERM_45S_CPUVRISNS1 THERMSENSE_DIFFPAIR CPUVR_ISNS3_P

CPUVR_ISUM_R_PTHERM_1TO1_45SSENSE_DIFFPAIR THERM

SENSE_1TO1_45S SENSE CPUVR_ISNS_N

SENSE_1TO1_45S ISNS_HS_COMPUTING_PSENSESENSE_DIFFPAIR

SENSE_1TO1_45SSENSE_DIFFPAIR ISNS_HS_OTHER5V_NSENSE

SENSE_1TO1_45SSENSE_DIFFPAIR ISNS_HS_OTHER3V3_PSENSE

SENSE_1TO1_45S ISNS_HS_OTHER3V3_NSENSESENSE_DIFFPAIR

SENSE_1TO1_45S CPUVR_ISNS_PSENSE

THERM_1TO1_45SSENSE_DIFFPAIR THERM P1V05_GPU_PEX_IOVDD_SNS_P

CPUVR_ISNS2THERM_45S_CPUVRISNS1 THERMSENSE_DIFFPAIR CPUVR_ISNS2_N

CPUVR_ISUM_R_NSENSE_DIFFPAIR THERM_1TO1_45S THERM

CPUVR_ISNS3THERM_45S_CPUVRISNS1 THERMSENSE_DIFFPAIR CPUVR_ISNS3_N

CPUVR_ISNS2THERM_45S_CPUVRISNS1 THERMSENSE_DIFFPAIR CPUVR_ISNS2_P

TBT_THERMDNTHERM_1TO1_45S THERM

TBT_THERMDPTHERM_1TO1_45SSENSE_DIFFPAIR THERM

AUDIO_DIFFPAIR AUDIO ISNS_TBT_NAUDIODIFF

SENSE_DIFFPAIR ISNS_SSD_R_PTHERMTHERM_1TO1_45S

ISNS_SSD_NTHERMTHERM_1TO1_45S

THERM ISNS_SSD_R_NTHERM_1TO1_45S

THERMTHERM_1TO1_45S P1V05S0_CS_NSENSE_DIFFPAIR THERM P1V05S0_CS_PTHERM_1TO1_45S

AUDIO_DIFFPAIR ISNS_TBT_PAUDIOAUDIODIFF

SENSE_DIFFPAIR THERM GFXIMVP_ISNS1_NTHERM_1TO1_45S

SENSE_DIFFPAIR THERM GFXIMVP_ISNS1_PTHERM_1TO1_45S

GFXIMVP_ISNS1_PTHERM_1TO1_45S THERMSENSE_DIFFPAIR

CPUVR_ISNS1THERM_45S_CPUVRISNS1 THERMSENSE_DIFFPAIR CPUVR_ISNS1_NCPUVR_ISNS1THERM_45S_CPUVRISNS1SENSE_DIFFPAIR CPUVR_ISNS1_PTHERM

P1V05S0_SENSETHERM P1V05S0_SENSE_NTHERM_1TO1_45S

P1V05S0_SENSE P1V05S0_SENSE_PTHERMSENSE_DIFFPAIR THERM_1TO1_45S

AUDIO ISNS_TBT_R_NAUDIODIFF

THERM_1TO1_45SSENSE_DIFFPAIR THERM ISNS_SSD_PAUDIODIFF AUDIO ISNS_TBT_R_P

SENSE_DIFFPAIR THERM FINTHMSNS_D_NTHERM_1TO1_45S

SENSE_1TO1_45S SENSE ISNS_1V35_MEM_PSENSE_DIFFPAIR

SENSE_1TO1_45S SENSE ISNS_1V35_MEM_R_PSENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_1V35_MEM_N

SENSE_1TO1_45S SENSE ISNS_1V35_MEM_R_N

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_AIRPORT_PSENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_AIRPORT_N

SENSESENSE_1TO1_45S ISNS_AIRPORT_R_N

SENSE_DIFFPAIR SENSESENSE_1TO1_45S ISNS_LCDBKLT_PSENSE_DIFFPAIR ISNS_LCDBKLT_NSENSESENSE_1TO1_45S

ISNS_PCH_PSENSE_1TO1_45SSENSE_DIFFPAIR SENSEISNS_PCH_NSENSE_DIFFPAIR SENSE_1TO1_45S SENSE

SPKRAMP_LIN_NAUDIOAUDIODIFF

AUDIODIFF AUD_SPKRAMP_LIN_PAUDIO

AUDIOAUDIODIFF AUD_SPKRAMP_RIN_N

SENSESENSE_1TO1_45S ISNS_AIRPORT_R_P

SENSE_DIFFPAIR FINTHMSNS_D_PTHERMTHERM_1TO1_45S

THERMSENSE_DIFFPAIR THERM_1TO1_45S DDR3THMSNS_D1_P

GNDGND

<BRANCH>

<SCH_NUM>

<E4LABEL>

118 OF 118

82 OF 82

47 68 82

47 68 82

47 68 82

47 68 82

57

45

48

48

48

46

46

46

46

45

51 53

51 53

51 54

51 54

54 55

53

53

53 55 72

53 55 72

47 66

51 53

51 53

53 55 72

51 53

53

53

53

53

53

51 53

12 14 15 17 18 19 21 31 32 34 61 64 66 67 70 71 72

11 12 13 14 15 17 19 20 29 33 35 44 45 46 47 48 49 51 52 55

66 67 68

70 72

57

53

53

57

53

53 55 72

53 55 72

6 8 10 21 66 67 70

51

51

47

51 53

54 55

53 55 72

53 55 72

53

53 55 72

53

53

51 53

47

47

57

47

82

47 66

46 59

46

46

45

45

45

45

46

46 59

46

46 59

46 59

48

28 48

46

46

46

46

46 62

46 62

46

82

82

82

46 59

46 59

62

62

46

46

46

48

46

46

46

46

47

47 63

47 63

53

53

53

47

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48

ALIASES RESOLVED - InformaticaNapoli · w w w . c h i n a f i x . c o m table_bomgroup_item...

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