ALCT Virtex-E and Spartan-6 firmware Abstractmadorsky/alctv/firmware/2013-06-13/alct_firmwa… ·...

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ALCT Virtex-E and Spartan-6 firmware

University of Florida/Physics

A. Madorsky

2018-10-25

Abstract

This document describes the details of Virtex-E and Spartan-6 firmware implementation in ALCT.

Table of Contents

ABSTRACT ............................................................................................................................................................................... 1

TABLE OF CONTENTS .............................................................................................................................................................. 1 LIST OF TABLES ....................................................................................................................................................................... 2

VIRTEX/SPARTAN JTAG REGISTERS .............................................................................................................................. 3

Virtex/Spartan FPGA Instruction Register ........................................................................................................................ 3 Virtex/Spartan ID Register ................................................................................................................................................ 4 Virtex/Spartan Configuration Register .............................................................................................................................. 5 Virtex/Spartan Trigger Register ......................................................................................................................................... 7 Virtex/Spartan Bypass Register ......................................................................................................................................... 7 Hot Channel Mask Register ............................................................................................................................................... 7 Delay Line Register. .......................................................................................................................................................... 8 Delay line control register. ................................................................................................................................................. 8 Collision mask register ...................................................................................................................................................... 8 Extended configuration register ......................................................................................................................................... 9 Output FIFO....................................................................................................................................................................... 9 Hit counters ...................................................................................................................................................................... 10

DAQ DATA FORMAT FOR ALCT2001 .............................................................................................................................. 11

ALCT-2006 ALGORITHM DESCRIPTION. ...................................................................................................................... 14

1. One-shots. .................................................................................................................................................................... 15 2. Pattern detectors ........................................................................................................................................................... 15 3. Ghost Cancellation Logic (GCL) ................................................................................................................................. 16 4. Best track selector. ....................................................................................................................................................... 17 5. Track promotion. ......................................................................................................................................................... 17

TTC SYSTEM ......................................................................................................................................................................... 18

TEST POINTS AND LEDS. ................................................................................................................................................... 19

REVISION HISTORY ............................................................................................................................................................ 19

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List of Tables

Table 1: Virtex/Spartan JTAG instructions for ALCT2001. ....................................................................... 3 Table 2: Virtex/Spartan ID Register ............................................................................................................ 4 Table 3: Virtex/Spartan Configuration Register .......................................................................................... 5 Table 4: Virtex/Spartan Trigger Register .................................................................................................... 7 Table 5: Hot Channel Mask Register ........................................................................................................... 7

Table 6: Output FIFO format ....................................................................................................................... 9 Table 7: Hit Counters Register Format ...................................................................................................... 10 Table 8 ALCT DAQ format ...................................................................................................................... 11 Table 9 Bit fields explanation .................................................................................................................... 13 Table 10 ALCT0 and ALCT1 field description ........................................................................................ 14

Table 11: Quality codes ............................................................................................................................. 15 Table 12. TTC codes decoded by ALCT. .................................................................................................. 18

Table 13: Test points ................................................................................................................................. 19

Table 14: LEDs .......................................................................................................................................... 19

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Virtex/Spartan JTAG Registers

Virtex/Spartan FPGA Instruction Register

This registers stores a 5-bit JTAG instruction. Instruction bits are shifted in LSB first from TDI. A fixed

bit pattern of B"1001" is shifted out on TDO during the Shift-IR JTAG state to aid in software

debugging. (Is this true for AM design?) Concentrator instructions select which one of the configuration

registers is placed between TDI and TDO during JTAG data cycles.

Instructions and data are shifted in from TDI in the order LSB first.

Table 1: Virtex/Spartan JTAG instructions for ALCT2001.

Binary Hex OpCode Description

Selected Data

Register Length

00000 00 RdID Read ID Register ID Register 40

00001 01 RdHCM Read Hot Channel Mask

Hot Channel

Mask

192,288,384,

576,6722

00010 02 WrHCM Write Hot Channel Mask

Hot Channel

Mask

192,288,384,

576,6722

00110 06 RdCfg Read Configuration Register

Configuration

Register Shadow 69

00111 07 WrCfg Write Configuration Register

Configuration

Register 69

00011 03 RdTrig Read Trigger Register

Trigger Register

Shadow 5

00100 04 WrTrig Write Trigger Register Trigger Register 5

01101 0D Wdly

ASIC Delay Write selected chain

(see specs of the delay line

control register) Data Register 120

01101 0E Rdly

ASIC Delay Read selected chain

(see specs of the delay line

control register) Data Register

121

10000 10 YRread extended config register read Data Register 31

10001 11 CNread hit counters read Hit counters

96,32,224,

96,961

10011 13 CollMaskRead Read collision mask register Data Register

112,168,224,

336,3922

10100 14 CollMaskWrite Write collision mask register Data Register

112,168,224,

336,3922

10101 15 DelayCntrlRead Delay line control register read 5,5,6,9,92

10110 16 DelayCntrlWrite Delay line control register write 5,5,6,9,92

10111 17 InputEnable

Write this command into the

JTAG instruction register to

enable input register clock. Used No data

1 Five numbers are shown for ALCT 192, 288, 384, 576, and 672, respectively.

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Binary Hex OpCode Description

Selected Data

Register Length

for debugging.

11000 18 InputDisable

Write this command into the

JTAG instruction register to

disable input register clock. Used

for debugging. No data

11001 19 YRwrite Extended config register write Output register 31

11010 1A Osread

Output FIFO read. Used for

debugging via JTAG and for

FAST site operation while TMB

is not available

Output storage

data

49,49,49,

51,512

11111 1F Bypass Bypass Scan Register Bypass Register 1

Virtex/Spartan ID Register

This is a 40-bit read-only register that contains fixed information about the Virtex/Spartan chip,

firmware version number, and chip ID number. Typical values are shown below, but the date and

version fields can change value whenever the Xilinx logic is re-compiled. The chip ID number is hard-

wired on the printed circuit board.

Table 2: Virtex/Spartan ID Register

Field Bits Name Description

39:36 4 month binary code

35:31 5 day binary code

30:19 12 year binary code

18:17 2 reserved

16 1 seu (see Table 9)

15 1 sp6 (see Table 9)

14 1 pb (see Table 9)

13 1 rl (see Table 9)

12 1 ke (see Table 9)

11 1 mr (see Table 9)

10 1 np (see Table 9)

9 1 bf (see Table 9)

8:6 3 wgn (see Table 9)

5:0 6 ver firmware version

Total 40

2 Five numbers are shown for ALCT 192, 288, 384, 576, and 672, respectively.

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Virtex/Spartan Configuration Register

This is a read/write shift-register that contains all of the programmable configuration bits for the logic.

Table 3: Virtex/Spartan Configuration Register

Field Bits Dflt Name firmware

(xml)

Description

Virtex/Spartan Trigger Modes [1:0] 2 0 trig_mode[1:0]

(alct_trig_mode) Virtex/Spartan Trigger Mode: 0 = Pre-Trigger on either Collision muon or Accelerator muon pattern 1 = Only Pre-Trigger on Accelerator muon patterns 2 = Only Pre-Trigger on Collision muon patterns 3 = Pre-Trigger on Collision muons, accelerator muon vetoes Pre-Trigger

[2] 1 0 ext_trig_en

External Trigger Enable: 0 = disable external trigger 1 = enable external trigger In the external trigger mode, the board monitors the ext_trig input signal. The input data on each clock will be processed only if ext_trig input is ==1 in this clock.

[3] 1 0 send_empty If equal to 1, ALCT will send DAQ data for empty events, for which it did not find any tracks. If equal to 0, DAQ for events with no tracks will not be sent.

[4] 1 0 inject 0 = Input data enabled 1 = Input data enabled only if ext_inject input is == 1

[12:5] 8 1 bxc_offset[7:0] This offset is loaded into internal BX counter in ALCT upon BC0

Pre-Trigger Controls [15:13] 3 2 nph_thresh[2:0]

(alct_nplanes_hit_ pretrig)

Number of Planes Hit Threshold for Pre-Trigger for collision tracks Range = 0 to 6 CSC layers If the board encounters nph_thresh or more layers hit in collision or accelerator patterns for a particular key WG, the pattern detection process starts for this particular WG. This event is named “pretrigger”. Pretriggers for different key WGs are independent and can happen simultaneously. They are not reported to the next stages of the ALCT logic. Pretrigger is used to mark the exact number of the bunch-crossing when the track crossed the chamber.

[18:16] 3 4 nph_pattern[2:0] (alct_nplanes_hit_ pattern)

Plane hits required after drift delay to allow an LCT-trigger for collision tracks Range = 0 to 6 CSC layers If there was a pretrigger for a key WG, drift_delay clocks later the board counts the layers hit in the patterns for this key WG again. If the number of layers hit in one of the patterns is equal or more than nph_pattern, this event is reported to the next stages of trigger logic. This event is named “trigger”. Triggers for different key WGs are independent and can happen simultaneously

[35:33] 3 0 acc_thresh[2:0] (alct_nplanes_hit_accel_pretrig)

Number of Planes Hit Threshold for Pre-Trigger for accelerator tracks (see nph_thresh description for details)

If set to 0, value of nph_thresh is used instead of it [59:56] 3 0 acc_pattern[2:0]

(alct_nplanes_hit_accel_pattern)

Plane hits required after drift delay to allow an LCT-trigger for accelerator tracks (see nph_pattern description for details)

If set to 0, value of nph_pattern is used instead of it [20:19] 2 3 drift_delay[1:0]

(alct_drift_delay) Drift delay after pre-trigger, 25n steps Range = 0 to 3 [0 to 75ns] See description of nph_pattern parameter for explanation.

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Raw Hits FIFO Controls [25:21] 5 7 fifo_tbins[4:0]

(alct_fifo_tbins) Total number of FIFO time bins per wire group Range = 0 to 31 decimal [25ns steps]

[30:26] 5 1 fifo_pretrig[4:0] (alct_fifo_pretrig)

FIFO time bins before trigger [included in total] Range = 0 to 31 decimal [25ns steps] If the l1a_delay parameter has been timed in to be in the middle of the ALCT L1A window, then the number of time bins before pretrigger is equal to (fifo_pretrig-ALCT_FPGA_latency)+(l1a_window-1)/2.The total number of time bins in DAQ readout is determined by fifo_tbins parameter. ALCT_FPGA_latency = 6 currently.

[32:31] 2 1 fifo_mode[1:0] FIFO Mode 0 = No raw hits dump 1 = Full dump [all LCT chips] 2 = Local dump [only LCT chips with hits] (not yet implemented)

Level 1 Accept [43:36] 8 78h l1a_delay[7:0] Level 1 Accept delay after trigger

Range = 0 to 255 decimal L1A signal is expected in the time window from l1a_delay to l1a_delay+ l1a_window clocks after the trigger event. If L1A arrives in this window, the DAQ data for this trigger event will be reported during DAQ readout.

[47:44] 4 3 l1a_window[3:0] (alct_l1a_window_width)

Level 1 Accept window width [25ns steps] Must be an odd value. For more details, see description of l1a_delay parameter.

[51:48] 4 1 l1a_offset[3:0]

Level 1 Accept counter Pre-Load value [arbitrary value] Range = 0 to F hex

[52] 1 0 l1a_internal

L1A generated internally during L1A window 0 = L1A comes from CCB via TMB 1 = L1A generated internally in L1A window for each track found in any key WG.

Board ID [55:53] 3 5 board_id[2:0]

ALCT2001 circuit board ID [arbitrary value] Range = 0 to 7

ALCT-Bus [60] 1 0 lhc_cycle_sel Selector of BX counter terminal (rollover) count:

1 = 3564 (LHC) 0 = 924 (beam test)

[64] 1 0 config_report report configuration settings in DAQ readout (implemented in DAQ-2006 format)

[65] 1 0 alct_amode (alct_accel_mode)

ALCT Accelerator Muon Mode [affects all LCT chips] 0 = Prefer Collision-muons 1 = Prefer Accelerator-muons To disable accelerator or collision tracks use trig_mode parameter

[66] 1 0 zero_suppress 0 = do not suppress zeros in DAQ readout 1 = suppress zeros in DAQ readout See DAQ readout format for details

[67] 1 1 trig_info_en 0 = do not write trigger information to the output FIFO. ALCT output will be written into the output FIFO only when DAQ readout is in progress. 1 = write trigger information to the output FIFO. If the valid track is detected in this clock, the entire ALCT output is written into the output FIFO. Please see “Output FIFO” section of this document.

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[68] 1 0 sn_select Selector of the serial number device to read via JTAG: 0 = ALCT serial number 1 = Mezz card serial number

[59,61,62,63]

4 0 reserved

Total 69

Virtex/Spartan Trigger Register is a 5-bit read/write shift-register that generates various internal triggers. During a register-read

instruction, the "shadow" copy of the actual Trigger Register is shifted out on JTAG TDO, so the read

operation is non-destructive.

Table 4: Virtex/Spartan Trigger Register

Data in bits 1, 0 Binary Hex

Description

00 0 Do Nothing

11 3 Self-generate External Test Pulse (AFEB)

Data in bits 2, 3 Binary Hex

Description

00 0 Pulse generated with the JTAG command goes to test

pulse output (see table above)

01 1 Adb_sync_pulse goes to test pulse output

10 2 Adb_async_pulse goes to test pulse output

11 3 External test pulse signal from LEMO connector goes to

test pulse output

Data bit 4 if set to 1 inverts the test pulse output.

Virtex/Spartan Bypass Register is a 1-bit read/write shift-register that is inserted between TDI and TDO when no other registers have

been selected, or when the Bypass instruction is selected.

Hot Channel Mask Register

is a 192, 288, 384, 576 or 672-bit register setting the hot channel mask.

Table 5: Hot Channel Mask Register

Bits Default state Layer HCmask[ n-1: 0] All 1s 1

HCmask[2n-1: n] All 1s 2

HCmask[3n-1:2n] All 1s 3



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n in this table is 32 for ALCT-192, 48 for ALCT-288, 64 for ALCT-384, 96 for ALCT-576, 112 for

ALCT-672

Delay Line Register. There are 3, 4, 73 chains by 6 delay lines each connected to Virtex/Spartan FPGA. The selection which

chain to work with is done using the Delay line control register (see section below). Please use the

“alct_fast_lib.c” function “alct_download_delay” to write the delay codes and patterns into them. See

the description of this library for details.

Delay line control register.

This is the 5,6 or 9-bit4 register which selects which delay line chain you are working with, and allows

to set or reset the control signals common for all delay lines. Format of this register is shown below:

{cs_dly[(2,3,64):0], settst_dly, rs_dly}

cs_dly – chain-select signals

settst_dly – settst signal common for all delay lines

rs_dly – reset signal common for all delay lines

Please use the function “alct_download_delay” from “alct_fast_lib.c” library to write the delay codes

and patterns into them. This library handles the Delay line and control registers correctly. See the

description of this library for details.

Collision mask register is accepting 4,6,8,12 or 144 28-bit masks. Mask 0 is working for WG 0-7, mask 1 for WG 8-15, and so

on, one mask for 8 WGs. Each mask contains 14 bits for each of the two possible collision patterns. The

bit mapping for the first collision mask is shown below:

Pattern A:

ly0 2 1 0

ly1 4 3

ly2 5

ly3 7 6

ly4 10 9 8

ly5 13 12 11

Pattern B (for software compatibility only, will be removed

eventually):

ly0 16 15 14

3 Three numbers are shown for ALCT-192 and 288, ALCT-384, ALCT-576 and 672, respectively. 4 Five numbers are shown for ALCT 192, 288, 384, 576, and 672, respectively

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ly1 18 17

ly2 19

ly3 21 20

ly4 24 23 22

ly5 27 26 25

As you can see, the table forms the shape of the envelope of all possible patterns. The numbers are the

bit positions in the collision mask, responsible for this particular hit in the pattern. Setting some of the

mask bits to 0 you can disable the corresponding hits and make the FPGA analyze only the enabled hits,

forming any pattern in the limits of the envelope. This can also be used for disabling some layers

completely. Default is all 1s. Please see algorithm description section for details.

Extended configuration register (previously output register):

length: 31 bits. Bit 0 is Output_storage_enable, used for jtag tests. All other bits reserved.

Output FIFO is used to log any relevant output data coming from ALCT. Whatever appears on the output connectors

of ALCT – triggering information, DAQ readout information – is simultaneously written into this FIFO,

but only if “valid” bit is set for the best muon or DAQ readout is in progress, or both conditions are met

simultaneously. OSread command allows to read one 49-bit word from this FIFO at a time. The format

of this word is shown below:

Table 6: Output FIFO format

Name Description Bit

position FIFOempty If equal to 1 than FIFO is empty. Typically used for polling

FIFO.

MSB

FirstAcceleratorFlag Shows if the first best track is accelerator track

FirstQuality[1:0] Quality of the first best track

FirstKeyWG[(5,5,65):0] Key wire group of the first best track

FirstPatternB If equal to 1 and FirstAcceleratorFlag == 0, collision pattern B

was found for this track, otherwise pattern A

SecondAcceleratorFlag Shows if the second best track is accelerator track

SecondQuality[1:0] Quality of the second best track

SecondKeyWG[(5,5,65):0] Key wire group of the second best track

SecondPatternB If equal to 1 and SecondAcceleratorFlag == 0, collision pattern

B was found for this track, otherwise pattern A

DAQinfo[18:0] DAQ readout information. See Error! Reference source not found. for details.

bxn[8:0] Bunch crossing counter LSB

Output FIFO write operation is enabled if:

YRIclkEnr is set to 1 (see output register description) AND

5 Three numbers are shown for ALCT 288, 384 and 672, respectively.

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Input clock is enabled (see Table 8, InputEnable command).

Triggering information is written into the FIFO only if “trig_info_en” bit of the configuration register is

set to 1 (see Table 11).

Output FIFO depth is 1023 words, which allows reading the DAQ information for up to 10 time

bins. If output FIFO is used for DAQ readout, fifo_tbins parameter in the configuration register

should be less of equal to 10.

Hit counters

These counters are connected to the output of the trigger logic, and are used to count triggers found in

arrays of key wiregroups corresponding to the boundaries of HV segments in the chambers. Each

counter counts for 10 sec, then the result is stored for readout, the counter is reset to 0 and starts

counting again. The key wiregroup boundaries in different types of ALCTs are shown below:

Table 7: Hit Counters Register Format

hit counter

register bits

ALCT types

31:0 63:32 95:64 127:96 159:128 191:160 224:192

ALCT192 1-12 13-22 23-32

ALCT288 1-48

ALCT384 1-16 17-24 25-28 29-40 41-48 49-52 53-64

ALCT576 1-32 33-64 65-96

ALCT672 1-44 45-80 81-112

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DAQ data format for ALCT2001

Table 8 ALCT DAQ format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit number

1 1 0 1 1 0 1 1 0 0 0 0 1 0 1 0 0xDB0A – header

1 1 0 1 BXN at the time of L1A[11:0] Note 12

1 1 0 1 L1A_counter[11:0] L1A counter

1 1 0 1 Readout_counter[11:0] Readout counter

0 cp lof rof BXN[11:0] BXN, flags

Notes 1, 7

0 r r zse BXN_before_reset[11:0]

0 r r r seu sp6 wp pb rl ke mr n/p b/f wgn Firmware flags

Note 1

0 Firmware version LCT_bins[3:0] Raw_bins[4:0] Reported LCT and Raw

hit time bin number

0 Virtex/Spartan ID register [14:0] Virtex/Spartan ID

register,

Trigger Register

Notes 3, 9

0 Virtex/Spartan ID register [29:15]

0 r r TrReg[4:2] Virtex/Spartan ID register [39:30]

0 Configuration register bits [14:0]

Configuration register.

Notes 3, 9




0 r r r r r r Configuration register bits [68:60]

0 r Collision mask register [13:0] Collision mask register

Notes 3, 9 0 r Collision mask register [27:14]

More Collision mask register words here

0 r r r Hot Channel Mask [11:0]

Hot channel mask

Notes 3, 9



More Hot Channel Mask words here

0 r r r ALCT0[11:0] Best and second best

ALCTs found during

L1A window

Notes 1,2, 10

0 r r r ALCT1[11:0]

More ALCT words here

0 r zsf Layer 0 [11:0] Raw hit dump, zero

suppression flags

Note 1, 4, 11

0 r zsf Layer 0 [23:12]

0 r zsf Layer 0 [35:24]

More raw hit dump words here

1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 1 0xDE0D – evener

1 1 0 1 0 CRC [10:0] CRC

Note 5 1 1 0 1 0 CRC[21:11]

1 1 0 1 tc Word count [10:0] Word count

Note 6

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Color coding:

Yellow – required bits (headers, eveners, etc)

Green – reserved bits, will be all zeroes but can be used in later versions

Blue – More words of the same type as the word above

White – relevant information (see explanation in Table 9)

Notes:

1. See Table 9

2. See Table 10

3. See corresponding sections in this document

4. Raw hits are transmitted using the following algorithm:

word_count = 0; // time bin loop

for (tb = 0; tb < Raw_bins; tb++)

{ // layer loop

for (i = 0; i < 6; i++)

{ // if layer does not have hits and zero suppression on

if (layer[i] == 0 && zero_suppress)

{ // replace layer with single word, set zsf = 1

daq = 0x1000;

word_count++;

}

else // layer part loop

// layer part is 12 bit long

// ALCT-384 variant shown

// ROUNDUP(64 wiregroups per layer/12) = 6 layer parts

for (j = 0; j < 6; j++)

{

lsb = j * 12; // low bit

msb = lsb + 11; // high bit

if (msb > 63) msb = 63; // last layer part is truncated // transmit layer i, bits from low to high

daq = layer[i][msb:lsb];

word_count++;

}

}

} // transmit padding until word count is multiple of 4 (zsf = 3)

while ((word_count & 3) != 0)

{

daq = 0x3000;

word_count++;

}

5. CRC is calculated for data bits [15:0] using the following parameters: Poly = 10000000000000000000011

Data width = 16

CRC width = 22

CRC init = 0

Data bit first = MSB

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Evener and word count are not included into CRC.

6. Word count includes CRC words.

7. L1A does not always come exactly l1a_delay clocks after the track is found by ALCT.

There is a window (l1a_window parameter, 3 clocks by default), in which ALCT is trying to

find the tracks corresponding to each L1A. So, 12-bit BXN in word 5 of the DAQ format is the

BX number l1a_delay clocks ago from L1A. BXN of each LCT can be found by taking BXN

and adding LCT bin number to it.

8. For the calculation of the length of DAQ readout and its parts, see

ALCT_DAQ_format_length.xls

9. This field is transmitted only if cp == 1.

10. This field is transmitted only if LCT_bins is not 0

11. This field is transmitted only if Raw_bins is not 0

12. Needed by DDU to detect missynchronization.

Table 9 Bit fields explanation

Name Explanation

r Reserved, always 0

wgn number of wiregroups: 1 – 192, 2 – 288, 3 – 384, 5 – 576, 6 – 672

b/f 0 – backward, 1 – forward (only for ME1/1)

n/p 0 – negative, 1 – positive (only for ME1/1)

mr Mirrored version

ke If 1 - tracks with equal quality cancelled in GCL

rl 0 – FPGA latency 10 clocks, 1 – FPGA latency 6 clocks (drift waiting time

included)

pb 0 – pattern B enabled, 1 – pattern B disabled

wp 1 – wide pattern version, uses the entire chamber as one pattern, 0 – regular

lof 1 - LCT buffer overflow. ALCT words will not be transmitted

rof 1 – Raw hit buffer overflow. Raw hit dump will not be transmitted

BXN Bunch crossing counter L1A_delay clocks before L1A for this readout

ALCT0

ALCT1

Best and second best ALCTs found during each clock in L1A window. This

section repeats LCT_bins times.

Raw hit dump This section contains all raw hit information.

BXN_before_reset at BC0 signal, the state of internal BX counter is written into this register, and

then the BX counter is reset. This register is used to detect synchronization

problems.

L1A_counter Internal L1A counter, also sometimes called Event counter.

Readout_counter Counts the number of actually completed DAQ readouts since last reset. The

readouts counted are guaranteed to be completed. Used to debug “missing”

DAQ blocks, to make sure ALCT is sending them all.

tc this bit is set by TMB, 1 if CRC check was OK, 0 otherwise

cp Configuration present flag. If set to 1, DAQ format includes the following

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fields:

1. Virtex/Spartan ID register

2. TrReg

3. Configuration register

4. Collision mask register

5. Hot Channel Mask

If cp = 0; the above fields are not included.

This bit is programmable via configuration register bit [64].

LCT_bins How many LCT bins are reported in this readout. This number is always

even, and is calculated like this: LCT_bins = l1a_window + 1, but may

become 0 in case of LCT buffer overflow (lof flag is 1): However, the number

of meaningful LCT bins is equal to l1a_window; the last LCT bin transmitted

is padding, always 0. The padding is necessary to make the total number of

DAQ words a multiple of 4, as required by DDU.

Raw_bins How many raw hit time bins are reported in this readout. This number should

be equal to fifo_tbins parameter from configuration register, but may become

0 in case of:

1. Raw hit buffer overflow (rof flag is 1)

2. fifo_mode parameter is 0

zse Zero suppression enabled. If set, expect zero-suppressed raw hits. If not set,

all raw hits transmitted as is.

zsf Zero suppression flags.

0: no suppression for this data word, treat as part of layer

1: this word replaces an entire layer that has no hits

2: reserved value, should not appear in data

3: raw hit padding to make DAQ block's length multiple of 4, ignore this

word

sp6 If set to 1 this is Spartan-6 FPGA, otherwise Virtex-E

seu If set to 1 a single-event-upset has been detected at some point in the past.

This works only in Spartan-6 FPGA. In Virtex-E, this flag is always set to 0.

Table 10 ALCT0 and ALCT1 field description

Bits Name Description

0 Valid This track is valid if this bit is 1

2:1 Quality Quality of the track

3 Accelerator muon This track is detected as accelerator pattern if this bit is 1

4 Pattern B This track is detected by pattern B if this bit is 1,

otherwise it is detected by pattern A.

11:5 Key wiregroup

number

Shows what key wiregroup detected this pattern

ALCT-2006 algorithm description.

This section describes the basics of the ALCT-2006 algorithm, which is implemented in XCV600E

FPGA for ALCT288, ALCT384, and XCV1000E for ALCT672. This description is provided only for

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the reference for program model writers, and does not include some information (timing, some control

registers, DAQ readout description, etc.).

The algorithm is pipelined. Shown below are the steps of this pipeline:

1. One-shots.

One-shots detect the rising edge on each of the 192,288,384,576, or 672 input bits, and start the output

pulse at this moment. The output pulse duration is 6 clocks (150 ns). This is used to allow any drifting

ions created by the charged particle to reach the wires.

2. Pattern detectors The outputs of the one-shots are supplied to the pattern detectors. There are 32,48,64,96, or 112 of them

– because there are as many key wire groups for which the patterns can be found.

Each pattern detector can detect the following patterns:

Programmable “collision” pattern

Fixed “accelerator” pattern

The input data for the collision pattern detector are selected as shown below:

n-2 n-1 n Layer 1

n-1 n Layer 2

n Layer 3

n n+1 Layer 4

n n+1 n+2 Layer 5

n n+1 n+2 Layer 6

n in this diagram is the key wire group number, for which this particular pattern detector is searching the

patterns. The programming of the programmable collision pattern is implemented as a simple masking-

out of the bits, which we do not want to include in the pattern. Shown below is the pseudo-language

formula for pattern detection: number of layers hit for collision pattern =

(L1[n-2]& m1) | (L1[n-1]& m2) | (L1[n] & m3) +

(L2[n-1]& m4) | (L2[n] & m5) +

(L3[n] & m6) +

(L4[n] & m7) | (L4[n+1]& m8) +

(L5[n] & m9) | (L5[n+1]& m10) | (L5[n+2]& m11) +

(L6[n] & m12) | (L6[n+1]& m13) | (L6[n+2]& m14) ;

Lx in this expression means Layer x, [y] means bit y (from the layer), mz means collision pattern mask

bit z.

The accelerator pattern is a vertical pattern which cannot be reprogrammed. The formula for it looks like

this (see “formula for collision pattern diagram” above for explanation):

number of layers hit in the accelerator pattern =

L1[n] + L2[n] + L3[n] + L4[n] + L5[n] + L6[n] ;

Each pattern detector reports quality of the track that has been found, according to the following table:

Table 11: Quality codes

Layers hit in the pattern Quality code

3 or less 0

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4 1

5 2

6 3

There are several parameters, which the user can adjust, that change the functionality of the pattern

detector. They are described in this document, Table 3. Their names are:

trig_mode

nph_thresh

nph_pattern

acc_thresh

acc_pattern

drift_delay

Pattern detector’s dead time

Pattern detectors have “dead time”, individual for each detector. Dead time in one detector does not

affect any other detectors. The explanation is below:

On each BX, the number of layers that have hits in them is counted. Let’s call this count “sumac”. If

sumac is more or equal than nph_thresh parameter, an internal time counter (bxac) starts counting,

incrementing on each BX. Once this counter reaches value of drift_delay parameter, and if sumac

at that time is more or equal to nph_pattern parameter, the pattern is reported as detected. As long as

sumac >= nph_thresh, bxac continues counting and stops at the maximum value of 7. In order

for bxac to reset and start counting again, so another pattern can be detected, sumac must drop below

the value of nph_thresh parameter. Since sumac is the count of layers with hits, and these hits are

actually extended pulses from the output of the one-shots, it means that most of the one-shot pulses must

end in order to reset bxac.

An accurate simulation of the dead time requires implementation of the pattern detector logic as

described above. Making simplified assumptions does not always work.

3. Ghost Cancellation Logic (GCL)

The outputs of the pattern detectors are connected to the ghost cancellation logic.

Tracks passing through the chamber often get registered by two or more pattern detectors, especially if

the user programmed wide patterns. This way the “ghost” track(s) are reported along with the actual

track. To avoid that, GCL analyzes the pattern detector’s outputs and cancels the ghosts as shown below:

t - quality of current track candidate (WG)

vt – valid flag of current track candidate (WG)

top - quality of track candidate in WG+1 (same clock as t)

vtop – valid flag of track candidate in WG+1 (same clock as t)

bot - quality of track candidate in WG-1 (same clock as t)

vbot – valid flag of track candidate in WG-1 (same clock as t)

vtp – valid flag of track candidate in WG+1 or WG-1 up to 4 clocks in the past

if ((t <= top && vtop) || (t < bot && vbot)) vt = 0;

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else if (vtp) vt = 0;

4. Best track selector. The search goes on simultaneously for two tracks, TA and TB. Priority for TA is given to wiregroups

with larger numbers, priority in search of the TB is given to wiregroups with smaller numbers. It may

happen that TA==TB, in case there is just one track in the chamber. When TA and TB are found, the

following algorithm is used to determine the best (t1) and second best (t2):

// in the code below:

// nX_Y means wiregroup number of track Y (1=TA or 2=TB) of quality X (0,1,2,3)

// nX_Y signals are the outputs of the search modules

// NOTRK means "no track"

q1 = 0; q2 = 0; // zero qualities of t1, t2

w1 = 0; w2 = 0; // zero wiregroups of t1,t1

v1 = 0; v2 = 0; // zero valid flags of t1,t2

If (n3_1 != NOTRK)

begin

w1 = n3_1; q1 = 3; v1 = 1;

If (n3_1 != n3_2) begin w2 = n3_2; q2 = 3; v2 = 1; end Else

If (n2_1 != NOTRK) begin w2 = n2_1; q2 = 2; v2 = 1; end Else


If (n0_1 != NOTRK) begin w2 = n0_1; q2 = 0; v2 = 1; end

end

Else

begin

If (n2_1 != NOTRK)

begin

w1 = n2_1; q1 = 2; v1 = 1;




end

Else

begin

If (n1_1 != NOTRK)

begin

w1 = n1_1; q1 = 1; v1 = 1;



end

Else

begin

If (n0_1 != NOTRK)

begin

w1 = n0_1; q1 = 0; v1 = 1;

If (n0_1 != n0_2) begin w2 = n0_2; q2 = 0; v2 = 1; end

end

end

end

end

This “colliding” search algorithm makes the entire best track selector fit into one clock’s time (25 ns).

5. Track promotion. The best collision and accelerator tracks that are found in the previous step are modified according to the

following configuration variable:

alct_amode

Please see Table 3 for details.

Finally, the following parameters for each of the two best tracks are reported to the output of the board:

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Valid flag

Quality of track

Key wire group

Accelerator muon flag (1 means accelerator pattern was found)

TTC system TTC commands decoded by ALCT are shown in Table 12.

Table 12. TTC codes decoded by ALCT.

Command name Command code received from CCB

BC0 1

Resync 3

Start Trigger 6

Stop Trigger 7

In response to these commands, ALCT synchronization state machine operates as shown in Figure 1.

Figure 1. ALCT TTC state machine diagram.

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Test points and LEDs.

Table 13: Test points

Pin Name Description TH1-1 Input Enable see InputEnable command in Table 8 for explanation

TH1-2 L1A This signal is set to 1 when there was external L1A or internal L1A (if

enabled).

TH1-3 L1Awindow This signal shows a time window when the trigger data are being saved into

the internal memory. It should begin right after L1A and be l1a_window

clocks in length.

TH1-4 Ttc_stop_trigger Ttc_stop_trigger signal

TH1-5 Ttc_start_trigger Ttc_start_trigger signal

TH1-6 Ttc_bx0 Ttc_bx0 signal

TH1-7 FMM_trig_stop “Trigger” Stop signal

TH1-8 Ttc_L1reset Ttc_L1reset signal

TH1-9 Valid L Second best track valid bit

TH1-10 Valid H First best track valid bit

TH1-11 Valid Hd First best track valid bit, delayed by l1a_delay clocks

TH1-12 Write FIFO Write FIFO signal from DAQ data stream (bit 18)

TH1 is the header on the ALCT (near mezzanine board), the name TH1 is written on the board. -1, -2

and -3 are pin numbers in this header. Pins 1 and 2 are marked on the board.

The LEDs assignment is shown below:

Table 14: LEDs

LED Name Description D26 Jstate0 JTAG state machine state bit 0

D27 Jstate1 JTAG state machine state bit 1



Revision History

4/13/03 V2.4 AM Multiple errors fixed, text updated to describe all ALCT types.

Unimplemented features are excluded. DAQ data format added.

4/28/04 V2.5 AM DAQ format table fixed, in CRC and E0D words the first 4 bits are 0xD.

Test point table is updated.

10/26/05 V2.6 AM Table 3 bxc_offset parameter is loaded into BX counter on BC0 (request

from T.Y. and Wesley)

10/26/05 V2.6 AM Table 3 - lhc_cycle_sel parameter added

10/26/05 V2.6 AM Table 3 – fifo_pretrig offset is corrected (10, was 12 by mistake)

10/26/05 V2.6 AM In ALCT 2001 algorithm description, Ghost Cancellation Logic section is

modified to reflect changes in the firmware.

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10/26/05 V2.6 AM Table 8 – bxn_before_reset parameter added for LCT0 (request from T.Y.

and Wesley)

8/11/06 V2.7 AM Firmware versions for chambers with partially used inputs added (ALCT-

192 and 576). L1a_offset parameter default value corrected.

4/10/07 V2.8 AM added separate config register fields for accelerator track threshold

and pattern

YR is now extended config register, with just bit[0] used for test

mode enable

added YRread command

nph_pattern and acc_pattern added to DAQ01 format

fifo_pretrig description is updated thanks to JH

Trigger algorithm description updated to reflect the reduced latency

and q=0 valid scheme.

hit counter added

03/31/08 V2.9 AM DAQ-06 format inserted, 2001 DAQ format is removed

Trigger algorithm description elaborated a bit

09/12/08 V2.10 AM Virtex-E Firmware section split out of the rest of ALCT document

L1A_window made odd only, per message 34210 on 2008-09-09

from Greg and Jay.

LCT_bins quantity logic changed

LCT_bins padding added

parameter names as used in XML files added to Virtex config

register, per message 31711 from Jay on 2008-07-15

Virtex ID register updated

Algorithm description section corrected to describe Best Track

Selector better.

6/4/2009 V2.11 AM Loopback and error correction added for I/O cables, using UCLA

code as guidance

Output latency increased by 2 clocks because of that

07/06/10 V2.12 AM Zero suppression in DAQ data added

Extended configuration register size corrected

08/04/10 V2.13 AM Added padding words to DAQ, to make block's length a multiple of

4 as required by DDU

removed zero-suppression of entire time bin due to implementation

problem, only layers are suppressed.

06/18/11 V2.14 AM Fixed error in overflow detection of DAQ buffer, reworked L1A

fifo

03/01/2012 V2.15 AM Reverted to ISE version 8.2. Firmware compiled with ISE 10 is not

working on 4 ALCTs of different types for unknown reason.

03/19/2012 V2.16 AM With ISE 8.2, different set of ALCTs (of various types) is

malfunctioning, so the problem is not with ISE release

This version is compiled using ISE 10.1 again

Timing target is 21 ns (used to be 23 ns in the past)

Unused functionality is removed (hit counters, configuration

reporting). This brings LUT count down a little bit

Fmm_trig_stop signal is used to reset most of the logic now, both in

trigger and DAQ path. This is done to satisfy the simulator. Logic

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in the actual chip is reset on power-up to zeros, but simulator does

not take this into account.

Project settings are reworked to keep most of them as set by

default, with only absolutely necessary modifications

Complete timing simulation at 21 ns clock has shown a subtle

timing issue in ALCT-384. This has been fixed in this version

All other types of firmware – no problems.

09/10/2012 V2.17 AM Added firmware versions for Spartan-6 mezzanine card

Added SP6 flag to Virtex/Spartan-ID register and DAQ readout, so

the user can see which FPGA it is

Added SEU flag to Virtex/Spartan-ID and DAQ readout. This flag

works only in Spartan-6. It will be set to 1 if Spartan-6 detects an

SEU.

Fixed bit numbers in Table 2 (Virtex/Spartan ID register). Online

software uses correct bit numbers, but no one told me this table was

showing them incorrectly.

05/18/2017 V2.18 AM Added TTC state diagram and commands description

10/25/2018 V2.19 AM Added more details on dead time in pattern detectors

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