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ANALOG NON-LINEAR MULTI-VARIABLE FUNCTION EVALUATION BY
PIECE-WISE LINEAR APPROXIMATION
A Thesis
Presented to
The Graduate Faculty of The University of Akron
In Partial Fulfillment
of the Requirements for the Degree
Master of Science
Dileep Reddy Desai
August, 2010
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ANALOG NON-LINEAR MULTI-VARIABLE FUNCTION EVALUATION BY
PIECE-WISE LINEAR APPROXIMATION
Dileep Reddy Desai
Thesis
Approved: Accepted:
Co-Advisor Dean of the College
Dr. Joan E. Carletta Dr. George K. Haritos
Co-Advisor Dean of the Graduate School
Dr. Robert Veillette Dr. George R. Newkome
Committee Member Date
Dr. Kye-Shin Lee
Department Chair
Dr. Alex De Abreu-Garcia
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ABSTRACT
A method for the evaluation of non-linear multi-variable functions using analog
circuits is developed. The non-linear multi-variable functions are approximated with
piece-wise linear functions using a Chebyshev approximation technique. Then the
obtained linear equations are implemented using current-mode analog circuitry consisting
of current comparators and current mirrors. A quarter cycle of a sinusoidal function has
been approximated with two lines with a maximum error of 2.75% of the full-scale
output current range in the circuit simulations. A more complicated logarithmic function
of two variables that is useful as a logarithmic number system subtractor is also
approximated with two lines, with a maximum error of 4.26% in the circuit simulations.
Implementation of the logarithmic number system subtractor requires a min-max current
selector; this circuit sorts two input currents. The min-max current selector works for
input currents over a 20A range, from 70A to 90A, and has a maximum output
current error of 10nA. It uses a current comparator that has a worst-case input-offset
current of 5nA and a differential gain of 2.025V/nA. The logarithmic number system
subtractor can be used for image processing applications such as finding the forward and
backward differences of the neighboring pixels of an image.
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DEDICATION
Dedicated to my Parents and Sister.
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TABLE OF CONTENTS
........................................................................................................................................ Page
LIST OF TABLES ........................................................................................................... viiiLIST OF FIGURES ........................................................................................................... ix
CHAPTER
I INTRODUCTION ............................................................................................................ 1II BACKGROUND ............................................................................................................. 6
2.1 Piece-wise linear approximation ............................................................................... 62.2 Linear arithmetic units .............................................................................................. 92.3 Piece-wise linear function evaluator ....................................................................... 11
III DESIGN OF A MIN-MAX CURRENT SELECTOR................................................. 153.1 Design of the current comparator ............................................................................ 163.2 Design of the Schmitt trigger .................................................................................. 213.3 Design of the current mirrors and multiplexers ...................................................... 25
IV ANALOG IMPLEMENTATION OF A SINUSOIDAL FUNCTION OF ONEVARIABLE ................................................................................................................ 334.1 Approximation of sin(x1) ......................................................................................... 334.2 Circuit implementation of the function sin(x1) ........................................................ 36
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4.2.1 Design of the arithmetic unit ............................................................................ 374.2.2 Design of the current comparator and the multiplexer ..................................... 39
4.3 Simulation Results................................................................................................... 43V ANALOG IMPLEMENTATION OF LOGARITHMIC NUMBER SYSTEM (LNS)
SUBTRACTION......................................................................................................... 465.1 Approximation of LNS subtraction ......................................................................... 475.2 Circuit implementation of LNS subtraction ............................................................ 51
5.2.1 Design of the min-max current selector ........................................................... 525.2.2 Design of the arithmetic unit ............................................................................ 525.2.3 Design of the current comparator and the multiplexer ..................................... 55
5.3 Simulation results .................................................................................................... 575.4 Application of LNS subtraction .............................................................................. 65
VI CONCLUSION AND FUTURE WORK .................................................................... 67BIBLIOGRAPHY ............................................................................................................. 70APPENDIX A ................................................................................................................... 73
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LIST OF TABLES
Table .............................................................................................................................. Page
3.1 Maximum absolute current errors from corner simulations of the min-max current
selector ........................................................................................................................ 30A.1 Channel dimensions of transistors in min-max current selector ................................ 73A.2 Channel dimensions of transistors in the analog implementation of the sine
function ....................................................................................................................... 74A.3 Channel dimensions of transistors in the analog implementation of LNS
subtraction ................................................................................................................... 75
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LIST OF FIGURES
Figure.............................................................................................................................Page
2.1: Linear arithmetic unit using a voltage-mode approach ............................................... 92.2: Block diagram of a linear arithmetic unit using a current-mode approach ............... 102.3: Block diagram of piece-wise linear function evaluator ............................................. 113.1: Block diagram of a min-max current selector ........................................................... 153.2: Block diagram of proposed current comparator ........................................................ 163.3: Schematic of a current comparator ............................................................................ 173.4: Transfer characteristics of different transistors of a current comparator in common-
mode for two different common-mode input currents .............................................. 193.5: Differential response of current comparator for three different common-mode
currents showing voltages Vout1and Vout2................................................................. 213.6: Schematic of Schmitt trigger circuit .......................................................................... 223.7: Voltage transfer characteristics of the Schmitt trigger circuit ................................... 233.8: Output voltage of current comparator (Vout) and Schmitt trigger (Vst) for three
different common-mode input currents ..................................................................... 243.9: Schematic of current mirrors and multiplexers.......................................................... 253.10: Schematic of min-max current selector ................................................................... 263.11: Output currents (Ihighand Ilow) of min-max current selector for 85A common-mode
current, both full scale and magnified ....................................................................... 27
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5.7: Total schematic of analog implementation of LNS subtraction. ............................... 585.8: LNS subtraction results when 1is fixed at 80A and 2is varying. ....................... 595.9: Plots of error between outputs when
1is fixed at 80A and
2is varying. ............ 60
5.10: LNS subtraction results when 1is fixed at 70A and 2is varying. ..................... 615.11: Plots of error between outputs when 1is fixed at 70A and 2is varying. .......... 625.12: LNS subtraction results when 1is fixed at 90A and 2is varying. ..................... 635.13: Plots of error between outputs when 1 is fixed at 90A and 2is varying. ......... 64
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approximations implemented using FPGAs, some of which are presented in [3, 4, 5, 6].
All of these techniques use digital hardware and operate on digital inputs.
In some applications, functions must be evaluated on analog input signals. In this
case, one implementation possibility is to first convert the analog input signals to digital
signals and then use digital function evaluation methods. This requires the use of analog-
to-digital converters (ADCs). The accuracy of the evaluated function depends on the
resolution of the ADC, and the speed of evaluation depends on the ADCs conversion
time.
Alternatively, a function can be evaluated on analog input signals directly by
using analog electronics, using components such as operational amplifiers and
comparators. Implementing functions with analog circuitry has several advantages. No
ADCs are needed, and so the delay associated with the ADC conversion time is
eliminated. The analog circuitry is typically lower in cost, simpler, and much faster than a
digital implementation.
The goal of this thesis is to show a process for the design of analog evaluation
hardware for non-linear multi-variable functions using analog circuits with analog input
signals. The ranges of the input and the output variables are mapped to ranges of currents
or voltages. Then the non-linear multi-variable function is represented with a piece-wise
linear approximation, by breaking the input space into regions and approximating the
function within each region with a linear function. The linear functions and the
boundaries between regions are chosen so as to minimize the worst-case error between
the approximation and the original function. Then the linear functions are implemented
using analog circuitry and the output from the correct linear function for the given set of
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inputs is selected. For the examples given in this thesis, the goal is that the maximum
error in the piece-wise linear approximation itself should not exceed 10% of the output
current or voltage range, and that the additional error introduced by the analog circuit
implementation should not be more than another 2%.
To determine in which region a particular set of input values lies, so that the
appropriate line in the piece-wise linear approximation can be routed to the output,
comparators are needed. In this thesis, a current-mode approach is followed, so a current
comparator is designed to compare linear combinations of input currents with constant
currents. A current comparator of similar design is also used in a min-max current
selector, which is needed to sort currents for our second example function which includes
an absolute value. For the min-max current selector application, both inputs to the current
comparator may vary through the full input current range; therefore, the common-mode
input current range of this current comparator must cover this full current range. In this
thesis, a novel current comparator is designed which has the required full-scale common-
mode input current range and also a high differential gain.
In this thesis two non-linear functions are implemented as examples. A non-linear
function of a single variable sin(1) on the interval 0, 2has been approximated using apiece-wise linear approximation with two regions and then implemented using analog
circuitry. The input current corresponding to 1 ranges from 70A to 90A. Themaximum error in the output current of the analog implementation is 2.75% of the full-
scale output current range.
With a similar approach, a more complicated nonlinear function of two variables
is implemented. This function is referred to as a logarithmic number system (LNS)
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subtraction; if two real values and are represented in LNS representation as 1 = log10 + , and 2 = log10 + , respectively, their difference in LNSrepresentation is defined as
log10
+
. To ensure that LNS subtraction is
always defined, the absolute value of the difference is calculated. The inputs
corresponding to 1and 2range from 70A to 90A. The maximum error in the analogimplementation is 4.26% of the full-scale output current range.
The application motivating the work in this thesis to implement LNS subtraction
involves processing the outputs of a logarithmic CMOS image sensor. Each pixel
produced by a logarithmic CMOS image sensor is in the form of an analog current; this
current is a shifted and scaled version of the logarithm of the current produced by the
photodiode in the corresponding pixel sensor, which is in turn related to the intensity of
the light falling on the photodiode. Thus, the pixel sensor output current can be viewed as
an LNS representation of the light intensity.
Usually, the individual pixel sensor output currents of the logarithmic CMOS
image sensor are converted one by one into digital pixels and then processed digitally.
The analog-to-digital conversion itself needs several clock cycles. To reduce the time and
hardware required for processing the outputs of a logarithmic CMOS image sensor,
analog circuits may be used. It is common to need to calculate forward differences or
backward differences, which require the subtraction of neighboring pixels. Because the
pixels themselves are in LNS representation, this subtraction of neighboring pixels
requires LNS subtraction. In this thesis, the designed LNS subtraction circuit is
appropriate for this application.
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The remainder of this thesis is organized as follows. Related background work is
described in Chapter II. The design, operation and performance of a min-max current
selector are discussed in Chapter III. The implementation of a non-linear function of a
single variable sin(1) using analog circuits is described in Chapter IV. Theimplementation of a non-linear function of two variables log + usinganalog circuits, when log10 + and log10 + are given as inputs, isdiscussed in Chapter V. Finally, conclusions are drawn and possible future work is
described in Chapter VI.
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CHAPTER II
BACKGROUND
Analog circuits are capable of evaluating functions that are linear combinations of
variables and constants with ease. Such linear combinations of variables and constants
require the multiplication of variables by constant scaling factors and the addition of
variables. If variables are represented as analog voltages, multiplication by scaling factors
and addition can be done simply using operational amplifiers and resistors. If variables
are represented as analog currents, current mirrors can be used.
A non-linear multi-variable function can be implemented with analog circuits if it
can be approximated as a piece-wise linear function, using different linear functions for
different ranges of the inputs. Generally, the more linear functions pieced together to
produce an approximation, the lower the error of that approximation, since the
approximation will be better able to follow the bends of the function. This chapter
describes a technique for piece-wise linear approximation, methods for evaluating linear
functions of multiple variables, and finally an architecture for implementing a piece-wise
linear function.
2.1 Piece-wise linear approximation
A piece-wise linear approximation to a non-linear multi-variable function divides
the input space of the function into a number of regions, and approximates the function in
each region as a linear combination of the inputs. Any one of the several piece-wise
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approximated. Together, the 2r fitting points define a set of r lines to be used for the
piece-wise linear approximation; if the 2r fitting points are sorted in the order of
increasing input values, and then split into pairs, each pair defines one line. The
breakpoints between the subintervals are the intersections between pairs of successive
lines.
1. To start, an initial set of 2rfitting points is required. Fitting points are placed at thestart and the end points of the range of the input variable. These are the terminal points
of the function. The remaining 2r2 fitting points are chosen arbitrarily within therange. The initial piece-wise linear approximation is constructed using these 2rfitting
points.
2. The error between the resulting piece-wise linear approximation and the function iscalculated, and the points corresponding to the worst-case errors in each subinterval
are found. These points are termed local error peaks.
3.In each subinterval, the fitting point nearer to the local error peak is moved a givendistance towards the local error peak. Moving the fitting points in this way will cause
the worst-case error to decrease.
4. Steps 2 and 3 are repeated until the local error peaks in all subintervals are equal inmagnitude.
The result of the Chebyshev approximation technique is a set of lines that approximates
the function throughout the input space in such a way that the worst-case errors of the
approximation in each region are equal in magnitude.
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2.2 Linear arithmetic units
Implementation of the proposed analog non-linear multi-variable function
evaluator requires analog implementation of linear functions of the form
= 11 + 22 + + + , (2.2)where 1, 2, , are the input variables to the function, is the scaling factorcorresponding to the variable , and c is a constant. A block of analog circuitry thatevaluates a linear function is termed a linear arithmetic unit. A linear arithmetic unit is
implemented using either a voltage-mode or a current-mode approach. For a voltage-
mode approach, the input variables 1, 2, , and the outputyare mapped to a set ofvoltages 1, 2, , and . For a current-mode approach, they are mapped to a set ofcurrents 1, 2, , and .
To implement the linear function using a voltage-mode approach, an operational
amplifier with some resistors is required as shown in Fig. 2.1. The operational amplifier
v1
v2
vn
vc
R1
R2
Rn
R
Rf
vo
c
f
n
n
fff
o vR
Rv
R
Rv
R
Rv
R
Rv 2
2
1
1
Figure 2.1: Linear arithmetic unit using a voltage-mode approach
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circuit scales each input voltage by its respective scaling factor and producesan output voltage equal to the sum of all the scaled input voltages. The scaling factors of
the input voltages (i.e., the resistor ratios
) are related to the linear function
coefficients in a way that depends on the mappings between the input variables andthe input voltages . Similarly, the constant cis implemented using a voltage and aresistorR.
To implement the linear function using the current-mode approach, several scaled
current mirrors are required as shown in Fig. 2.2. The current mirrors produce mirrored
versions of the input currents 1, 2, , , each scaled by its respective scaling factor. Thescalings are achieved by setting the aspect ratios of the transistors in the current mirrors
appropriately. The constant in the linear function can be implemented by using a constant
Scaled
currentmirror
i1 i2 in
p1i1 p2i2 pnin
Output (io)
Constant
currentsource
ic
Scaled
currentmirror
Scaled
currentmirror
cnno iipipipi 2211
Figure 2.2: Block diagram of a linear arithmetic unit using a current-mode approach
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current source. The scaling factors for the input currents (i.e., the coefficients ) arerelated to the linear function coefficients in a way that depends on the mappingsbetween the input variables and the input currents . Similarly, the constant c ismapped to a current which is produced by the constant current source. Finally, thelinear function is implemented by summing all of the currents at a node.
2.3 Piece-wise linear function evaluator
Fig. 2.3 shows the block diagram of an analog implementation of a piece-wise
linear function of multiple variables. Linear arithmetic units are used to implement each
of the linear expressions in the piece-wise linear function. The region decoder determines
which one of the linear expressions represents the correct output, and controls the r-to-1
multiplexer to pass the output of the corresponding linear arithmetic unit through to the
output of the piece-wise linear function evaluator.
To implement the region decoder, a set of comparators is needed to select the
correct region for the given set of inputs. The input variables 1, 2, , (coded in
Region
Decoder
Linear
Arithmetic
Unit1
Linear
Arithmetic
Unit 2
Linear
Arithmetic
Unit r
x1x2 xn
y1 y2 yr
r-to-1
MultiplexerSelect
Output f(x1, x2, , xn)
Figure 2.3: Block diagram of piece-wise linear function evaluator
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implementation as either voltages or currents) will satisfy a particular linear inequality
condition for each region. To implement these conditions, the region decoder may
incorporate additional linear arithmetic units as well as comparators and decoding logic.
The outputs of the decoding logic are fed to the multiplexer as select control signals.
In addition to the region decoder and the linear arithmetic units already described,
the piece-wise linear function evaluator requires an r-to-1 multiplexer. The multiplexer
routes the output of the one arithmetic unit selected by the region decoder to the output of
the system. The multiplexer can be implemented using transmission gates.
When the voltage-mode approach and the current-mode approach to analog
evaluation of a piece-wise linear function are compared, the current-mode approach has
the advantage that it requires less hardware than the voltage-mode approach. It uses no
operational amplifiers; further, it requires no resistors, which are difficult to implement
accurately in integrated circuits. For these reasons a current-mode approach is a good
choice for analog evaluation of piece-wise linear functions and is used in this thesis.
To implement the region decoder needed for a current-mode approach, a current
comparator is needed. A current comparator should work with a specified accuracy over
its entire input current range. Several different current comparator design strategies have
been reported. In [10], a single input current is compared with multiple fixed threshold
currents using simple current mirrors. Circuits in [11, 12] are designed to determine
whether a single input current is leaving or entering the circuit, effectively comparing the
input current with zero. Another current comparator circuit in [13] compares a single
input current with a fixed reference current by using a modified Wilson current mirror.
All of these designs effectively compare one variable current with a fixed value; for our
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application, two variable input currents must be compared. The current comparator
circuit presented in this thesis is designed by modifying the circuit proposed in [10] to
accommodate two variable input currents, while achieving good sensitivity and common-
mode response.
In some cases, including the example in Chapter V, the inputs to the non-linear
multi-variable function must be sorted before evaluating the piece-wise linear function.
As the current-mode approach is implemented, a current sorter is needed to sort the
inputs. A current sorter takes in a number Nof input currents, and provides copies of the
same currents, sorted in order of magnitude, at Noutputs. The basic building block for a
current sorter is a min-max current selector. This is a circuit that takes two input currents,
and provides two output currents, one a mirrored copy of the smaller of the two input
currents, and one a mirrored copy of the larger of the two input currents.
Several min-max current selectors have been proposed in the literature [14-19].
Some are based on current-mode winner-take-all networks [14, 15, 16, 17]; a current
conveyer [18] and self-controlled cross-coupled transistors [19] have also been proposed.
The circuits can be compared in terms of the range of input currents on which they work,
and how closely the output currents match the input currents. Of the winner-take-all
networks [14, 15, 16, 17], the most accurate has an input range of 29A and a maximum
output current error of 10nA. The other approaches [18, 19] provide less accuracy and a
smaller input range. In this thesis, conventional current mirrors and the current
comparator already mentioned are used to construct the min-max current selector, to
obtain accuracy similar to that of the most accurate of the current-mode winner-take-all
circuits. Chapter III presents the design of a min-max current selector, including the
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current comparator that accommodates two variable inputs. The comparator is also used
in Chapters IV and V in region decoders for evaluating our two example non-linear
functions.
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CHAPTER III
DESIGN OF A MIN-MAX CURRENT SELECTOR
When a non-linear multi-variable function evaluation is implemented with analog
circuits, it may require the input variables of the function to be sorted. For a current-mode
approach, a current sorter is needed to sort the variables. Any number of currents may be
sorted by sorting two currents at a time. A min-max current selector is a circuit that takes
as input two currents, and provides as output two currents, one a mirrored copy of the
smaller of the two input currents, and one a mirrored copy of the larger of the two input
currents.
The min-max current selector described in this chapter operates for input currents
ranging from 70A to 90A. The block diagram of the min-max current selector is
Current
Comparator
Schmitt
Trigger
Current
Mirrors and
Multiplexer
I1
I2
Vout2
Ilow
Ihigh
Select
Figure 3.1: Block diagram of a min-max current selector
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shown in Fig. 3.1. The min-max current selector has three distinct parts: a current
comparator that determines which input current is larger, a Schmitt trigger circuit that
sharpens the output of the current comparator, and current mirrors and multiplexers that
mirror the input currents and route the appropriate mirrored current to each output. These
three parts are described separately.
3.1 Design of the current comparator
A block diagram of the current comparator is shown in Fig. 3.2. The current
comparator has two stages, a differential current amplifier stage to produce a voltage
proportional to the difference between the input currents, and a gain stage to drive the
output towards the rails. The differential current amplifier stage consists of a PMOS
cascode current mirror and two NMOS cascode current mirrors, with the two NMOS
cascode current mirrors acting as a differential pair, and the PMOS cascode current
Figure 3.2: Block diagram of proposed current comparator
PMOS CascodeCurrent Mirror
Gain Stage
Vout1Vout2
I1
NMOS CascodeCurrent Mirror 2
VDD
I2
NMOS CascodeCurrent Mirror 1
I1
Differential Current Amplifier Stage
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mirror acting as the load. It is similar to the structure in [17], but replaces simple current
mirrors with cascode current mirrors. Using cascode current mirrors increases the
resolution of the current comparator while keeping the area of the overall current
comparator reasonably small, because even relatively short transistors in a cascode
current mirror can mirror current more accurately than longer transistors in a simple
current mirror.
A transistor-level circuit diagram for the proposed current comparator is shown in
Fig. 3.3, where the two input currents are shown as current sources I1and I2within the
circuit. The first NMOS cascode current mirror produces a copy of input current I1at the
drain of transistor M2, and then the PMOS cascode current mirror produces another copy
of I1 at the drain of transistor M6. Simultaneously, the second NMOS cascode current
mirror produces a copy of input current I2at the drain of transistor M4. The differential
M1 M2
M5 M6
M4A
M10
M9
M3A
M6AM5A
VDD Gain Stage
M2AM1A
M4 M3
M7
M8
Vout1 Vout2
I1
I2
PMOS Cascode
Current Mirror
NMOS Cascode
Current Mirror 1
NMOS Cascode
Current Mirror 2
V1
Differential Current
Amplifier Stage
Figure 3.3: Schematic of a current comparator
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operation of the comparator results from connecting the drains of M6 and M4 in series.
When current I1is greater than current I2, the PMOS source tries to force a larger current
through the NMOS sink. As a result, the voltage Vout1 increases. Similarly, when I2 is
greater than I1, the voltage Vout1decreases.
The sizes of the transistors in the differential current amplifier stage are chosen
considering both the differential gain and the bias point. The gain of the differential
current amplifier is determined by the output resistances of the PMOS and NMOS current
mirrors. The gain of the differential current amplifier stage can be increased by increasing
the transistor lengths, or, as done here, by using cascoded transistors. The relative sizes of
the PMOS cascode current mirror and the two NMOS cascode current mirrors were
chosen so as to give a Vout1 of half of VDD(2.5V) for a midrange common-mode input of
80A.
Because the current comparator must work over a range of input currents, the
common-mode response of the differential current amplifier is important. A look at the
transfer characteristics of transistor combinations M2/M2A, M4/M4A, M5/M5A, and
M6/M6A helps to illustrate how Vout1 changes with the common-mode input. Fig. 3.4
shows these transfer characteristics. Transistors M5 and M5A are a cascoded
combination of diode-connected transistors; together they follow a square-law
characteristic, as shown in the figure. This curve remains fixed irrespective of variations
in the input currents. If the two input currents I1and I2are equal, the transistors M1 and
M1A will have the same gate voltages, respectively, as M3 and M3A. Further, the
transistor combinations M2/M2A and M4/M4A will have the same drain transfer
characteristics.
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The voltage V1 is determined by the point of intersection of the drain transfer
characteristic of transistor combination M2/M2A and the square-law curve of transistor
combination M5/M5A. As we vary the input currents, this point of intersection will vary
along the square-law curve of transistors M5/M5A. Thus as I1 and I2increase together, V1
will decrease.
The voltage Vout1 is determined by the point of intersection of the drain transfer
characteristics of M6/M6A and M4/M4A. The drain transfer characteristic of M6/M6A
will be governed by the gate voltages of M5/M5A (which are equal to the gate voltages
of M6/M6A) and this curve intersects the square-law curve of M5/M5A at the point
where VD,M6 = VG,M6. This means that the point of intersection of the drain transfer
Figure 3.4: Transfer characteristics of different transistors of a current comparator in
common-mode for two different common-mode in ut currents
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
10
20
30
40
50
60
70
80
90
100
DrainCurrents(A)
Drain Voltages (V)
Transfer characteristics ofM2/M2A & M4/M4A for
80A Input Current
Transfer characteristics ofM2/M2A & M4/M4A for
90A Input Current
Transfer characteristics of
M6/M6A for 80AInput Current
Transfer characteristics of
M6/M6A for 90A
Input CurrentTransfer characteristics ofM5/M5A
Vout1
for 90A
Common mode current Vout1for 80A
Common mode current
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characteristics of M4/M4A and M6/M6A is the same as the intersection point of the drain
transfer characteristic of M2/M2A and the square-law curve of M5/M5A. Since M4/M4A
and M2/M2A have the same drain transfer characteristics, the voltage Vout1is equal to V1.
As the common-mode input current varies, Vout1varies according to the square-
law characteristic of M5/M5A. Fig. 3.4 shows the drain characteristics of M4/M4A and
M6/M6A for two different common-mode input currents. At higher common-mode input
currents, Vout1is decreased, and at lower common-mode input currents, Vout1is increased.
The sensitivity of Vout1 to the common-mode input current depends on the W/L ratio of
the PMOS current mirror; for bigger W/L ratios, the PMOS transistors M5/M5A have
steeper square-law curves, so that their drain-to-source voltages (and therefore Vout1) vary
less with the current through them. The W/L ratio of the PMOS current mirror should be
made large enough that variations in the bias point Vout1are small.
The differential current amplifier is followed by a gain stage, implemented as a
pair of cascaded push-pull amplifiers that drives the output voltage closer to the supply
rails. The push-pull amplifier outputs are biased at half of VDDfor a midrange common-
mode input. The variation in Vout1 resulting from the common-mode variations of the
input currents is small enough that the comparator output is not driven to a supply rail
unless a differential input current is applied.
Fig. 3.5 shows the differential response of the current comparator for three
different common-mode input currents. From the plot for a midrange common-mode of
80A, we can see that the voltage Vout1correctly indicates which input current is larger; it
is above 2.5V (half of VDD) when the input current difference is negative, and below
2.5V when the difference is positive. With common-mode changes, the plots cross the
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direction. The output makes a sharp transition from 0V to 5V when the input crosses
1.9V in a falling direction.
The positive feedback in the Schmitt trigger circuit and the resulting hysteresis in
its characteristic are caused by transistors M13 and M14. When the input of the Schmitt
trigger is low, M11 and M11A are on, and the output Vstis at VDD. The transistor M14 is
also on, providing a positive feedback that tends to keep the output high, by pulling the
source terminal of M12 above ground. When the input rises to 3V, transistors M12 and
M12A begin to turn on in spite of M14spositive feedback. When this happens Vstbegins
to fall, and transistor M14 turns off, eliminating the positive feedback that had been
pulling Vst up. Then, Vst decreases abruptly toward a steady state near ground. At the
same time, M13 turns on, providing positive feedback to pull V stdown, and transistors
M11 and M11A turn off. Thus, the output voltage is stable at the two rails, and makes
abrupt transitions between them depending on the variations in the input voltage.
Figure 3.7: Voltage transfer characteristics of the Schmitt trigger circuit
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vout2
(V)
Vst
(V)
Vst
when Vout2
is increasing
Vst
when Vout2
is decreasing
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The Schmitt trigger output Vst and its complement (Select), derived using an
inverter, are used as the select control signals for the multiplexers that route the mirrored
input currents, smoothly and unambiguously, to the proper outputs. The abrupt switching
of the Schmitt trigger output minimizes the transient current spikes that could otherwise
occur at the multiplexer outputs.
The differential transfer characteristics of the current comparator and the Schmitt
trigger, considered together for three different common-mode current inputs, are shown
in Fig. 3.8. All of the transitions are sharp; the Schmitt trigger output makes a transition
from supply rail to supply rail for a 0.1nA change in the differential input current. The
output transitions for rising and falling differential input currents are so close together
that they cannot be distinguished in the figure. The transitions happen not always at zero,
Figure 3.8: Output voltage of current comparator (Vout) and Schmitt trigger (Vst) for three
different common-mode input currents
-30 -20 -10 0 10 20 300
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I2-I
1(nA)
V
out2
&
Vst
(volts)
Vout2
for I1=70A
Vout2
for I1=80A
Vout2
for I1=90A
Vstfor I1=70A whenI2is increasing
Vst
for I1=80A when
I2is increasing
Vst
for I1=90A when
I2is increasing
Vst
for I1=70A when
I2is decreasing
Vst
for I1=80A when
I2is decreasing
Vstfor I1=90A whenI2is decreasing
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but at different values of the differential input current depending on the common-mode
input current. The figure shows that over the common-mode range, an input current
difference of 5nA can be resolved; i.e., a difference of 5nA or more in the input currents
will result in the proper digital output voltage, regardless of the common-mode input
current.
3.3 Design of the current mirrors and multiplexers
In addition to the current comparator and the Schmitt trigger circuits already
described, a min-max current selector needs current mirrors to produce copies of the
input currents and current multiplexers to route the appropriate copy to each output. The
circuit diagram for these additional components is shown in Fig. 3.9.
When Select , which is the output Vstof the Schmitt trigger, is VDD, indicating thatI2is the larger of the two input currents, transistors M27, M28, M29 and M30 are off and
M17
M18 M19
M19AM18A
VDD
M17A
M26M25
M20
M20A`
`
M21
M22 M23
M23AM22A
M21A
M24
M24A`
`
M1
M3AM1A
M3
M27 M28 M29 M30 M31 M32
Ilow Ihigh
I1'
Mux1 Mux2
I1 I2
LoadLoad
I2'
Select
Select
(Vst)
Figure 3.9: Schematic of current mirrors and multiplexers
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Figure3.10
:Schematicofmin-maxcurrentselector
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transistors M25, M26, M31 and M32 are on. Then the mirrored version I1' of input
current I1 is passed through Mux1 to Ilow, and the mirrored version I2' of input current I2is
passed through Mux2 to Ihigh. Similarly, a Schmitt trigger output of ground routes I2' to
Ilowand I1' to Ihigh. The current mirrors used to produce I1' and I2' must be long enough to
mirror the currents accurately, independent of the load connected to them. The transistors
in the multiplexers should be wide enough that there is not much voltage drop across
them when they are on.
The full schematic of the min-max current selector is shown in Fig. 3.10. The
channel dimensions of the transistors are listed in Table A.1 in Appendix A. In addition
70 72 74 76 78 80 82 84 86 88 9070
75
80
85
90
I2(A)
Ilow,
Ihigh
(A)
Ilow
Ihigh
I1
I2
84.99 84.992 84.994 84.996 84.998 85 85.002 85.004 85.006 85.008 85.0184.985
84.99
84.995
85
85.005
85.01
85.015
I2(A)
Ilow,
Ihigh
(A)
Ilow
Ihigh
I1
I2
Currents routed
incorrectly
Currents mirroredinaccurately
{
Figure 3.11: Output currents (Ihighand Ilow) of min-max current selector for 85A
common-mode current, both full scale and magnified
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to the channel dimensions (i.e. W L), the number of fingers in each transistor is also
given in the table. When a transistor has multiple fingers, it means that it is composed of
multiple transistors of the given channel dimensions connected in parallel. Thus, the
effective width of the transistor is the given dimension W multiplied by the number of
fingers.
The min-max current selector is simulated with both the input currents (I1and I2)
varying from 70A to 90A. Fig. 3.11 shows the current outputs (Ihighand Ilow) of a min-
max current selector for an example with one input current fixed at 85A, and the other
input current swept from 70A to 90A. The first plot in the figure indicates that the
input currents are correctly routed to the proper outputs. The second plot of Fig. 3.11 is a
Figure 3.12: Output currents (Ihighand Ilow) of min-max current selector for 70Acommon-mode current, both full scale and magnified
69 69.2 69.4 69.6 69.8 70 70.2 70.4 70.6 70.8 7169
69.5
70
70.5
71
I2(A)
Ilow,Ihigh
(A)
Ilow
Ihigh
I1
I2
69.985 69.988 69.991 69.994 69.997 70 70.003 70.006 70.009 70.012 70.015
69.99
70
70.01
70.02
I2(A)
Ilow,Ihigh
(A)
Ilow
Ihigh
I1
I2
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magnified view centered on the point at which both currents are 85A. This plot shows
that the input currents are routed to the correct outputs except for input current
differences between
2nA and 0nA, i.e., for I2between 84.998A and 85.000A.
Simulations for common-mode input currents of 70A and 90A are also
performed. For a 70A common-mode input simulation, one input current is fixed at
70A and the other input current is swept from 69A to 71A; the simulation results for
this case are shown in Fig. 3.12. The second plot of Fig. 3.12 shows that the output
currents are correctly routed except for current differences between 0nA and 3.5nA. For a
90A common-mode input simulation, one input current is fixed at 90A and the other
input current is swept from 89A to 91A; the simulation results for this case are shown
in Fig. 3.13. The second plot of Fig. 3.13 shows that output currents are correctly routed
Figure 3.13: Output currents (Ihighand Ilow) of min-max current selector for 90A
common-mode current, both full scale and magnified
89 89.2 89.4 89.6 89.8 90 90.2 90.4 90.6 90.8 91
89
89.5
90
90.5
91
I2(A)
Ilow
,Ihigh
(A)
Ilow
Ihigh
I1
I2
89.98 89.985 89.99 89.995 90 90.005 90.01 90.015 90.0289.97
89.98
89.99
90
90.01
I2(A)
Ilow,Ihigh
(A)
Ilow Ihigh I1 I2
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except for current differences between 5nA and 0nA. This maximum absolute error of5nA is the worst-case routing error over the entire common-mode input range.
Output errors are also introduced by the current mirror circuits, regardless of the
common-mode or differential current values. Figures 3.11, 3.12, and 3.13 show that the
error introduced by the current mirrors is about 5nA over all simulated conditions. When
combined with the worst-case routing error of 5nA, this results in a total worst-case error
of 10nA in the output current. The output currents of the min-max current selector are
used as inputs to the region decoder and the arithmetic unit while evaluating a function.
The errors in the output currents may cause the region decoder to select the wrong region
for a set of input currents if they are very near to the boundary of a region. The errors in
the output currents will also affect the calculations done in the arithmetic units, which
will increase the error in the output of the function evaluated.
The input-offset error and the total output current error reported above were found
for a typical-typical (TT) model neglecting any process variations. The simulations were
repeated using 3 process variation models for four process corners: slow-slow (SS),
Table 3.1 Maximum absolute current errors from corner simulations of the min-maxcurrent selector
Corner Input-offset error Total output current error
TT 5nA 10nA
SS (worst speed) 286.7nA 485.8nA
FF (worst power) 42.1nA 86.5nA
FS (worst one) 16.8nA 32.2nA
SF (worst zero) 12.5nA 22nA
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fast-fast (FF), fast-slow (FS), and slow-fast (SF). Table 3.1 lists the maximum absolute
errors found over the common-mode input current range for each case. The worst case,
which is for the SS corner, represents about a 1.5% input offset error and a 2.5% output
current error. The issue of reducing the sensitivity of the design to process variations will
be a possible subject of future work.
To determine the speed of response of the min-max current selector, a transient
simulation is done in which a fixed current of 80A is applied to the input I2, while a step
from 70A to 90A is applied to the other input I1. The results are shown in Fig. 3.14.
Both the output currents Ihighand Ilowsettle to within 1% of their final values in 168ns.
Figure 3.14: Step response of min-max current selector
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.470
80
90
Time (s)
I1,
I2(A)
I1
I2
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.440
60
80
95
Time (s)
Ilow(
A)
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.440
60
80
95
Time (s)
Ih
igh
(A)
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The first 100ns of delay is the propagation delay through the current comparator. During
this time, Ilowfollows the change in I1. At about t = 1.11s, the output of the comparatorswitches. The current spikes seen at this time, result from imperfect synchronization of
the switching of the transmission gates in the multiplexers.
Thus the design of a min-max current selector is completely described and
verified with all the simulation results in this chapter. The min-max current selector is
needed to sort the variables in some multi-variable functions. In the next chapter, the
design of a non-linear function of a single variable sin(1) using analog circuits isdiscussed. In Chapter V, the implementation of a logarithmic number system (LNS)
subtraction using current-mode analog circuits is discussed. The LNS subtraction is a
more complicated non-linear function of two variables in which a min-max current
selector is needed to sort the two input currents.
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CHAPTER IV
ANALOG IMPLEMENTATION OF A SINUSOIDAL FUNCTION OF ONE
VARIABLE
In this chapter, the design of an integrated circuit to evaluate a nonlinear function
of a single variable is presented. The function sin(
1) is implemented as an example. A
piece-wise linear approximation of sin(1) on the interval 0, 2 is found, and analogcircuitry is designed to evaluate the linear functions and to select the appropriate one to
produce the output. With a similar approach, the implementation of a logarithmic number
system subtraction, which is a more complicated function of two variables, is discussed
in Chapter V.
4.1 Approximation of sin(1)On the interval 0,
2, the function sin(1) is to be approximated as a piece-wise
linear function using the Chebyshev approximation algorithm. This algorithm chooses the
slopes and y-intercepts of the lines, and the breakpoints between the lines, so as to
minimize the worst-case error between the approximation and the function sin(1).Providing an approximation to evaluate the function sin(1) over the input interval 0, 2is enough to be able to evaluate sin(1) for all other real inputs; other input ranges aresimply shifted or reflected copies of the interval 0,
2.
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The piece-wise linear approximation to be used here involves the combination of
two linear expressions, as
sin1 11 + 1, 0 1 21 + 2, 1 2 (4.1)where 1and 2are the slopes of the lines, 1and 2are the y-intercepts of the linesand bis the breakpoint between the two lines. These equations can be implemented using
analog circuits once the slopes and the y-intercepts have been determined.
Fig. 4.1 shows the first quarter cycle of the function sin(1) and its piece-wiselinear approximation using two lines, found with a Chebyshev approximation. On the
figure, the two lines are annotated with their slopes and y-intercepts. Fig. 4.2 shows the
Figure 4.1: Plot of piece-wise linear approximation of sin(x1) with two lines
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.57080
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
X: 0
Y: 0.02425
x1(radians)
Sin(x1
)
X: 1.571
Y: 1.024
X: 0.9299
Y: 0.8255
Function Sin(x1)
Piece-wise linear approximation
Slope=0.8623255Y-intercept=0.024251
Slope=0.310189Y-intercept=0.53701
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plot of the error between the non-linear function and its approximation. From Fig. 4.2, it
is seen that the maximum and minimum errors for the piece-wise linear approximation
are equal in magnitude.
Knowing the slopes and y-intercepts of the two lines for the approximation, the
approximation can be easily implemented with analog circuitry. To implement the linear
functions using analog circuitry, the input and output variables of the function sin(1)have to be mapped to analog signals. The analog input current I infrom 70A to 90A is
used to represent the range of input 1from 0 to2. A linear mapping is assumed betweenthe independent variable 1 and the input current Iin, so that Iin = 1 + , where = 20A
2 = 12.7324A and = 70A. Similarly, a range of analog output currents Iout
Figure 4.2: Plot of error between sin(1) and its piece-wise linear approximation with twolines
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5708-0.025
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0.02
0.025
X: 0
Y: -0.02425
ErrorAmplitude
x1(radians)
X: 0.9287
Y: -0.02425
X: 1.571
Y: -0.02425
X: 1.254
Y: 0.02425
X: 0.53
Y: 0.02425
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from 0 to 20A is used to represent the range of the function sin(1) in the first quartercycle from 0 to 1. A linear mapping is assumed between the function value and the output
current, so that Iout =
sin(
1), where
= 20
A. Substituting these mappings into
Equation (4.1), the function approximation becomes
Iout = sin1 (1 Iin + 1), 70A (2 Iin + 2), 90A . (4.2)After replacing the coefficients, ,,1,2, 1,and 2with their values, Equation (4.2)becomes
Iout = 20A sin1 1 Iin Ib1 , 70A Iin Ith2 Iin Ib2 , Ith Iin 90A (4.3)Where 1 = 1.3545 , 2 = 0.4872, Ib1 = 94.3326A, Ib2 = 23.3669A, and Ithrepresents the output current at the point of intersection between the two lines. Equation
(4.3) shows the two linear functions that must be implemented in analog circuitry in order
to design a hardware unit to evaluate the function sin(1). At the point of intersection ofthe two lines, the value of x1 is 0.9287, which corresponds to a current ofIth =
81.8244A.
4.2 Circuit implementation of the function sin(1)The block diagram in Fig. 4.3 shows the analog implementation of the function
sin(x1). The circuit has three distinct parts: an arithmetic unit that implements the two
linear functions, a current comparator that determines which one of the two lines should
be used to approximate the function sin(1), given the input current Iin, and a multiplexerthat routes the corresponding current to the output. These three parts are described in the
next two sections.
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4.2.1 Design of the arithmetic unit
The arithmetic unit is used to implement the two linear functions which
approximate the function sin(
1). The two linear expressions to calculate the output
current Ioutin Equation (4.3) have to be implemented with the help of current subtractors.
In these linear expressions, there are negative coefficients for the bias currents and
positive coefficients for Iin, which means that the two bias currents have to be subtracted
from the corresponding scaled versions of the input current.
A transistor-level schematic of the arithmetic unit is shown in Fig. 4.4. The input
current Iin, which is shown as a current source in the circuit diagram, is mirrored from the
drain of transistor of M1 to the drain of transistor M18 to produce a copy of I in. This
current is mirrored again to the drains of transistors M20 and M21 to produce two
different scaled versions of Iin, shown in Fig. 4.4 as 1 and 2Iin . The two scaling
Current
ComparatorSubtractor 1 Subtractor 2
a1
Iin Ith Iin Ib1
a2
Iin Ib2
Multiplexer
Output
Arithmetic
Unit
Iinvaries from
70A to 90A
Select
Idiff1 Idiff2
Figure 4.3: Block diagram of analog implementation of the function sin(x1)
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produced by the NMOS cascode transistors which act as current sinks. The first linear
expression in Equation (4.3) is implemented by producing 1Iin from transistor M20 andsubtracting Ib1by sinking the current through transistor M24. Similarly the second linear
expression in Equation (4.3) is implemented by producing 2Iin from transistor M21 andsubtracting Ib2by sinking the current through transistor M27. The current differences Idiff1
and Idiff2, which are the currents left after subtracting the bias currents from their
respective scaled versions of the input current, are the outputs of the arithmetic unit.
These currents will flow to the load through the multiplexer.
4.2.2 Design of the current comparator and the multiplexer
The current comparator used in the function evaluation is similar to the one
incorporated in the min-max current selector, as described in Chapter III. The first input
to the comparator is the input current Iinand the second is the constant threshold current
Iththat corresponds to the point of intersection of the two lines used to approximate the
function sin(x1). This current comparator produces a digital output, which conveys
Iin
M2
M5 M6
M4A
M11
M10
M6AM5A
M2A
M4
M8
M9
Vout1V1
M12
M13A
M12A
M13
M16
M17
M14
M15
`
VDD
Select
M1A
M1
M3A
M7
M3
Vout2Ith
Iin
NMOS Cascode
Current Mirror 1
NMOS Cascode
Current Mirror 2
PMOS Cascode
Current Mirror Schmitt Trigger
Select
M29M28 M30 M31
IoutputLoad
M32A
M32 Multiplexer
Idiff1 Idiff2
Figure 4.5: Schematic of current comparator and multiplexer
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whether the input current is greater than or less than the threshold current. The output of
this current comparator is used to determine which one of the two lines used to
approximate the function sin(x1) should be selected.
A transistor-level circuit diagram for the current comparator and multiplexer is
shown in Fig. 4.5. The input current Iin is shown as a current source in the schematic. The
input current Iinis mirrored from the drain of transistor M1 to produce a copy of the input
current Iin at the drain of transistor M6. The threshold current Ith is produced by the
voltage divider consisting of M7, M3, and M3A and then mirrored to the drain of
transistor M4. The current Ith, which corresponds to the point of intersection of two lines
used to approximate the function sin(x1), is 81.8244A.
Figure 4.6: Differential response of the current comparator and its expanded version
70 72 74 76 78 80 82 84 86 88 900
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iin
(A)
Vout2
(V)
81.8 81.81 81.82 81.83 81.84 81.850
1
2
3
4
5
Expanded version
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The operation of the comparator is similar to that of the current comparator in the
min-max current selector. The main difference is that, because it has only one variable
input current, the design is optimized to switch states at a fixed threshold. The relative
sizes of the PMOS cascode current mirror and the two NMOS cascode current mirrors
were chosen so as to give a Vout1 of half of VDDwhen the input current Iinis equal to Ith.
Two cascaded push-pull amplifiers are implemented to amplify the variations of Vout1
from the bias point. Values of Vout1 above or below half of VDD drive the push-pull
amplifier outputs to the appropriate supply rail. The response of the current comparator is
shown in Fig.4.6. The expanded plot shows that the output voltage Vout2 rises sharply
from ground to VDD within a short span of 10nA change in the input current. The
transition is centered within 0.1nA of the nominal threshold current Ith = 81.8244Aand has a differential gain of 1.285V/nA.
A Schmitt trigger is used to produce an unambiguous digital signal from the
output of the current comparator. The Schmitt trigger used here is the same as the one
incorporated in the min-max current selector, as described in Chapter III. The Schmitt
trigger output Select and its complement (Select), derived using an inverter, are used asthe select control signals for the multiplexer.
Based on the control signals Select and Select , the multiplexer routes one of thetwo current differences Idiff1or Idiff2to the output. When Select is VDD, indicating that Iin
is larger than Ith, transistors M28 and M29 are off and transistors M30 and M31 are on, so
as to pass the current difference corresponding to the second linear expression in
Equation (4.3) through the multiplexer to Iout. Similarly, when Select is ground, the
transmission gates route the current difference corresponding to the first linear expression
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Figure4.7:Totalschematicofsinefunctionimplementation
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wise linear approximation (i.e., the Matlab result), and the output of the analog
implementation. The graphs of piece-wise linear approximation and the output of the
analog implementation cannot be distinguished from one another in the figure.
The differences among the function sin(1), the piece-wise linear approximation,and the output of the analog implementation are shown in Fig. 4.9. The maximum error in
the piece-wise linear approximation is 0.48A, which is 2.4% of the full-scale output
current range. The maximum additional error introduced by the electronics is 57nA. The
maximum error between the function sin(1) and the analog implementation is 0.55A.The additional error introduced in the analog implementation is slightly larger than 10%
of the error in the piece-wise linear approximation itself. The overall maximum error
percentage is 2.75% of the full-scale output current range.
Figure 4.9: Plots of error between function sin(1), piece-wise linear approximation, andanalog implementation
70 72 74 76 78 80 82 84 86 88 90
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Iin
(A)
ErrorCurrent(A)
Error between functionsin(x
1) and piece-wise
linear approximation
Error between piece-wiselinear approximation andanalog implementation
Error between function
sin(x1) and
analog implementation
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From the simulation results, it is observed that most of the error in the output is
due to the piece-wise linear approximation of the function sin(1). If the approximationwere done with more than two linear functions, the overall error in the output would be
reduced. However, the amount of circuitry needed for the analog implementation would
increase considerably.
If the function sin(1) were evaluated using a voltage-mode approach, theimplementation of the arithmetic unit would require two operational amplifiers, whereas
it requires only a few current mirrors with the current-mode approach. This means that
the voltage-mode approach requires more hardware than the current-mode approach.
With the voltage-mode approach, changes in the linear expressions require the resizing of
resistors. With the current-mode approach, changes in the linear expressions require the
redesign of the current mirrors.
This chapter discusses a method to evaluate the function sin(x1) which depends on
only a single variable. The approximation of function sin(x1) and its implementation with
current-mode analog circuits have been discussed in detail. The overall error percentage
in the analog implementation is 2.75%. In the next chapter, an analog implementation of
a more complicated function of two variables, log10 + when log10 + and log10 + are given as inputs, will be discussed in detail.
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CHAPTER V
ANALOG IMPLEMENTATION OF LOGARITHMIC NUMBER SYSTEM (LNS)
SUBTRACTION
In this chapter, a method of evaluating the logarithmic number system (LNS)
subtraction of two numbers using analog integrated circuits is discussed. LNS subtraction
finds the difference between two numbers represented in a logarithmic number system. If
1 = log10 + and 2 = log10 + are the base-10 LNS representationsof two numbers and , the absolute difference is represented by log10 + . Thus LNS subtraction evaluates this non-linear function, given1and2as inputs. Several papers [22-27] have been published on how to evaluate LNSsubtraction using digital implementations based on a field-programmable gate array. Our
approach to evaluate LNS subtraction is to rearrange the function so that it can be
approximated using a piece-wise linear function of a single variable, and then implement
the piece-wise linear function using analog circuitry. This LNS subtraction can be used to
find the forward and backward differences of neighboring pixels of an image obtained
from a logarithmic CMOS camera.
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5.1 Approximation of LNS subtraction
A base-10 logarithmic number system is assumed, such that two numbers and
are represented as
1 =
log10
+
and
2 =
log10
+
. Assuming that
> , the LNS subtraction of 1and2can be rewritten as log10 + = log10 + log10 1 + . (5.1)In Equation (5.1), log10 + can be replaced by 1, and can be replaced by1021/ . With these substitutions, Equation (5.1) may be written as
log10
+
=
1 +
log10
1
1021/
= 1 + 2 1. (5.2)
Equation (5.2) is in a form that is ready to be implemented in current-mode analog
circuitry. For the implementation, the difference 2 1 can be found easily from thedifference of the two input currents; the difference is used as the input to a piece-wise
linear approximation of the non-linear function . Finally the LNS subtraction iscompleted by summing the output of
with the input
1.
To calculate log10 + from Equation (5.2) using analog circuits,only (2 1) has to be approximated using a piece-wise linear approximation. Thesimplest approximation involves the use of two linear functions. Using more than two
linear functions would increase the accuracy of the approximation, but would also
increase the amount of hardware required for the implementation. In any case, the
Chebyshev approximation algorithm may be used. Before starting the algorithm, first the
range of the inputs to the function which is being approximated has to be found. Here in
2 1,the variable is 2 1. The range of the variable 2 1depends on therange of the inputs 1and 2.
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The range of the input variables 1and2depends on the system from which theinputs are taken. Here 1 and 2 are the pixel output currents of a logarithmic CMOSimage sensor. Any pixel output current of a logarithmic CMOS image sensor is a shifted
and scaled version of the logarithm of the current produced by a photodiode, due to the
input light illumination on the photodiode. The range of input to the photodiode is five
decades of light illumination, for which a typical photodiode produces a current from
1pA to 100nA [27]. The photodiode produces the current linearly only from 4pA to
100nA for a 4.398 decade range of input light illumination, and only this slightly reduced
range should be considered for the simulations. The photodiode current is amplified by a
pixel readout circuit, which produces the pixel output current. For our assumed readout
circuitry, taken from [28], a photodiode current of 100nA, which corresponds to the
highest illumination, results in a pixel output current of 70A, and a photodiode current
of 4pA, which corresponds to the lowest illumination, results in a pixel output current of
90A. Thus, the variables
1and
2range from 70A to 90A.
In addition to determining the range of the input variables, it is now possible to
calculate the value of the coefficientp in the expressions for the pixel currents 1and 2.From Equation (5.2), to evaluate log10 + from the inputs 1and 2, onlythe value of the coefficient has to be calculated; the value of q is not required. Thevalue of can be found by subtracting the two pixel currents 1and 2, as
2 1 = log10 . (5.3)If 2 = 90A, which is the largest pixel current, and 1 = 70A, which is the smallestpixel current, the value of
may be found from the ratio of the corresponding photodiode
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currents as = 4pA100nA = 4 1 05. Hence, from Equation (5.3), = 4.548A. Note
that is negative, as 1 < 2implies > .Returning to the discussion of the range of
2
1, as the range of the inputs
1
and 2 to the LNS subtraction has been determined as 70A to 90A, the maximumdifference between the inputs is 20A. The minimum difference can be zero; however,
because the logarithm of zero is infinity, the piece-wise linear approximation cannot be
expected to be accurate at that point. The minimum value of 2 1 for which theapproximation of (2 1) will be evaluated is chosen as 20nA. The value of thefunction f when 2 1 = 20nA is 9.0813A. If the minimum value of 2 1 werereduced, the maximum value offwould increase. Thus, the errors in the piece-wise linear
approximation throughout the range would be greater.
Figure 5.1: Plot of piece-wise linear approximation of with two lines0 2 4 6 8 10 12 14 16 18 20
-1
0
1
2
3
4
5
6
7
8
9
X: 0.4795
Y: 1.929
f(x)(A)
x(A)
f(x)
Piece-wise linear approximation with two lines
slope=-13.1640y-intercept=8.2405
slope=-0.1552y-intercept=2.0033
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selector, which sorts the two input currents so as to provide a copy of the smaller of the
two input currents at one output and a copy of larger of the two input currents at the other
output; an arithmetic unit which scales the larger and the smaller currents and adds a bias
current to each of them; a current comparator, which determines which one of the two
lines used to approximate the function fshould be selected for the given input currents;
and a multiplexer, which routes the corresponding current sum to the output. These four
parts are described in the next three sections.
5.2.1 Design of the min-max current selector
The min-max current selector takes two input currents, and provides as output two
currents, one a mirrored copy of the smaller of the two input currents, and the other a
mirrored copy of the larger of the two input currents. This operation is essential to the
LNS subtraction, which involves evaluating the absolute value of a difference. The
design, operation and performance of the min-max current selector are already discussed
in Chapter III.
5.2.2 Design of the arithmetic unit
The arithmetic unit is used to implement the two linear expressions which
approximate the function . In deriving Equation (5.5), it is assumed that > . Sincepis negative, this implies that 1 is less than 2. So 1 and 2can be replaced in Equation(5.5) by the currents Ilowand Ihigh, respectively. If the slopes and y-intercepts of the lines
are inserted in Equation (5.5), two equations are obtained which could be implemented
using the analog circuits. The two equations obtained are
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log10 + 1 1 Ilow + 1 Ihigh + Ib1 0 Ihigh Ilow Ith 1 2 Ilow + 2 Ihigh + Ib2 , Ith Ihigh Ilow 20A , (5.6)where1 = 13.1640,2 = 0.1552, Ib1 = 8.2405A, and Ib2 = 2.0033A. Thepoint of intersection between the two lines is defined by Ith = 479.5nA. In both linearexpressions in Equation (5.6), the coefficients of Ihigh(that is, 1and 2) are negative,and the coefficients of the other terms are positive. This means that the scaled versions of
the current Ihighhave to be subtracted from the respective sums of the other two currents.
The minimum value of the output of the LNS subtraction, obtained when Ilow = 70
A
and Ihigh = 90A, is equal to 68.8993A. The maximum value of the output, obtainedwhen both input currents are equal to 90A, is equal to 98.2405A. Therefore, the full-
M52A
M52
M34A
M34
M60A
M60
M53 M54
M54AM53A
VDD
M56 M57
M57A
M58
M62
M62A
M63
M59
M59A
M61
M61AM56A
Ilow
M33
M33A
M55
M55A
Ihigh
Isum1 Isum2
Ib1(1-m1)Ilow Ib2(1-m2)Ilow
high1Imhigh2 Im
Figure 5.4: Schematic of the arithmetic unit
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5.2.3 Design of the current comparator and the multiplexer
The current comparator has two inputs; the first input is the larger of the two input
currents Ihighand the second input is the sum of the smaller of the two input currents and
the threshold current (Ilow+ Ith). This current comparator produces a digital output, which
conveys whether the difference between the larger and the smaller of the two input
currents is greater or less than the threshold current. The output of this current
comparator is used to select which one of the two linear functions implemented to
approximate the function has to be selected.A transistor-level schematic for the current comparator and the multiplexer is
shown in Fig. 5.5. The min-max current selector provides Ilow and Ihigh to this current
comparator. The current comparator is similar to the one in the min-max current selector,
except that a constant current Ithis added to one of the inputs. The current Ilowis mirrored
from the drain of the transistor M33 to produce a copy of it at the drain of the transistor
M38. Simultaneously, the current Ihighis mirrored from the drain of the transistor M34 to
Ilow
M35
M37 M38
M34A
M45
M44
M38AM37A
M35A
M34
M42
M43
Vout3
V2
M39 M40
M40AM39A
M41
M46
M47A
M46A
M47
M50
M51
M48
M49
M33
M33A
M36
M36A
Ihigh
Select
VDD
Vout4
IthIhigh
Ilow
NMOS Cascode
Current Mirror 1
NMOS Cascode
Current Mirror 2
PMOS Cascode
Current Mirror
Schmitt Trigger
Select
M65M64 M66 M67
Ioutput
Load
M68A
M68 Multiplexer
Isum1 Isum2
Figure 5.5: Schematic of the current comparator and multiplexer
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currents, there is a maximum input-offset current of 9nA. The current comparator has a
differential gain of 1.7025V/nA.A Schmitt trigger is used to produce an unambiguous digital signal from the
output of the current comparator. The Schmitt trigger produces an output voltage Select that is railed to VDD if Ihigh Ilow > Ith , and railed to ground if Ihigh Ilow < Ith . TheSchmitt trigger output Select and its complement (Select), derived using an inverter, areused as the sel