AKD4497-SA Rev.0 English Manual · 6.Begin evaluation by following the procedure below. [Supported...

[AKD4497-SA]

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1. General Description

The AKD4497-SA is an evaluation board for the AK4497 (Premium 32-bit 2ch DAC) that supportsNetwork-Audios, USB-DAC, Car-Audio Systems. It integrates differential output low pass filters, allowingquick evaluation with digital audio interface.

■ Ordering Guide

AKD4497-SA -- Evaluation Board for the AK4497(A USB I/F board for IBM-AT compatible computers and control software areincluded in this package.)

2. Function

10-pin Header for Serial Control Low Pass Filters (LPF) for Pre-amplifier Outputs Digital Audio Interface (AK4118A)

COAX In

AK4497

2nd Order LPF

Rch

LchDIR

Opt InAK4118A

Figure 1. AKD4497-SA Block Diagram (Note 1)

Note 1. Circuit schematics are attached at the end of this document.

AK4497 Evaluation Board Rev.0

AKD4497-SA

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3. Board Appearance

■ Appearance Diagram

J500

SW100

SW200

U1

J400

J300

PORT200

J403

J402

J401

J501

J404

SW300

PORT201

PORT300

Filter Block1-1

Filter Block2-1

Filter Block1-2

Filter Block2-2

RegulatorBlock4

RegulatorBlock3

RegulatorBlock1

Regulator

Block2

U300

Bottom Side

Figure 2. AKD4497-SA Outline View

■ Description

(1) Connectors for Power Supply and GND ( J500 / +15V, J404 / -15V, J501 / GND )Connectors for power supply and the groundRefer to the “Power Supply Connections” for details.

(2) SPDIF Input Connectors (J300 / BNC Connector, PORT300 / Optical Connector)Input a SPDIF signal to the AK4118A.Set the R303 resistance to short when using the J300 (BNC Connector) jack.Set the R302 resistance to short when using the PORT300 (Optical Connector).

(3) Analog Differential Output Terminals (J400 / J401, XLR Connector)Differential Analog Output Connector

(4) Analog Output Terminals (J402 / J403, BNC Connector)Single-ended Analog Output Connector

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(5) EXT PORT (PORT200)10-pin Header for External InterfacingExternal digital audio devices are interfaced to this port.Set the R202, R204, R206 and R208 resistances to short when using the PORT200 (EXT).

Pin I/O Function pin I/O Function

1 I MCLK 10 P GND2 I BICK 9 P GND3 I SDTO 8 P GND4 I LRCK 7 P GND5 I WCK 6 P GND

Table 1. PORT200 (EXT) Pin Assignments

(6) AK4118A (U300)The AK4118A is a digital audio transceiver.It is used when evaluating sound quality of the AK4497 by SPDIF signals.

(7) µP-IF PORT (PORT201)10-pin Header for the USB I/F boardConnect the USB I/F board for IBM-AT compatible computers to this port for a connection to a USB port ofa PC. Refer to the “Serial Control Mode” for details

(8) Dip Switches (SW100 / SW300)Setting Switches for the AK4497 and the AK4118A.Upside is “H” (ON) and Downside is “L” (OFF).Refer to “■ Resistance and DIP Switch Settings” for details.

(9) SW200 ( Toggle switch )Toggle type-switch PDN for AK4497 and the AK4118A.“H” : PDN = High“L” : PDN = Low

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4. Operation Sequence

Operation sequence

1). Power Supply Connections2). Evaluation Mode3). ■ Resistance and DIP Switch Settings4). Power-up

■ Power Supply Connections

Name Color Voltage Content NoteDefaultSetting

J500(REG(+15V))

Red +10 to +15VMVDD (AK4497),Op-Amp

This jack is always needed. +15V

J404(REG(-15V))

Blue -10 to -15V Op-Amp This jack is always needed. -15V

J501(AVSS)

Black 0V Ground This jack is always needed. 0V

Table 2. Power Supply Connections

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■ Evaluation Mode

(1) Evaluation with a DIR (COAX) < Default >

The J300 (COAX) jack is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCK andSDATA from the input data of the J300 (COAX) connector.Set the R303 resistance to short, and set the R201 (MCLK), R203 (BICK), R207 (LRCK) and R205(SDTO) resistances to short.

Resistance Settings with DIR:COAX / OPT : R303 = short (COAX)MCLK : R201 = short (DIR)BICK : R203 = short (DIR)LRCK : R207 = short (DIR)SDTO : R205 = short (DIR)

(2) Evaluation with a DIR (OPTICAL)

The PORT300 (OPTICAL) is used in this mode. The DIR (AK4118A) generates MCLK, BICK, LRCKand SDATA from the input data of the PORT300 (OPTICAL) connector.Set the R302 resistance to shot, and set the R201 (MCLK), R203 (BICK), R207 (LRCK) and R205(SDTO) jumper pins to “DIR”.

Resistance Settings with DIR:COAX / OPT : R302 = short (OPT)MCLK : R201 = short (DIR)BICK : R203 = short (DIR)LRCK : R207 = short (DIR)SDTO : R205 = short (DIR)

(3) In the case that all interface clocks including the master clock are input externally. (PORT200)

Input all interface clocks including the master clock to the PORT200 (DSP).Set R202 (MCLK), R204 (BICK), R208 (LRCK) and R206 (SDTO) resistances to short.

Resistance Settings with External Clocks:COAX / OPT : R303 = short (COAX) <default>MCLK : R202 = short (EXT)BICK : R204 = short (EXT)LRCK : R208 = short (EXT)SDTO : R206 = short (EXT)

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■ Resistance and DIP Switch Settings

(1) Resistance Settings

[R201 / R202 (MCLK)]: MCLK pin input selectR201 short: MCLK signal is supplied from the DIR (AK4118A). < Default >R202 short: MCLK signal is supplied from the PORT200.

[R203 / R204 (BICK)]: BICK pin input selectR203 short: BICK signal is supplied from the DIR (AK4118A). < Default >R204 short: BICK signal is supplied from the PORT200.

[R205 / R206 (SDTO)]: SDATA pin input selectR205 short: SDATA signal is supplied from the DIR (AK4118A). < Default >R206 short: SDATA signal is supplied from the PORT200.

[R207 / R208 (LRCK)]: LRCK pin input selectR207 short: LRCK signal is supplied from the DIR (AK4118A). < Default >R208 short: LRCK signal is supplied from the PORT200.

[R303 / R302 (COAX / OPT)]: SPDIF signal for AK4118AR303 short: SPDIF signal is supplied from the J300 (COAX) connector. < Default >R302 short: SPDIF signal is supplied from the PORT300.

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(2) DIP Switch SettingUpside is ON (“H”), and Downside is OFF (“L”).

[SW300]: Setting of the AK4118A

No. Name ON (“H”) OFF (“L”) Default

1 OCKS1 Master Clock setting for AK4118ARefer to Table 5.

L2 OCKS0 L

Table 3. SW300 Setting

[SW100]: Setting of the AK4497

No. Name ON (“H”) OFF (“L”) Default

1 SSLOWDigital Filter Setting Refer to Table 6.

( In Pararell Control Mode)

L2 SD H3 SLOW L

4HLOAD

/I2C

Heavy Load Mode Normal Mode

L( In Pararell Control Mode)

I2C-BusControl Mode

3-wireSerial Control Mode

5 PSNPSN pin= “H”

(Pararell Control Mode)PSN pin= “L”

Serial Control Mode)L

6ACKS/CAD1

Auto Setting Mode Manual Setting Mode

L( In Pararell Control Mode)

CAD1 pin= “H” CAD1 pin= “L”

Table 4. SW100 Setting

Mode OCKS1 OCKS0 MCKO1 fs (max)

0 L L 256fs 96 kHz < Default >1 L H 256fs 96 kHz2 H L 512fs 48 kHz3 H H 128fs 192 kHz

Table 5. Master Clock Setting

SSLOW SD SLOW Mode

L L L Sharp roll-off filterL L H Slow roll-off filterL H L Short delay sharp roll-off filter < Default >L H H Short delay slow roll-off filterH L L Super Slow roll-off filterH L H Super Slow roll-off filterH H L Low dispersion Shot Delay filterH H H Reserved

Table 6. Digital Filter Setting

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■ Power-up

Upside is ON (“H”), and Downside is OFF (“L”).

[SW200] (PDN): DAC / DIR Reset control. It must be set to “H” during operation.After power-up, the AKD4497-SA must be reset once.To reset the AKD4497-SA, set the SW200 toggle switch to “L” and power down theAK4497 and the AK4118A. Then, release the power-down by setting back the SW200 to“H”.

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■ Serial Control Mode (PSN pin = “L”)

When using this evaluation board in serial control mode, settings of the CAD1 pin and the CAD2 pin on theboard must match the Chip Address settings of the control software.

(1) 3-wire Serial Control Mode: (I2C pin= “L”)(2) I2C Bus Control Mode: (I2C pin= “H”)

The AKD4497-SA should be connected to a PC (IBM-AT compatible) via a USB control box(AKDUSBIF-B) included in this package. The USB control box is connected to a PC with a USB cable andthe AKD4497-SA with a 10-pin flat cable. (Note 2, Note 3)

Note 2. The AKD4497-SA accepts only one AKDUSBIF-B at one time. It does not operate if two or moreAKDUSBIF-Bs are connected.

Note 3. Connect the 10pin Flat Cable as the red line of the cable is connected to the 1 pin of the 10pin Headerof the board.

PC

USB Cable

AKDUSBIF-B

USBConnector

Evaluation BoardAKDXXXX-YY

10pinConnector

DeviceAKXXXX

10pin Flat Cable

Set Red line to No.1 pin side.

Figure 3. AKDUSBIF-B Connection

Figure 4. AKDUSBIF-B

AKDUSBIF-B

Evaluation BoardPC

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5. Control Software Manual

■ Evaluation Board and Control Software Manual

1.Set up the evaluation board as needed, according to the previous terms.2.Connect the evaluation board to a PC with USB cable.3.USB control is recognized as HID (Human Interface Device) on PC. When it is not recognized properly, please

reconnect the evaluation board to PC.4. Insert the CD-ROM labeled “AKD4497-SA Evaluation Kit” into the CD-ROM drive.5.Access the CD-ROM drive and double-click the icon “AKD4497-SA.exe” to open the control program.6.Begin evaluation by following the procedure below.

[Supported OS]Windows XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7)64bit OS is not supported.

Figure 5. Control Program Window

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■ Operation Overview

Register map is controlled by this control software.

Frequently used buttons, such as the register initializing button “Write Default”, are located outside of theswitching tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.

1.[Port Reset]: Reset connection to PCClick this button after the control software starts up and the evaluation board is connected tothe PC via USB cable.

2.[Write Default]: Register InitializationUse this button to initialize the registers when the device is reset by a hardware reset.

3.[All Write]: Execute write command for all registers displayed.

4.[All Read]: Execute read command for all registers displayed. (Note 2)

5.[Save]: Save current register settings to a file.

6.[Load]: Execute data write from a saved file.

7.[All Reg Write]: [All Reg Write] dialog box pops up.

8.[Data R/W]: [Data R/W] dialog box pops up.

9.[Sequence]: [Sequence] dialog box pops up.

10.[Sequence(File)]: [Sequence(File)] dialog box pops up.

Note 2. The [All Read] button is only valid when the interface mode for register control is in I2C bus controlmode.

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■ Tab Functions

1. [REG] Tab: Register Map

This tab is for register read and write.

Each bit on the register map is a push-button switch.Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)

Grayed out registers are Read-Only registers. They cannot be controlled.

The registers which are not defined on the datasheet are indicated as “---”.

Figure 6. REG Window

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[Write] button: Data Write Dialog

Select the [Write] button located on the right of the each corresponding address when changing two or more bitson the same address simultaneously.

Click the [Write] button for the register pop-up dialog box shown below.

When the checkbox next to the register is checked, the data will become “1”. When the checkbox is notchecked, the data will become “0”. Click [OK] to write the set values to the registers, or click [Cancel] to cancelthis setting.

Figure 7. Register Set Window

[Read] button: Data Read (Only in I2C-bus Control Mode)

Click the [Read] button located on the right of the each corresponding address to execute a register read.

The current register value will be displayed in the register window as well as in the upper right hand DEBUGwindow.Button Down indicates “1” and the bit name is shown in red (when read only the bit name is shown in dark red).Button Up indicates “0” and the bit name is shown in blue (when read only the bit name is shown in gray)

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■ Dialog Box

1. [All Reg Write]: All Register Write dialog box

Click [All Reg Write] button in the main window to open register setting file window shown below.Register setting files saved by [SAVE] button may be applied.

Figure 8. [All Reg Write] Window

[Open (left)]: Select a register setting file (*.akr).[Write]: Execute register write with selected setting file.[Write All]: Execute register write with all selected setting files.

Selected files are executed in descending order.[Help]: Open help window.[Save]: Save register setting file assignment. File name is “*.mar”.[Open (right)]: Open saved register setting file assignment “*. mar”.[Close]: Close dialog box and finish process.

~ Operating Suggestions ~

1. Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should bestored in the same folder.

2. When register settings are changed by [Save] button in the main window, re-read the file to reflect newregister settings.

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2. [Data R/W]: Data R/W Dialog Box

Click the [Data R/W] button in the main window for data read/write dialog box.Data is written to the specified address.

Figure 9. [Data R/W] Window

[Address] Box: Input data write address in hexadecimal numbers.[Data] Box: Input write data in hexadecimal numbers.[Mask] Box: Input mask data in hexadecimal numbers.

This value “ANDed” with the write data becomes the input data.[Write]: Write data generated from Data and Mask value is written to the address specified in “Address” box.

(Note 3)[Read]: Read data from the address specified in “Address” box. (Note 4)[Close]: Close dialog box and finish process.

Data write will not be executed unless [Write] is clicked.

Note 3. The register map will be updated after executing the [Write] command.Note 4. The [Read] button is only valid when the interface mode for register control is in I2C bus control mode.

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3. [Sequence]: Sequence Dialog Box

Click the [Sequence] button in the main window for Sequence dialog box.Register sequence may be set and executed.

Figure 10. [Sequence] Window

~ Sequence Setting ~

Set register sequence according to the following process.

1. Select a command

Use [Select] pull-down box to choose commands.Corresponding input boxes will be valid.

<Combo Box>• No_use: Not using this address• Register: Register write• Reg(Mask): Register write (Masked)• Interval: Take an interval• Stop: Pause the sequence• End: End the sequence

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2. Input Sequence

[Address]: Data Address[Data]: Write Data[Mask]: Mask

This value “ANDed” with the write data becomes the input data.When Mask = 0x00, current setting is hold.When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.Upper 4bit is hold to current setting.

[Interval]: Interval Time

Valid boxes for each process command are shown below.

・No_use : None

・Register : [Address], [Data], [Interval]

・Reg(Mask) : [Address], [Data], [Mask], [Interval]

・Interval : [Interval]

・Stop : None

・End : None

~ Control Buttons ~

Functions of Control Buttons are shown below.

[Start] button : Execute the sequence.[Help] button : Open a help window.[Save] button : Save sequence settings as a file. The file name is “*.aks”.[Open] button : Open a sequence setting file “*.aks”.[Close] button : Close the dialog box and finishes the process.

Stop Sequence

When “Stop” command is selected in the sequence, the process is paused at this step. It is resumed byclicking the [Start] button. The process starts from the step shown in [Start Step] box. This step numberreturns to “1” when the sequence is executed until the end. Input arbitrary step number to the [Start Step]box to start the process from the middle of sequence.

The process sequence can be restarted from the beginning by writing “1” to the [Start Step] box andclick the [Start] button during the process.

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4. [Sequence(File)]: Sequence(File) Dialog

Click the [Sequence(File)] button to open sequence setting file dialog box shown below.Files saved in the “Sequence setting dialog” can be applied in this dialog.

Figure 11. [Sequence (File)] Window

[Open (left)] button: Select a sequence setting file (*.aks)[Start ] button: Execute the sequence by the setting of selected file.[Start All] button: Execute sequence with all selected setting files.

Selected files are executed in descending order.[Help] button: Open help window.[Save] button: Save register setting file assignment. File name is “*.mas”.[Open (right)] button: Open saved sequence setting file assignment “*. mas”.[Close] button: Close dialog box and finish process.

~ Operating Suggestions ~

1. Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should bestored in the same folder.

2. When “Stop” command is selected in the sequence, the process is paused at this step and a message shownbelow pops up. The sequence is resumed by clicking “OK” button.

Figure 12. Sequence Pause Window

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6. Measurement Results

[Measurement condition]

Measurement unit : Audio Precision APX 555 Audio Analyzer

MCLK : 256fs (44.1 kHz), 256fs (96 kHz), 128fs (192 kHz)

BICK : 64fs

fs : 44.1kHz, 96kHz, 192kHz

Bit : 24bit

Power Supply : AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V

Pass : DIR → AK4497 → Cannon Connector

Interface : Internal DIR (44.1 kHz, 96 kHz, 192 kHz)

Temperature : Room Temperature

Operational Amplifiers : OPA1611, OPA1612

Control Soft Register : HLOAD=”1”, SC2=”1”

fs=44.1kHz

Parameter Input signal Measurement filterResults

Lch / Rch

S/(N+D) 1kHz, 0dB20kHz LPF

116.9 dB / 116.6 dB

DR 1kHz, -60dB124.2 dB / 124.1 dB

A-weighted 126.5 dB / 126.3 dB

S/N “0” data20kHz LPF 124.1 dB / 124.1 dB

A-weighted 126.5 dB / 126.4 dB

fs=96kHz


Lch / Rch


114.1 dB / 115.1 dB

DR 1kHz, -60dB 121.5 dB / 121.5 dB

S/N “0” data 40kHz LPF 121.6 dB / 121.5 dB

fs=192kHz


Lch / Rch


115.3 dB / 114.6 dB

DR 1kHz, -60dB 121.5 dB / 121.3 dB

S/N “0” data 40kHz LPF 121.5 dB / 121.6 dB

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■ Capacitance between the VREFH pin and the VREFL pin

Distortion (THD+N) can be improved by increasing the capacitance of a capacitor between the VREFH pin andthe VREFL pin. Applicable capacitors are C108 and C111 in the circuit schematic.

Figure 13. THD+N vs. Input Frequency Comparison by Capacitance

C=470uF

C=10uFC=100uF

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[Plots]fs = 44.1 kHz

AK4497 THD+N vs. Input LevelAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 14. THD+N vs. Input Level

AK4497 THD+N vs. Input FrequencyAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 15. THD+N vs. Input Frequency

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fs = 44.1 kHz

AK4497 LinearityAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 16. Linearity

AK4497 Frequency ResponseAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 17. Frequency Response

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fs = 44.1 kHz

AK4497 CrosstalkAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 18. Crosstalk

AK4497 FFT (0dBFS Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 19. FFT (0dBFS Input)

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fs = 44.1 kHz

AK4497 FFT ( -60dBFS Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 20. FFT (-60dBFS Input)

AK4497 FFT ( No Signal Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=44.1kHz

Figure 21. FFT (No Signal Input)

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fs = 96 kHz

AK4497 THD+N vs. Input LevelAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


AK4497 THD+N vs. Input FrequencyAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


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fs = 96 kHz

AK4497 LinearityAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


AK4497 Frequency ResponseAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


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fs = 96 kHz

AK4497 CrosstalkAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


AK4497 FFT (0dBFS Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


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fs = 96 kHz

AK4497 FFT (-60dBFS Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


AK4497 FFT (No Signal Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz


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fs = 192 kHz

AK4497 THD+N vs. Input LevelAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


AK4497 THD+N vs. Input FrequencyAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


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fs = 192 kHz

AK4497 LnearityAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


AK4497 Frequency ResponseAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


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fs = 192 kHz

AK4497 CrosstalkAVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


AK4497 FFT (0dBFS Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


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fs = 192 kHz

AK4497 FFT (-60dBFS Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


AK4497 FFT (No Signal Input)AVDD=TVDD=DVDD=1.8V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz


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7. Revision History

Date(y/m/d)

ManualRevision

BoardRevision

Reason Page Contents

15/10/30 KM122100 0 First Edition - -

20/03/09 KM122101 0 Change 7Change setting.Table 6. Digital Filter Setting

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IMPORTANT NOTICE

0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the informationcontained in this document without notice. When you consider any use or application of AKM productstipulated in this document (“Product”), please make inquiries the sales office of AKM or authorizeddistributors as to current status of the Products.

1. All information included in this document are provided only to illustrate the operation and applicationexamples of AKM Products. AKM neither makes warranties or representations with respect to the accuracyor completeness of the information contained in this document nor grants any license to any intellectualproperty rights or any other rights of AKM or any third party with respect to the information in thisdocument. You are fully responsible for use of such information contained in this document in your productdesign or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU ORTHIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCTDESIGN OR APPLICATIONS.

2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarilyhigh levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life,bodily injury, serious property damage or serious public impact, including but not limited to, equipmentused in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used forautomobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to controlcombustions or explosions, safety devices, elevators and escalators, devices related to electric power, andequipment used in finance-related fields. Do not use Product for the above use unless specifically agreed byAKM in writing.

3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible forcomplying with safety standards and for providing adequate designs and safeguards for your hardware,software and systems which minimize risk and avoid situations in which a malfunction or failure of theProduct could cause loss of human life, bodily injury or damage to property, including data loss orcorruption.

4. Do not use or otherwise make available the Product or related technology or any information contained inthis document for any military purposes, including without limitation, for the design, development, use,stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products(mass destruction weapons). When exporting the Products or related technology or any informationcontained in this document, you should comply with the applicable export control laws and regulations andfollow the procedures required by such laws and regulations. The Products and related technology may notbe used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited underany applicable domestic or foreign laws or regulations.

5. Please contact AKM sales representative for details as to environmental matters such as the RoHScompatibility of the Product. Please use the Product in compliance with all applicable laws and regulationsthat regulate the inclusion or use of controlled substances, including without limitation, the EU RoHSDirective. AKM assumes no liability for damages or losses occurring as a result of noncompliance withapplicable laws and regulations.

6. Resale of the Product with provisions different from the statement and/or technical features set forth in thisdocument shall immediately void any warranty granted by AKM for the Product and shall not create orextend in any manner whatsoever, any liability of AKM.

7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior writtenconsent of AKM.

Rev.1

- 34-

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CSN

SMUTE-L

CCLK/SCL

SD

CDTI/SDA

SLOW

SSLOW

SSLOWSD

SLOW

HLOAD/I2C-S

PSN

ACKS/CAD1

VSSL VSSR

WCK

H

L

SMUTE-H

*Default SettingDIF0/DZFL=LDIF1/DZFR=HDIF2/CAD0=LDEM0/DSDL=H

*Default SettingGAIN/DSDR=LTDM0/DCLK=LTDM1=LDCHAIN=LINVR=LTESTE=L

LDOE=L

SD

AT

A1/D

SD

L

PD

N

HLOAD/I2C-S

LR

CK

/DIN

R

BIC

K/B

CK

PSN-S

SSLOW-SSD-SSLOW-SHLOAD/I2C-SPSN-S

ACKS/CAD1-S

SD-SSLOW-S

LD

OE

ACKS/CAD1-S

SSLOW-S

AVSS AVSS

AVSS

AVSS

AVSS

AVSS

AV

SS

AV

SS

AV

SS

AVSS

AVSS

VREFHR

VREFLR

VREFHL

VREFLL

AVDD

MCLK

AO

UT

LP

AO

UT

LN

VDDL VDDR

AO

UT

RN

AO

UT

RP

CD

TI/S

DA

CC

LK

/SC

L

CS

N

LR

CK

/DIN

R

SD

AT

A1/D

SD

L

BIC

K/B

CK

PD

N-0

DVDD

TVDD

WC

K

TV

DD

TVDD

TVDD

TV

DD

Title

Size Document Number Rev

Date: Sheet ofAK4497 64LQFP 0

AKD4497-SA

A3

1 5Wednesday, October 28, 2015

Title



AKD4497-SA

A3


Title



AKD4497-SA

A3


R114

open

C1150.1u

R125 0

+ C111470u(A)

R128 open

R150

10k

C1130.1u

+C1161u(A)

R105

0

U1AK4497 Plastic

LD

OE

1

PD

N2

BIC

K/B

CK

3

SD

AT

A/D

INL

4

LR

CK

/DIN

R5

SS

LO

W/W

CK

6

TD

MO

7

SM

UT

E/C

SN

8

SD

/CC

LK

/SC

L9

SL

OW

/CD

TI/

SD

A1

0

DIF

0/D

ZF

L1

1

DIF

1/D

ZF

R1

2

DIF

2/C

AD

01

3

PS

N1

4

HL

OA

D/I

2C

15

VS

SR

38

VS

SR

39

GAIN/DSDR17

ACKS/CAD118

TDM0/DCLK19

TDM120

INVR22

TESTE23

VREFHR24

VREFHR25

VREFHR26

VREFLR27

VREFLR28

VREFLR29

VCMR30

AOUTRN31

AOUTRN32

AO

UT

RP

33

AO

UT

RP

34

VD

DR

37

VD

DR

36

VD

DR

35

DE

M0

/DS

DL

16

DCHAIN21

VS

SR

40

VS

SL

41

VS

SL

42

VS

SL

43

VD

DL

44

AO

UT

LP

48

AO

UT

LP

47

VD

DL

46

VD

DL

45

AOUTLN49

AOUTLN50

VCML51

VREFLL52

VREFLL53

VREFLL54

VREFHL55

VREFHL56

VREFHL57

EXTR58

AVDD59

AVSS60

MCLK61

DVDD62

DVSS63

TVDD64

R147 100

+C10410u(A)

R116

open

R131 open

R141 open

R113

0

+

C108470u(A)

+

C100 10u(A)

R101

(short

)C

117

100p

R130 0

R120

0

R143 100

C1060.1u

R123 open

R108

100

R140 0

R118

0

R126 0

R111

100

+ C11410u(A)

R151

10k

C1070.1u

R121

open

R152

10k

R146 100

R119

open

R133 openR

110

100

+

C10510u(A)

R145 100

R132 0

R153

10k

R102

(short

)

C102 0.1u

R112

100

R148

10k

R137 open

C1090.1u

R142 100

SW100

1 2 3 4 5 6

12

11

10

9 8 7

R107

0

R117

open

+

C101 10u(A)

R124 open

R135 open

R103

(short

)

R109

51

R136 0

C103 0.1u

R144 100

R139 open

R134 0

R122 0

R100 33k

R129 0

C1100.1u

R138 0

R149

10k

R115

0

R104

(short

)R127 open

R106

open

+C11210u(A)

- 35-

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

5 5

HL

LRCK

MCLK

SDTOBICK

DIR

DIR

DIR

EXT

EXT

EXT

EXT

DIR

CDTI/SDA

CCLK/SCL

CSNCSNCCLK/SCLCDTI/SDA

CS

NS

CL

/CC

LK

SD

A/C

DT

I

VCC -> TVDD

VCC -> TVDDMCLK

BICK

SDTO

LRCK

WCK

CDTI/SDA-10PINCCLK/SCL-10PINCSN-10PIN

CCLK/SCL

CDTI/SDA

CSN

AVSS AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

MCLK-DIR

BICK-DIR

SDTO-DIR

LRCK-DIR

VCC-R1

PDN-0-R1

MCLK-R1

BICK/BCK-R1

SDATA1/DSDL-R1

LRCK/DINR-R1

VCC-R1

TVDD

CCLK/SCL

CDTI/SDA

TVDD

CSN

MCLKMCLK-R1

TVDD

BICK/BCK-R1LRCK/DINR-R1

SDATA1/DSDL-R1

BICK/BCKLRCK/DINR

SDATA1/DSDL

PDN-0-R1 PDN-0

WCK-R1

WCK-R1 WCK

Title


Date: Sheet ofDigital Signal for AK4497 0

AKD4497-SAA3


Title



AKD4497-SAA3


Title



AKD4497-SAA3


R206open

R210

51

C200

0.1u

R211

51

R201

0

R228

100k

R207

0

R225

470

R202open

U202PCA9306DP1

GND1

VREF12

SCL13

SDA14

EN8

VREF27

SCL26

SDA25

R215 51

R208open

C2010.1u

PORT201

uP-I/F

1357910

8642

R224

470

C203 0.1u

PORT200

EXT

12345 6

78910

C206

0.1u

R212

51

R227

100k

R209

51

R219 0

R231

10k

D200

KA

C204

0.1u

U201

74VCX541

A12

A23

A34

A45

A56

A67

A78

A89

OE11

OE219

Y118

Y217

Y316

Y415

Y514

Y613

Y712

Y811

VCC20

GND10

R222

10

k

R226

470

SW200PDN

213

C2020.1u

R221

10

k

R229

10k

R203

0

R214 51

R216 51U200

74HC14

GND7

1A1

3A5

5A11

5Y10

3Y6

1Y2

2Y4

4Y8

6Y12

6A13

4A9

2A3

VCC14

R230

10k

R200

10k

R204open

R213 0

R223

10

k

U203PCA9306DP1

GND1

VREF12

SCL13

SDA14

EN8

VREF27

SCL26

SDA25

R218 51

R232

10k

R205

0

R217 51

R220

10

k

C205 0.1u

- 36-

5

5

4

4

3

3

2

2

1

1

E E

D D

C C

B B

A A

OC

KS

0

H

L

OC

KS

1OPT

COAX

Change:DIF2-0=HLH -> HLL

BICK-DIR

MCLK-DIR

SDTO-DIR

LRCK-DIR

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

OCKS0-R

OCKS0-R

SDTO-DIR

OCKS1-R

LRCK-DIR

MCLK-DIR

OCKS1-R

PDN-0

BICK-DIR

VCC-R1

VCC-R1

VCC-R1

VCC-R1

VCC-R1

VCC-R1

Title


Date: Sheet of

<AK4118A-DIR> 0

AKD4497-SA

A3


Title


Date: Sheet of

<AK4118A-DIR> 0

AKD4497-SA

A3


Title


Date: Sheet of

<AK4118A-DIR> 0

AKD4497-SA

A3


R301

75

R313 0

C306

0.1u

+

C30910u

R303

0

C304 0.1u

R314 0

R306 open

+

C303 10u

L300 47uH1 2

SW300

1 24 3

R305

47

k

+C30110u

R307 0

PORT300

RX-OPT

OUT1

VCC3

GND2

U300

IPS0/RX41

NC2

DIF0/RX53

TEST24

DIF1/RX65

VSS16

DIF2/RX77

IPS1/IIC8

P/SN9

XTL010

XTL111

TV

DD

13

NC

/GP

11

4

TX

0/G

P2

15

TX

1/G

P3

16

BO

UT

/GP

41

7

CO

UT

/GP

51

8

UO

UT

/GP

61

9

VO

UT

/GP

72

0

DV

DD

21

VS

S2

22

MC

KO

12

3

BICK26

MCKO227

DAUX28

XTO29

XTI30

PDN31

CM0/CDTO/CAD132

CM1/CDTI/SDA33

OCKS1/CCLK/SCL34

OCKS0/CSN/CAD035

INT036

AV

DD

38

R3

9

VC

OM

40

VS

S3

41

RX

04

2

NC

43

RX

14

4

TE

ST

14

5

RX

24

6

VS

S4

47

RX

34

8

VIN/GP012

LR

CK

24

SDTO25

INT

13

7

C302 0.1u

C308

0.1u

J300RX-COAX

12345

R315

0R316 10k

R308 open

+

C30710u

R309 0

R310 0

R311 open

C305

0.47u

R304

47

k

C300

0.1u

R302open

R30051

R312 0

- 37-

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

5 5

Lch

Rch

-15V

AVSS

AVSS AVSS

AVSS

AVSSAVSS

AVSSAVSS

AVSSAVSS

AVSS

AVSS AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AOUTLP

AOUTLN

AOUTRP

AOUTRN

MVDD

MVDD

Title


Date: Sheet ofExternal LPF 0

AKD4497-SAA3

4 5Thursday, October 29, 2015

Title



AKD4497-SAA3


Title



AKD4497-SAA3


R811

10

0

C40727n

+

C43110u

R434620

R418short

C41927n

R810

10

0

+

C444470u

R411100

J402LOUT

+

-

U400B

OPA1612

5

67

84

R410220

+

-

U403

OPA16113

26

74

C80356n

R417100

R42120k

R41520k

R428620

+C433100u

+C441100u

R404220

R80022

R425620

R406short

R405100

R460

Short

J401

22

33

11

R412short

R813

10

0

R440short

+

-

U402

OPA16113

26

74

R439620

R40122

C40127n

C4281n

R80222

C41327n

R422220

R416220

+

C443100u

C80156n

J404

R441open

R435620

+

C40610u

R41922

C4361n

C4420.1u

R812

10

0

C4340.1u

+

C41810u

R40320k

R429620

C4400.1u

R424620

+

-

U401B

OPA1612

5

67

84

C4301n

R41322

+

C40010u

R80322

+

-

U401A

OPA1612

3

21

84

+

C435100u

C80056n

+

C43910u

R431open

+

C41210u

R400short

R438620

C80256n

R423100

+

-

U400A

OPA1612

3

21

84

C4320.1u

R430short

R40722

J400

22

33

11

R80122

C4381n

R40920k

J403ROUT

- 38-

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

5 5

AVSS

REG(+15V)

LT1963AEST-1.8

1.8V

5V

5V

3.3VVCC-R1 -> AK4118A, DigitalSignal

VCC-R -> Regulator(3.3V->1.8V)

3.3V

AVSS

DVSS-LAYER1

DVSS-LAYER4

AVSSAVSS AVSSAVSSAVSSAVSS AVSS

AVSS

AVSS

AVSSAVSS AVSS

AVSS AVSSAVSSAVSS AVSSAVSSAVSS

AVSS AVSSAVSSAVSS AVSSAVSSAVSS

AVSS

VREFHL

MVDD

VCC-R AVDD

DVDD

TVDD

VREFHR

MVDD

MVDD

VDDR

VDDL

MVDD

VCC-R1

VCC-R

VREFLR

VREFLL

Title


Date: Sheet ofPuwer Supply Unit 0

AKD4497-SAA3


Title



AKD4497-SAA3


Title



AKD4497-SAA3


Q502

BCP 56

D505

R500

270

+ C5090.1u

D503 R524 (short)

R531

(short)

R501

200

R506

(short)

C5200.1u

J500D500

Q501SB1188 CSC

R515

200

R523 (short)

R509510

+ C5081u

+ C5150.1u

T500

IN OUT

GN

D

+C530470u

J501

R5173.9k

R514

270

R519

(short)

+ C51647u

R5033.9k

R505

(short)+

C50547u

R5043.6k

R502510

R51810k

+C51747u

+C5070.1u

R512

(short)

+ C5140.01u

R5103.9k

R507

270

U500

AD817A/AD

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

+ C51047u

+C506470u

+C512470u

U501

AD817A/AD

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

R530

(short)

R516510

R5113.6k

R521 (short)

+C51847u

D502

D501

+C52147u

C5190.1u

+C5130.1u

+ C5030.1u

R551

(dummy short)

Q503SB1188 CSC

+C5010.1u

Q505SB1188 CSC

U502

AD817A/AD

NC1

-IN2

+IN3

V-4

NC8

V+7

OUT6

NC5

+C500470u

+ C5021u

Q500

BCP 56

Q504

BCP 56

R513

(short)

+C51147u

+ C50447u

D504

R508

200

R520

(short)

R550

(dummy short)

- 39-

AKD4497-SA Rev.0 English Manual · 6.Begin evaluation by following the procedure below. [Supported...

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Transcript of AKD4497-SA Rev.0 English Manual · 6.Begin evaluation by following the procedure below. [Supported...