Lecture 8• Thin-Body MOSFET’s Process II

– Source/Drain Technologies– Threshold Voltage Engineering

Reading: multiple research articles (reference list at the end of this lecture)

Atom Probe Tomography for Dopants in FinFETs

A.K. Kambham (imec), VLSI-T 2012

FinFET Source/Drain Doping Challenges: I. Fin Amorphization

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TCAD Simulation Results L. Pelaz, IEDM (2009)

• After the high energy implantation,Source/Drain regions are alwaysamorphized.→ Requires annealing for S/D regrowthto prevent leakage and reliability issues.

• Source/Drain For <110> FinFETs, the(111) planes will eventually prevent the Sire-crystallization.

R. Duffy, APL (2007)

FinFET Source/Drain Doping Challenges: II. Vertical Conformance

L. Pelaz, IEDM (2009)

Cross-sectional (left) and lateral(right) view of the B concentrationin a FinFET implanted region with:

Energy Dose Tilta 0.5 1015 10o

b 2 1015 10o

c 0.5 5x1015 10o

d 0.5 1015 45o

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TCAD Simulation Results

After 1100oC Spike Annealing

Effective Channel Length (Leff)

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• More reasonable (than Lg) parameter to optimize device performance with a certain gate pitch (i.e. technology node).

Source Drain Gate Overlap

Gate Underlap

Impacts of Source/Drain Doping Conformance

H=2

5nm

Lg=20nm

Leff starts from 30nm

SOI FinFETw/ Gauss doping in S/D region

Non-conformal S/D Doping

H=2

5nm

SOI FinFETw/ Uniform doping in S/D region

Lg=20nmConformal S/D Doping

Leff is always 30nm

Doping concentration (cm-3)

1.0E+201.3E+178.3E+13-4.3E-12-6.6E-15-1.0E-19

W=15nm

W=15nm

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.710-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Normalized over Weff = 2*Hfin + Wfin

Vds=0.7VLgate = 20nm

Dra

in C

urre

nt (A

/um

)

Gate Voltage (V)

W=1um Planar FinFET w/ Conformal S/D Dop. FinFET w/ Gaussian S/D Dop.

• S/D doping conformance strongly affects FinFET’s Leff and causing performance change.

Simulated SOI FinFET Performance

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Y. Sasaki, IEDM (2008)

Self-Regulatory Plasma Doping in FinFET’s S/D

Dense Fins High Aspect-Ratio Fins

S/D Doping Optimizations for Improving FinFET Performance

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• A multi-step implantation with different energies and ion species improves the vertical doping conformance.

T. Yamashita, VLSI-T (2011)

-20%

-50%

In Situ-Doped S/D in FinFETs

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(100)

(011)

(111)

Intel’s TriGate FET’s S/D

TCAD Simulation Results of S/D epi-regrowth after etching

• Simulation shows the final source/drain shape doesn’t depend on the initial Si over etch depth.

Courtesy of V. Moroz and M. Choi (Synopsys)

Source Drain

In Situ-doped

Retrograde Well

-20 0 201015

1016

1017

1018

1019

1020

Bor

on D

opin

g C

once

ntra

tion

(cm

-3)

Distance along Channel (nm)

~ 3 nm/dec

Impact of FinFET’s Raised S/D Shape

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H. Kawasaki, IEDM (2009)

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Why We Want Multiple VTH?

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Back Biasing Tuning in UTBB SOI MOSFETs

-0.4 0.0 0.4 0.8 1.210-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-0.4 0.0 0.4 0.8 1.2

n-FDSOILg=10um

Dra

in C

urre

nt (A

/um

)

Gate Voltage (V)

Vds=1.2V

Vb=2VVb=0VVb=-2V

n-FDSOILeff=52nm

Vds=1.2V

Vds=10mV

Gate Voltage (V)

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Body Bias

T. Skotnicki, IEDM SC (2010)

• Reverse Back Biasing: VBG: NMOS(-), PMOS(+) → VTH

• Forward Back Biasing:VBG: NMOS(+), PMOS(-) → VTH

(Back Biasing) Body Coefficient

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CBOX

Cox

∆ 2

∆ 1

Vg

Vbg

Strong Forward BiasStrong Reverse Bias

CBOX

Cox

 

  

 

∆

∆ 1

∆ 2

-3 -2 -1 0 1 2 30.1

0.2

0.3

0.4

0.5

tBOX=5nm

Measured tSOI=11nm tSOI=7nm tSOI=4nm tSOI=5nm

Back Bias (V)

Bod

y C

oeffi

cien

t

tBOX=11nm

Simulated

// ,

// ,

Reverse Bias

Forward Bias

so that VTH = r ·VBG

Define coefficient r :

UTBB SOI MOSFET’s VTH Engineering

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T. Skotnicki, IEDM SC (2010)

Impact of Back Biasing on UTBB SOI MOSFET’s Electrostatics

Q. Liu, VLSI-T (2011)

10/17/2013 15Nuo Xu EE 290D, Fall 2013

STMicroelectronics’ 28nm UTBB FDSOI MOSFETs

• RBB (or counter-type GP): → better electrostatics

• FBB (or same-type GP): → worse electrostatics

DIB

L (m

V/V)

N. Xu, VLSI-T (2012)

Impact of Back Biasing on UTBB SOI MOSFET’s Carrier Mobility

0.1 1

100

200

300

400

500

Back Bias

Elec

tron

Mob

ility

(cm

2 /V.s

)

Effective Field (MV/cm)

+2V +1.5V +1V 0V -1V -2V

(100) Si Universal

1012 1013

100

200

300

400

500

Vb=0V Vb=-1V Vb=-2V

Elec

tron

Mob

ility

(cm

2 /V.s

)

Inversion Electron Concentration (cm-2)

Vb=2V Vb=1.5V Vb=1V

(100)/<110> n-FDSOI T=300K

• RBB (or counter-type GP): → lower mobility

• FBB (or same-type GP): → higher mobility

• still follows universal mobility curve

• However, what matters IONis eff at a certain Ninv.

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UTBB’s eff vs. Eeff

Reduction due to HKMG (First)

UTBB’s eff vs. Ninv

Back Biasing in Tri-Gate MOSFET

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BB-Vth Tuning vs. WFin BB-Vth Tuning vs. HFinTEM of Nanowire Tri-Gate FET

Si

M. Saitoh, VLSI-T (2012)

• Back Biasing will be ineffective to tune VTH when the back surface area is relatively small.

→ Not an option for typical FinFETs.

FinFET’s VTH Engineering

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0.0 0.2 0.4 0.610-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Npeak=1e19cm-3

Npeak=3e18cm-3

Npeak=2e18cm-3

Npeak=1e18cm-3

HP: Nfin=1e16, Lg=14nm

LP: Nfin=1e18, Lg=20nm

Nor

mal

ized

Dra

in C

urre

nt (A

/um

)

Gate Voltage (V)• The VTH tuning ability of channel doping is limited in FinFET, due

to the shrink of Si volume as well as the superposition from PTS doping profile.

• Multiple gate length (Leff) has to be used to tune VTH.

C.-H. Lin, VLSI-T (2012)

State-of-the-Art FinFET’s SoC

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NMOS: Ioff-Idsat

C.-J. Jan, IEDM (2012)

Intel’s 20nm TriGate MOSFET

R. Brain, VLSI-T (2013)

Knobs: • gate length (Lg & Leff)• Doping (PTS, Fin…)

Wordline

Summary of FinFET and UTBB SOI MOSFET’s VTH Engineering

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HVT

RVT

LVT

SLVT100 nA

10 nA

1 nA

100 pA

10 pA

IEFF

IOFF (nA/um)

High Doping, Long Lg

High Doping, Moderate Lg

Low Doping, Moderate Lg

Low Doping

HVT

RVT

LVT

SLVT

IEFF

IOFF (nA/um)

RBB + GP doping, Long Lg

RBB + GP doping

FBB + GP doping

ZBB + GP doping

• Assuming single gate metal (workfunction) for each type (N or P) of MOSFETs.

FinFET UTBB SOI MOSFET

ReferencesFinFET Source/Drain1. L. Pelaz, L. Marques, M. Aboy, P. Lopez, I. Santos, R. Duffy, “Atomistic Process Modeling Based on

Kinetic Mone Carlo and Molecular Dynamics for Optimization of Advanced Devices,” IEEEInternational Electron Device Meeting Tech. Dig., pp. 513-516, 2013.

2. R. Duffy, M.J.H. Van Dal, B.J. Pawlak, M. Kaiser, R.G.R. Weemaes et al., “Solid Phase Epitaxyversus Random Nucleation and Growth in sub-20nm Wide Fin Field-Effect Transistors,” AIP AppliedPhysics Letters, Vol.90, 241912, 2007.

3. Y. Sasaki, K. Okashita, K. Nakamoto, T. Kitaoka, B. Mizuno et al., “Conformal Doping for FinFETsand Precise Controllable Shallow Doping for Planar FET Manufacturing by a Novel B2H6/HeliumSelf-Regulatory Plasma Doping Process,” IEEE International Electron Device Meeting Tech. Dig.,pp. 917-920, 2008.

4. T. Yamashita, V.S. Basker, T. Standaert, C.-C. Yeh, T. Yamamoto et al., “Sub-25nm FinFET withAdvanced Fin Formation and Short Channel Effect Engineering,” Symposium on VLSI TechnologyDig., pp.14-15, 2011.

5. M. Choi, V. Moroz, L. Smith, O. Penzin, “14nm FinFET Stress Engineering with Epitaxial SiGeSource/Drain,” International SiGe Technology and Device Meeting Tech. Dig., 2012.

6. H. Kawasaki, V.S. Basker, T. Yamashita, C.-H. Lin, Y. Zhu et al., “Challenges and Solutions ofFinFET Integration in an SRAM Cell and a Logic Circuit for 22nm Node and Beyond,” IEEEInternational Electron Device Meeting Tech. Dig., pp. 289-292, 2009.

UTBB SOI VTH Tuning7. T. Skotnicki, “CMOS Technologies – Trends, Scaling and Issues,” IEEE International Electron

Device Meeting Short Course, 2010.

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References8. Q. Liu, F. Monsieur, A. Kumar, T. Yamamoto, A. Yagishita et al., “Impact of Back Bias on Ultra-Thin

Body and BOX (UTBB) Devices,” Symposium on VLSI Technology Dig., pp.160-161, 2011.9. N. Xu, F. Andrieu, B. Ho, B.-Y. Nguyen, O. Weber et al., “Impact of Back Biasing on Carrier

Transport in Ultra-Thin-Body and BOX (UTBB) Fully Depleted SOI MOSFETs,” Symposium on VLSITechnology Dig., pp.113-114, 2012.

FinFET VTH Tuning10. M. Saitoh, K. Ota, C. Tanaka, K. Uchida, T. Numata, “10nm-Diameter Tri-Gate Silicon Nanowire

MOSFETs with Enhanced High-Field Transport and VTH Tunability through Thin BOX,” Symposiumon VLSI Technology Dig., pp.11-12, 2012.

11. C.-H. Lin, R. Kambhampati, R.J. Miler, T.B. Hook, A. Bryant et al., “Channel Doping Impact onFinFETs for 22nm and Beyond,” Symposium on VLSI Technology Dig., pp.15-16, 2012.

12. (Intel’s Tri-Gate SoC) C.-H. Jan, U. Bhattacharya, R. Brian, S.-J. Choi, G. Gurello et al., “A 22nmSoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra LowPower, High Performance and High Density SoC Applications,” IEEE International Electron DeviceMeeting Tech. Dig., pp.44-47, 2012.

13. (Intel’s Tri-Gate eDRAM) R. Brian, A. Baran, N. Bisnik, H.-P. Chen, S.-J. Choi et al., “A 22nm HighPerformance Embedded DRAM SoC Technology Featuring Tri-Gate Transistors and MIMCAPCOB,” Symposium on VLSI Technology Dig., pp.16-17, 2013.

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