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PrimeTime: Introduction to Static Timing Analysis Unit 6: Specifying Timing Exceptions6-1

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Specifying Timing ExceptionsPrimeTime: Introduction to Static Timing AnalysisSynopsys 34000-000-S16

Agenda: Day Two

DAY2222 I/O Paths and Exceptions LabUnit

Introduction to Timing Models (QTM)7

8

Specifying Timing Exceptions6

Constraining I/O Interface Paths5

Summary9

Performing STA

Customer Support10


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Unit Objectives

� List 4 timing exception commands and state their legal start and end points

� Specify false path exception in 3 design examples

� Write down the relationship between the Setup and Hold Multipliers when applying a multicycle path exception

� State the command to look for ignored exceptions

� Give 2 recommendations to specify timing exceptions effectively

After completing this unit, you should be able to:


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The Inputs and Outputs of PrimeTime

Reports

PrimeTime

Technology Libraries

SDFTiming

Models in .db format

Gate-LevelNetlist Constraints Exceptions

SetupFile

Log,Script Files

Our Focus


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Five Step Static Timing Analysis Flow

READREAD

CONSTRAINCONSTRAIN

EXCEPTIONSEXCEPTIONS

CHECKCHECK

ANALYZEANALYZEOur Focus


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What are Timing Exceptions?

Timing exceptions are used to overridethe default single-cycle constraints

described by create_clock, set_input_delay, and set_output_delay.

Timing exceptions are used to overridethe default single-cycle constraints

described by create_clock, set_input_delay, and set_output_delay.

F1 F2

single clock cycle


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Timing Exception Commands

set_false_path

set_multicycle_path

set_max_delay

set_min_delay

Removes timing constraints from a timing path

Allows more than one clock cycle for a timing path

Specifies max and min delays on paths

Restores the default timing constraints on specified paths

reset_path

Reports current timing exceptionsreport_exceptions

Timing exceptions can be applied to any timing path:Timing exceptions can be applied to any timing path:


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Applying Exceptions 1/2

When using –from and –to options, you need to specify legal path start and end points:

pt_shell> set_false_path –from A –to R1/D

pt_shell> set_false_path –from clk1 –to clk2

A D Q

R1

clk1

clk2

D Q

R2

Start & EndEndStart

Input Ports and Clock Pins

of Registers

Output Ports and Data Pins of Registers

Clock Objects, Registers

The complete commands for the example shown above should be:set_false_path –from [get_pins A] –to [get_pins R1/D]set_false_path –from [get_clocks clk1] –to [get_clocks clk2]

When specifying register cell names for the start and end points, (under the hood) PrimeTime will look for the actual start and end pins of the register cell and apply the timing exception correctly for you.

You can be very specific with timing exceptions with -to/-from/-through options by specifying rise or fall edges. New options include:-rise_from

-fall_from

-rise_to

-fall_to

-rise_through

-fall_through


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Applying Exceptions 2/2

� When using the –through option, any pin can be used to describe the path:

� The path from R1/CP to R2/D will be false

� Assumption: No fanin/fanout

pt_shell> set_false_path –through U12/Z

D Q

R1

clk

D Q

R2U12

Z

When using the –through option, multiple –through arguments mean AND, multiple pins in one –through are an OR.Example:set_false_path –through A –through B –through {C D}

means set a false path through the path that goes through “A and B and (C or D).”


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Multiple Paths

pt_shell> set_multicycle_path 2 -from FFA/CP \

-through Multiply/Out -to FFB/D

pt_shell> set_multicycle_path 2 -from FFA/CP \

-through Multiply/Out -to FFB/D

One-Cycle Path

Two-Cycle Path

Multiply

Add sel

FFAFFB

-through

-from -toIn

OutD

CP

In this example, it is sufficient to specify Multiply/Out using the –through option, without the -from and –to.


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� The paths through both A’s and both B’s cannot happen:� They are logical false paths!

� Use the -through option:

set_false_path –through mux1/A –through mux2/A

set_false_path –through mux1/B –through mux2/B

Logically False Paths

01 0

1mux1

mux2

AA

BB

You can find logical false paths with the “report_timing –true/-false/-justify” command. This command will apply input combinations and trace through the netlist to find whether the reported path is logically correct. Consult the PrimeTime User Guide for a detailed explanation.Generally, you would only set this path as a false path if it appears in the timing reports with a violation.


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Paths Between Asynchronous Clocks

current_design FUNC_CORE

/* Make sure register-register paths meet timing */create_clock -period 10 [get_ports CLKA]create_clock -period 10 [get_ports CLKB]

/* Don’t optimize logic crossing clock domains */set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]

CLKA(100 Mhzfrom OSC1)

CLKB(100 Mhzfrom OSC2)

DN X

Des_BDes_ADes_A

FUNC_CORE

D DQ Q Q

CLKA and CLKB are asynchronous to each other.To exclude Timing analysis between these 2 clock domains, specify the path(s) as false paths.


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Constrain Tri-states at the Top-Level

Tri-states can be the cause of many false paths.

set_false_path -through [get_pins U1/DATA_BUS_OUT[1]] \

-through [get_pins U1/DATA_BUS_IN[1]]

UART

CPU

TIMER

TOP_BLOCK

U1 U2

U3DATA_BUS

DATA_BUS_OUT DATA_BUS_IN


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Multi-cycle Paths

Clock period is 10 ns. Per Specification, the adder takes 6 clock cycles.How do you constrain the design?

Clock period is 10 ns. Per Specification, the adder takes 6 clock cycles.How do you constrain the design?

A

B

D Q

AE

D Q

BE

D Q

E

Clk

Y

C_reg

+ 64

64

64

0 0 0 0 0 1

D Q

< 60 ns

shift_reg


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Timing with Multi-cycle Constraints

create_clock -period 10 [get_ports CLK]

set_multicycle_path 6 –setup -to [get_pins C_reg[*]/D]

create_clock -period 10 [get_ports CLK]

set_multicycle_path 6 –setup -to [get_pins C_reg[*]/D]

0ns 10CLK

20 30 40 50 60-10

Launch Capture

IDEAL: TH < Adder_Delay < (60 - TSU)C_reg/D

PT assumes change could occur near any clock edge causing metastability!

C_reg/D

Where does PT perform hold analysis?

TSU = setup timeTH = hold time

PT will perform the setup analysis on edge 6, i.e. at 60 ns. This will allow the adder’s logic to have a delay of (60 – setup_time – uncertainty).


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Default Hold Check

set_multicycle_path -setup 6 -to [get_pins C_reg[*]/D]

set_multicycle_path -hold 0 -to [get_pins C_reg[*]/D]



0ns 10CLK

20 30 40 50 60-10

Launch Capture

C_reg/D

IMPLICIT!

(50 + TH) < Combo_Logic < (60 - TSU)

Default Hold

Check

Why is hold check performed at 50 ns?

The default Hold check is always performed one edge before the setup check.PT assumes that the clock edges at 10-50 ns can cause metastability if they occur at the same time thedata changes. Putting the hold check at 50 ns is the safest.


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Set the Proper Hold Constraint





0ns 10CLK

20 30 40 50 60-10

Setup Checkwith MS = 6

C_reg/D

OVERRIDE!

DESIRED RESULT: ALLOW 60ns for ADDER

D QD Q +C_reg

Now allows change between TH and (60 - TSU)

Hold checks for : MH = 5 MH = 4 MH = 3 MH = 2 MH = 1 MH = 0

MH = MS - 1

E E

MH stands for Hold Multiplier, MS for Setup Multiplier. The Setup multiplier counts up with increasing clock cycles, the Hold multiplier counts up with decreasing cycles. The origin (0) for the Hold Multiplier is always at the Setup Multiplier – 1 position.


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Precedence of Timing Exceptions

set_false_path –from clk1 –to clk2

set_max_delay 7 –from F1 –to F2

set_false_path –from clk1 –to clk2

set_max_delay 7 –from F1 –to F2

F1

clk1clk2

F2

More than one exception set on the path from F1 to F2.set_false_path has higher precedence!(see student notes)

PrimeTime uses the following general precedence rules, when applying multiple exceptions to the same path:

• set_false_path > set_max_delay or set_min_delay > set_multicycle_path• pin > clock• -from > -to > -through• tighter constraint > looser constraint

For more detailed information refer to the PrimeTime User Guide: Advanced Timing Analysis.


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Ignored Timing Exceptions

PrimeTime will warn you when invalid exceptions are applied.

pt_shell> set_false_path -from FF1/Q

Warning: Object 'FF1/Q' is not a valid

startpoint. (UITE-216)

How would you correct this exception?

set_false_path -from FF1/Q -- Invalid because this is an INVALID start point.The exception needs the CLK pin of the flip-flop, so the correct syntax would be:set_false_path -from FF1/CLK


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Warning: There are timing exceptions which are ignored.Warning: There are timing exceptions which are ignored.

Always Check for Invalid Exceptions

pt_shell> check_timing

Warning: There are timing exceptions which are ignored.

From To Setup Hold---------------------------------------------------------

FF1/Q * FALSE FALSE

Warning: There are timing exceptions which are ignored.

From To Setup Hold---------------------------------------------------------

FF1/Q * FALSE FALSE

pt_shell> check_timing -verbose -ignored

To remove any unwanted exceptions, use the reset_path command, e.g.:reset_path –from FF1/Q

You may also use the command report_exceptions –ignored to view ignored exceptions.


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Reduce Number of Timing Exceptions

To reduce the run-time for timing analysis, minimize the total number of exceptions!

The paths from F1_reg to F2_reg are false. How many exceptions do each of the following commands generate?

set_false_path -from F1_reg[*]/CPset_false_path -from F1_reg[*]/CP 3

set_false_path -from [get_clocks clk1] -to [get_clocks clk2]set_false_path -from [get_clocks clk1] -to [get_clocks clk2] 4

for {set i 1} {$i <= 32} {incr i} {set_false_path -from F1_reg[$i]/CP -to F2_reg[$i]/D

}

for {set i 1} {$i <= 32} {incr i} {set_false_path -from F1_reg[$i]/CP -to F2_reg[$i]/D

}2

set_false_path -from F1_reg[*]/CP -to F2_reg[*]/Dset_false_path -from F1_reg[*]/CP -to F2_reg[*]/D 1

clk1clk2

F1 F2 F332

The most efficient way to specify timing exceptions is between clock domains!


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Optimizing Analysis Time 1/2

� The -through option requires more CPU for large designs� Do not use -through unless it is necessary

set_multicycle_path 2 -from U1/CP -through U2/A-through U3/B -through U4/A

-through U5/C -to U6/D

set_multicycle_path 2 -from U1/CP -through U2/A-through U3/B -through U4/A

-through U5/C -to U6/D

Sub-Optimal:Sub-Optimal:

set_multicycle_path 2 -to U6/Dset_multicycle_path 2 -to U6/D

To help PT’s run time, use -to option when possible.

Optimal:Optimal:


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Optimizing Analysis Time 2/2

Use set_disable_timing instead of set_false_path -throughwhen there is one pin.

set_false_path -through [get_pins ADDER/CI]set_false_path -through [get_pins ADDER/CI]

set_disable_timing [get_pins ADDER/CI]set_disable_timing [get_pins ADDER/CI]

Sub-Optimal:Sub-Optimal:

Optimal:Optimal:

Slow

Fast


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Lab Overview and Review

� Apply Multicycle and false path exceptions on a complex design

� How do you know where in a design to apply a multicycle path constraint?

� After applying a multicycle path constraint, how can you verify the constraint has been applied correctly?

LAB

60 min

Lab Review

Answers will follow.


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Test For Understanding

� A path between 2 flops are controlled by a 200 MHz clock. The path delay is 13 ns worst case. Clock has a network delay of 3 ns, and an uncertainty of 1 ns. Assume both setup and hold time are 0.5 ns. The best case delay of this path is known to be 6 ns. Write down the exceptions such that there will not be any setup or hold violations:

______________________________________________

______________________________________________

� How can you constrain a path from an asynchronous Reset input port to the Rst pin of a flop? The worst case absolute delay is 3 ns and the best case absolute delay is 0.9 ns.

______________________________________________

______________________________________________

Agenda: Day Tworead.pudn.com/.../PrimeTime_Intro_to_STA/print... · PrimeTime: Introduction to...

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