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INDEXCHAPTER 1 INTRODUCTION

1.1.Background of the Algorithm

1.2.About AES Algorithm 1

1.3. Notation and Conventions 3

1.3.1. Inputs and Outputs 3

1.3.2. Bytes 4

1.3.3. Arrays of Bytes 5

1.3.4. The State 5

1.3.5. The State as an Array of Columns 8

1.4. Mathematical Background 8

1.4.1. Addition 8

1.4.2. Multiplication 9

1.4.3. Multiplication by x 11

1.4.4. Polynomials with Coefficients in GF (28) 12

1.5. Encryption & Decryption 15

1.6. Cryptography & Types 16

CHAPTER 2 ENCRYPTION 22

2.1. Encryption Process 22

2.2. Bytes Substitution Transformation 24

2.3. Shift Rows Transformation 27

2.4. Mixing of Columns Transformation 28

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2.5. Addition of Round Key Transformation 29

2.6. Key Schedule Generation 30

CHAPTER 3 DECRYPTION 34

3.1. Decryption Process 34

3.2. Inverse Bytes Substitution Transformation 35

3.3. Inverse Shift Rows Transformation 36

3.4. Inverse Mixing of Columns Transformation 37

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Background of the AES Algorithm:

The National Institute of Standards and Technology, (NIST), solicited proposals

for the Advanced Encryption Standard, (AES). The AES is a Federal Information

Processing Standard, (FIPS), which is a cryptographic algorithm that is used to protect

electronic data. The AES algorithm is a symmetric block cipher that can encrypt,

(encipher), and decrypt, (decipher), information. Encryption converts data to an

unintelligible form called cipher-text. Decryption of the cipher-text converts the data

back into its original form, which is called plaintext. The AES algorithm is capable of

using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks

of 128 bits.

Many algorithms were originally presented by researchers from twelve different

nations. Fifteen, (15), algorithms were selected from the first set of submittals. After a

study and selection process five, (5), were chosen as finalists. The five algorithms

selected were MARS, RC6, RIJNDAEL, SERPENT and TWOFISH. The conclusion was

that the five Competitors showed similar characteristics. On October 2nd 2000, NIST

announced that the Rijndael Algorithm was the winner of the contest. The Rijndael

Algorithm was chosen since it had the best overall scores in security, performance,

efficiency, implementation ability and flexibility, [NIS00b]. The Rijndael algorithm wasdeveloped by Joan Daemen of Proton World International and Vincent Fijmen of

Katholieke University at Leuven.

About the AES algorithm:

The Rijndael algorithm is a symmetric block cipher that can process data

blocks of 128 bits through the use of cipher keys with lengths of 128, 192, and 256 bits.

The Rijndael algorithm was also designed to handle additional block sizes and key

lengths. However, the additional features were not adopted in the AES. The hardware

implementation of the Rijndael algorithm can provide either high performance or low

cost for specific applications. At backbone communication channels or heavily loaded

servers it is not possible to lose processing speed, which drops the efficiency of the

overall system while running cryptography algorithms in software. On the other side, a

low cost and small design can be used in smart card applications, which allows a wide

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range of equipment to operate securely.

AES is a block cipher with a block length of 128 bits. AES allows for three

different key lengths: 128, 192, or 256 bits. AES will assume that the key length is 128

bits. Encryption consists of 10 rounds of processing for 128-bit keys, 12 rounds for 192-

bit keys, and 14 rounds for 256-bit keys. Except for the last round in each case, all other

rounds are identical. Each round of processing includes one single-byte based substitution

step, a row-wise permutation step, a column-wise mixing step, and the addition of the

round key. The order in which these four steps are executed is different for encryption

and decryption. To appreciate the processing steps used in a single round, it is best to

think of a 128-bit block as consisting of a 4 4 matrix of bytes, arranged as follows:

Byte(0) Byte(4) Byte(8) Byte(12)




Therefore, the first four bytes of a 128-bit input block occupy the first column in the 4

4 matrix of bytes. The next four bytes occupy the second column, and so on. The 4 4

matrix of bytes is referred to as the state array. AES also has the notion of a word. A

word consists of four bytes that is 32 bits. Therefore, each column of the state array is a

word, as is each row. Each round of processing works on the input state array and

produces an output state array. The output state array produced by the last round is

rearranged into a 128-bit output block. Unlike DES, the decryption algorithm differs

substantially from the encryption algorithm. Although, overall, the same steps are used in

encryption and decryption, the order in which the steps are carried out is different, as

mentioned previously.

AES, notified by NIST as a standard in 2001, is a slight variation of the Rijndael

cipher invented by two Belgian cryptographers Joan Daemen and Vincent Rijmen.

Whereas AES requires the block size to be 128 bits, the original Rijndael cipher works

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with any block size (and any key size) that is a multiple of 32 as long as it exceeds 128.

The state array for the different block sizes still has only four rows in the Rijndael cipher.

However, the number of columns depends on size of the block. For example, when the

block size is 192, the Rijndael cipher requires a state array to consist of 4 rows and 6

columns.

DES was based on the Feistel network. On the other hand, what AES uses is a

substitution-permutation network in a more general sense. Each round of processing in

AES involves byte-level substitutions followed by word-level per-mutations. Speaking

generally, DES also involves substitutions and permutations, except that the permutations

are based on the Feistel notion of dividing the input block into two halves, process-ing

each half separately, and then swapping the two halves. The nature of substitutions and

permutations in AES allows for a fast software implementation of the algorithm.

1.2. Notation and Conventions

1.2.1. Inputs and Outputs

The input and output for the AES algorithm consists of sequences of 128 bits.

These sequences are referred to as blocks and the numbers of bits they contain are

referred to as their length. The Cipher Key for the AES algorithm is a sequence of 128,

192 or 256 bits. Other input, output and Cipher Key lengths are not permitted by this

standard. The bits within such sequences are numbered starting at zero and ending at oneless than the sequence length, which is also termed the block length or key length. The

number iattached to a bit is known as its index and will be in one of the ranges 0 i =107)

Advantages of ICs over discrete components

While we will concentrate on integrated circuits , the

properties of integrated circuits-what we can and cannot efficiently put in an

integrated circuit-largely determine the architecture of the entire system.

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Integrated circuits improve system characteristics in several critical ways. ICs

have three key advantages over digital circuits built from discrete components:

Size. Integrated circuits are much smaller-both transistors and

wires are shrunk to micrometer sizes, compared to the millimeter

or centimeter scales of discrete components. Small size leads to

advantages in speed and power consumption, since smaller

components have smaller parasitic resistances, capacitances, and

inductances.

Speed. Signals can be switched between logic 0 and logic 1 much

quicker within a chip than they can between chips.

Communication within a chip can occur hundreds of times faster

than communication between chips on a printed circuit board.

The high speed of circuits on-chip is due to their small size-smaller

components and wires have smaller parasitic capacitances to slow

down the signal.

Power consumption. Logic operations within a chip also take much

less power. Once again, lower power consumption is largely due

to the small size of circuits on the chip-smaller parasitic

capacitances and resistances require less power to drive them.

VLSI and systems

These advantages of integrated circuits translate into advantages at the system

level:

Smaller physical size. Smallness is often an advantage in itself-

consider portable televisions or handheld cellular telephones.

Lower power consumption. Replacing a handful of standard

parts with a single chip reduces total power consumption.

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Reducing power consumption has a ripple effect on the rest of

the system: a smaller, cheaper power supply can be used; since

less power consumption means less heat, a fan may no longer

be necessary; a simpler cabinet with less shielding for

electromagnetic shielding may be feasible, too.

Reduced cost. Reducing the number of components, the power

supply requirements, cabinet costs, and so on, will inevitably

reduce system cost. The ripple effect of integration is such that

the cost of a system built from custom ICs can be less, eventhough the individual ICs cost more than the standard parts

they replace.

Understanding why integrated circuit technology has such profound influence

on the design of digital systems requires understanding both the technology of

IC manufacturing and the economics of ICs and digital systems.

Applications

Electronic system in cars.

Digital electronics control VCRs

Transaction processing system, ATM

Personal computers and Workstations

Medical electronic systems.

Etc.

Applications of VLSI

Electronic systems now perform a wide variety of tasks in daily

life. Electronic systems in some cases have replaced mechanisms that operated

mechanically, hydraulically, or by other means; electronics are usually smaller,

more flexible, and easier to service. In other cases electronic systems have

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created totally new applications. Electronic systems perform a variety of tasks,

some of them visible, some more hidden:

Personal entertainment systems such as portable MP3 players

and DVD players perform sophisticated algorithms with

remarkably little energy.

Electronic systems in cars operate stereo systems and displays;

they also control fuel injection systems, adjust suspensions to

varying terrain, and perform the control functions required for

anti-lock braking (ABS) systems.

Digital electronics compress and decompress video, even at

high-definition data rates, on-the-fly in consumer electronics.

Low-cost terminals for Web browsing still require sophisticated

electronics, despite their dedicated function.

Personal computers and workstations provide word-processing, financial analysis, and games. Computers include

both central processing units (CPUs) and special-purpose

hardware for disk access, faster screen display, etc.

Medical electronic systems measure bodily functions and

perform complex processing algorithms to warn about unusual

conditions. The availability of these complex systems, far from

overwhelming consumers, only creates demand for even more

complex systems.

The growing sophistication of applications continually pushes the design and

manufacturing of integrated circuits and electronic systems to new levels of

complexity. And perhaps the most amazing characteristic of this collection of

systems is its variety-as systems become more complex, we build not a few

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general-purpose computers but an ever wider range of special-purpose

systems. Our ability to do so is a testament to our growing mastery of both

integrated circuit manufacturing and design, but the increasing demands of

customers continue to test the limits of design and manufacturing

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2.VERILOG HDL

Verilog HDL is a hardware description language that can be used to model a digital system at

many levels of abstraction ranging from the algorithmic-level to the gate-level to the switch-level.

The complexity of the digital system being modeled could vary from that of a simple gate to a

complete electronic digital system, or anything in between. The digital system can be described

hierarchically and timing can be explicitly modeled within the same description.

The Verilog HDL language includes capabilities to describe the behavior-al nature of a design,

the dataflow nature of a design, a design's structural composition, delays and a waveform

generation mechanism including aspects of response monitoring and verification, all modeled using

one single language. In addition, the language provides a programming language interface through

which the internals of a design can be accessed during simulation including the control of a

simulation run.

The language not only defines the syntax but also defines very clear simulation semantics for

each language construct. Therefore, models written in this language can be verified using a Verilog

simulator. The language inherits many of its operator symbols and constructs from the C

programming language. Verilog HDL provides an extensive range of modeling capabilities, some of

which are quite difficult to comprehend initially. However, a core subset of the language is quite

easy to leam and use. This is sufficient to model most applications.

2.1 History:

The verilog HDL language was first developed by Gateway Design Automation in 1983 as

hardware are modleling language for their simulator product, At that time ,twas a propnetary

language. Because of the popularity of the,simulator product, Verilog HDL gained acceptance as a

usable and practical language by a number of designers. In an effort to increase the popularity of the

language, the language was placed in the public domain in 1990. Open verilog International (OVI)

was formed to promote Verilog. In 1992 OVI decided to pursue standardization of verilog HDL as an

IEEE standard. This effort was succeful and the language became an IEEE standard in 1995. The

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complete standard is described in the verilog hardware description language reference manual. The

standard is called std 1364-1995.

2.2 Major Capabilities:

Listed below are the majort capabilities of the verilog hardware description:

Primitive logic gates, such as and, or and nand, are built-in into the language.

Flexibility of creating a user-defined primitive (UDP). Such a primitive could either be a

combinational logic primitive or a sequential logic primitive.

Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into the

language.

Explicit language constructs are provided for specifying pin-to-pin delays, path delays and

timing checks of a design.

A design can be modeled in three different styles or in a mixed style. These styles are:

behavioral style - modeled using procedur-al constructs; dataflow style - modeled using

continuous assign-ments; and structural style - modeled using gate and module

instantiations.

There are two data types in Verilog HDL; the net data type and the register data type. The

net type represents a physical connection between structural elements while a register type

represents an abstract data storage element.

Figure.2-1 shows the mixed-level modeling capability of Verilog HDL, that is, in one design,

each module may be modeled at a different level.

Fi :2-1 Mixed level modellin

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Verilog HDL also has built-in logic functions such as & (bitwise-and) and I (bitwise-or).

High-level programming language constructs such as condition- als, case statements, and

loops are available in the language.

Notion of concurrency and time can be explicitly modeled.

Powerful file read and write capabilities fare provided.

The language is non-deterministic under certain situations, that is, a model may produce

different results on different simulators; for example, the ordering of events on an event

queue is not defined by the standard.

2.3 SYNTHESIS:

Synthesis is the process of constructing a gate level netlist from a register-transfer level

model of a circuit described in Verilog HDL. Figure.2-2 shows such a process. A synthesis system may

as an intermediate step, generate a netlist that is comprised of register-transfer level blocks such as

flip-flops, arithmetic-logic-units, and multiplexers, interconnected by wires. In such a case, a second

program called the RTL module builder is necessary. The purpose of this builder is to build, or

acquire from a library of predefined components, each of the required RTL blocks in the user-

specified target technology.

Having produced a gate level netlist, a logic optimizer reads in the netlist and optimizes the

circuit for the user-specified area and timing constraints. These area and timing constraints may also

Figure.2-2 synthesis process

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be used by the module builder for appropriate selection or generation of RTL blocks. In this book, we

assume that the target netlist is at the gate level. The logic gates used in the synthesized netlists are

described in Appendix B. The module building and logic optimization phases are not described in this

book.

The above figure shows the basic elements ofVerilog HDL and the elements used in

hardware. A mapping mechanism or a construction mechanism has to be provided that translates

the Verilog HDL elements into their corresponding hardware elements as shown in figure.2-3

Fig.2-3 Typical design process

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RESULTS

ENCRYPTION WF

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DECRYPTION WF

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