AEEC405 – Microprocessor Architecture

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AEEC405 – Microprocessor Architecture

description

AEEC405 – Microprocessor Architecture. Some Information. Instructor Details. Main Book. Course Overview. Prerequisites: AEEE203, AEEE200, AEEE237 Introduction to microprocessors: microprocessor technologies Pin and signal descriptions loading and timing of the 80x86 microprocessors. - PowerPoint PPT Presentation

Transcript of AEEC405 – Microprocessor Architecture

Page 1: AEEC405  –  Microprocessor Architecture

AEEC405 – Microprocessor Architecture

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Some Information

Title: The Intel Microprocessors: 8086,80186,80286,80386, 80486, Pentium and Pentium Pro Processors, Pentium II, Pentium III and Pentium 4: Architecture, Programming and Interfacing

Author: B. Brey Publisher: Prentice Hall Edition: Third Year 2003 ISBN: 0-13-1911651

Instructor Details

Main Book

NAME: Dr. Konstantinos Tatas OFFICE: 107, FRC (library) OFFICE HOURS: ?????????? EMAIL: [email protected] WEB PAGE http//www.fit.ac.cy/staff/com.tk

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Course Overview1. Prerequisites: AEEE203, AEEE200, AEEE237 2. Introduction to microprocessors: microprocessor technologies Pin and signal descriptions loading and timing of the 80x86 microprocessors. Bus drivers, clock and reset circuits. 2. Memory interfacing, and synchronization: Interfacing with EPROMs, Static and Dynamic RAMs. Address decoding, memory maps and memory mirroring. Static and dynamic bus contention. Memory timing analysis, synchronization3. Input/Output interfacing: Isolated and memory mapped I/O. LEDs, 7-segment displays, switches, keyboards relays and ac loads. I/O synchronization using interrupts and the polling technique. Interrupts. Use of programmable I/O devices. 3. Analog interfacing: Digital to analog and analog to digital converters4. Laboratory Work: Individual or small group experiments performed with single board computers.

Experiments include monitor commands, reset circuits, buffering, memory interfacing and I/O interfacing.

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Course Assessment

Assignment – 15% (approx. week 10) Mid-term exam – 15% (approx. week 6) Laboratory work – 10% Final – 60%

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HISTORICAL PERSPECTIVE 1st generation: 1945 - 1955

– Tubes, punchcards 2nd generation: 1955 - 1965

– transistors 3rd generation: 1965 – 1980

– Integrated circuits 4th generation: 1980 –

– PCs and workstations

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1st generation (1945-1955)• Programming was done in machine

language• No operating system• Programming and maintenance done

by one group of people

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ENIAC – The first electronic computer (1946)

18,000 tubes300 Tn170 KWatt

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2nd generation (1955-1965)

Transistor-based Fairly reliable Clear distinction between designers,

manufacturers, users, programmers, and support personnel.

Only afforded by governments, universities or large companies (millions $)

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2nd generation (1955-1965)

Program was first written on paper (FORTRAN) and then punched into cards

Cards were then delivered to the user.

Mostly used for scientific and technical calculations– Solving differential equations

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3rd generation (1965-1980) IC-based operation IBM develops compatible systems Tradeoffs in performance, memory,

I/O etc). Greater MHz/$

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4th generation (1980-1990)

LSI-based PCs Significantly cheaper User-friendly software 2 dominant operating systems:

– MS DOS: IBM PC (8088, 80286, 80386, 80486)

– UNIX: RISC workstations

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5th generation (1990-) PC networks Network operating systems Each machine runs its own operating

system Users don’t care where their

programs are being executed

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Famous quotes “Future computers may weigh less than 1,5

tn”, (1949) “I believe there is a world market for five

computers”, T. Watson, IBM CEO (1943) “There is no particular reason why someone

would want a computer at home”, K. Oslon, president of DEC (1974)

“640Κbytes of memory should be enough for anybody”, B. Gates, president of Microsoft (1981)

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Moore’s Law

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Intel 4004 Micro-Processor

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Computer architecture

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Performance Measures

CC: Clock cycle count CT: clock period f : clock frequency

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Example Calculate the execution time for 6 Load/Store

and 3 ALU instructions and the average MIPS for a machine running at 500 MHz:

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RISC vs. CISC– Complex instruction set computer (CISC):

Large instruction set; Complex operations; Complex addressing modes; Complex hardware, long execution time; Minimum number of instructions needed for a given task; Easy to program, simpler compiler.

– Reduced instruction set computer (RISC): Small instruction set; Simple instructions to allow for fast execution (fewer steps); Large number of registers; Only read/write (load/store) instructions should access the main memory, one MM access per instruction; Simple addressing modes to allow for fast address computation; Fixed-length instructions with few formats and aligned fields to allow for fast instruction decoding; increased compiler complexity and compiling time; simpler and faster hardware implementation, pipelined architecture.

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RISC vs. CISC example CISC (M68000)

– Add the content of MM location pointed to by A3 to the component of an array starting at MM address 100. The index number of the component is in A2. The content of A3 is then automatically incremented by 1.

RISC (MIPS)

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Memory Architecture

Von Neumann: Common memory for data and instructions

Harvard: Separate data and instruction memories

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Von Neumann Memory Architecture

memoryCPU

PC

address

data

IRADD r5,r1,r3200

200

ADD r5,r1,r3

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Harvard Memory Architecture

CPU

PCdata memory

program memory

address

data

address

data

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Pipelining Dividing the processing task into stages, which

are executed in parallel

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Application-Specific Processors

Processors optimized for a specific application domain– DSP processors

Multiplier/accumulator in ALU, Harvard memory architecture

– Multimedia processors Image processing/video hardware accelerators

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Assembler/Compiler technologies

Increased productivity by using high-level languages

For critical tasks and embedded systems, assembly is commonly used

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References

Weste, Harris, CMOS VLSI Design: A Circuits and Systems Perspective

Patterson, Hennessy - Computer Organization and Design; The Hardware-Software Interface, 2E (Morgan Kaufman, 1997)

Fundamentals Of Computer Organization And Architecture (2005) Wiley