Advisor: Dr. Chandra
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Transcript of Advisor: Dr. Chandra
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Advisor: Dr. Chandra
Christopher Picard Michael Neuberg
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Radar Basics CSU Facilities Hardware Accelerator Pawnee Update Next Semester Plans
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Radar- RAdio Detection And Ranging
Transmits microwaves
Elevation position, ∅ Azimuth Position, Ѳ
National Weather Service
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Old CHILL Dish and Antenna
Constructing new dish location
Generates waveform of signals
Builds up signal and transmits
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Pawnee Facility
Inside the Radome
GPS, DSP, etc
Signal Monitors and Generator
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Parametric Time Domain Method (PTDM) Prevents the need for Fourier Transforms Prevents signal Leakage
Problem Requires calculating inverses and
determinates of large matrices Can not perform calculations in real time on
standard CPU Solution Requirements
Implement PTDM algorithm in real time
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Graphics Card Can perform multiple
operations in parallel Designed to optimize
required matrix calculations
Nvidia CUDA Compute Unified
Device Architecture
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SpecificationMultiprocessor 16Memory 1.5 GBShared Memory 16 KB per MPRegisters 8192 per MPThreads 768Memory Bandwidth
76.8 GB/Sec
Hewlett Packard xw 9400 workstation
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Replace synchros with optical encoders
Interface encoders and signal processor with FPGA
Design and build interface board
Improves radar tracking and positioning
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Why replace synchros?
Stegmann ARS-20 absolute encoder
Rotating encoder disk
Enhanced resolution
Reduces noise and cost with less wires
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Xilinx Spartan-3E FPGA
BASYS board
Printed Circuit Board
VHDL programming
Generate clock signal
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Donations
CHILL Radar FacilityEncoders, development board, circuit board ($1,250)
Hewlett Packardxw 9400 workstation, 2 Quadro Fx 5600
($4,500)
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Hardware Accelerator Tasks Start Date
Finish Date
Durations
Get system setup and successfully run simple test CUDA programs.
12/10/07 1/21/08 6 Weeks
Finish CUDA code that optimizes performance on real sample data
1/21/08 2/18/08 4 Weeks
Integrate CUDA code with algorithm code.
2/18/08 3/31/08 6 Weeks
Configure system to interact with radar interface and integrate system into site.
3/31/08 4/14/08 2 Weeks
Hardware Update Tasks Start Date
Finish Date
Durations
Finish programming interface for FPGA(Combine data, state machine, transmit)
------------- 1/27/08 12 Weeks
Design printed circuit board 1/27/08 3/23/08 8 WeeksBuild, test, and debug circuit board 3/23/08 4/13/08 3 Weeks
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http://www.engr.colostate.edu/ece-sr-design/AY07/radar/index.html
Acknowledgments Dr. Chandra Jim George Cuong Nguyen Darryl Benally Hewlett Packard