Advanced Operational Amplifiers - Integrated Systems Labcad.knu.ac.kr/lecture/analvlsi/opa2.pdf ·...
Transcript of Advanced Operational Amplifiers - Integrated Systems Labcad.knu.ac.kr/lecture/analvlsi/opa2.pdf ·...
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Advanced Operational Amplifiers
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Kyungpook National University
Integrated Systems Lab, Kyungpook National University
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Advanced Current Mirrors and Opamps
Two-stage opamps in many commercial ICs
Modern opamps gaining in popularity
Advanced current mirrors
Folded-cascode opamps
Current-mirror opamps
Fully-differential opamps: better noise rejection
Current-feedback opamps: large gain-bandwidth product
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Wide-Swing Cascode Current Mirrors
Output-impedance degradation by short-channel effects
Ro enhancement by cascoding: limits signal swing
Q4 lowers VDS of Q3 to match to VDS of Q2: Io = Ii
Q2 and Q3 biased at the edge of the active region.
Effective gate-source voltages for IB = Ii = Io = ID3
Veff = Veff2 = Veff3 =
√
2ID3
µnCox(W/L)
Veff5 = (n + 1)Veff , Veff1 = Veff4 = nVeff
VG1 = VG4 = VG5 ≡ Veff5 + Vtn = (n + 1)Veff + Vtn
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A wide-swing cascode current mirror with two-transistor
diode-connected circuit (whose input resistance ≃ 1/gm)
Q3
Q4
Ii
Q2
Q1
W
(n + 1)2L
Q5
IB
W
n2L
W
L
Io = Ii
Vo ≥ 0.4 V
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Minimum allowable output voltage for n = 1
VDS2 = VDS3 = VG5 − VGS1 = VG5 − (Veff1 + Vtn) = Veff
∴ Vo ≥ Veff1 + VDS2 = (n + 1)Veff = 2Veff ≃ 0.4 ∼ 0.5 V
To ensure that all transistors are in the active region
VDS4 = VG3 − VDS3 = (Veff + Vtn)− Veff = Vtn > Veff4 = nVeff
∴ Vtn > nVeff ≃ 0.2 ∼ 0.25 V
Take (W/L)5 smaller to bias Q2 and Q3 with slightly larger VDS than
the minimum ← no sharp boundary between linear and active
regions, body effect of Q1 and Q4 (VSB > 0, Vt1 ↑, VGS1 ↑, VDS2 ↓)
VDS2 ≃ Veff + (0.1 ∼ 0.15) V
L2 = 2.5λ and L1 = 4λ (twice Lmin) to reduce short-channel effects
(VDS2 < VDS1) and maximize the pole frequency (ωp2 ∝ 1/L, 1/L2)
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Wide-Swing Constant-gm Bias Circuit
Minimizes most of second-order imperfections caused by the
finite-output impedance without greatly restricting signal swings.
n-channel wide-swing cascode current mirror: Q1 −Q5
p-channel wide-swing cascode current mirror: Q6 −Q10
Cascode bias circuit: Q11 −Q14
Start-up circuit: Q15 −Q18
This bias circuit for stabilized gms allows the performance of realized
opamps to be accurately predicted using moderately simple equations.
This constant-gm bias circuit had been realized and verified for a
0.8-µm CMOS technology, and is very important in analog design.
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A wide-swing constant-gm bias circuit: small W/L for Q18
RB 5 kΩ
Q2
Q1
Q9
Q8
Q3
Q4
Q5
Q10
Q15
Q18
Vbn
Vcn
Vcp
Vbp
Q14
Q13 Q17
Q16
Q6
Q7
Q12
Q11
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Enhanced Output-Impedance Mirrors
Cascode current mirror with regulated cascode transistor to increase
output resistance Ro → gain boosting
Basic idea is to use a negative feedback amplifier to keep VDS of Q2
as stable as possible → Io is less sensitive to the output signal.
Ro = [gm1rds1(1 + A) + 1] rds2 + rds1 ≃ gm1rds1rds2(1 + A)
Practical limitation of Ro by a parasitic conductance between the
drain of Q1 and its substrate due to short-channel effects
← substrate current by impact ionization
Reduced enhancement for bipolar transistors due to the base current
Need for local compensation capacitors to prevent ringing and
substantial increase of settling time for large signal transients
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An enhanced output-impedance current mirror
Ii
Q3 Q2
Q1
+
−A
VB
Ro
−+−Avds2
+gm1vgs1vgs1 rds1
rds2
−
Circuit equations for regulated cascode current mirror: Ro = vt/it
vgs1 = −Avds2 − vds2 = −(1 + A)vds2 = −(1 + A)rds2it
it = gm1vgs1 + (vt − rds2it)/rds1
vt = (rds1 + rds2)it− gm1rds1vgs1 = [rds1 + rds2 +(1+A)gm1rds1rds2]it
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Sackinger Realization of Enhanced Ro Mirrors
The feedback amplifier is realized by CS amplifiers: A ≃ gm3rds3/2
Ro = (gm1rds1)rds2
“gm3rds3
2
”
=gm1gm3rds1rds2rds3
2
The signal swing is significantly reduced due to the feedback amplifier.
VDS5 ≡ VDS2 = VGS3 = Veff3 + Vtn ≫ Veff2
Ii
Q4
Q5
Q6
IB2
Q2
Q1
Io
Q3
IB1
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Wide-Swing Current Mirror with Enhanced Ro
Diode-connected transistors Q4 and Q8 are used as dc level shifters.
All transistors are biased with the same current density and the same
Veff except for Q3 and Q7: Veff =√
2ID/µnCox(W/L)
Ii = 7IB, Veff3 = Veff7 = 2Veff
VDS2 = VG3 − VGS4 = (2Veff + Vtn)− (Veff + Vtn) = Veff
Power dissipation of this mirror with the shown W/L values would be
almost doubled over that of a classical cascode mirror.
Power dissipation can be reduced at the expense of speed by biasing
the enhancement circuitry (Q3, Q4, Q7, Q8) at lower current density.
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A wide-swing current mirror with enhanced output impedance
Ii 7IB
Q5
Q6
Q8Q7
IB4IB
Q2
Q1
Io
Q4 Q3
4IBIB
70
80
1010
70
80
10 10
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A modified version of wide-swing enhanced output-impedance mirror:
slightly mismatching, but less area, instability, and power dissipation
Ii
Q5Vcn
circuitBias
Q6 Q2
Q1
Io = Ii
Q4 Q3
4IBIB
Q7
70
70
1010
70
70 10
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Folded-Cascode Opamp
Modern CMOS opamps are designed to drive only capacitive loads.
No voltage buffer → higher speed and larger signal swing.
Only a single high-impedance node at the output of an opamp.
The admittance at all other node is on the order of gm.
The speed of the opamp is maximized by having all internal node of
low impedance → reduced voltage signals and large current signals →current-mode opamps (ωH ≃ 1/
∑
τi = 1/∑
RioCi).
The compensation is usually achieved by the load capacitance: larger
CL, more stable but slower.
These opamps = operational transconductance amplifiers (OTAs)
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Q1, Q2 = differential transistors
Q5, Q6 = cascode transistors + dc level shifters
A single stage with a high gain of 3000 due to the high output
resistance by cascoding
Q7 ∼ Q10 = Wilson, cascode, or wide-swing current mirror
Q12, Q13 = clamp transistors : to increase the slew rate and recover
quickly from slewing as clamping the drain voltages of Q1 and Q2
Dominant pole compensation by CL or an additional capacitor
Lead compensation by a resistor placed in series with CL
Bias current of cascode transistors is derived by a current subtraction
→ IB1, IB2 from the same bias circuit using replication principle
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A folded-cascode operational amplifier with clamp transistors
Q9
Q7
Q10
Q8
VB
Q6
CL
Q17
Q1 Q2
Q16
Q14
Q15
Q11
Q3 Q4
Q5
Vi+ Vi−
Vo
Q13Q12
IB2
IB1
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Small Signal Analysis
Two signal paths have slightly different transfer functions due to poles and
zeros caused by the current mirror. For an nMOS mirror, a pole-zero
doublet occurs at frequencies greater than ωta and can be ignored.
Ignoring HF poles and zeros (ωp2 ≫ ωta) and assuming that gm5 and gm6
are much larger than gds3 and gds4, the transfer function is given by
AV =Vo
Vi
≃ gm1ZL(s) =gm1Ro
1 + sRoCL
„
Ro =gmr2
d
3∼
gmr2d
2
«
The unity-gain frequency of the opamp
ωta ≃gm1
CL
=
p
2ID1µnCox(W/L)1
CL
Maximizing gm1 maximizes the unity-gain bandwidth ωta for the given load
capacitance CL (dominant pole).
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gm1 is maximized by using wide nMOST and larger bias current than
that of cascode and mirror MOSTs of the output node → maximizes
Ro and dc gain, better thermal noise performance (v2n = 4kT
2
3gm)
A practical upper limit on the ratio of ID1 to ID5 might be around 4
due to biasing by current subtraction.
Lead compensation by a resistor RC : chosen to place a zero at 1.2ωta
AV =gm1
1/Ro + 1/(RC + 1/sCL)≃ gm1(1 + sRCCL)
sCL
The second poles are primarily due to the time constants introduced
by the resistances and parasitic capacitances at the sources of the
p-channel cascode transistors: Cs6, Rs6 =1
gm6
(1 + RL/rds6)
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Slew Rate
A large differential input voltage → Q1 to be turned on hard, Q2 to
be turned off → ID4 will be directed through Q6 into CL.
SR =ID4
CL
Since designing IB2 > ID3, both Q1 and the current source IB2 will
go into the triode region: ID3 = ID1 = ID17.
The source and drain voltage of Q1 approaches VSS to decrease IB2.
When coming out of slewing, the source and drain voltage of Q1 must
slew back to a voltage close to VDD.
This additional slewing time greatly increases the transient times and
the distortion for switched-capacitor applications.
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Clamp transistors Q12, Q13 are turned off during normal operation.
Their main purpose is to clamp the drain voltages of Q1 or Q2 so
they don’t change as much during slewing.
A second effect dynamically increases the bias currents of Q3 and Q4
during slewing.
Q12 conducts with the current coming from Q11.
The current increase in Q11 causes the currents in Q3 and Q4 to also
increase until the sum of the currents Q3 and Q12 is equal to IB2.
The increase in bias current of Q4 results in an increase of the
maximum current available for charging CL.
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Current-Mirror Opamp
Another popular opamp for driving on-chip capacitive loads
All nodes are low impedance except for the output node.
A reasonable overall gain can be achieved by using good current
mirrors with high output impedance.
Approximate transfer function for current gain K
AV =Vo
Vi= Kgm1ZL(s) =
Kgm1Ro
1 + sRoCL
Unity-gain frequency
ωta ≃Kgm1
CL=
K√
2ID1µnCox(W/L)1CL
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A current-mirror opamp with wide-swing cascode current mirrors:
ID12 = KID11 = KID1 = KIB/2
IB
Q1
Q3
Q5
Q2
Q4
Q6
VB2
Q7
Q9
Q11
Q13
Q8
Q10
Q12
Q14
VB2
VB1
Vi+ Vi−
Vo
CL
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Total current is known for a given power-supply voltages and PD.
It = (3 + K)ID1 = PD/(VDD − VSS)
For larger values of K, the opamp transconductance Gm ≡ Kgm1 is
larger, ωta is also larger if not limited by high-frequency poles, and
the dc gain A0 is larger for fixed It.
ωta =Kgm1
CL≡ Gm
CL=
K√3 + K
√
2ItµnCox(W/L)1CL
Ro ≃gm10r
2ds10
2=
√
2KID1µpCoxK(W/L)12
V 2A
(KID1)2
=
√
2µpCox(W/L)12
V 2A
K(ID1)3/2
A0 = Kgm1Ro =(3 + K)
√µnµpCox(W/L)1V
2A
It
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A practical upper limit on K might be around five.
The important nodes to determine the nondominant poles are the
drain of Q1 primarily, and the drains of Q2 and Q9 secondly.
For given It, increasing K (ID1 ↓, W8 ↑) increases the time constant
of these nodes. → The second pole moves to lower frequencies.
For high speed operation, K might be taken as small as one. K = 2
might be a reasonable compromize for general purpose.
Slew rate of the current-mirror opamp
SR =KIB
CL
For K = 4, 4/5 of the total bias current will be available for charging
or discharging CL during slewing ← 4IB/(IB + 0 + 0 + 4IB).
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This result gives a current-mirror opamp superior slew rates even
when compared to a folded-cascode opamp with clamp transistors.
No large voltage transients due to low impedance nodes.
For the larger bandwidth and slew rate, the current-mirror opamp is
usually preferred over a folded-cascode opamp.
However, CMO will suffer from larger thermal noise (smaller gm)
because input transistors are biased at a lower proportion of It.
Example 6.3: analysis for transistor sizes given in Table 6.2
(1) K = 2, ID1 = It/(3 + K) = (PD/5)/5 = 80 µA
(2) gm1 =√
2ID1µnCox(W/L)1 = 1.7 mA/V
(3) fta = Kgm1/2πCL = 54 MHz
(4) SR = KIB/CL = K2ID1/CL = 32 V/µs
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Linear Settling Time
Time constant for linear settling time: affected by both the feedback
factor β and the effective load capacitance CL, 0.1% ts = 7τ
τ =1
ω3dB
=1
βωta, ωta =
gm1
CC,
gm1
CL,
Kgm1
CL
Feedback factor by return ratio analysis: CC = compensation
capacitance, Cp = input capacitance of opamp (parasitic + switch)
β =1/s(C1 + Cp)
1/s(C1 + Cp) + 1/sC2
=C2
C1 + C2 + Cp
Effective load capacitance: Ci = input capacitance of the next stage
CL = Ci + CC +C2(C1 + Cp)
C1 + C2 + Cp
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Fully Differential Opamps
Balanced circuits: symmetric and differential inputs and outputs
Rejection of common-mode noise from the substrate and switches
But can not reject a differential noise by voltage-dependent nonlinearities
that cause more noise to feed into one signal path than the other.
One drawback is that a common-mode feedback circuit must be added.
The design of a good CMFB circuit is not trivial: the speed performance
comparable to the differential path, the limitation of continuous-time
CMFB circuits on maximum allowable signal, the glitch injection and
increase of load capacitance for switched-capacitor CMFB circuits.
Slew-rate reduction due to fixed-bias currents in output current mirror
Regardless of limitations, differential designs are becoming more popular.
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Fully Differential Folded-Cascode Opamp
Cascode current sources: Q7 and Q8, Q9 and Q10
The CMFB circuit will detect the average of two output signals.
The negative slew rate is limited by the bias currents of Q9 or Q10.
Clamp transistors Q11, Q12 to minimize transient voltage changes.
Drain nodes of the input devices will be responsible for the second
pole → each signal path consists of only this and output nodes.
The complementary topology with nMOS as cascode transistor is
often a reasonable choice for high-speed designs. But the dc gain
would become smaller due to the input transistors of pMOS.
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A fully differential folded-cascode opamp
Q9
Q7
Q10
Q8
Q6
Q13VB4
Q1 Q2
CMFBcircuit
+
−
VB1
VB2
VB3
Q3 Q4
Q5
Vi+ Vi− Vo
Q12Q11
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Fully Differential Current-Mirror Opamp
Topology selection: whether the dc gain or bandwidth is more
important, whether CL or second pole is limiting the bandwidth.
nMOS input transistors: larger dc gain, lower thermal noise.
pMOS input transistors: larger bandwidth, lower 1/f noise.
For a general-purpose fully differential opamp: large pMOS input
transistors, a current gain of K = 2, and wide-swing enhanced
output-impedance cascode mirrors and current sources.
The negative slew rate is limited by the bias currents of Q13 or Q14.
It is possible to modify the designs to improve slew rate at the
expense of small-signal performances using additional circuitry.
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A fully differential current-mirror opamp
IB
Q1
Q3
Q5
Q2
Q4
Q6
VB2
Q7
Q9
Q11
Q13
Q8
Q10
Q12
Q14
CMFBcircuit
+
−Vo
VB2
VB1
Vi+ Vi−
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Alternative Fully Differential Opamps
A fully differential current-mirror opamp with bidirectional output drive:
four current mirrors having two outputs for sourcing and sinking.
For a large differential input, the current going into Vo+ will be KIB , and
the current being sinked from Vo− will also be KIB due to other mirror.
A class AB fully differential current-mirror opamp: low power, two
differential pairs connected in parallel, a differential pair Q3, Q4, a level
shifter (Q1: source follower, Q2: diode), small IB (class AB).
For a large differential input voltage, the pair Q3, Q4 turns off, while the
current through the pair Q7, Q8 increases dynamically due to a lowered
gate voltage of Q7 → a very large slew-rate performance, but a major
problem for low supply voltage due to VCM ≥ 2VGS + Veff = 2Vt + 3Veff
Level shifters → noise increase, lowering second poles by parasitics
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A fully differential current-mirror opamp with bidirectional output
drive: the CMFB circuit is not shown.
1 : 1
K : 1
Q1Vi+
IB
Q2 Vi−
1 : 1
1 : K
1 : KK : 1
Vo−Vo+
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A class AB fully differential opamp: the CMFB circuit is not shown.
K : 1
Q8
Q1
Vi+
Q2
IB
Q3
Q4
1 : KQ5
Vi−
Q6
Q7
IB
1 : KK : 1
Vo−Vo+
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A fully differential opamp composed of two single ouput opamps
+
−vi
−+Avi vo
Single output
+
−vi −+ Avi
+
−vo
Differential output
+
−vi
−+Avi
−++
−
vo
Balanced differential output
−
+
+
−
−
++
−
vi vo
Implementation
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A fully differential opamp having rail-to-rail ICMR: ∆Gm < 15%
Q5
M1
I1
Q1 Q2 Q3 Q4
Q6
M2
I2
Q9 Q10
Q7 Q8
I4 I4
I3 I3
Vbn
Vbp
Vi+
Vi−
VB1
VB2
Vo− Vo+
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Common-Mode Feedback Circuits
The CMFB circuitry is often the most difficult part of the opamp to
design → two approaches (continuous time, switched capacitor)
Continuous-time approach: limitation on signal swing, dependence of
CM voltage VCM on signal due to finite CMRR, circuit nonlinearity,
and device mismatch → unstability of common-mode loop
For input differential signal Vd, ID1 = ID3 and ID2 = ID4 assuming
VCM ≡ (Vo+ + Vo−)/2 = 0, CMRR = ∞ (ID depends only on Vd)
ID5 = ID2 + ID3 = (IB/2 + ∆I) + (IB/2−∆I) = IB
Thus ID5 will not change even when large differential signal voltages
are present. If VC is used to control the bias voltages of the output
stage, the bias currents in the output stage will be independent of
whether the input differential signal is present or not.
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A continuous-time CMFB circuit: VCM = 0, VC = control voltage
IB
Q1Vo+ Q2
IB
Q3 Q4 Vo−
VC
Q5
Q6
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If a positive CM voltage is present, this voltage will cause both ID2
and ID3 to increase, which causes VC to increase. This voltage will
increase the current of nMOS current sources at the output stage,
which will cause the CM voltage to decrease and return to zero.
A modified CMFB circuit having twice the common-mode gain and
0.01% linearity. If a positive common-mode voltage is present, the
drain current of Q5 will be IB + 4∆I instead of IB + 2∆I.
A alternative continuous-time CMFB circuit: less signal swing due to
dc level shift, more difficult to compensate owing to additional nodes.
The phase margin and step response of the common-mode loop
should be verified by simulation for unstability by CM signals.
Designing continuous-time CMFB circuits that are both linear and
operate with low supply voltage is an area of continuing research.
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A modified CMFB circuit having twice the common-mode gain
IB
Q1Vo+ Q2
IB
Q3 Q4 Vo−
VC
Q5
Q6
Q7
IB
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A continuous-time CMFB circuit with accurate output balancing:
VCM = VBAL, linear detection of VCM by two identical resistors
Q3Vref Q4
Q5VC Q6
Q1Vo+
20 kΩ 20 kΩ
Q2 Vo−
1.5 pF 1.5 pFIBIB
VA
VA = VCM − VGS1
Vref = VBAL − VGS1
VBAL = 0, Vo+ = −Vo−
VGS1 = VGS2
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A Switched-Capacitor CMFB Circuit
Use for larger output signal swing and linear detection of VCM
Capacitors CC generate the average VCM of the output voltages.
This circuit acts like a simple RC low-pass filter having a dc input
signal VB: in steady state vC = VCM + VB, CS = (0.1− 0.25)CC
φ1 φ2vo+
CS
−
v1
+CC
−
v2
+
φ2 φ1vo−
CC
−
v3
+CS
−
v4
+
M1
VB
vC
VR VR
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Analysis of Switched-Capacitor CMFB Circuit
Analysis by conservation of charge: q(φ1) = q(φ2)
Phase φ1: v′1 = v′4 = VB − VR, v′C = v′o+ + v′2 = v′o− + v′3
Phase φ2: short (v1 = v2, v3 = v4), steady state (v′2 = v2, v′3 = v3)
CSv′1 + CCv′2 + CCv′3 + CSv′4 = CSv1 + CCv2 + CCv3 + CSv4
2CS(VB − VR) + CC(v2 + v3) = (CC + CS)(v2 + v3)
v2 + v3 = 2(VB − VR), vC = vo+ + v2, vC = vo− + v3
∴ vC =vo+ + vo−
2+ VB − VR → VCM + VB − VR
∴ v′C =v′o+ + v′o−
2+ VB − VR → VCM + VB − VR
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Current-Feedback Opamps
Popular recently in high gain and high speed applications using
complementary bipolar technology → CMOS technology
Feedback gain can be changed without significantly affecting loop gain
→ a single compensation capacitor can be used irrespective of gain.
The input signal vi is applied to a high-impedance input, while a
feedback current if connects to a low-impedance node vn.
The voltage vn is equal to the input signal vi due to the class-AB
unity-gain buffer of Q1, Q2, and two diodes for biasing.
Because Ro is very large, a small feedback current if results in a large
output voltage vo → if ≃ 0 for a finite output voltage.
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A current-feedback opamp: vi ≃ vn, if ≃ 0
IR
Q1
1 : 1
IR
Q2
1 : 1
CC Ro
1 vo
R1
R2
vivn
IR − if/2
IR + if/2
if
if
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Voltage gain: if ≃ 0, vi ≃ vn = voR1/(R1 + R2)
vo
vi=
R1 + R2
R1
= 1 +R2
R1
Loop gain: breaking the loop and injecting a test signal vt at the top
of R2 (if = vt/R2 for vi = 0) → loop gain is independent of R1
Aβ ≡ − vo
vt
∣
∣
∣
∣
vi=0
= − ifvt
vo
if= − 1
R2
−1
sCC + 1/Ro=
Ro/R2
1 + sRoCC
Unity-gain frequency of the loop gain Aβ: ωt ≃ 1/R2CC
Transfer function: if = (vo − vi)/R2 − vi/R1, vo = −if (Ro ‖ CC)
if =−vi(R1 + R2)
R1R2 + R1Ro/(1 + sRoCC), vo =
−ifRo
1 + sRoCC
Af (s) =vo
vi=
ifvi
vo
if=
(R1 + R2)Ro
(R2 + Ro)R1
1
1 + sCC(R2 ‖ Ro)
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Bandwidth: Ro ≃ gmr2o/4≫ R2
Af (s) ≃ R1 + R2
R1
1
1 + sR2CC, ∴ ω3dB =
1
R2CC= ωt
The various closed-loop gains can be realized by changing R1 without
affecting the unity-gain frequency or the closed-loop stability.
This independence of gain on stability does not occur for voltage-
feedback amplifiers: Af (s) ≃ 1/β(1 + s/βωta), ωt = βgm/CC
Limitations: R1 ≫ 1/(gm1 + gm2), use of a purely resistive feedback
network, but difficult to compensate if reactive components are used
in the feedback network, noiser for Darlington-pair input stage.
Regardless of these limitations, CFOs exhibit excellent high-frequency
characteristics and are quite popular in many video and
telecommunications applications.
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Homework & Project
Problems: 6.1, 6.2, 6.7, 6.10, 6.24.
Design a fully-differential CMOS operational amplifier for the
following specifications.
Performances Specifications Performances Specifications
Power supply ±2.5 V Input CMR ±1 V
CL 0.5 pF Output swing ±1 V
DC gain 60 dB Settling time 15 ns
The design objective is minimizing the power dissipation. Explain
why you chose your architecture over alternatives. Draw a circuit
schematic with all device sizes. Include the design procedure and the
calculation of design parameters. Provide simulation results for
verification.
Integrated Systems Lab, Kyungpook National University