Advanced Layout & Routing Techniques

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Advanced Layout & Routing TechniquesPresented By: Janine FlaggSr. Field Applications EngineereMail: [email protected]

2 © 2014 EMA Design Automation. EMA confidential.

Agenda

• Constraint Manager

• Constraint Resolution

• Electrical Constraints− Differential Pairs

− Total Etch Length

− Wiring

− Vias

− Impedance

− Min/Max Propagation Delay

− Relative Propagation Delay

• Flex Routing

• Reuse− Technology Files

− Front-to-Back Design Reuse

− Placement Replication

− CircuitSpace

• Demos− Differential Pair Routing

− Total Etch Length – Delay Tune

− Multi-Line Routing (Flex)

− Placement Replication

− Front-to-back Design Reuse

− CircuitSpace


• Constraint Manager includes five types of constraints:– Electrical Constraints: Performance characteristics – Physical Constraints: Line width, via selection, and layer restrictions– Spacing Constraints: Clearances between lines, pads, vias, and

copper areas (shapes)– Same Net Spacing Constraints: Clearances between lines, pads,

vias, and copper areas (shapes) on the same net– Design Constraints: Package to package checks, soldermask &

pastemask checks and negative plane island checks

• Physical and Spacing include two categories of constraints:– Default Rules: Used to specify rules to be applied to nets that have

no special routing requirements– Special Rules: Nets that require unique constraints

Constraint Manager


Setup > Constraints > Constraint Manager … or …

Constraint ManagerInterface


Analyze > Analysis Modes > Electrical Modes

OrCAD PCB Designer Professional Allegro PCB Designer

Constraint ManagerAnalysis Modes


• Top displays element information

– Description– X/Y location– Net name

• Bottom displays constraint rules

– Constraint set name– Constraint set rules– Constraint values

Constraint ResolutionPhysical

Display > ConstraintSingle select


• Top displays element information

– Description– X/Y location– Net name

• Bottom displays constraint rules

– Constraint set name– Constraint set rules– Constraint values

Constraint ResolutionSpacing

Display > ConstraintDrag Select


• Total Etch Length Constraint• Differential Pair Constraints

– Uncoupled Length

Electrical ConstraintsOrCAD PCB Designer Professional


• Wiring Constraints‒ Net Scheduling‒ Parallelism‒ Layer Sets Rules

• Via Constraints− Max Via Count − Matched Vias

• Impedance• Min/Max Propagation Delays• Differential Pair - Static Phase Tolerance• Relative Propagation Delay

Additional Electrical Constraints Allegro PCB Designer


• Net Naming Convention• Auto Setup of Differential Pairs in OrCAD Capture• Auto Generation of Differential Pairs in PCB Editor• Defining Differential Pairs in Constraint Manager• Anatomy of a Differential Pair• Physical Differential Pair Constraints• Electrical Differential Pair Constraints• Differential Pair Routing Options• Working with Differential Pairs

Differential Pairs


Naming Rules for Signals within Differential Pairs

Examples:•

SignalName_P SignalNameP

SignalName_N SignalNameN

SignalName_H SignalNamaH

SignalName_L SignalNameL

SignalName_+ SignalName+

SignalName_- SignalName-

Differential PairsSignal Naming Convention for Auto Setup


Tools > Create Differential Pair > Auto Setup

Differential Pairs Auto Setup in OrCAD Capture


Logic > Assign Differential Pair > Auto Generate…

Differential PairsAuto Generate in PCB Editor


Create > Differential Pair…

Differential PairsDefining in Constraint Manager


• The trace width that should be used to route the differential pair nets the majority of the time

• The width you prefer your differential pairs to be routed

Anatomy of a Differential PairPrimary Line Width

Min Line Width


• The Spacing, edge to edge, that should be used to route the differential pair nets the majority of the time

• The rule you prefer your differential pairs to follow• This only applies to the two differential pair nets. Other net

spacing to the differential pair nets is controlled by the Spacing Rule set Line to Line clearance

Anatomy of a Differential PairPrimary Gap

Primary Gap


• Rules to be applied when the traces must “squeeze” down to be routed between pins/vias (for example, in BGA areas)

• Neck Gap is the new spacing, edge to edge, that should be routed to route the differential pair

• Neck Width is the new trace width that should be used to route the differential pairs

Anatomy of a Differential PairNeck Width and Neck Gap

Neck Width

Neck Gap


• Coupled Tolerance (+)/(-)‒ Provides a coupling range based on the Primary Separation Gap‒ Summing Primary Separation Gap and Coupled Tolerance (+)

provides the maximum coupled gap‒ Subtracting Primary Separation Gap and Coupled Tolerance (-)

provides the minimum coupled gap‒ Values above or below these become an uncoupling event

Anatomy of a Differential PairSeparation Gap Tolerance

Primary Separation plus (+) Tolerance

Primary Separation plus (+) Tolerance

Primary Separation minus (-) Tolerance

Primary Separation minus (-) Tolerance

Primary Separation GapPrimary Separation Gap


• For the differential pair itself• If set, this value must be less than your Primary Gap minus the

Coupled Tolerance Minus value• Use this value to override the Spacing Constraint set line-to-

line value

Anatomy of a Differential PairMinimum Line Space

Min Line Spacing


• Maximum length of uncoupled trace summed throughout the entire differential pair route

• See green etch below:

Anatomy of a Differential PairMax Uncoupled Length

Gathered

Ungathered


• Choices are Include & Ignore• Controls whether or not to include the etch length from pin to

gather point when calculating Max uncoupled length

Anatomy of a Differential PairGather Control

Include OR Ignore this total length

This length is ALWAYS included

Gather points


• Allowable difference in length between the differential pair nets• When the Phase Tolerance Value is -1 (unspecified), phase

checking is disabled

Note: Available only in Allegro PCB Designer and above.

Anatomy of a Differential PairStatic Phase Tolerance

Length of net A

Length of net B


• Differential Pair Constraints set in the Physical Domain

Differential Pairs Physical Constraints


• Differential Pair Constraints set in the Electrical Domain

Differential Pairs Electrical Constraints


Differential Pairs Routing Options

Horizontal

Vertical

Diagonal Up

Diagonal Down

Route > Connect


• Once seeded, it is possible to route tandem differential pairs as well as edge coupled.

Differential Pairs Routing Options


• Pseudo-segments graphically show uncoupling errors in the board– Once the length of uncoupled etch exceeds the set value, every

segment that is uncoupled is highlighted in this way

• Red and Green Meter guides the routing of Differential Pairs and signals with Length Constraints– Static Phase Tolerance– Total Etch Length

Note: Meter available only in Allegro PCB Designer and above.

Working with Differential Pairs


• May be assigned to a Net, Xnet, Bus or Differential Pair• Both Min and Max are etch length values with optional units • If no units are specified, drawing units are assumed • Either value is optional – May specify only Min, or only Max

Electrical ConstraintsTotal Etch Length


• Use the Delay Tune function to add length• May also be used to match the length of a group of nets

Electrical Constraints Total Etch Length - Delay Tune


Electrical Constraints Wiring - Topology & Stub Length



Electrical Constraints Wiring - Layer Sets & Exposed Length



Electrical Constraints Wiring - Parallel



Electrical Constraints Vias - Via Count & Match Vias



Electrical Constraints Impedance



Electrical Constraints Min/Max Propagation Delays

Note: Available only in Allegro PCB Designer and above


Electrical Constraints Relative Propagation Delay

Note: Available only in Allegro PCB Designer and above


• Flex Board

Flex Routing


• Multi-Line Routing is used for Flex Routing

Flex Routing


• Technology files (tech files) contain: ‒ Parameters‒ Design-level constraint data ‒ Constraint Modes‒ Cross-section‒ User-defined properties

• Stored on disk• Preserve company standards while creating new databases• Results reported in techfile.log

ReuseTechnology Files


File > Export > Techfile…

ReuseTechnology File - Export


File > Import > Techfile…

ReuseTechnology File - Import


• Circuits may be placed, routed and saved for design reuse • Requires the use of external Hierarchy in OrCAD Capture

ReuseFront-to-Back Design Reuse

Hierarchical block placed at top level schematic is referencing an external design that has already been placed and routed in PCB Editor and saved as a Reuse Module


• Reuse Modules may be placed as if they were one component

ReuseFront-to-Back Design Reuse


• Available in Placement Application Mode only• Allows creation of seed circuits • May be replicated

‒ Within the current design ‒ From one design to another

• May include:‒ Component Placement‒ Related Routing‒ Local Shapes‒ Reference Designator Placement

ReusePlacement Replication



Step 1 and 2

Create original circuit and select components

Step 5

Enter a name for the Module Definition File and Save

Step 4

Hover over a pin and RMB – Snap pick to - Pin

Step 3

Hover over a component and RMB – Place replicate create, then RMB - DONE



Step 1

Window - select targeted components

Step 4

Place replicated circuits

Step 2

Selected components a pin and RMB – Place replicate apply – module name


• CircuitSpace plugs into Cadence Allegro and OrCAD PCB Editors as a command menu

• Is not accessible as a separate executable

• Menu is available to the left of PCB Editor’s Help menu

ReuseCircuitSpace


• CircuitSpace adds the following to the PCB Editor:‒ CircuitSpace pull-down menu‒ CircuitSpace properties‒ CircuitSpace documentation

• Driven from within the native layout application • Engine actions are non-blocking• Uses “verb/noun” command structure• Implements Right-Mouse-Button pop-up menu

‒ With options for the current command

ReuseCircuitSpace


• Edit Board Parameters form specifies type of schematic data to be used‒ Allegro HDL‒ Allegro CIS‒ Mentor DxDesigner ‒ PDF‒ None = Rooms

ReuseCircuitSpace – Schematic Data


• CircuitSpace “Clusters” components based on schematic the information provided:

• Clusters may be ‒ Moved & Rotated‒ Mirrored‒ Automatically Placed‒ Replicated‒ Aligned‒ Merged‒ Saved as a “Template”

• Templates may be:‒ Applied to multiple channels within a design‒ Applied to multiple designs

ReuseCircuitSpace - Clusters


• Single-Sided Auto

Placement

• Double-Sided Auto

Placement

ReuseCircuitSpace – Auto Placement of Clusters


• Propagating Placement across clusters

ReuseCircuitSpace – Propagating Placement


• Templates may be previewed before applying

ReuseCircuitSpace – Previewing Templates


• Etch may be mapped to the desired layers on the target board

ReuseCircuitSpace – Applying Templates


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Advanced Layout & Routing Techniques

Engineering

Transcript of Advanced Layout & Routing Techniques