Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation

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Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation Darcy Bullock, P.E. Professor Purdue University

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Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation. Darcy Bullock, P.E. Professor Purdue University. Requested Topics. What is Hardware-in-the-Loop (HITL) Why would you use it Historical Perspective Future Challenges. What is HITL. - PowerPoint PPT Presentation

Transcript of Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation

Page 1: Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation

Advanced Evaluation Techniques and Hardware-In-The-Loop Simulation

Darcy Bullock, P.E.ProfessorPurdue University

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Requested TopicsWhat is Hardware-in-the-Loop (HITL)Why would you use itHistorical PerspectiveFuture Challenges

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What is HITLTesting and Evaluation of control equipment/algorithms with a simulated plant

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What is HITLGoal

Typical

HITL

SimulatedController

SimulatedPlant

Control Equipment

SimulatedPlant

Control Equipment

Real World Traffic

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Why would you want to use HITL

So you can make mistakes (and learn from them) in the lab, not the field. Then when you deploy, there should be fewer surprises.So you have a controlled environment in which to experiment and quantify benefits.So you have a facility for students to try things and learn from their mistakes.Probe the “corners” of a control system without worrying about the consequences of failure

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Functional Evaluation

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Hmm.What if we could control a suitcase tester with a computer.

Monitor 24 volt phase outputsGround loop detector inputs as directed.

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Performance Based Evaluation

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Still Do Suite Case Testing

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SystemSetupw/Master

ClosedLoop

Netw ork

Closed Loop Managem ent Software

Clo

sed

Loop

Com

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icat

ion

Inte

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Cab

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RS

-232

from

Clo

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p S

oftw

are

to S

yste

m M

aste

r

RS

-232

from

CO

RS

IM to

Sim

ulat

ion

Inte

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Net

wor

k

RS

-422

CID

Net

wor

k

CORSIM Network S im ula tion

Controller InterfaceDevice (CID)

Netw ork

RealW orldModel

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Alternative to HITLSuitcase tester Ok feature individual tester Virtually impossible to evaluate

interaction of various features on a single controller much less a “system” of controllers

“Full Up Testing”…. Plug everything together and hope they work

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Historical PerspectiveHITL has been used extensively by other industries for several decades.1985 at University of Vermont when Prof Bob Dawson explained his simulation system for testing/developing the control system on a PDP-11 controlling the gravel washing/production system.

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Gate Control Logic1986 worked on a speed sieve design for gate control at the IBM Essex Junction Plant1987 senior design project worked with EE student and.. he built the control hardware.. I built a simulator in Modula II.

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1993Moved to LSU in Baton Rouge, LATom Urbanik invites me to participate with his team on the IVHS Research Center ProposalDeveloped HITL concept for Smart Diamond Testing

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Dec 1993 Smart Diamond Testing Concept

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1994 Smart Diamond Test Plan

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1994 Smart Diamond Equipment Concept

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Further DevelopmentsTexSIM developed for Smart Diamond Monty willl discuss nextCORSIM extended for hardware in the loop

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Controller Interface Device(CID) ~1997

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1997-Present CID Uses Testing ACS Lite algorithmsAlgorithm developmentController feature testingLaboratory Based Instruction

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1997 – Present HardwareTTI PlatformIdaha PlatformUniv. of Minnesota PlatformNaztec/Eagle PlatformPortland PLC PlatformEmergence of a Software Platform (Univ of Arizona, Siemens, Univ of Utah)

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Purdue HITL Laboratory

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Project SetupChoose a real system to design and simulateObtain plans, volumes, etc. from DOTSystems that are being constructed, need to be upgraded, or were recently upgraded are ideal

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Project Selections

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S B L T N B W B L T E B N B L T S B E B L T W B1 2 3 4 5 6 7 8

M a i n S t r e e t T h r o u g h 1 0 sS i d e S t r e e t T h r o u g h 7 sA l l L e f t T u r n s 5 s

Y e l l o w C l e a r a n c e

R e d C l e a r a n c e

P e d e s t r i a n C l e a r a n c e

P e d e s t r i a n W a l k 7 s e c o n d s

M a x 1 G r e e n M a x 1 = 1 . 3 * S y n c h r o S p l i t

V e h i c l e E x t e n s i o nF o r 3 s e c o n d V e h E x t : V e h E x t = 3 s e c - G a p A l l o w

T p = p e r c e p t i o n t i m e ( u s u a l l y 1 s e c . )V v = a v e r a g e v e h i c l e s p e e d o n a p p r o a c h ( m p h )

a = d e c e l e r a t i o n r a t e ( 1 0 f e e t / s 2 )W = a d j a c e n t a p p r o a c h w i d t h ( f e e t )L = a v e r a g e v e h i c l e l e n g t h ( u s u a l l y 2 0 f e e t )c = l a n e w i d t h ( f e e t )V w = a v e r a g e w a l k i n g s p e e d ( u s u a l l y 4 f e e t / s 2 )

M i n i m u m G r e e n

N o d e 1 6

P a r a m e t e r C a l c u l a t i o n

2aV * 1 .47 T Yellow v

p

vV * 1.47L W

Red

wV.5c - c) * Lanes of (#

Clr Ped

vAllow V * 1 .4 7

(f eet)Len g th D etecto r L G ap

Project: Design ProcessCalculate timing parameters

5 5 5 510 107 7

3.0 3.0 3.0 3.04.0 4.03.5 3.51.5 1.5 1.5 1.52.0 2.02.0 2.0

20 20 20 2050 5040 403.0 3.0 3.0 3.02.5 2.52.5 2.5

15 1515 157 77 7

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Project: Design ProcessObtain cycles, offsets, and splits from Synchro or Highway Capacity Software

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Project: Real-Time Simulation

Controllers are configured with the calculated timings and coordination timings

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Project: Real-Time Simulation

Simulation model is built using proposed geometries and vehicle volumes and imported into CORSIM

ITRAF CORSIM

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I/O MappingVehicle sensors are mapped to the corresponding phases by the students

DetectorCards

Controller

ControllerMapping

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“Final Lab Exam”1 controller plugged into 1 CID for each intersectionAll CIDs plugged in to 1 PC running CORSIMAll controllers plugged in to 1 PC running remote software

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Closed Loop Monitoring Screens

PC set up to monitor the system remotely Change

controller parameters

View signal and detector status

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For future HITL ChallengesCommercially viable CIDs that supports both TS2 Type 1 and Type 2 I/O AND aWell supported integration with an accepted simulation model (CORSIM)Blurring of software/hardware in the loopFormally addressing the timing latency issue between simulation clock and controller.