Possibilities and challenges in electronics building and production

technology

On some cooperation with CPD Center AB

Professor Jerker DelsingEISLAB

High density electronics

DriversPrice - price scales with size and volume

Low power - shorter leads, less R,LC -> lower operation voltage (P=U2/R)

Performance - shorter leads -> higher clock frequencies

Comparison Si - PWB

Silicon: 8 - 32 nmPCB: 50 - 250 um

3 - 4 order of magnitude in difference

What about PWB?!

First PCB:s early 1900The print and etch process patented 1913 - PWB

Feature sizes Trace width - 40 um -- 100 um Via size - 50 um - .... Multi layer boards - 40 layers

Limitation due to the etch process

Component package

Chip bonding

Bondwires usually consist of one of the following materials:

Aluminum

Copper

Gold

Wire diameters start at 15 µm and can be up to several hundred micrometres for high-powered applications.

Thermosonic bonding

Ultrasonic bonding

The wet PCB dream

Sequential Build Up of PWB parts

The CBM process

• Polymer molecules attach and create Polymer “structures” on the surface

• Works UP FROM surface instead of DOWN INTO surface

• First molecule fastens on surface with a strong covalent bonding

• On surface and inside holes (1:12)

Copper Build-up

Bare substrate

Polymer Structure build-up

0.5 – 4 μmElectroless Copper

Galvanic platingto desired level

CBM process

Standard processes

Cu on Teflon© (with primer, TetraEtch)

Etching vs Sequential build Up (SBU)

SBU

Potentially smaller feature sizes

Enabling embedded component - embedded chip technology

What’s the difference?

Standard Copper

CBM™ copper

FR4

First experiments

10 um line width

Strategies for circuit board interconnect based on the

CBM™ process

Solder free interconnect

Solder free interconnect

Solder free interconnect

Application of CBM™ grafting chemistry

Solder free interconnect

Solder free interconnect

CBM™ grafting polymer

Solder free interconnect

Solder free interconnect

Benefits

Takes away:Capsule ~35% of component costBonding ~35% of component cost

Smaller feature sizes at circuit board enablesCircuit board area reductionSmall chip pads

100x100 um today -> 5x5 um -> chip area saving of 400 times100 pads -> 1mm2 -> 0.0025 mm2

Chip size directly proportional to costShorter interconnect leads

Less RLCLower power requirementsHigher performance

Can we do this today?

LTU has the following lab facilities currently used in research cooperation with CPD Center AB

Clean room facility featuring Down to ISO 14644-1 class 5 CBM™ process Lithography Via hole drilling

CBM

Lab scale CBM process capable of small series production

Lithography

Laser lithography Advanced laser writer Line width < 700 nm

Via making - laser ablation

Cold ablation via diameter<5um