Advanced Analog Integrated Circuits Matchingboser/courses/240B/lectures/M13 Matching.pdfTHspread for...

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B. E. Boser 1 Advanced Analog Integrated Circuits Matching Bernhard E. Boser University of California, Berkeley [email protected] Copyright © 2016 by Bernhard Boser EE240B – Matching

Transcript of Advanced Analog Integrated Circuits Matchingboser/courses/240B/lectures/M13 Matching.pdfTHspread for...

Page 1: Advanced Analog Integrated Circuits Matchingboser/courses/240B/lectures/M13 Matching.pdfTHspread for 90nm NMOS and PMOS: Ørandom variations comparable to slow/fast spread Ref: M.

B. E. Boser 1

Advanced Analog Integrated Circuits

Matching

Bernhard E. BoserUniversity of California, Berkeley

[email protected]

Copyright © 2016 by Bernhard Boser

EE240B – Matching

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B. E. Boser 2

Issue

• In SPICE, two transistors with equal dimensions and terminal voltages (and temperature) carry the same current

• In Si, the current are (slightly) mismatched– Why?– How much mismatch?– Fix?– Verification?

EE240B – Matching

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Origins of Mismatch

EE240B – Matching

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Wafer to Wafer Variations

Parameter Slow Nominal FastVTH 0.5V 0.4V 0.3V

µCox (NMOS) 200 µA/V2 250 µA/V2 300 µA/V2

µCox (PMOS) 100 µA/V2 130 µA/V2 160 µA/V2

CMIM 1.2 fF/µm2 1 fF/µm2 0.8 fF/µm2

Rpoly 80 W/◻ 70 W/◻ 60 W/◻

Rnwell 1.3 kW/◻ 1 kW/◻ 0.7 kW/◻

EE240B – Matching

Wafer 1§ all NMOS fast§ all PMOS nominal§ all C nominal§ all R fast

Wafer 2§ all NMOS slow§ all PMOS slow§ all C fast§ all R nominal

• Verify performance for all combination (with simulator)• Also low/high supply and temperature

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B. E. Boser 5

Advanced Analog Integrated Circuits

Random Variations

Bernhard E. BoserUniversity of California, Berkeley

[email protected]

Copyright © 2016 by Bernhard Boser

EE240B – Matching

Page 6: Advanced Analog Integrated Circuits Matchingboser/courses/240B/lectures/M13 Matching.pdfTHspread for 90nm NMOS and PMOS: Ørandom variations comparable to slow/fast spread Ref: M.

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Random Variations

Ref: M. Pelgrom, “Matching properties of MOS transistors,” IEEE JSSC, 10/1989, pp. 1433-9.

EE240B – Matching

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B. E. Boser 7

Parameters for typical 180nm CMOS

Parameter ValueAvt (MOS) 5 mV-µmAb (MOS) 1 %-µmADIs/Is (BJT) 2 %-µmADb/b (BJT) 4 %-µmADC/C (MIM capacitor) 1 %-µmADR/R (Poly resistor) 3 %-µm

EE240B – Matching

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B. E. Boser 8

Avt for 180nm CMOS

• Good match between heuristic model and experimental data, except– minimum channel length (actual length is smaller than drawn)– very long channel device

EE240B – Matching

Ref: M. Pelgrom et al, “A designer’s view on mismatch,” Chapter 13 in Nyquist A/D Converters, Sensors, and Robustness, Springer 2012, pp. 245-67.

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Avt versus Gate Oxide Thickness

• Avt increases ~1mV×µmfor every nm of gate insulator thickness– for well-engineered process

• But: circuits get smaller …

• Avt scaling design: e.g.– Outlier for 0.6µm PMOS is

result of compensating implant, leading to high variability

– beyond 0.6µm node dedicated well implant is used

EE240B – Matching

Ref: M. Pelgrom et al, “A designer’s view on mismatch,” Chapter 13 in Nyquist A/D Converters, Sensors, and Robustness, Springer 2012, pp. 245-67.

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B. E. Boser 10

Advanced Analog Integrated Circuits

Yield

Bernhard E. BoserUniversity of California, Berkeley

[email protected]

Copyright © 2016 by Bernhard Boser

EE240B – Matching

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Random Mismatch - Example

What is the mismatch between two MIM capacitors with 𝑊 = 𝐿 = 20µm?

𝜎∆0 0⁄ =𝐴∆0 0⁄

20µm×20µm� =1%×µm20µm = 0.05%

à 68.2% of all devices fabricated match to ±0.05%.

EE240B – Matching

https://en.wikipedia.org/wiki/Standard_deviation

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Yield

• Fraction of devices that meet specification

• Large customers tolerate less than 1ppm failures– 6s design– Testing, binning– Capacitor example: 1sà ±0.05%, 6sà ±0.3%,

EE240B – Matching

Interval Yield Fraction Bad1s 68.3% 1/3

2s 95.4% 1/22

3s 99.7% 1/370

4s 99.99% 1/16,000

5s 99.999% 1/1,700,000

6s 99.999 999 8% 1/507,000,000

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B. E. Boser 13

Advanced Analog Integrated Circuits

Mismatch in Mirrors and Differential Pairs

Bernhard E. BoserUniversity of California, Berkeley

[email protected]

Copyright © 2016 by Bernhard Boser

EE240B – Matching

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B. E. Boser 14

Mismatch in Current Mirror

EE240B – Matching

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B. E. Boser 15

Differential Pair

EE240B – Matching

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Verification

1. PVT– Process, voltage, temperature– Perform verification for all combinations on design and extracted

netlist

2. Random variations– Monte-Carlo analysis

EE240B – Matching

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Technology Trend

• slow/fast spread decreases– better process control

• random variations increase– smaller devices

EE240B – Matching

VTH spread for 90nm NMOS and PMOS:Ø random variations comparable to

slow/fast spread

Ref: M. Pelgrom et al, “A designer’s view on mismatch,” Chapter 13 in Nyquist A/D Converters, Sensors, and Robustness, Springer 2012, pp. 245-67.