ADSD Fall2011 12 Multipliers

8/3/2019 ADSD Fall2011 12 Multipliers

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Dr. Rehan Hafiz Lecture # 12

ADSD Fall 2011


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Course Website for ADSD Fall 2011

http://lms.nust.edu.pk/

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Lectures: Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm

Contact: By appointment/EmailOffice: VISpro Lab above SEECS Library

Acknowledgement: Material from the following sources has been consulted/used in theseslides:1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan3. [STV] Advanced FPGA Design, Steve Kilts4. Ercegovacs Book: Digital Arithmetic 20045. Dr. Shoab A Khans CASE Lectures on Advanced Digital System Design

Material/Slides from these slides CAN be used with following citing reference:

Dr. Rehan Hafiz: Advanced Digital System Design 2010

Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.
http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/http://creativecommons.org/licenses/by-nc-sa/3.0/


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Lecture Overview

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Last Lecture Multi-Operand Addition

This Lecture

Binary Multiplication

Signed/Unsigned Numbers

Architecture

Q format MultiplicationCorrection Vector


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Binary Multiplication

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Addition of multiple terms

Sequential using a single adder

Combinational Logic using compression trees

[CIL]


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Sequential Multiplier-1

5


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How Right Shifting the Accumulator

Register helps ?6

If Multiplying bit is 1 ADD Multiplicand & Shift

If Multiplying bit is 0 Just Shift

http://www.parl.clemson.edu/~walt/ece327/mult.v
http://www.parl.clemson.edu/~walt/ece327/mult.vhttp://www.parl.clemson.edu/~walt/ece327/mult.v


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7


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Can we furthersave a register

Add 0 or Add 1


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Make use of

Product Register


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Sequential Multiplier-3 Example

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Fractional Numbers

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Multiplication of two numbers Qm.n & Qo.p

result into a product with Q(m+o).(n+p) bits.

Taking 2s complement of fractional number

Same as for usual integer binary numbers

Take Bitwise Complement

Add 1

-Dont Get Confused by Book Example


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Signed Number Multiplication

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(Incorrect; result should be 1)


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Negative Multiplicand, Positive Multiplier

Sign Extend the Multiplicand equal to the product bits before the multiplication process


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Signed Multiplicand, Positive Multiplier[Fractional Number]

Align the bits & then forget about the fractional dot !

Sign Extend the Multiplicand equal to the product bits before the multiplication process


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Positive Multiplicand, Negative Multiplier

Sign Extend the Multiplier equal to Multiplicand bit

Last Partial Product needs to be subtracted OR Add 2s complement


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Positive Multiplicand, Signed Multiplier[Fractional Number]


Sign Extend the Multiplier equal to Multiplicand bit



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Signed Multiplicand, Signed Multiplier

Sign Extend the Multiplier



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Signed Negative Multiplicand, Signed Negative Multiplier(Fractional Number)


Sign Extend the Multiplier



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Signed Multiplier

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We can adjust the previous algorithm to work

with signed integers

make sure each shift is an arithmetic shift

right shift extend the sign bit (keep the MS bit the sameinstead of shifting in a 0).


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Example (-1 * -1)

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P 0 0 0 0 1 0 1 1

Add 1 1 1 1

= 1 1 1 1 1 0 1 1

S 1 1 1 1 1 1 0 1

Add 1 1 1 1

= 1 1 1 0 1 1 0 1

S 1 1 1 1 0 1 1 0

Add 1 1 1 1

= 1 1 1 0 0 1 1 0S 1 1 1 1 0 0 1 1

Add(2s

)

0 0 0 1

= 0 0 0 0 0 0 1 1

S 0 0 0 0 0 0 1

At each addition Perform 4 bit

addition, Discard Carry out & Shift

Right while replicating MSB


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Example (-1 * -5) (1111*1011)

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P 0 0 0 0 1 0 1 1

Add 1 1 1 1

= 1 1 1 1 1 0 1 1

S 1 1 1 1 1 1 0 1

Add 1 1 1 1

= 1 1 1 0 1 1 0 1

S 1 1 1 1 0 1 1 0

Add 0 0 0 0

= 1 1 1 1 0 1 1 0S 1 1 1 1 1 0 1 1

Add(2s

)

0 0 0 1

= 0 0 0 0 1 0 1 1

S 0 0 0 0 0 1 0 1


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Example (1 * -5) (0001*1011)

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P 0 0 0 0 1 0 1 1

Add 0 0 0 1

= 1

S 1

Add 1

= 1 1

S 1 1

Add

= 1 1S 0 1 1

Add(2s

)

1 1 1 1

= 1 1 1 1 0 1 1

S 1 1 1 1 1 0 1 1

C l iti & i l


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Complexities & special cases

Sign Extension, 2c Complement23

Two things have to be done dynamically

Sign Extension

2s Complement

What can be done ?

Wh t d b t


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What can we do about

Sign Extension24

Rather than following a selective sign extension

for signed numbers we follow a common policy

for all (+ve & -ve) numbers

Policy Complement the sign bit

Always extend with ONEs

Add ONE to the sign bit

+

B is positive (S=0)

B=0 0 0 0 0 0 . 1 1 0 1 0 1 1B=1 1 1 1 1 0 . 1 1 0 1 0 1 1

0 0 0 0 0 0 . 1 1 0 1 0 1 1

1

B is negative (S=1)

B=1 1 1 1 1 1 . 1 1 0 1 0 1 1B=1 1 1 1 1 1 . 1 1 0 1 0 1 1

1 1 1 1 1 1 . 1 1 0 1 0 1 1

1+


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Example-Sign Extension

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(.) (.) (.) (.)

(.) (.) (.) (.)

1 1 1 1 (.) (.) (.) (.)

1 1 1 (.) (.) (.) (.)1 1 (.) (.) (.) (.)

1 (.) (.) (.) (.)

1 1 1 1

Policy

Complement the sign bit

Add ONE to the sign bitAlways extend with ONEs

C d thi b t 2


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Can we do something about 2s

complement & its sign extension26

Do 2s Complement (.)(.)(.)(.)

1+

Than do Sign Extension

1(.)(.)(.)(.)

1 1+

So the MSB is complemented two times; first due to2s complement & secondly due to sign extension.

Since complement of complement is the original bit.

MSB needs not to be complemented

E l


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Example-

Sign Extension & 2s Complement27

(Carries) (.) (.) (.) (.)

(3) (2) (1) (1) (.) (.) (.) (.)

1 1 1 1 (.) (.) (.) (.)

1 1 1 (.) (.) (.) (.)

1 1 (.) (.) (.) (.)

1 (.) (.) (.) (.)

1 1 1 1

1

1 0 0 1 0 0 0 0

Exercise:

-2 * -2 or -2 *2

Correction Vector

for multiplication

of TWO 4-bit signednumbers

Due to 2s

complement


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2s Complement Example

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1 1 1 0

(1) (1) (2) (2) 1 1 1 0

1 0 0 0

0 1 1 0

0 1 1 0

1 0 0 1

1 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0


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2s Complement Example

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1 1 1 0

(1) (1) (2) (2) 1 1 1 0

1 0 0 0

0 1 1 0

0 1 1 0

1 0 0 1

1 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0 Output

Add


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Correction Vector Examples

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Discard the carries after the MSBNote the different Correction Vectors for +ve & -ve numbers


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Benefit of Correction Vector

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Reduced Logic

Generalized Algorithms

Designing a Fast Multiplier


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Designing a Fast Multiplier

(Single Cycle Multiplication)32

Formation of PartialProducts

Sign extension ORGeneration of CorrectionVector

Addition of PP

Wallace/DadaCompression Tree

Final Addition using anyfast Ripple Carry Adder

Formation of PartialProducts

Addition of PartialProducts

(Reduction)

Final Addition Stage

MultiplicationMultiplier

Product

ADSD Fall2011 12 Multipliers

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