FTE 2008 AE22 Lab: PCI-ExpressGroup/Presentation Title

Agilent Restricted2008-May-05Month ##, 200XPage 1

ADS Workshop on PCI Express®PCI EXPRESS is a registered trademark of the PCI –SIG

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Agenda

• Brief introduction to key specifications

• Create and analyze PCI Express channel

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PCI Express Physical Channel

lane

Transmit

Receive

Each lane is AC coupled

Device BDevice A

PC

I E

xp

ress C

on

ne

cto

r

Point to Point serial link communication

PCI Gen1 – 2.5 GT/s/lane (Giga transfer per second)

PCI Gen2 – 5.0 GT/s/lane

• AC coupling capacitor

• Min value – 75 nF

• Max value – 200 nF

• Preferred value 100 nF

• Size 0402 provide best performance 0603 is fair

• Should be symmetrically placed with in a diff pair

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Transmit Signal SpecificationsDifferential Peak to Peak Output Voltage

0.4 V (min)

0.6 V (max)

0.266 V (min)

0.4 V (max)

VTX-DIFFP-P = 2*|VTX-D+-VTX-D-|= 0.8 V (min.)= 1.2 V (max.)

VTX-DE-RATIO = -3.5 dB (Typ.)

= -3.0 dB (Min.)= -4.0 dB (Max.) Transition Bit

VTX-Diff-P-P (min) =0.8V

De emphasized Bit

VTX-Diff-P-P (max) =0.566V

(3 dB)

VTX-Diff-P-P (min) =0.505V

(4 dB)

0 V

0.7

UI

Eye mask

2.5G de-emphasis = -3.5 +/- 0.5

5G de-emphasis = -3.5 +/- 0.5 OR -6.0 +/- 0.5

Low swing voltage levels = no de-emphasis

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Transmit Signal SpecificationsRise and Fall Time

Trise > 0.125 UI

Measured between 20-80% at transmitter package pins

Tfall > 0.125 UI

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PCI Tx/Rx Return Loss

• Differential return loss measured for package + Rx die

• Differential return loss Requirements : -10 dB or better

• Die termination should be 50 Ohms

– Return Loss

• RLTX-DIFF 10 dB measured over 50 MHz to 1.25 GHz

• RLTX-CM 6 dB measured over 50 MHz to 1.25 GHz

– Differential Impedance

– 100 Ohms (Typ.)

– 80 Ohms (Min.)

– 20 Ohms (Max.)

– Unit Interval (UI)

– 400 ps (Typ.)

– 399.88 ps (Min.)

– 400.12 ps (Max.)

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Simulation Compliance Eye

+ =

Rather than including jitter in the simulation, include its effects to qualify eye diagram performance

VTX-Diff-P-P (min) =0.175V

0 V

TX Jitter Simulation Compliance Eye

0.75 UI

TTX-MAX-JITTER = 1-TTX-EYE

= 0.25 UI

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Receiver Eye Mask

VTX-Diff-P-P (min) =0.175V 0 V

0.4 UI

0.0875 V (min.)

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Stackup and Trace Topologies• Four layer stackup (0.062 in PCB) with 0.5 Oz copper for microstrip

• 1 Oz copper for 6+ layer strip line structure

• Trace length matching between pairs not required due to embedded clock and lane de-skew in the receiver – Makes routing easier and longer trace traces feasible (max lane to lane skew is 1.6 ns)

• Max. recommended trace length on system board < 12 in

• Max. recommended trace length on add in card < 3.5 in

• Maximum skew tolerable within differential pair is 5 mil for add in card, 10 mil for system board

VCC

VSS

47 mil

4.4 mil

4.4 mil

TX TX TX

VCC

VSS

47 mil

4.4 mil

4.4 mil

RX TX RX

Non Interleaved Interleaved

5 mil 7 mil 20 mil

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System Jitter Budget for 2.5 GT/s

399.13Root Sum Square (RSS) Total Tj

458Linear Total Tj

35160120.62.8RX

2090900Media

2310841.94.7Ref Clock

2210060.62.8TX

%Tj at BER 10-12

(ps)Max Dj (ps)Min Rj (ps)Jitter Contribution

@ 2.5 GT/s

RSS equation for BER 10-12 Tj = Σ Djn +14.069 *√ Σ Rjn2

The Rj of the components are independent and convolve as the root sum square.

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System Jitter Budget for 5 GT/s

200Root Sum Square (RSS) Total Tj

231.6Linear Total Tj

3480602.8RX

2558580Media

1943.604.7Ref Clock

2250302.8TX

%Tj at BER 10-12

(ps)Max Dj (ps)Min Rj (ps)Jitter Contribution

@ 5 GT/s

RSS equation for BER 10-12 Tj = Σ Djn +14.069 *√ Σ Rjn2

The Rj of the components are independent and convolve as the root sum square.

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PCI Express Link Components

• Transmitters/Receivers on an ASIC on a system board

• Package

• Via breakout

• Differential transmit/receive traces on system board

• Via for signal transition to inter-layer

• PCI Express connector and add-in card interface/riser card interface

• Differential transmit/receive traces on add-in card

• AC-coupling capacitors

• Transmitter/Receivers on an ASIC on the add-in card

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Exercise

1. Create a PCI Express source in ADS

2. Create a PCI Express simulation compliance transmitter mask

3. Create a second source with jitter added

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PCI-Express Design Guide

Allow easy setup and simulation

of a PCI Express Channel

Provides

– Easy simulation setup

– Representative channel components

– Allow you to quickly predict the effect of your design on the system performance

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Component of PCI Express Design Guide

• Transmitter

– Source with de-emphasis

– Source with jitter

– SERDES model

• Channel

– Packages model

– Via breakout

– Daughter card traces

– PCI-Express connector

– System board trace

• Eye mask

– Transmit mask

– Receive mask

• Physical components

– Package

– Add card trace

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Create a PCI Express Compliance Source in ADS

• Transmitter data rate 2.5 Gbps (400 ps)

• Output voltage level for the transition bit 400 mV

• De-emphasis 3.5 dB

• Rise/fall time (20-80%) 0.125 UI

• Rise/fall time mismatch 0.10 UI (max)

• Random jitter 2.8 ps

• Periodic jitter 60.6 psec (1.5 MHz)

• Total jitterp-p 0.25 UI

• Common mode voltage level 0 V

• Output differential impedance 100 Ohms

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Exercise -1

• Simulate PCI Express Transmitter

Run

simulation

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Eye Diagram

Voltage Level Of Differential Signal

Data Rate

Differential Voltage

De-emphasis Level

Transition Bit MaskDe-emphasized Bit Mask

Exercise: Change the eye diagram measurement for single ended voltage

Exercise: Plot time domin voltage waveform

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Single Ended Eye Diagram

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Eye Diagram (contd.)

Change De-emphasis Level

De-emphasized Bit Mask

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PCI Express Source with Jitter

Jitter parameters

Run

simulation

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Basic PCI Express Channel Simulation

16” Channel

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Receive Mask Testing

Mask includes transmitter

contribution due to jitter

Mask will automatically position itself in

the center of eye

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Channel with Via Models

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Tuning Interconnect Parameters

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Modeling Crosstalk Channel

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Exercise- Package Simulation

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PCI Express Connector Simulation

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Exercise-5Create a PCI Express Channel

Transmitter � Package � Via breakout �Daughter card trace � Connector �System board

trace � Via breakout � Package

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Exercise-5Create a PCI Express Channel

Transmitter � Package � Via breakout �Daughter card trace � Connector �System board

trace � Via breakout � Package

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Create a PCI Express Channel (contd.)

Transmitter � Package � Via breakout �Daughter card trace � Connector �System board

trace � Via breakout � Package

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Create a PCI Express Channel (contd.)

4” trace 12” trace

Transmitter Package Via breakout Connector Via breakout Package

Add in Card Trace System Board Trace

Node name: outp

Node name: outp

R= 50 Ohm

C= 2 pF

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Simulated Data

20 40 60 800 100

-100

0

100

-200

200

time, nsec

outp

, m

V

20 40 60 800 100

-0.2

0.0

0.2

-0.4

0.4

time, nsec

outp

-outn

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Eye Diagram Plot

100 200 300 400 500 600 700 8000 900

-0.2

0.0

0.2

-0.4

0.4

time, psec

eye_plo

t

How do we create eye mask?

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Install Mask Templates

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PCI Express Channel Simulation

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Performance Comparison

Simple Channel

Actual Channel

Add results from basic channel simulation and compare results

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TDR Simulation

Package + Via breakout

Add-in Card Trace

Connector

System Board Trace

Package + Via breakout

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Layout Co-Simulation

Package Model

Package Model

Add in Card

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Momentum Simulation

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Package Co-simulation

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3D Preview of Package

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Transistor Level Driver Model

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Verification- Transmitter Eye Mask

Where all we failed in the eye mask?

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PCI Express Channel with Stratix-II GX Driver

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Eye Diagram Performance

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Equalizer Simulation

Push inside and see details

how equalizer is defined

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Equalized Cable Simulation

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Eye Diagram Performance

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Using Frequency Domain Model to Create De-emphasis

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Coder/De-Coder

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Input and Output Data Stream