Adding sensors to intersection
17
Hardware Computer Organization for the Software Professional Arnold S. Berger 1 Adding sensors to intersection W E S N WT ET •N/S is a major road •E/W lights stay red until an E/W car is detected
description
Adding sensors to intersection. N/S is a major road E/W lights stay red until an E/W car is detected. S. W. WT. ET. E. N. Flow chart for busy intersection. Algorithm: 1- NS is green and EW is red for 20 seconds. 2- If no E/W car is waiting, go to #1 - PowerPoint PPT Presentation
Transcript of Adding sensors to intersection
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 1
Adding sensors to intersection
W
E
S
N
WT
ET
•N/S is a major road•E/W lights stay red until an E/W car is detected
•N/S is a major road•E/W lights stay red until an E/W car is detected
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 2
Flow chart for busy intersection
NS REDEW GREEN20 Seconds
NS REDEW YELLOW5 Seconds
NS GREENEW RED
20 Seconds
NS YELLOWEW RED
5 Seconds
WT = 1
ET = 1
NO
YESYES
NO
• Algorithm: 1- NS is green and EW is red for 20 seconds. 2- If no E/W car is waiting, go to #1 3- Else Allow EW traffic to go for 20 seconds 4- Go to #1
KEY POINTS •State of E/W traffic sensors can modify the behavior of the system• Diamonds represent decision points in the Algorithm
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 3
Timing diagram for traffic signal
0 5 10 15 20 25 30 35 40 45 50
Time, seconds
EW GREEN 10
EW YELLOW 10
EW RED 10
10
10
10
NS GREEN
NS YELLOW
NS RED
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 4
Timing diagram as a vector set
NS GREENNS YELLOWNS REDEW GREENEW YELLOWEW RED
Time
0
5
10
15
20
25
30
35
40
45
50
0 0 1 1 0 0 0C
0 0 1 1 0 0 0C
0 0 1 1 0 0 0C
0 0 1 1 0 0 0C
0 1 0 1 0 0 14
1 0 0 0 0 1 21
1 0 0 0 0 1 21
1 0 0 0 0 1 21
1 0 0 0 0 1 21
1 0 0 0 1 0 22
0 0 1 1 0 0 0C
Hexadecimal State
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 5
Designing the traffic controller
NS REDEW GREEN20 Seconds
NS REDEW YELLOW5 Seconds
NS GREENEW RED
20 Seconds
NS YELLOWEW RED
5 Seconds
Flow chart Flow chart NS RED
EW GREEN
NS REDEW GREEN
NS REDEW GREEN
NS REDEW GREEN
NS REDEW YELLOW
NS GREENEW RED
NS GREENEW RED
NS GREENEW RED
NS GREENEW RED
NS GREENEW RED
Redraw so that everystate is 5 seconds long
Redraw so that everystate is 5 seconds long
State variables
0000 0H
0001 1H
0010 2H
0011 3H
0100 4H
0101 5H
0110 6H
0111 7H
1000 8H
1001 9H
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 6
D flip-flop synchronizes states
The output values in the register is the address of the memory cell for the data that determines the next state of the outputs after the clock arrives
The output values in the register is the address of the memory cell for the data that determines the next state of the outputs after the clock arrives
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CLK
D0
D1
D2
D3
A0
A1
A2
A3
16 x 6 Memory Array
D REGISTER
D4
D5
NSG
NSY
NSR
EWG
EWY
EWR
Clock frequency = 0.2 Hz
State Variableprovides theinput
State Variableprovides theinput
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 7
Traffic controller state table
State Outputs
ROM Address
ROM ContentsQ3 Q2 Q1 Q0 D5 D4 D3 D2 D1 D0
0 0 0 0 0H 0 0 1 1 0 0 0CH0 0 0 1 1H 0 0 1 1 0 0 0CH0 0 1 0 2H 0 0 1 1 0 0 0CH0 0 1 1 3H 0 0 1 1 0 0 0CH0 1 0 0 4H 0 1 0 1 0 0 14H0 1 0 1 5H 1 0 0 0 0 1 21H0 1 1 0 6H 1 0 0 0 0 1 21H0 1 1 1 7H 1 0 0 0 0 1 21H1 0 0 0 8H 1 0 0 0 0 1 21H1 0 0 1 9H 1 0 0 0 1 0 22H1 0 1 0 AH X X X X X X Don’t Care1 0 1 1 BH X X X X X X Don’t Care1 1 0 0 CH X X X X X X Don’t Care1 1 0 1 DH X X X X X X Don’t Care1 1 1 0 EH X X X X X X Don’t Care1 1 1 1 FH X X X X X X Don’t Care
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 8
State sequencing
Use the ROM contents to sequence from one state to the next Use the ROM contents to sequence from one state to the next
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CLK
A0
A1
A2
A3
16 x 10 Memory
Array
D REGISTER
NSG
NSY
NSR
EWG
EWY
EWR
Clock frequency = 0.2 Hz
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 9
New state table with sequencing
Next State Outputs
ROM Contents
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Current StateROM Address
0H 0 0 0 1 0 0 1 1 0 0 04CH1H 0 0 1 0 0 0 1 1 0 0 08CH2H 0 0 1 1 0 0 1 1 0 0 0CCH3H 0 1 0 0 0 0 1 1 0 0 10CH 4H 0 1 0 1 0 1 0 1 0 0 154H5H 0 1 1 0 1 0 0 0 0 1 1A1H6H 0 1 1 1 1 0 0 0 0 1 1E1H 7H 1 0 0 0 1 0 0 0 0 1 221H8H 1 0 0 1 1 0 0 0 0 1 261H9H 0 0 0 0 1 0 0 0 1 0 022HAH X X X X X X X X X X Don’t CareBH X X X X X X X X X X Don’t Care CH X X X X X X X X X X Don’t Care DH X X X X X X X X X X Don’t CareEH X X X X X X X X X X Don’t Care FH X X X X X X X X X X Don’t Care
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 10
Adding inputs
NS REDEW GREEN20 Seconds
NS REDEW YELLOW5 Seconds
NS GREENEW RED
20 Seconds
NS YELLOWEW RED
5 Seconds
WT = 1
ET = 1
NO
YESYES
NO
NSGEWR
NSGEWR
NSGEWR
NSGEWR
WT
ET
NO
NSYEWR
NSREWG
NSREWG
NSREWG
NSREWG
YES
YES
0H
1H
2H
3H
4H
5H
NSREWY6H
7H
9H
8H
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 11
Traffic light controller with inputs
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CLK
A0
A1
A2
A3
64 x 10 Memory
Array
D REGISTER
NSG
NSY
NSR
EWG
EWY
EWR
Clock frequency = 0.2 Hz
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
ET
WT
D4
D5
Q4
Q5
A4
A5
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 12
Abbreviated ROM Contents
A5 A4 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 X X 0 0 0 1 1 0 0 0 0 10 0 0 1 X X 0 0 1 0 1 0 0 0 0 10 0 1 0 X X 0 0 1 1 1 0 0 0 0 10 0 1 1 0 0 0 0 0 0 1 0 0 0 0 10 0 1 1 0 1 0 1 0 0 1 0 0 0 0 10 0 1 1 1 0 0 1 0 0 1 0 0 0 0 10 0 1 1 1 1 0 1 0 0 1 0 0 0 0 10 1 0 0 X X 0 1 0 1 1 0 0 0 1 00 1 0 1 X X 0 1 1 0 0 0 1 1 0 00 1 1 0 X X 0 1 1 1 0 0 1 1 0 00 1 1 1 X X 1 0 0 0 0 0 1 1 0 01 0 0 0 X X 1 0 0 1 0 1 0 1 0 01 0 0 1 X X 0 0 0 0 0 1 0 1 0 01 0 1 0 X X 0 0 0 0 0 0 0 0 0 01 0 1 1 X X 0 0 0 0 0 0 0 0 0 01 1 0 0 X X 0 0 0 0 0 0 0 0 0 01 1 0 1 X X 0 0 0 0 0 0 0 0 0 01 1 1 0 X X 0 0 0 0 0 0 0 0 0 01 1 1 1 X X 0 0 0 0 0 0 0 0 0 0
State WT ET Next State Outputs
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 13
Simplified Schematic Diagram
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 14
Sequential Digital Machine
ExternalInputs
Current State
OUTPUTS
Microsequenceror
ROMStateFlip-Flops
Clock
NEXT STATE
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 15
Adding two numbers together
• Assume that we want to add two 4-bit numbers together • We assume that we have a 4-bit full adder made up of 4, 1-bit full
adder circuits connected as shown below:
Cout
3
DB3 DB2 DB1 DB0
2 1 0
Cin = 0
A3 B3 A2 B2 A1 B1 A0 B0
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 16
State machine sequence
ConnectA0..A3
to Adder
ConnectB0..B3
to Adder
AddA0..A3
toB0..B3
Save stateof Cout
StoreSUM
• In this example it would require 5 clock cycles to perform this addition
Register holding A0..A3
Register holding B0..B3
4-bit full adder
Register holding A0..A3
Cout
Hardware Computer Organization for the Software ProfessionalArnold S. Berger 17
Glimpse at processor design
• The ASM is the basis for almost all of today’s computing engines• The Instruction Set Architecture is determined by the microcode
stored in a ROM section of the processor• The processor sequences through a series of states determined by:
- The instruction - Contents of internal registers- Results of arithmetic or logical operations- Type of memory addressing mode being used- Asynchronous internal or external events (interrupts)
FetchInstruction
DecodeInstruction
ComputeOperand 1Address
FetchOperand 1
ComputeOperand 2Address
FetchOperand 2
PerformOperation
Writeback
Results
AdvanceProgram Counter
