adc_DNL_INL

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ADC Guide, Part 5: ADC Non-Linearity (DNL/INL) and monotonic transfer function By Sachin Gupta and Akshay Phatak, Cypress Semiconductor Previously, we explored gain error in ADCs. This part of article series talks about different type of non- linearity in an ADC’s transfer function. In contrast to the other types of errors we’ve discussed, ADCs cannot be calibrated to remove non-linearity. As a consequence, these specifications should be considered carefully when selecting an ADC for a particular application. Differential non-linearity (DNL): For an ideal ADC, the output is divided into 2 N uniform steps, each with width . Any deviation from the ideal step width is called differential non- linearity (DNL) and is measured in number of counts (LSBs). For an ideal ADC, the DNL is 0LSB. In a practical ADC, DNL error comes from its architecture. For example, in a SAR ADC, DNL error may be caused near the mid range due to mismatching of its DAC. Let us consider an example of a 3-bit ADC with transfer characteristics as shown in Figure 1. In this ADC, each input step should be exactly 1/8 of the full-scale input range (1 LSB of this ADC). Given that this ADC has an input range of 8V, the first output-code transition is caused by an input change of 0.5V (Full-scale input range/16 = ½ LSB), which is as expected. However, the second transition, from 001 to 010, takes place after an input change of 1.25V (1.25 LSB), and so is too large by 0.25 LSB. Similarly, there is a variation in step size at each of the following steps. The DNL of this particular ADC can be specified as 0.75 LSB, which is the maximum deviation from the ideal step size of this ADC throughout its transfer. Figure 1: Representation of DNL in an ADC transfer curve.

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Transcript of adc_DNL_INL

Page 1: adc_DNL_INL

ADC Guide, Part 5: ADC Non-Linearity (DNL/INL) and monotonic transfer function

By Sachin Gupta and Akshay Phatak, Cypress Semiconductor

Previously, we explored gain error in ADCs. This part of article series talks about different type of non-

linearity in an ADC’s transfer function.

In contrast to the other types of errors we’ve discussed, ADCs cannot be calibrated to remove non-linearity.

As a consequence, these specifications should be considered carefully when selecting an ADC for a particular

application.

Differential non-linearity (DNL): For an ideal ADC, the output is divided into 2N

uniform steps, each with

width . Any deviation from the ideal step width is called differential non- linearity (DNL) and is measured in

number of counts (LSBs).

For an ideal ADC, the DNL is 0LSB. In a practical ADC, DNL error comes from its architecture. For example, in a

SAR ADC, DNL error may be caused near the mid range due to mismatching of its DAC.

Let us consider an example of a 3-bit ADC with transfer characteristics as shown in Figure 1. In this ADC, each

input step should be exactly 1/8 of the full-scale input range (1 LSB of this ADC). Given that this ADC has an

input range of 8V, the first output-code transition is caused by an input change of 0.5V (Full-scale input

range/16 = ½ LSB), which is as expected.

However, the second transition, from 001 to 010, takes place after an input change of 1.25V (1.25 LSB), and

so is too large by 0.25 LSB. Similarly, there is a variation in step size at each of the following steps. The DNL of

this particular ADC can be specified as 0.75 LSB, which is the maximum deviation from the ideal step size of

this ADC throughout its transfer.

Figure 1: Representation of DNL in an ADC transfer curve.

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Differential nonlinearity greater than 1 LSB in an ADC can result in missing codes in the transfer

characteristics. Figure 2 shows one such example. Due to a very wide step at 010, the ADC never produces

the output 011, instead jumping directly from 010 to 100. Therefore, the output of this ADC has the code 011

missing due to its large DNL.

Figure 2: Missing code in ADC transfer curve due to large DNL.

Missing codes can be realized from histogram plots of an ADC’s output. Figure 3 shows one such

experimental histogram. The figure depicts the number of times a particular output code appeared on the

output of a delta sigma ADC when the input was grounded. If we look at this plot, code ‘-2’ never appears on

the output of the ADC.

This code is missing due to DNL error. In this particular case, the DNL error appeared near ground itself,

which is why it could be captured with a histogram drawn to see noise performance by grounding the inputs.

In general, DNL error can appear anywhere in the ADC’s range and to test for it, the input must be tested

throughout the range and the resulting output observed.

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Figure 3: Histogram of an ADC output with input connected to ground.

Missing codes do not pose a serious problem as a DC characteristic itself, meaning the applications where

one output of ADC is taken out and processed. However, when we consider an application such as the

digitization of an analog waveform, missing codes can introduce significant amount of distortion. In Figure 4,

every time the input signal crosses Vx, there is a distortion introduced due to the code which is missing at this

point.

Figure 4: Distortion in ADC output due to missing code in transfer characteristics.

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Though DNL may not be an important DC specification, it should be looked carefully in high-precision

applications. Also, DNL error can occur at different output codes across the complete output range of the

ADC, even for devices produced by the same manufacturer. There is no way to overcome DNL for an ADC.

Again, the DNL specification needs to be examined carefully before making the final selection of an ADC for a

given application.

Monotonicity: In an ADC, if the output code always increases with an increase in the ADC input and

always decreases with a decrease in the ADC input, this is called monotonic. If an ADC has DNL error

≥ -1 LSB and ≤ 1 LSB, it will be monotonic.

Integral non-linearity (INL): INL is a measure of how closely the ADC output matches its ideal response. INL

can be defined as the deviation in LSB of the actual transfer function of the ADC from the ideal transfer curve.

INL can be estimated using DNL at each step by calculating the cumulative sum of DNL errors up to that point.

In reality, INL is measured by plotting the ADC transfer characteristics as explained below.

INL is popularly measured in two ways:

•Best fit (best straight line) method •End point method Best Fit INL: The best fit method of INL measurement considers offset and gain error. One can see in Figure 5

that the Ideal transfer curve considered for calculating best-fit INL does not go through the origin. The ideal

transfer curve here is drawn such that it depicts the nearest first-order approximation to the actual transfer

curve of the ADC.

The intercept and slope of this ideal curve can lend us the values of the offset and gain error of the ADC.

Quite intuitively, the best fit method yields better results for INL. For this reason, many times this is the

number present on ADC datasheets.

Figure 5: Best Fit INL.

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The only real use of the best fit INL number is to predict distortion in AC applications. This number would be

equivalent to the maximum deviation for an AC application. However, it is always better to use the distortion

numbers than INL numbers. To calculate the error budget, end-point INL numbers provide a better

estimation. Also, this is the specification which is generally provided in datasheets. So, one has to use the

same instead of end-point INL.

End-point INL: The End-Point method provides the worst case INL. This measurement passes the straight line

through the origin and maximum output code of the ADC. (Refer Figure 6). As this method provides the worst

case INL, it is more useful to use this number as compared to the one measured using best fit for DC

applications. This INL number would be typically useful for error budget calculation. This parameter must be

considered for applications involving precision measurements and control.

Figure 6: Endpoint INL.

About the authors Sachin Gupta is a Senior Applications Engineer in the Global Applications team at Cypress Semiconductor Corp. He can be reached at [email protected]. Akshay Phatak is an Applications Engineer with Cypress Semiconductor. He holds a Bachelor's degree in

Electronics and Telecommunications form College of Engineering, Pune (India). He likes to work on mixed-

signal embedded systems. He can be reached at [email protected].