ADC and DAC testing Static Dynamic - CSIC · • Difficult to perform: involved test set-up and...
Transcript of ADC and DAC testing Static Dynamic - CSIC · • Difficult to perform: involved test set-up and...
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 20 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Static and dynamic measurements
ADC and DAC testingStatic
Signal-to-noise
Gainerror
Non-linearityINL, DNL
-FS/4 0 FS/4 FS/2Analog input
0
1
2
3
4
5
6
7
Ou
tpu
t co
de
FS/2
missing
codesnon-
monotonicity
DC
Acc
ura
cyDynamic
Clock max. rate
Signal DC or lowfrequency
Clock max. rate
Signal variablefreq. & amplitude
ratioDistortionOffset
SNDR(SINAD)Conversion
time (ADC)IP3
SFDR
Noise
THD
DynamicRange,
Dynamicnon-linearitytest
Settling time,Glitches (DAC)
0 2e+05 4e+05 6e+05 8e+05 1e+06Frequency (Hz)
-150
-125
-100
-75
-50
-25
0
Am
plit
ud
e (
dB
V)
ENOB
SN
DR
(dB
)
Amplitude (dBV)
SN
DR
(dB
)
Conversion time (s)
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 21 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters What must be measured for proper characterisation
Static characteristics (Accuracy: INL, DNL, missing codes, non-monotonicity)
• Important only for low-frequency ADC or DAC conversion: Instrumentation, control
• Dynamic limitations (S/H, buffers...) not included
• Easy to obtain because no high-frequency test set-up is required
• Meaningless for high-frequency converters
Dynamic characteristics (SNR, SNDR, SFDR, IP3, THD, ENOB)
• Essential for medium- and high- frequency ADCs or DACs
• Both static and dynamic errors are included in dynamic measurements (i.e. ENOB)
• Difficult to perform: involved test set-up and measurement processing
• Dynamic characteristics must be obtained for full-scale maximum-frequency input
ENOB (bit)
87.87.67.47.2
25 Signal Freq. (MHz)50 75
8bit, 150 MSample/s ADC
7.2bit at 75MHz input frequency~ 8bit at low frequency
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 22 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Offset, gain error and linearity: Static measure for DACs
Digitalpattern
generatorDi
DAC Vo
Voltmeter
Precision
0 1 2 3 4 5 6 7Input code (3bit)
-FS/2
0.0
+FS/2
Ana
log
outp
ut
IdealActual
1LSB (ideal)∆4
DNLj ∆j LSB–=
INL1
0 1 2 3 4 5 6 7Input code (3bit)
0.0
+FS/2
Ana
log
outp
ut
IdealActual
Offset
After offsetcorrection
Gainerror
Best-fit line
0 5 10 15Code
-0.05
-0.03
-0.01
0.01
0.03
0.05Without correction
After offset and
Best-fit straight line
gain correction
INL measurements for the same 4bit DAC
LS
B4b
it
-.33
-.20
-.07
.07
.20
.33% FS
Control
Trigger
Data
(D.U.T.)
3bit DAC
Usually:
INL INLMax=
DNL DNLMax=
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 23 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Offset, gain error and linearity: Static measure for ADCs
-FS/4 0 FS/4 FS/2Analog input
0
1
2
3
4
5
6
7
Out
put c
ode
IdealActual
Offset
1/2LSB
1LSB(ideal)
Offsetcorrected
Gainerror
-FS/2 -FS/4 0 FS/4 FS/2Analog input
0
1
2
3
4
5
6
7
Out
put c
ode
1LSB(ideal)
∆3
DNLj ∆ j LSB–=
INL5
DNL3 LSB>
Missing code
0 5 10 15Output code
-0.75
-0.50
-0.25
0.00
0.25
0.50
0.75
LS
B4b
itWithout correction
After offset and
Best-fit straight line
gain correctionThe best-fit line methodusually gives the lowestINL, but it doesn’t linearity in someapplications
represent the converter
Digital
comp.DoADCVi
(D.U.T.)
−+
Di
CIA
IB
VoltmeterDigital
IdealActual
Servo loop method• No high-resolution ramp generator needed; large robustness.
• Slow for high-resolution. Sensitive to code stability.
INL measurements for the same 4bit ADC
D i
D i 1–
D i Do≥
D i Do<
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 24 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Offset, gain error and linearity: Dynamic measurement
Signal
generatorDo
ADCVi IdealDAC
Vo
(D.U.T.)
Code density method
Ideal
Actual
-FS/2 FS/2
Missing code
7
012
3
45
6
Output code
Code density (%)25 50
Missing code
bin tooshort
bin toolong
Right size bin
7
012
3
45
6
Outputcode
2550Ideal Code density (%)
Time
Signal
• Apply an accurately known signal
• Histogram of the output codes
• Bin size can be obtained from thehistogram data♦ If signal = ramp, bin size is pro-
portional to code density.
Triangular
Precision ramp
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 25 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Offset, gain error and linearity: Dynamic measurement
Histogram
DNL
INL
5-bit ADCMissingcodes
Histogram
INL
DNL
10-bit ADC
Sig
nal
n -> n+1 code transition point:
-FS/2
+FS/2Precisionsinewave
Code density method with sinewaves• Signal amplitude slightly above FS/2
• Signal frequency
♦ fs = sampling frequency♦ P = number of signal period (odd, prime number:
1,3,5,7...)♦ M = total number of samples taken
• If sinewave generator is not precise enough,divide ADC FS in sections
fxPM-----
fS= • Allows evaluation of the accuracy of high-fre-quency converters
• Requires synchronisation for high resolution
• Otherwise, the number of samples neededmay be prohibitive: 40Msamples for 16bit!,within 0.1LSB
• Slow for high resolution
Pros/Cons
v0 A πnC0
ntotal------------ 1–
sin=
A
vn A πnCn
ntotal------------
Vn 1–
A-------------
sin 1–+sin=
nCn = number of occurrences of code n
ntotal = total number of samples
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 26 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Offset, gain error and linearity: Dynamic measurement
Code density method example (4bit ADC)
Measuredcode histogram
Extratedcode transition
After offset andgain error correction
• ADC features:♦ Offset error = -2.017%FS = -0.303LSB♦ Gain error = 4.595%FS = 0.689LSB♦ DNL = 2.873%FS = 0.431LSB♦ INL = 1.531%FS = 0.230LSB
INL
DNL
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 27 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Output spectrum and derived measurements - I
Sampled data
Am
plitu
de
Discontinuities
Windoweddata
Data windowing
• Required when sampled data do not con-tain an integer number of signal periods
♦ FFT assumes that sampled data are peri-odic with period equal to the sampled timeslot
♦ Such periodicity may require a “jump”, thuscorrupting the results
♦ Windowing alter start and end data to avoiddiscontinuities
• Windowing reduces sidelobes but alsoreduces frequency resolution
# sample
Window(#)1
0
X
=
0 50 10010-20
10-16
10-12
10-8
10-4
100
PS
D
Freq. (kHz)
5 6 7 8
10-6
10-4
10-2
100
♦ Compromise between sidelobe suppression and frequency resolution
16384-point FFT
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 28 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Output spectrum and derived measurements - II
Sinewave
generatorDo
ADCVi
Using MATLAB
• Windowing the signal...>> Np = # points;
>> W = blackman(Np); or >> W = kaiser(Np, 60);• FFT...
>> fs = sampling frequency>> [ys,f] = psd(Vo,Np,fs,W,[ ]); f -> frequency
• Spectrum (amplitude)>> sp_a = ys*norm(W)^2/sum(W)^2*4;
• Spectrum (power spectral density)>> sp_psd = ys*norm(W)^2/sum(W)^2/(fs/Np);
• Plotting...>> semilogx(f,10*log10(sp_a));
>> semilogx(f,10*log10(sp_psd));
IdealDAC
Vo
Frequency (Hz)-150
-125
-100
-75
-50
-25
0
Am
plitu
de (
dBV
)
-180-155
-130
-105-80
-55-30
-5
Pow
er s
pect
ral d
ensi
ty (
dB/H
z)
signal amplitude
harmonic amplitude
Frequency (Hz)
Digitalsinewavegenerator Di
DAC Vo
(D.U.T.)(D.U.T.)
Spe
ctru
man
alys
er
Software
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 29 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Output spectrum and derived measurements
0 2e+05 4e+05 6e+05 8e+05 1e+06Frequency (Hz)
-150
-125
-100
-75
-50
-25
0A
mpl
itude
(dB
V)
noise floor
signal
2nd har. 3rd har.
offsetSFDR THD dB 10log10
Vharj2∑
Vsig2---------------------=
Total harmonic distortion (dB)
Spurious-free dynamic range (dB)
SFDRdB
20log10
Vsig Vsp⁄( )=
Vsig
Vsp
2nd-order
Frequency (Hz)
Am
plitu
de (
dB
V) products
2-tone input
3rd-orderproducts
f1 f2
2f2 f1–2f1 f2–
f2 f1+
f2 f1–Difficultto removewhen f1 f2≈
Converter input (dBV)
Con
vert
er o
utpu
t (dB
V)
Signal
3rd-
inte
rm.
IP3
3rd-orderintercept point
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 30 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Signal-to-noise ratio and other dynamic measurements
Spectral estimation of SNR
• Integrating PSD in the signal band...>> sp_psd_bin = sp_psd*(fs/Np);
>> sum(sp_psd_bin[“only noise”]);
Frequency (Hz)
-150
-125
-100
-75
-50
-25
0
PS
D x
freq
uenc
y bi
n (d
B)
In-b
and
err
or
po
wer
(d
B)
Filter
-80dB in-banderror power
SNRVsig
2 2⁄
error power------------------------------=
Minimum Sinusoidal Error (MSE) method
• Basis:♦ Apply a sinusoidal input♦ Fit the converter output to a sinewave of the
same frequency + offset + some harmonics♦ The fitting coefficients are offset and har-
monic amplitudes♦ The fitting error is noise
• No FFT required
• Requires a reconstruction filter
• Slow for large number of harmonics
• Non-convergence for very corrupted data
Pros/Cons1.0e-03Time-1.0
-0.5
0.0
0.5
1.0
Vo(
V)
Transient
Validoutput
VfitVoff Ai 2πj
fxfs---- φj+
sin∑+=
Voff 85.4mV=
A1 960mV=A2 9.5mV=A2 3.2mV=Noise 0.1mVrms=
SNR 37dB=THD 40– dB=
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 31 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Signal-to-noise ratio and other dynamic measurements
0 2e+05 4e+05 6e+05 8e+05 1e+06Frequency (Hz)
-150
-125
-100
-75
-50
-25
0
Am
plitu
de (d
BV
)
2nd har.3rd har.
• In the presence of distortion♦ SNR does not represent accuracy♦ Add power of the harmonics to the noise power...
♦ SNDRdB
20log10Vsig
2 2⁄noise harmonics power+-----------------------------------------------------------------------
=
Signal-to-(noise + distortion) ratio (SNDR)
Dynamic range (DR)
• SNR varies with the input level♦ Ranging from SNR=0dB (signal = error) to SNRmax for FS input
♦ Dynamic range
♦ Equivalently
♦ or
DRdB
20log10VFS
VSNR=0dB------------------------
=
DR SNRmax=
DR 10logVFS
2 2⁄error power---------------------------------
=
SN
R(d
B)
Amplitude (dBV)
Overloading
SNRpeak
Ext
rap
ola
ted
SNR=0dB
VSNR=0dB VFS
Effective number of bits (ENOB)
♦ DR of an ideal B bit converter = , then♦ for given DR,
♦ Measure of the overall dynamic performance
3 2 2B 1–( )⋅ENOB
bitDR
dB1.76–( ) 6.02⁄=
Dyn
amic
ran
ge
DR
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 32 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Dynamic characterisation of high-speed ADCs-I
SFDR
SNDR=39dB
Sinewave
generatorDo
ADCVi Aux.DAC
Vo
(D.U.T.)
Clk S÷
Spe
ctru
man
alys
er
• Very high-frequency testing♦ Involves PCB design♦ Increases equipment requirements♦ Digital caption of ADC output not possible
• Preferred solution♦ Direct ADC-DAC testing: auxiliary DAC♦ DAC accuracy must be higher than ADC accu-
racy: hard to fulfil If fClk_ADC = fClk_DAC.
♦ DAC performance is relaxed by subsampling♦ Signal band reduced by S; noise PSD increased
by S => SNR does not change♦ Fundamental, harmonics, etc. translated to the
new signal baseband => THD, SFDR do notchange.
0 10 20 30 40 50Frequency (MHz)
-150
-125
-100
-75
-50
-25
0
PS
D x
freq
uenc
y bi
n (d
B)
SNDR=39dB
SFDR
Subsampledspectrum
Originalspectrum
Subsampled direct ADC-DACmethod
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 33 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Dynamic characterisation of high-speed ADCs-II
Envelope testSinewave
generatorDo
ADCVi SlowDAC
Vo
(D.U.T.)
Spectrumanalyser
fx
fClk
2--------- ∆f+=
fClk
0 5 10 15 20 25 31ADC output code
Cod
e de
nsity
(%
)
Missingcode
Large DNLcodes
DigitizingOscilosc.fClk
S---------
0 5e-04 1e-03Time (s)
-1.0
-0.8
-0.5
-0.2
0.0
0.2
0.5
0.8
1.0
DA
C o
utp
ut
(V)
10.24MS/s 160kS/s
∆f 1kHz=
S 64=
Envelope frequency = ∆f
Resolution largerthan that of theADC under test
5bit ADC
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 34 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Conversion time (ADC) and settling time (DAC)
Sinewave
generatorDo
ADCVi IdealDAC
VoDigital
sinewavegenerator Di
DAC Vo
(D.U.T.)(D.U.T.)
Spe
ctru
man
alys
er
SoftwarefClk fClk
0 0.5 1.0 1.5 2.0Output period (µs)
55
60
65
70
75
80
SN
DR
(dB
)
Conversiontime
Varying clock frequency
13b ADC
0 0.1 0.2 0.3Output period (µs)
40
45
50
55
SN
DR
(dB
)
Settlingtime
9b DAC
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 35 of 36 IMSE - Σ∆ Design Group
Characterising Data Converters Settling time measurement (DAC) - II
Time
-FS/2
-FS/2
str str str str str str
Vo
Time
-FS/2
-FS/2
Vo
str str str str str
str
Patterngenerator
Di
DAC
Vo
(D.U.T.)0..001..11
fClk
str
ON CHIP
ProgrammableDelay
Vset
Vset
Vset
Voltmeter
Precision
reconstruction
Vo
str
Integrator
Design of Embeddable Data Converters: Prototyping and Characterisation...Slide 36 of 36 IMSE - Σ∆ Design Group
References
• M.I. Montrose: Printed Circuit Board Design Techniques for EMC Compliance, IEEE Press 1996.
• R. Morrison: Grounding and Shielding Techniques in Instrumentation 3rd Ed., John Wiley & Sons, 1986
• C.S. Walker: Capacitance, Inductance and Crosstalk Analysis, Artech House, 1990.
• J.L. Lamay and H.T. Bogard: “How to Obtain Maximum Practical Performance from State-of-the-Art Delta-Sigma Analog-to-Digital Converters,” IEEE Trans. on Instrumentation and measurement, Vol. 41, pp. 861-867, December 1992.
• E. Haseloff: “Printed Circuit Board Layout for Improved Electromagnetic Compatibility”. Texas InstrumentsApplication Report, 1996.
• D. Brooks: UltraCAD Design Notes, 1993-1995.
• J. Berrie: “The Defensive Design of Printed-Circuit Boards,” IEEE Spectrum, pp- 76-81, September 1999.
• A. Mayer, R. Plitschka: “High Speed Testing: An Introduction and Reference Guide to the Testing of High-Speed Digital Integrated Circuits”. Hewlett Packard Application Notes, 1989.
• Dynamic Characterization of A/D Converters with the HP 82000M. Hewlett Packard Application Notes, 1992.
• R. Friedrich: “Testing 20bit Measurement AD Converters with Hp82000M”. Hewlett Packard ApplicationNotes.
• “Terms, Definitions, and Letter Symbols for Analog-to-Digital and Digital-to-Analog Converters”. JEDECStandard No. 99, Addendum No.1, July 1989
• B. Razavi: Principles of Data Conversion System Design, IEEE Press, 1995
• R. van de Plassche: Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic Pub-lishers, 1994.