A/D Flash MCU with EEPROM - Home - Holtek...Configuration Option..... 166 Application Circuits........

A/D Flash MCU with EEPROM

HT66F0187

Revision: V1.20 Date: ��st 2�� 201��st 2�� 201�

Rev. 1.20 2 ��st 2�� 201� Rev. 1.20 3 ��st 2�� 201�

HT66F0187A/D Flash MCU with EEPROM


Table of Contents

Features ................................................................................................................ 7CPU Feat�res ..............................................................................................................................�Peripheral Feat�res ......................................................................................................................�

General Description ............................................................................................. 8Block Diagram ...................................................................................................... 8Pin Assignment .................................................................................................... 9Pin Description .................................................................................................. 10Absolute Maximum Ratings .............................................................................. 13D.C. Characteristics ........................................................................................... 14A.C. Characteristics ........................................................................................... 17HIRC Electrical Characteristics ........................................................................ 18A/D Converter Electrical Characteristics ......................................................... 19Comparator Electrical Characteristics ............................................................ 20Power on Reset Characteristics ....................................................................... 20System Architecture .......................................................................................... 21

Clockin� and Pipelinin� ..............................................................................................................21Pro�ram Co�nter ........................................................................................................................22Stack ..........................................................................................................................................23�rithmetic and Lo�ic Unit – �LU ................................................................................................23

Flash Program Memory ..................................................................................... 24Str�ct�re .....................................................................................................................................24Special Vectors ..........................................................................................................................24Look-�p Table .............................................................................................................................24Table Pro�ram Example .............................................................................................................25In Circ�it Pro�rammin� – ICP ....................................................................................................26On-Chip Deb�� S�pport – OCDS ..............................................................................................2�

RAM Data Memory ............................................................................................. 27Str�ct�re .....................................................................................................................................2�Data Memory �ddressin� ...........................................................................................................28General P�rpose Data Memory .................................................................................................28Special P�rpose Data Memory ..................................................................................................2�

Special Function Register Description ............................................................ 30Indirect �ddressin� Re�ister – I�R0� I�R1� I�R2 ......................................................................30Memory Pointers – MP0� MP1H/MP1L� MP2H/MP2L ...............................................................30�cc�m�lator – �CC ....................................................................................................................32Pro�ram Co�nter Low Re�ister – PCL ......................................................................................32Look-�p Table Re�isters – TBLP� TBHP� TBLH .........................................................................32Stat�s Re�ister – ST�TUS ........................................................................................................33

Rev. 1.20 2 ��st 2�� 201� Rev. 1.20 3 ��st 2�� 201�



EEPROM Data memory ..................................................................................... 35EEPROM Data Memory Str�ct�re .............................................................................................35EEPROM Re�isters ...................................................................................................................35Readin� Data from the EEPROM ..............................................................................................3�Writin� Data to the EEPROM .....................................................................................................3�Write Protection ..........................................................................................................................3�EEPROM Interr�pt .....................................................................................................................3�Pro�rammin� Considerations .....................................................................................................38

Oscillator ............................................................................................................ 39Oscillator Overview ...................................................................................................................3�System Clock Configurations ....................................................................................................3�External Crystal/Ceramic Oscillator – HXT ...............................................................................40Internal RC Oscillator – HIRC ...................................................................................................41External 32.�68kHz Crystal Oscillator – LXT .............................................................................41Internal 32kHz Oscillator – LIRC ...............................................................................................42S�pplementary Oscillators ........................................................................................................42

Operating Modes and System Clocks ............................................................ 43System Clocks ..........................................................................................................................43System Operation Modes ..........................................................................................................44Control Re�isters .......................................................................................................................45Fast Wake-�p ............................................................................................................................4�Operatin� Mode Switchin� ........................................................................................................48Standby C�rrent Considerations ...............................................................................................52Wake-�p ....................................................................................................................................52Pro�rammin� Considerations ....................................................................................................53

Watchdog Timer ................................................................................................. 53Watchdo� Timer Clock So�rce ...................................................................................................53Watchdo� Timer Control Re�ister ..............................................................................................53Watchdo� Timer Operation ........................................................................................................55

Reset and Initialisation ...................................................................................... 56Reset F�nctions ........................................................................................................................56Reset Initial Conditions .............................................................................................................58

Input/Output Ports ............................................................................................ 61P�ll-hi�h Resistors .....................................................................................................................62Port � Wake-�p ..........................................................................................................................62I/O Port Control Re�isters ..........................................................................................................62I/O Port So�rce C�rrent Control .................................................................................................62Pin-remappin� F�nctions ...........................................................................................................64I/O Pin Str�ct�res .......................................................................................................................65Pro�rammin� Considerations ....................................................................................................66

Timer Modules – TM .......................................................................................... 67Introd�ction ................................................................................................................................6�TM Operation .............................................................................................................................6�

Rev. 1.20 4 ��st 2�� 201� Rev. 1.20 5 ��st 2�� 201�



TM Clock So�rce ........................................................................................................................68TM Interr�pts ..............................................................................................................................68TM External Pins .......................................................................................................................68TM Inp�t/O�tp�t Pin Control Re�isters ......................................................................................6�Pro�rammin� Considerations .....................................................................................................�2

Standard Type TM – STM .................................................................................. 73Standard TM Operation ..............................................................................................................�3Standard Type TM Re�ister Description ...................................................................................�3Standard Type TM Operatin� Modes ........................................................................................�8

Periodic Type TM – PTM .................................................................................... 88Periodic TM Operation ...............................................................................................................88Periodic Type TM Re�ister Description ......................................................................................88Periodic Type TM Operatin� Modes ...........................................................................................�3

Analog to Digital Converter – ADC ................................................................. 102�/D Overview ...........................................................................................................................102�/D Converter Re�ister Description .........................................................................................103�/D Converter Data Re�isters – S�DOL� S�DOH ...................................................................103�/D Converter Control Re�isters – S�DC0� S�DC1� S�DC2� �CERL ....................................104�/D Operation ..........................................................................................................................108�/D Reference Volta�e .............................................................................................................10��/D Converter Inp�t Si�nal ...................................................................................................... 110Conversion Rate and Timin� Dia�ram ..................................................................................... 110S�mmary of �/D Conversion Steps .......................................................................................... 111Pro�rammin� Considerations ................................................................................................... 112�/D Transfer F�nction .............................................................................................................. 112�/D Pro�rammin� Examples .................................................................................................... 113

Serial Interface Module – SIM ......................................................................... 115SPI Interface ............................................................................................................................ 115SPI Re�isters ........................................................................................................................... 116SPI Comm�nication ................................................................................................................. 11�I2C Interface .............................................................................................................................122I2C Re�isters ............................................................................................................................123I2C Time-o�t Control .................................................................................................................130

Comparator ...................................................................................................... 132Comparator Operation .............................................................................................................132Comparator Interr�pt ................................................................................................................132Pro�rammin� Considerations ...................................................................................................132

SCOM Function for LCD .................................................................................. 134LCD Operation .........................................................................................................................134LCD Bias Control .....................................................................................................................134

UART Interface ................................................................................................. 136U�RT External Pins .................................................................................................................13�U�RT Data Transfer Scheme...................................................................................................13�

Rev. 1.20 4 ��st 2�� 201� Rev. 1.20 5 ��st 2�� 201�



U�RT Stat�s and Control Re�isters.........................................................................................13�Ba�d Rate Generator ...............................................................................................................143U�RT Set�p and Control..........................................................................................................145U�RT Transmitter.....................................................................................................................146U�RT Receiver ........................................................................................................................14�Mana�in� Receiver Errors .......................................................................................................14�U�RT Interr�pt Str�ct�re..........................................................................................................150�ddress Detect Mode ...............................................................................................................151U�RT Wake-�p ........................................................................................................................151

Low Voltage Detector – LVD ........................................................................... 152LVD Re�ister ............................................................................................................................152LVD Operation ..........................................................................................................................153

Interrupts .......................................................................................................... 154Interr�pt Re�isters ....................................................................................................................154Interr�pt Operation ...................................................................................................................15�External Interr�pt ......................................................................................................................160Comparator Interr�pt ................................................................................................................161M�lti-f�nction Interr�pt .............................................................................................................161�/D Converter Interr�pt ............................................................................................................161Time Base Interr�pt ..................................................................................................................162EEPROM Interr�pt ...................................................................................................................163LVD Interr�pt ...........................................................................................................................163TM Interr�pts ...........................................................................................................................163SIM Interr�pt ............................................................................................................................164U�RT Transfer Interr�pt ...........................................................................................................164Interr�pt Wake-�p F�nction ......................................................................................................164Pro�rammin� Considerations ...................................................................................................165

Configuration Option ....................................................................................... 166Application Circuits ......................................................................................... 166Instruction Set .................................................................................................. 167

Introd�ction ..............................................................................................................................16�Instr�ction Timin� .....................................................................................................................16�Movin� and Transferrin� Data ..................................................................................................16��rithmetic Operations ...............................................................................................................16�Lo�ical and Rotate Operation ..................................................................................................168Branches and Control Transfer ................................................................................................168Bit Operations ..........................................................................................................................168Table Read Operations ............................................................................................................168Other Operations ......................................................................................................................168

Instruction Set Summary ................................................................................ 169Table Conventions ....................................................................................................................16�Extended Instr�ction Set ..........................................................................................................1�1

Rev. 1.20 6 ��st 2�� 201� Rev. 1.20 � ��st 2�� 201�



Instruction Definition ....................................................................................... 173Extended Instruction Definition ................................................................................................182

Package Information ....................................................................................... 18944-pin LQFP (10mm×10mm) (FP2.0mm) O�tline Dimensions ................................................1�048-pin LQFP (�mm×�mm) O�tline Dimensions .......................................................................1�1

Rev. 1.20 6 ��st 2�� 201� Rev. 1.20 � ��st 2�� 201�



Features

CPU Features• OperatingVoltage

♦ fSYS=8MHz:2.2V~5.5V♦ fSYS=12MHz:2.7V~5.5V♦ fSYS=20MHz:4.5V~5.5V

• Upto0.2μsinstructioncyclewith20MHzsystemclockatVDD=5V

• Powerdownandwake-upfunctionstoreducepowerconsumption

• Oscillators♦ ExternalCrystal–HXT♦ External32.768kHzCrystal–LXT♦ InternalHighSpeedRC–HIRC♦ Internal32kHzRC–LIRC

• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP

• Fullyintegratedinternal8/12/16MHzoscillatorrequiresnoexternalcomponents

• Allinstructionsexecutedinonetothreeinstructioncycles

• Tablereadinstructions

• 115powerfulinstructions

• 8-levelsubroutinenesting

• Bitmanipulationinstruction

Peripheral Features• FlashProgramMemory:4K×16

• RAMDataMemory:256×8

• TrueEEPROMMemory:64×8

• WatchdogTimerfunction

• 46bidirectionalI/Olines

• Softwarecontrolled4-SCOMlinesLCDdriverwith1/2bias

• ProgrammableI/OportsourcecurrentforLEDapplications

• Twopin-sharedexternalinterrupts

• MultipleTimerModulefortimemeasure,inputcapture,comparematchoutput,PWMoutputorsinglepulseoutputfunctions

• SerialInterfaceModulewithSPIandI2Cinterfaces

• Full-duplexUniversalAsynchronousReceiverandTransmitterInterface–UART

• Onecomparatorfunction

• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals

• 8-channel12-bitresolutionA/Dconverter

• LowVoltageResetfunction

• LowVoltageDetectfunction

• Packagetype:44/48-pinLQFP

Rev. 1.20 8 ��st 2�� 201� Rev. 1.20 � ��st 2�� 201�



General DescriptionThedevice isaFlashMemory type8-bithighperformanceRISCarchitecturemicrocontroller.Offeringusers theconvenienceofFlashMemorymulti-programmingfeatures, thedevicealsoincludesawiderangeoffunctionsandfeatures.Othermemory includesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.

Analogfeaturesincludeamulti-channel12-bitA/Dconverterandcomparatorfunctions.Multipleandextremely flexibleTimerModulesprovide timing,pulsegenerationandPWMgenerationfunctions.CommunicationwiththeoutsideworldiscateredforbyincludingfullyintegratedSPIorI2Cinterfacefunctions, twopopular interfaceswhichprovidedesignerswithameansofeasycommunicationwithexternalperipheralhardware.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.

Afullchoiceofhighandlowspeed,internalandexternaloscillatorfunctionsareprovidedincludingafullyintegratedsystemoscillatorwhichrequiresnoexternalcomponentsforitsimplementation.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesusers theability tooptimisemicrocontrolleroperationandminimisepowerconsumption.

TheUARTmodulecan support applications suchasdatacommunicationnetworksbetweenmicrocontrollers, low-costdata linksbetweenPCsandperipheraldevices,portableandbatteryoperateddevicecommunication,etc.

TheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensurethat thedevicewillfindexcellentuseinapplicationssuchaselectronicmetering,environmentalmonitoring,handheldinstruments,householdappliances,electronicallycontrolledtools,motordrivinginadditiontomanyothers.

Block Diagram

8-bitRISCMCUCore

I/O Timer Modules

Flash Program Memory

EEPROMData

Memory

Flash/EEPROM Programming Circuitry

TimeBases

SIM(SPI/I2C)

Low Voltage Reset

Watchdog Timer

Low Voltage Detect

InterruptController

ResetCircuit

External HXT/LXT

Oscillators

12-bit A/DConverter

RAM Data Memory

SCOM UART

Internal HIRC/LIRCOscillators

+─

Comparator

Rev. 1.20 8 ��st 2�� 201� Rev. 1.20 � ��st 2�� 201�



Pin Assignment

HT66F0187/HT66V018744 LQFP-A

123456�8�1011

12 131415 161� 181� 20 2122232425262�282�30313233

3435363�383�4041424344

PC0/O

SC1

PE6/SCS

P�

4/�N

3P �

3/�N

4/VR

EFI

PE3/[STP1]

PB1/XT2V

SS

P�0/OC

DSD

�/ICPD

�

P�2/OCDSCK/ICPCK

PC1/O

SC2

PC2/STP0

PF0/SCK/SCLPB2/SDI/SD�

PB0/XT1

P�1/�N

5/VR

EF

PF1 /IN

T0/�N6

PB�/S

TP1I/�N

�

PE�/STCK1PB6/PTPI

PC3/PTCK/RXPB5/STP1

PB4/CLO/TXPB3/SDO

PD6/[STP0I]PD5/[INT1]PD4/[PTPI]PD3/[STP0]/[SCOM3]

PD2/[PTC

K]/[SCO

M2]

PD1/[P

TP]/[SCO

M1]

PD

0/INT1/[S

CO

M0]

P��/[S

TP1I]/�

N0

P�

6/STC

K0/�N1

P�5/STP

0I/�N2

PD�/CX

VD

DP

C�/S

CO

M3

PC

6/SC

OM

2P

C5/S

CO

M1

PC

4/SC

OM

0

PE5/[STCK1]/[TX]PE4/[STCK0]/[RX]

PE2/PTPPE1/C+PE0/C-

123456�8�101112

13141516 1�181�202122232425262�282�30313233343536

45464�48 3�383�4041424344

PB1/XT2VS

S

P�0/OCDSD�/ICPD�P�2/OCDSCK/ICPCK

PC2/STP0

PB

0/XT1

P �5/STP0I/ �

N2

P�4/�

N3

P�

3/�N

4/VR

EFI

P�

1/�N

5/VR

EF

PF 1/IN

T0/�N

6P

B�/S

TP1I/�

N�

PE�/STCK1PB6/PTPI

PC3/PTCK/RXPB4/CLO/TX

PD5/[INT1]PD4/[PTPI]PD3/[STP0]/[SCOM3]PD2/[PTCK]/[SCOM2]PD1/[PTP]/[SCOM1]PD0/INT1/[SCOM0]

PF2/[INT0]

PF3PF4PF5

PD6/[STP0I]PD�/CXPE0/C-PE1/C+

PE3/[STP1]

PE

4/[STCK

0]/[RX

]PE

5/[STC

K1]/[TX

]PC

4/SC

OM

0P

C5/S

CO

M1

PC

6/SC

OM

2P

C�/SC

OM

3

PB3/SDO

P�

6/STC

K0 /�N

1P

��/[S

TP1I]/�

N0

VD

D

PE6/SCSPF0/SCK/SCLPB2/SDI/SD�

PE2/PTP

PB5/STP1

PC0/O

SC1

PC1/O

SC2

HT66F0187/HT66V018748 LQFP-A

Note:1.Ifthepin-sharedpinfunctionshavemultipleoutputs,thenthefunctionattherightmostsideofthe“/”signwillhavehigherpriority.

2.TheOCDSDAandOCDSCKpinsaretheOCDSdedicatedpinsandonlyavailablefortheHT66V0187EVdevice.

Rev. 1.20 10 ��st 2�� 201� Rev. 1.20 11 ��st 2�� 201�



Pin DescriptionWiththeexceptionof thepowerpins,allpinsonthedevicecanbereferencedbyitsPortname,e.g.PA0,PA1etc.,whichrefertothedigitalI/Ofunctionofthepins.HoweverthesePortpinsarealsosharedwithotherfunctionsuchas theAnalogtoDigitalConverter,TimerModulepinsetc.Thefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.

Pin Name Function OPT I/T O/T Description

P�0/OCDSD�/ICPD�P�0 P�PU

P�WU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h and wake-�p.

OCDSD� — ST CMOS OCDS �ddress/Data� for EV chip onlyICPD� — ST CMOS ICP �ddress/Data

P�1/�N5/VREFP�1 P�PU


�N5 �CERL �N — �/D Converter inp�t channel 5VREF S�DC2 — �N �/D Converter reference volta�e o�tp�t

P�2/OCDSCK/ICPCKP�2 P�PU


OCDSCK — ST — OCDS Clock pin� for EV chip onlyICPCK — ST — ICP Clock pin

P�3/�N4/VREFIP�3 P�PU


�N4 �CERL �N — �/D Converter inp�t channel 4VREFI S�DC2 �N — �/D Converter Reference Volta�e Inp�t

P�4/�N3P�4 P�PU


�N3 �CERL �N — �/D Converter inp�t channel 3

P�5/STP0I/�N2

P�5 P�PUP�WU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h

and wake-�p.

STP0I PRMSTM0C1 ST — STM0 Capt�re inp�t


P�6/STCK0/�N1

P�6 P�PUP�WU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h

and wake-�p.

STCK0 PRMSTM0C0 ST — STM0 clock inp�t


P��/[STP1I]/�N0

P�� P�PUP�WU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h

and wake-�p.

STP1IPRM

TMPCSTM1C1

ST — STM1 Capt�re inp�t


PB0/XT1PB0 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.XT1 CO LXT — LXT oscillator pin

PB1/XT2PB1 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.XT2 CO — LXT LXT oscillator pin

PB2/SDI/SD�PB2 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.SDI SIMC0 ST — SPI serial data inp�tSD� SIMC0 ST CMOS I2C data line

PB3/SDOPB3 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.SDO SIMC0 — CMOS SPI serial data o�tp�t

Rev. 1.20 10 ��st 2�� 201� Rev. 1.20 11 ��st 2�� 201�




PB4/CLO/TX

PB4 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.CLO TMPC — CMOS System clock o�tp�t

TXPRMUCR1UCR2

— CMOS U�RT transmit line

PB5/STP1PB5 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

STP1 PRMTMPC — CMOS STM1 o�tp�t

PB6/PTPIPB6 PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

PTPI PRMPTMC1 ST — PTM Capt�re inp�t

PB�/STP1I/�N�

PB� PBPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


�N� �CERL �N — �/D Converter inp�t channel �

PC0/OSC1PC0 PCPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

OSC1 CO HXT — HXT oscillator pin

PC1/OSC2PC1 PCPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

OSC2 CO — HXT HXT oscillator pin

PC2/STP0PC2 PCPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


PC3/PTCK/RX

PC3 PCPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

PTCK PRMPTMC0 ST — PTM clock inp�t

RXPRMUCR1UCR2

ST — U�RT receive line

PC4/SCOM0PC4 PCPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

SCOM0 PRMSCOMC — �N Software controlled 1/2 bias LCD COM





PC�/SCOM3PC� PCPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


PD0/INT1/[SCOM0]

PD0 PDPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

INT1 PRMINTEG ST — External interr�pt 1 inp�t


PD1/[PTP]/[SCOM1]


PTP PRMTMPC — CMOS PTM o�tp�t


Rev. 1.20 12 ��st 2�� 201� Rev. 1.20 13 ��st 2�� 201�




PD2/[PTCK]/[SCOM2]


PTCK PRMPTMC0 ST — PTM clock inp�t


PD3/[STP0]/[SCOM3]




PD4/[PTPI]PD4 PDPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

PTPI PRMPTMC1 ST — PTM Capt�re inp�t

PD5/[INT1]PD5 PDPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

INT1 PRMINTEG ST — External interr�pt 1 inp�t

PD6/[STP0I]PD6 PDPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


PD�/CXPD� PDPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.CX CPC — CMOS Comparator o�tp�t

PE0/C-PE0 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.C- CPC �N — Comparator inp�t

PE1/C+PE1 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.C+ CPC �N — Comparator inp�t

PE2/PTPPE2 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

PTP PRMTMPC — CMOS PTM o�tp�t

PE3/[STP1]PE3 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


PE4/[STCK0]/[RX]

PE4 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


RXPRMUCR1UCR2

ST — U�RT receiver pin

PE5/[STCK1]/[TX]

PE5 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


TXPRMUCR1UCR2

— CMOS U�RT transmitter pin

PE6/SCSPE6 PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.SCS SIMC0 ST CMOS SPI slave select pin

PE�/STCK1PE� PEPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.


PF0/SCK/SCLPF0 PFPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.SCK SIMC0 ST CMOS SPI serial clockSCL SIMC0 ST CMOS I2C clock line

Rev. 1.20 12 ��st 2�� 201� Rev. 1.20 13 ��st 2�� 201�




PF1/INT0/�N6

PF1 PFPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

INT0 PRMINTEG ST — External interr�pt inp�t 0


PF2/[INT0]PF2 PFPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.

INT0 PRMINTEG ST — External interr�pt inp�t 0

PF3~PF5 PF3~PF5 PFPU ST CMOS General p�rpose I/O. Re�ister enabled p�ll-hi�h.VDD VDD — PWR — Power S�pplyVSS VSS — PWR — Gro�nd

Note:I/T:InputtypeO/T:OutputtypeOPT:Optionalbyconfigurationoption(CO)orregisteroptionPWR:PowerCO:ConfigurationoptionST:SchmittTriggerinputCMOS:CMOSoutputAN:AnalogsignalpinHXT:HighfrequencycrystaloscillatorLXT:LowfrequencycrystaloscillatorAsthePinDescriptionSummarytableappliestothepackagetypewiththemostpins,notalloftheabovelistedpinsmaybepresentonpackagetypeswithsmallernumbersofpins.

Absolute Maximum RatingsSupplyVoltage....................................................................................................VSS-0.3VtoVSS+6.0V

InputVoltage......................................................................................................VSS-0.3VtoVDD+0.3V

StorageTemperature.......................................................................................................-50°Cto125°C

OperatingTemperature....................................................................................................-40°Cto85°C

IOLTotal........................................................................................................................................ 80mA

IOHTotal.......................................................................................................................................-80mA

TotalPowerDissipation............................................................................................................ 500mW

Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder “AbsoluteMaximumRatings”maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.

Rev. 1.20 14 ��st 2�� 201� Rev. 1.20 15 ��st 2�� 201�



D.C. CharacteristicsTa=25°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD

Operatin� Volta�e (HXT) —

fSYS=fHXT=8MHz 2.2 — 5.5 VfSYS=fHXT=12MHz 2.� — 5.5 VfSYS=fHXT=16MHz 4.5 — 5.5 VfSYS=fHXT=20MHz 4.5 — 5.5 V

Operatin� Volta�e (HIRC) —fSYS=fHIRC=8MHz 2.2 — 5.5 VfSYS=fHIRC=12MHz 2.� — 5.5 VfSYS=fHIRC=16MHz 4.5 — 5.5 V

Operatin� Volta�e (LXT) — fSYS=fLXT=32.�68kHz 2.2 — 5.5 VOperatin� Volta�e (LIRC) — fSYS=fLIRC=32kHz 2.2 — 5.5 V

IDD

Operatin� C�rrent (HXT)

3V No load� all peripherals off� fSYS=fHXT=8MHz

— 1.0 1.5 m�5V — 2.0 3.0 m�3V No load� all peripherals off�

fSYS=fHXT=12MHz— 1.5 2.�5 m�

5V — 3.0 4.5 m�

5V No load� all peripherals off� fSYS=fHXT=16MHz — 4.5 �.0 m�

5V No load� all peripherals off� fSYS=fHXT=20MHz — 5.5 8.5 m�

Operatin� C�rrent (HIRC)

3V No load� all peripherals off� fSYS=fHIRC=8MHz


fSYS=fHIRC=12MHz— 1.2 1.8 m�

5V — 2.4 3.6 m�

5V No load� all peripherals off� fSYS=fHIRC=16MHz — 4.5 �.0 m�

Operatin� C�rrent (LXT)3V No load� all peripherals off�

fSYS=fLXT=32�68Hz— 10 20 μA

5V — 30 50 μA

Operatin� C�rrent (LIRC)3V No load� all peripherals off�

fSYS=fLIRC=32KHz— 10 20 μA

5V — 30 50 μA

Rev. 1.20 14 ��st 2�� 201� Rev. 1.20 15 ��st 2�� 201�





ISTB

Standby C�rrent(SLEEP0 Mode)

3V No load� all peripherals off� WDT off

— — 1 μA5V — — 2 μA

Standby C�rrent(SLEEP1 Mode)

3V No load� all peripherals off� WDT on

— — 3 μA5V — — 5 μA

Standby C�rrent(IDLE0 Mode)

3V No load� all peripherals off� fSUB on

— 3 5 μA5V — 5 10 μA

Standby C�rrent(IDLE1 Mode� HIRC)

3V No load� all peripherals off� fSUB on� fSYS=fHIRC=8MHz


fSUB on� fSYS=fHIRC=12MHz— 1.2 2.4 m�

5V — 1.5 3.0 m�

5V No load� all peripherals off� fSUB on� fSYS=fHIRC=16MHz — 2.0 4.0 m�

Standby C�rrent(IDLE1 Mode� HXT)

3V No load� all peripherals off� fSUB on� fSYS=fHXT=8MHz


fSUB on� fSYS=fHXT=12MHz— 0.6 1.2 m�

5V — 1.2 2.4 m�

5V No load� all peripherals off� fSUB on� fSYS=fHXT=16MHz — 2.0 4.0 m�

5V No load� all peripherals off� fSUB on� fSYS=fHXT=20MHz — 2.5 5.0 m�

VLVR Low Volta�e Reset Volta�e

— LVR enable� volta�e select 2.1V -5% 2.1 +5%

V— LVR enable�

volta�e select 2.55V -5% 2.55 +5%



VLVD Low Volta�e Detection Volta�e

— LVD enable� volta�e select 2.0V -5% 2.0 +5%

V



— LVD enable� volta�e select 2.�V -5% 2.� +5%





Rev. 1.20 16 ��st 2�� 201� Rev. 1.20 1� ��st 2�� 201�





VBG Band�ap Reference Volta�e — — -3% 1.04 +3% VILVR �dditional c�rrent for LVR Enable — LVD disable� VBGEN=0 — 20 25 μAILVD �dditional c�rrent for LVD Enable — LVR disable� VBGEN=0 — 20 25 μA

VIL Inp�t Low Volta�e for I/O Ports5V — 0 — 1.5 V— — 0 — 0.2VDD V

VIH Inp�t Hi�h Volta�e for I/O Ports5V — 3.5 — 5 V— — 0.8VDD — VDD V

IOL I/O Port Sink C�rrent3V VOL=0.1VDD 16 31 — m�5V VOL=0.1VDD 32 62 — m�

IOH I/O Port� So�rce C�rrent

3V VOH=0.�VDD

So�rce c�rrent=Level 0 -0.6� -1.33 — m�

5V VOH=0.�VDD

So�rce c�rrent=Level 0 -1.5 -3.0 — m�

3V VOH=0.�VDD


5V VOH=0.�VDD


3V VOH=0.�VDD

So�rce c�rrent=Level 2 -1.34 -2.6� — m�

5V VOH=0.�VDD

So�rce c�rrent=Level 2 -3.5 -�.0 — m�

3V VOH=0.�VDD

So�rce c�rrent=Level 3 -4.0 -�.0 — m�

5V VOH=0.�VDD

So�rce c�rrent=Level 3 -�.0 -14.0 — m�

RPH P�ll-hi�h Resistance for I/O Ports3V — 20 60 100 kΩ5V — 10 30 50 kΩ

IBI�S VDD/2 Bias C�rrent for LCD

5V ISEL[1:0]=00B 1�.5 25 32.5 μA5V ISEL[1:0]=01B 35 50 65 μA5V ISEL[1:0]=10B �0 100 130 μA5V ISEL[1:0]=11B 140 200 260 μA

VSCOM VDD/2 Volta�e for LCD COM Port 2.2V~ 5.5V No load 0.4�5VDD 0.5VDD 0.525VDD V

Rev. 1.20 16 ��st 2�� 201� Rev. 1.20 1� ��st 2�� 201�



A.C. CharacteristicsTa=25°C



fSYS

System Clock (HXT)

2.2V~ 5.5V fSYS=fHXT=8MHz — 8 — MHz

2.�V~ 5.5V fSYS=fHXT=12MHz — 12 — MHz


System Clock (HIRC)

2.2V~ 5.5V fSYS=fHIRC=8MHz — 8 — MHz

2.�V~ 5.5V fSYS=fHIRC=12MHz — 12 — MHz


System Clock (LXT) 2.2V~ 5.5V fSYS=fLXT=32.�68kHz — 32�68 — Hz

System Clock (LIRC) 2.2V~ 5.5V fSYS=fLIRC=32kHz — 32 — kHz

fLIRC Low Speed Internal RC Oscillator (LIRC)

3V Ta=25°C -10% 32 +10% kHz3V

±0.3V Ta=-40°C~85°C -40% 32 +40% kHz

2.2V~ 5.5V Ta=-40°C~85°C -50% 32 +60% kHz

5V Ta=25°C -10% 32 +10% kHz5V

± 0.5V Ta=-40°C~85°C -40% 32 +40% kHz

2.2V~5.5V Ta=-40°C~85°C -50% 32 +60% kHz

tTC xTCKn Inp�t Pin Minim�m P�lse Width — — 0.3 — — μstINT External Interr�pt Minim�m P�lse Width — — 10 — — μs

tRSTD

System Reset Delay Time (POR Reset� LVR Hardware Reset� LVR Software Reset� WDT Software Reset)

— — 25 50 100 ms

System Reset Delay Time (WDT Time-o�t Hardware Cold Reset) — — 8.3 16.� 33.3 ms

tSST

System Start-�p Timer Period (wake-�p from H�LT� fSYS off at H�LT)

— fSYS=fSUB=fLXT 128 — — tLXT

— fSYS=fH~fH/64� fH=fHXT 128 — — tHXT

— fSYS=fH~fH/64� fH=fHIRC 16 — — tHIRC

— fSYS=fSUB=fLIRC 2 — — tLIRC

System Start-�p Timer Period (wake-�p from H�LT� fSYS on at H�LT State)

— fSYS=fH~fH/64� fSYS=fHXT or fHIRC 2 — — tSYS

— fSYS=fLXT or fLIRC 2 — — tSYS

System Start-�p Timer Period (WDT Time-o�t Hardware Cold Reset) — — 0 — — tH

tBGS VBG T�rn On Stable Time — No load — — 150 �s

tLVDS LVDO Stable Time— For LVR enable�

VBGEN=0� LVD off → on — — 15 μs

— For LVR disable� VBGEN=0� LVD off → on — — 150 μs

tLVR Minim�m Low Volta�e Width to Reset — — 120 240 480 μstLVD Minim�m Low Volta�e Width to Interr�pt — — 60 120 240 μs

Rev. 1.20 18 ��st 2�� 201� Rev. 1.20 1� ��st 2�� 201�



HIRC Electrical CharacteristicsTa=25°C

Frequency Accuracy Trimmed 8MHz at VDD=3V



fHIRCHi�h Speed Internal RC Oscillator (HIRC)

3V Ta=25°C -2% 8 +2% MHz3V±0.3V Ta=0°C~�0°C -5% 8 +5% MHz3V±0.3V Ta=-40°C~85°C -15% 8 +15% MHz

2.2V~5.5V Ta=0°C~�0°C -�% 8 +�% MHz2.2V~5.5V Ta=-40°C~85°C -10% 8 +10% MHz

3V Ta=25°C -20% 12 +20% MHz3V Ta=25°C -20% 16 +20% MHz





5V Ta=25°C - 2% 8 +2% MHz5V±0.5V Ta=0°C~�0°C -5% 8 +5% MHz5V±0.5V Ta=-40°C~85°C -15% 8 +15% MHz


5V Ta=25°C -20% 12 +20% MHz5V Ta=25°C -20% 16 +20% MHz







3V Ta=25°C -20% 8 +20% MHz3V Ta=25°C -20% 16 +20% MHz







5V Ta=25°C -20% 8 +20% MHz5V Ta=25°C -20% 16 +20% MHz

Rev. 1.20 18 August 29, 2017 Rev. 1.20 19 August 29, 2017






fHIRCHigh Speed Internal RC Oscillator (HIRC)

5V Ta=25°C -2% 16 +2% MHz5V±0.5V Ta=0°C~70°C -5% 16 +5% MHz5V ± 0.5V Ta=-40°C~85°C -15% 16 +15% MHz2.2V~5.5V Ta=0°C~70°C -7% 16 +7% MHz2.2V~5.5V Ta=-40°C~85°C -10% 16 +10% MHz

5V Ta=25°C -20% 8 +20% MHz5V Ta=25°C -20% 12 +20% MHz

Note: 1. tSYS=1/fSYS

2.To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible.

A/D Converter Electrical CharacteristicsTa=25°C



VDD Operating Voltage — — 2.2 — 5.5 VVADI Input Voltage — — 0 — VREF VVREF Reference Voltage — — 2 — VDD V

DNL Differential Nonlinearity ─ VREF=VDD, tADCK=0.5μs, Ta=-40°C~85°C -3 ─ +3 LSB

INL Integral Nonlinearity ─ VREF=VDD, tADCK=0.5μs, Ta=-40°C~85°C -4 ─ +4 LSB

IADC Additional Current for ADC Enable2.2V No load (tADCK=0.5μs) ─ 1.0 2.0 mA3V No load (tADCK=0.5μs) ─ 1.0 2.0 mA5V No load (tADCK=0.5μs) ─ 1.5 3.0 mA

tADCK Clock Period — — 0.5 — 10 μstON2ST ADC on to ADC Start — — 4 — — μs

tADCConversion Time (Include ADC Sample and Hold Time) — — — 16 — tADCK

Note: ADC conversion time (tADC)=n (bits A/D converter) + 4 (sampling time), the conversion for each bit needs one ADC clock (tADCK).

Rev. 1.20 20 ��st 2�� 201� Rev. 1.20 21 ��st 2�� 201�



Comparator Electrical CharacteristicsTa=25°C



VDD Operatin� Volta�e — — 2.2 — 5.5 V

ICMP �dditional C�rrent for Comparator Enable3V — — 3� 56 μA5V — — 130 200 μA

VOS Inp�t Offset Volta�e 5V — -10 — 10 mVVCM Common Mode Volta�e Ran�e — — VSS — VDD-1.4 V�OL Open Loop Gain 5V — 60 80 — dB

VHYS Hysteresis 5VCHYEN =0 0 0 5 mVCHYEN =1 20 40 60 mV

tRP Response Time3V With 100mV overdrive — 3�0 560 ns5V With 100mV overdrive — 3�0 560 ns

Note:MeasuredwithcomparatoroneinputpinatVCM=(VDD-1.4)/2whiletheotherpininputtransitionfromVSSto(VCM+100mV)orfromVDDto(VCM-100mV).

Power on Reset CharacteristicsTa=25°C



VPOR VDD Start Volta�e to Ens�re Power-on Reset — — — — 100 mVRRPOR VDD Raisin� Rate to Ens�re Power-on Reset — — 0.035 — — V/ms

tPORMinim�m Time for VDD Stays at VPOR to Ens�re Power-on Reset — — 1 — — ms

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Rev. 1.20 20 ��st 2�� 201� Rev. 1.20 21 ��st 2�� 201�



System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheir internalsystemarchitecture.TherangeofthedevicetakeadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increased speedof operation and enhancedperformance.Thepipeliningschemeis implementedinsuchawaythat instructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcallinstructionsorextendedinstructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations, logicoperations,rotation,increment,decrement,branchdecisions,etc.Theinternaldatapathissimplifiedbymovingdata through theAccumulatorand theALU.Certain internal registersare implemented in theDataMemoryandcanbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsis required toprovidea functional I/OandA/Dcontrol systemwithmaximumreliabilityandflexibility.Thismakes thedevicesuitable for low-cost,high-volumeproduction forcontrollerapplications.

Clocking and PipeliningThemainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedat thebeginningof theT1clockduringwhichtimeanewinstruction isfetched.TheremainingT2~T4clockscarryout thedecodingandexecution functions. In thisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive instructioncycles, thepipeliningstructureof themicrocontrollerensures thatinstructionsareeffectivelyexecuted inone instructioncycleexceptextended instructions.Theexceptionto thisare instructionswhere thecontentsof theProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwill takeonemoreinstructioncycletoexecute.

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System Clocking and Pipelining

Rev. 1.20 22 ��st 2�� 201� Rev. 1.20 23 ��st 2�� 201�



For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.

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Instruction Fetching

Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas“JMP”or“CALL” thatdemandsa jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.

Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.

Program Counter

Program Counter High Byte PCL RegisterPC11~PC8 PCL�~PCL0

Program Counter

Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly.However,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.

Rev. 1.20 22 ��st 2�� 201� Rev. 1.20 23 ��st 2�� 201�



StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisorganizedinto8levelsandneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresultinastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.

Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.

StackPointer

Stack Level 2

Stack Level 1

Stack Level 3

:::

Stack Level 8

Pro�ram Memory

Pro�ram Co�nter

Bottom of Stack

Top of Stack

Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAALADD,LADDM,LADC,LADCM,LSUB,LSUBM,LSBC,LSBCM,LDAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLALAND,LOR,LXOR,LANDM,LORM,LXORM,LCPL,LCPLA

• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLCLRRA,LRR,LRRCA,LRRC,LRLA,LRL,LRLCA,LRLC

• IncrementandDecrement:INCA,INC,DECA,DECLINCA,LINC,LDECA,LDEC

• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETILSZ,LSZA,LSNZ,LSIZ,LSDZ,LSIZA,LSDZA

Rev. 1.20 24 ��st 2�� 201� Rev. 1.20 25 ��st 2�� 201�



Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthisdevicetheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmeda largenumberoftimes,allowingtheusertheconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdeviceofferuserstheflexibilitytoconvenientlydebuganddevelop their applicationswhilealsoofferingameansof fieldprogrammingandupdating.

StructureTheProgramMemoryhasacapacityof4K×16bits.TheProgramMemoryisaddressedby theProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.

000HInitialisation Vector

004H

FFFH 16 bits

Interr�pt Vectors

02CH

Look-�p Tablen00H

nFFH

030H

Program Memory Structure

Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation0000His reservedforuseby thedevicereset forprograminitialisation.Afteradevicereset isinitiated,theprogramwilljumptothislocationandbeginexecution.

Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressof thelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.

Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe“TABRD[m]”or“TABRDL[m]”instructions,respectivelywhenthememory[m]islocatedinsector0.Ifthememory[m]islocatedinothersectors,thedatacanberetrievedfromtheprogrammemoryusing thecorrespondingextended table read instruction suchas“LTABRD[m]”or“LTABRDL[m]”respectively.Whentheinstructionisexecuted,thelowerordertablebytefromtheProgramMemorywillbetransferredtotheuserdefinedDataMemoryregister[m]asspecifiedintheinstruction.ThehigherordertabledatabytefromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthistransferredhigherorderbytewillbereadas0.

Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.

Rev. 1.20 24 ��st 2�� 201� Rev. 1.20 25 ��st 2�� 201�



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Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.Thisexampleusesrawtabledata located in theProgramMemorywhich isstoredthereusingtheORGstatement.ThevalueatthisORGstatementis“0F00H”whichreferstothestartaddressofthelastpagewithinthe4KProgramMemoryofthemicrocontroller.Thetablepointerlowbyteregisterissetupheretohaveaninitialvalueof“06H”.ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress“0F06H”or6locationsafterthestartofthelastpage.NotethatthevalueforthetablepointerisreferencedtothefirstaddressofthepagethatTBHPpointedifthe“TABRD[m]”instructionisbeingused.ThehighbyteofthetabledatawhichinthiscaseisequaltozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRD[m]”instructionisexecuted.

BecausetheTBLHregister isaread/writeregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.

Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2:mov a, 06h ; initialise low table pointer - note that this address is ; referencedmov tblp, a ; to the last page or the page that tbhp pointedmov a, 0Fh ; initialise high table pointermov tbhp, a:tabrd tempreg1 ; transfers value in table referenced by table pointer data at ; program memory address 0F06H transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrd tempreg2 ; transfers value in table referenced by table pointer data at ; program memory address 0F05H transferred to tempreg2 and TBLH ; in this example the data 1AH is transferred to tempreg1 and ; data 0FH to register tempreg2:org 0F00h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh:

Rev. 1.20 26 ��st 2�� 201� Rev. 1.20 2� ��st 2�� 201�



In Circuit Programming – ICPTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.

TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:

Holtek Writer Pins MCU Programming Pins Pin DescriptionICPD� P�0 Pro�rammin� Serial Data/�ddressICPCK P�2 Pro�rammin� ClockVDD VDD Power S�pplyVSS VSS Gro�nd

TheProgramMemoryandEEPROMdataMemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefor theclock.Twoadditional linesarerequiredfor thepowersupply.The technicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.

Duringtheprogrammingprocess,takingcontroloftheICPDAandICPCKpinsfordataandclockprogrammingpurposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwopins.

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Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kΩorthecapacitanceof*mustbelessthan1nF.

Rev. 1.20 26 ��st 2�� 201� Rev. 1.20 2� ��st 2�� 201�



On-Chip Debug Support – OCDSThere isanEVchipnamedHT66v0187which isused toemulate therealMCUdevicenamedHT66F0187.ThisEVchipdevicealsoprovidesan“On-ChipDebug”functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicearealmostfunctionallycompatibleexceptforthe“On-ChipDebug”function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinis theOCDSData/Addressinput/outputpinwhiletheOCDSCKpin is theOCDSclock inputpin.Whenusersuse theEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsintheactualMCUdevicewillhavenoeffect in theEVchip.However, the twoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.ForamoredetailedOCDSdescription, refer to thecorrespondingdocumentnamed“Holteke-Linkfor8-bitMCUOCDSUser’sGuide”.

Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSD� OCDSD� On-chip Deb�� S�pport Data/�ddress inp�t/o�tp�tOCDSCK OCDSCK On-chip Deb�� S�pport Clock inp�t

VDD VDD Power S�pplyVSS VSS Gro�nd

RAM Data MemoryTheDataMemoryisan8-bitwideRAMinternalmemoryandis the locationwhere temporaryinformationisstored.

Dividedintotwotypes,thefirstofDataMemoryisanareaofRAMwherespecialfunctionregistersare located.Theseregistershavefixed locationsandarenecessary forcorrectoperationof thedevice.Manyof theseregisterscanbereadfromandwritten todirectlyunderprogramcontrol,however, someremainprotected fromusermanipulation.ThesecondareaofDataMemory isreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.

SwitchingbetweenthedifferentDataMemorysectorsisachievedbyproperlysettingtheMemoryPointerstocorrectvalue.

StructureTheDataMemory is subdivided into twosectors,allofwhichare implemented in8-bitwideMemory.EachoftheDataMemorysectorsiscategorizedintotwotypes,theSpecialPurposeDataMemoryandtheGeneralPurposeDataMemory.

TheaddressrangeoftheSpecialPurposeDataMemoryforthedeviceisfrom00Hto7FHwhiletheaddressrangeoftheGeneralPurposeDataMemoryisfrom80HtoFFH.

Special Purpose Data Memory General Purpose Data Memory

Available Sectors Capacity Sectors

0� 1 256 × 8 0: 80H~FFH1: 80H~FFH

Data Memory Summary

Rev. 1.20 28 ��st 2�� 201� Rev. 1.20 2� ��st 2�� 201�



00H

80H

FFH

Special P�rpose Data Memory

General P�rpose Data Memory

Sector 0Sector 1

40H

�FH

Data Memory Structure

Data Memory AddressingForthisdevicethatsupportstheextendedinstructions,thereisnoBankPointerforDataMemory.orDataMemorythedesiredSectorispointedbytheMP1HorMP2HregisterandthecertainDataMemoryaddress in theselectedsector isspecifiedby theMP1LorMP2Lregisterwhenusingindirectaddressingaccess.

DirectAddressingcanbeusedinallsectorsusingthecorrespondinginstructionwhichcanaddressallavailabledatamemoryspace.For theaccesseddatamemorywhich is located inanydatamemorysectorsexceptsector0, theextendedinstructionscanbeusedtoaccessthedatamemoryinsteadofusingtheindirectaddressingaccess.Themaindifferencebetweenstandardinstructionsandextendedinstructionsisthatthedatamemoryaddress“m”intheextendedinstructionscanbe9bits,thehighbyteindicatesasectorandthelowbyteindicatesaspecificaddress.

General Purpose Data MemoryAllmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperationinstructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.

Rev. 1.20 28 ��st 2�� 201� Rev. 1.20 2� ��st 2�� 201�



Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue“00H”.

00H I�R001H MP002H I�R103H MP1L04H05H �CC06H PCL0�H TBLP08H TBLH0�H TBHP0�H ST�TUS0BH0CH0DH0EH0FH10H

MP2H

11H12H

1�H

P�PU

18HP�WU

1BH1�H

1DH1CH

1FH

P�P�C

13H14H15H16H1�H

EE�

20H21H22H

28H

23H24H25H26H2�H

40H41H42H43H44H45H46H4�H48H4�H4�H4BH4CH4DH4EH4FH50H51H

53H54H

1EH

EEC

Sector 0� 1

55H56H

PBCPBPU

PB

�FH

MP1H

I�R2

LVRC

EEDS�DOL

S�DC0

PCPUPD

PCC

5�H58H5�H5�H

S�DOH

PRM

52H

MP2L

INTC1INTC2MFI0MFI1MFI2

TMPCWDTCTBC

CTRL

S�DC1S�DC2

Sector 0 Sector 1

INTC0

SIMTOCSLEDC0SLEDC1

USRSLEDC2

SCOMC

PDC

PF

PDPUPE

PECPEPU

PFCPFPUSMODLVDC

SIMC0

INTEG

SIMC1SIMD

SIMC2/SIM�

STM1C0STM1C1STM1DLSTM1DHSTM1�LSTM1�HSTM1RP

2�H2�H2BH2CH2DH2EH

38H3�H

3�H3�H

3CH3BH

3DH

3FH3EH

PTMC1PTMDLPTMDHPTM�LPTM�HPTMRPLPTMRPH

CPC�CERL

2FH30H31H32H33H34H35H

STM0C0STM0C1STM0DLSTM0DHSTM0�LSTM0�HSTM0RPPTMC0

PC

: Un�sed� read as 00H

36H

TXR_RXRBRG

UCR1UCR25BH

5CH5DH5EH

Special Purpose Data Memory

Rev. 1.20 30 ��st 2�� 201� Rev. 1.20 31 ��st 2�� 201�



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsections;howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Register – IAR0, IAR1, IAR2TheIndirectAddressingRegisters,IAR0,IAR1andIAR2,althoughhavingtheirlocationsinnormalRAMregisterspace,donotactuallyphysicallyexistasnormalregisters.Themethodof indirectaddressing forRAMdatamanipulationuses these IndirectAddressingRegistersandMemoryPointers, incontrast todirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0,IAR1andIAR2registerswillresult innoactualreadorwriteoperationtotheseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0,MP1L/MP1HorMP2L/MP2H.Actingasapair, IAR0andMP0cantogetheraccessdataonlyfromSector0while theIAR1register togetherwithMP1L/MP1HregisterpairandIAR2registertogetherwithMP2L/MP2HregisterpaircanaccessdatafromanyDataMemorysector.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtotheregistersindirectlywillresultinnooperation.

Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L FiveMemoryPointers,knownasMP0,MP1L,MP1H,MP2LandMP2H,areprovided.TheseMemoryPointersarephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister, IAR0,areused toaccessdata fromSector0,whileMP1L/MP1HtogetherwithIAR1andMP2L/MP2HtogetherwithIAR2areusedtoaccessdatafromalldatasectorsaccordingtothecorrespondingMP1HorMP2Hregister.DirectAddressingcanbeusedinalldatasectorsusingthecorrespondinginstructionwhichcanaddressallavailabledatamemoryspace.

ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.

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Indirect Addressing Program Example

Example 1data .section ‘data’adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ?code .section at 0 ‘code’org 00hstart:mov a, 04h ; setup size of blockmov block, amov a, offset adres1 ; Accumulator loaded with first RAM addressmov mp0, a ; setup memory pointer with first RAM addressloop: clr IAR0 ; clear the data at address defined by MP0inc mp0 ; increment memory pointersdz block ; check if last memory location has been clearedjmp loopcontinue:

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.

Example 2data .section ‘data’adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’org 00h start: mov a,04h ; setup size of block mov block,amov a,01h ; setup the memory sectormov mp1h,amov a,offset adres1 ; Accumulator loaded with first RAM address mov mp1l,a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1inc mp1l ; increment memory pointer MP1Lsdz block ; check if last memory location has been cleared jmp loop continue: :

Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificRAMaddresses.

Rev. 1.20 32 ��st 2�� 201� Rev. 1.20 33 ��st 2�� 201�



Direct Addressing Program Example using extended instructionsdata .section ‘data’temp db ? code .section at 0 ‘code ‘org 00h start: lmov a,[m] ; move [m] data to acclsub a, [m+1] ; compare [m] and [m+1] datasnz c ; [m]>[m+1]?jmp continue ; nolmov a,[m] ; yes, exchange [m] and [m+1] datamov temp,almov a,[m+1]lmov [m],amov a,templmov [m+1],acontinue: :

Note:Here“m” isadatamemoryaddress located inanydatamemorysectors.Forexample,m=1F0H,itindicatesaddress0F0HinSector1.

Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuserdefinedregisterandanother, it isnecessary todo thisbypassingthedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.

Program Counter Low Register – PCL Toprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.

Look-up Table Registers – TBLP, TBHP, TBLH Thesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.

Rev. 1.20 32 ��st 2�� 201� Rev. 1.20 33 ��st 2�� 201�



Status Register – STATUS This8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),SCflag,CZflag,powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe“CLRWDT”or“HALT”instruction.ThePDFflagisaffectedonlybyexecutingthe“HALT”or“CLRWDT”instructionorduringasystempower-up.

TheZ,OV,AC,C,SCandCZflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OV isset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDF isclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

• SCistheresultofthe“XOR”operationwhichisperformedbytheOVflagandtheMSBofthecurrentinstructionoperationresult.

• CZistheoperationalresultofdifferentflagsfordifferentinstuctions.Refertoregisterdefinitionsformoredetails.

Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.

Rev. 1.20 34 ��st 2�� 201� Rev. 1.20 35 ��st 2�� 201�



STATUS Register

Bit 7 6 5 4 3 2 1 0Name SC CZ TO PDF OV Z �C CR/W R R R R R/W R/W R/W R/WPOR x x 0 0 x x x x

“x”: �nknownBit7 SC:Theresultofthe“XOR”operationwhichisperformedbytheOVflagandthe

MSBoftheinstructionoperationresult.Bit6 CZ:Thetheoperationalresultofdifferentflagsfordifferentinstuctions.

ForSUB/SUBM/LSUB/LSUBMinstructions,theCZflagisequaltotheZflag.ForSBC/SBCM/LSBC/LSBCMinstructions, theCZflag is the“AND”operationresultwhichisperformedbythepreviousoperationCZflagandcurrentoperationzeroflag.Forotherinstructions,theCZflagwilllnotbeaffected.

Bit5 TO:WatchdogTime-outflag0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instructin

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibbles,inaddition,ornoborrowfromthehighnibbleintothelownibbleinsubstraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

The“C”flagisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.20 34 ��st 2�� 201� Rev. 1.20 35 ��st 2�� 201�



EEPROM Data memoryThisdevicecontainsanareaof internalEEPROMDataMemory.EEPROM,whichstands forElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply is removed.Byincorporating thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.

EEPROM Data Memory StructureTheEEPROMDataMemorycapacity is64×8bitsfor thedevice.Unlike theProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationstotheEEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinSector0andasinglecontrolregisterinSector1.

Capacity Address64×8 00H~3FH

EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinSector0,theycanbedirectlyaccessedinthesamewasasanyotherSpecialFunctionRegister.TheEECregister,however,beinglocatedinSector1,canbereadfromorwrittentoindirectlyusingtheMP1H/MP1LorMP2H/MP12LMemoryPointerpairandIndirectAddressingRegister,IAR1orIAR2.BecausetheEECcontrolregister is locatedataddress40HinSector1, theMemoryPointerlowbyteregister,MP1LorMP2L,mustfirstbeset tothevalue40HandtheMemoryPointerhighbyteregister,MP1HorMP2H,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.

RegisterName

Bit

7 6 5 4 3 2 1 0EE� — — D5 D4 D3 D2 D1 D0EED D� D6 D5 D4 D3 D2 D1 D0EEC — — — — WREN WR RDEN RD

EEPROM Registers List

EEA Register

Bit 7 6 5 4 3 2 1 0Name — — D5 D4 D3 D2 D1 D0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5~0 D5~D0:DataEEPROMaddress

DataEEPROMaddressbit5~bit0

Rev. 1.20 36 ��st 2�� 201� Rev. 1.20 3� ��st 2�� 201�



EED Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:DataEEPROMdataDataEEPROMdatabit7~bit0

EEC Register

Bit 7 6 5 4 3 2 1 0Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3 WREN:DataEEPROMWriteEnable

0:Disable1:Enable

This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.

Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle

This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.

Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable

This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.

Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle

This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.

Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.TheWRandRDcannotbesetto“1”atthesametime.

Rev. 1.20 36 ��st 2�� 201� Rev. 1.20 3� ��st 2�� 201�



Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.

Writing Data to the EEPROMTowritedatatotheEEPROM,theEEPROMaddressofthedatatobewrittenmustfirstbeplacedin theEEAregisterandthedataplacedin theEEDregister.Thenthewriteenablebit,WREN,in theEECregistermustfirstbesethightoenablethewritefunction.After this, theWRbit intheEECregistermustbe immediatelysethigh to initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbeforeimplementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.Notethatsetting theWRbithighwillnot initiateawritecycle if theWRENbithasnotbeenset.As theEEPROMwritecycle iscontrolledusingan internal timerwhoseoperation isasynchronous tomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedtozerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.Theapplicationprogramcanthereforepoll theWRbit todeterminewhenthewritecyclehasended.

Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispoweredon, theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheMemoryPointerhighbyteregisters,MP1HandMP2H,willbereset tozero,whichmeansthatDataMemorySector0willbeselected.AstheEEPROMcontrolregister is located inSector1, thisaddsa furthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuring that theWriteEnablebit in thecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.

EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.However,astheEEPROMiscontainedwithinaMulti-functionInterrupt,theassociatedmulti-functioninterruptenablebitmustalsobeset.WhenanEEPROMwritecycleends, theDEFrequest flagand itsassociatedmulti-functioninterruptrequestflagwillbothbeset.Iftheglobal,EEPROMandMulti-function interruptsareenabledandthestackisnotfull,a jumpto theassociatedMulti-functionInterruptvectorwilltakeplace.WhentheinterruptisservicedonlytheMulti-functioninterruptflagwillbeautomaticallyreset, theEEPROMinterruptflagmustbemanuallyresetbytheapplicationprogram.

Rev. 1.20 38 ��st 2�� 201� Rev. 1.20 3� ��st 2�� 201�



Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheMemoryPointerhighbyteregistercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoSector1wheretheEEPROMcontrolregisterexist.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.WhenwritingdatatheWRbitmustbesethighimmediatelyafter theWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.TheglobalinterruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.NotethatthedeviceshouldnotentertheIDLEorSLEEPmodeuntiltheEEPROMreadorwriteoperationistotallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.

Programming Examples

Reading data from the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, 040H ; setup memory pointer MP1LMOV MP1L, A ; MP1L points to EEC registerMOV A, 01H ; setup Memory Pointer high byte MP1HMOV MP1H, ASET IAR1.1 ; set RDEN bit, enable read operationsSET IAR1.0 ; start Read Cycle - set RD bitBACK:SZ IAR1.0 ; check for read cycle endJMP BACKCLR IAR1 ; disable EEPROM read/writeCLR MP1HMOV A, EED ; move read data to registerMOV READ_DATA, A

Writing Data to the EEPROM - polling methodMOV A, EEPROM_ADRES ; user defined addressMOV EEA, AMOV A, EEPROM_DATA ; user defined dataMOV EED, AMOV A, 040H ; setup memory pointer MP1LMOV MP1L, A ; MP1L points to EEC registerMOV A, 01H ; setup Memory Pointer high byte MP1HMOV MP1H, ACLR EMISET IAR1.3 ; set WREN bit, enable write operationsSET IAR1.2 ; start Write Cycle - set WR bitSET EMIBACK:SZ IAR1.2 ; check for write cycle endJMP BACKCLR IAR1 ; disable EEPROM read/writeCLR MP1H

Rev. 1.20 38 ��st 2�� 201� Rev. 1.20 3� ��st 2�� 201�



OscillatorVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughacombinationofconfigurationoptionsandrelevantcontrolregisters.

Oscillator Overview Inadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellas fully integrated internaloscillators, requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Alloscillatoroptionsareselected through theconfigurationoptions.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thedevicehas theflexibility tooptimize theperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.

Type Name Freq. PinsExternal Crystal HXT 400kHz~20MHz OSC1/OSC2Internal Hi�h Speed RC HIRC 8MHz/12MHz/16MHz —External Low Speed Crystal LXT 32.�68kHz XT1/XT2Internal Low Speed RC LIRC 32kHz —

Oscillator Types

System Clock Configurations Therearefourmethodsofgenerating thesystemclock, twohighspeedoscillatorsandtwolowspeedoscillators.Thehighspeedoscillatorsaretheexternalcrystal/ceramicoscillator-HXTandtheinternal8MHz,12MHz,16MHz,RCoscillator-HIRC.Thetwolowspeedoscillatorsaretheinternal32kHzRCoscillator-LIRCandtheexternal32.768kHzcrystaloscillator-LXT.SelectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.

Theactualsourceclockusedforeachof thehighspeedandlowspeedoscillators ischosenviaconfigurationoptions.Notethattwooscillatorselectionsmustbemadenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochooseano-oscillatorselectionforeitherthehighorlowspeedoscillator.TheOSC1andOSC2pinsareusedtoconnecttheexternalcomponentsfortheexternalcrystal.

Rev. 1.20 40 ��st 2�� 201� Rev. 1.20 41 ��st 2�� 201�



HIRCPrescaler

fH

LXT

Hi�h Speed Oscillator

Low Speed Oscillator

fH/2

fH/16

fH/64

fH/8

fH/4

fH/32

HLCLK�CKS2~CKS0

fSYS

fSUBfSUB

LIRC

HXT

fH

Hi�h Speed Oscillator Confi��ration Option

Low Speed Oscillator Confi��ration Option

Fast Wake-�p from IDLE or SLEEP Mode Control

(for HXT only )

System Clock Configurations

External Crystal/Ceramic Oscillator – HXT TheExternalCrystal/CeramicSystemOscillator isoneof thehighfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Formostcrystaloscillatorconfigurations, thesimpleconnectionofacrystalacrossOSC1andOSC2willcreatethenecessaryphaseshiftandfeedbackforoscillation,withoutrequiringexternalcapacitors.However,forsomecrystaltypesandfrequencies,toensureoscillation, itmaybenecessarytoaddtwosmallvaluecapacitors,C1andC2.Usingaceramicresonatorwillusuallyrequiretwosmallvaluecapacitors,C1andC2,tobeconnectedasshownforoscillationtooccur.ThevaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturer’sspecification.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

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Crystal/Resonator Oscillator – HXT

Rev. 1.20 40 ��st 2�� 201� Rev. 1.20 41 ��st 2�� 201�



HXT Oscillator C1 and C2 Values

Crystal Frequency C1 C212MHz 0pF 0pF8MHz 0pF 0pF4MHz 0pF 0pF1MHz 100pF 100pF

Note: C1 and C2 val�es are for ��idance only.

Crystal Recommended Capacitor Values

Internal RC Oscillator – HIRC TheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreefixedfrequenciesof8MHz,12MHz,16MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyofeither3Vor5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof8MHz,12MHzor16MHz.willhaveatolerancewithin2%.Notethat if this internalsystemclockoptionisselected,asitrequiresnoexternalpinsforitsoperation,I/OpinsarefreeforuseasnormalI/Opins.

External 32.768kHz Crystal Oscillator – LXTTheExternal32.768kHzCrystalSystemOscillatorisoneofthelowfrequencyoscillatorchoices,whichisselectedviaconfigurationoption.Thisclocksourcehasafixedfrequencyof32.768kHzandrequiresa32.768kHzcrystaltobeconnectedbetweenpinsXT1andXT2.Theexternalresistorandcapacitorcomponentsconnectedtothe32.768kHzcrystalarenecessarytoprovideoscillation.Forapplicationswhereprecise frequenciesareessential, thesecomponentsmayberequired toprovidefrequencycompensationduetodifferentcrystalmanufacturingtolerances.Duringpower-upthereisatimedelayassociatedwiththeLXToscillatorwaitingforittostart-up.

WhenthemicrocontrollerenterstheSLEEPorIDLEMode,thesystemclockisswitchedofftostopmicrocontrolleractivityand toconservepower.However, inmanymicrocontrollerapplicationsitmaybenecessary tokeep the internal timersoperationalevenwhenthemicrocontroller is intheSLEEPorIDLEMode.Todothis,anotherclock, independentof thesystemclock,mustbeprovided.

However,forsomecrystals,toensureoscillationandaccuratefrequencygeneration,itisnecessarytoadd twosmallvalueexternalcapacitors,C1andC2.TheexactvaluesofC1andC2shouldbeselectedinconsultationwiththecrystalorresonatormanufacturerspecification.Theexternalparallelfeedbackresistor,RP,isrequired.

Someconfigurationoptionsdetermineif theXT1/XT2pinsareusedfortheLXToscillatororasnormalI/Oorotherpin-sharedfunctionalpins.

• IftheLXToscillatorisnotusedforanyclocksource,theXT1/XT2pinscanbeusedasnormalI/Oorotherpin-sharedfunctionalpins.

• IftheLXToscillatorisusedforanyclocksource,the32.768kHzcrystalshouldbeconnectedtotheXT1/XT2pins.

Foroscillatorstabilityandtominimisetheeffectsofnoiseandcrosstalk, it isimportanttoensurethatthecrystalandanyassociatedresistorsandcapacitorsalongwithinterconnectinglinesarealllocatedasclosetotheMCUaspossible.

Rev. 1.20 42 ��st 2�� 201� Rev. 1.20 43 ��st 2�� 201�



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External LXT Oscillator

LXT Oscillator C1 and C2 Values

Crystal Frequency C1 C232.�68kHz 10pF 10pF

Note: 1. C1 and C2 val�es are for ��idance only.2. RP=5MΩ~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

LXT Oscillator Low Power Function TheLXToscillatorcanfunctioninoneoftwomodes,theQuickStartModeandtheLowPowerMode.ThemodeselectionisexecutedusingtheLXTLPbitintheTBCregister.

LXTLP Bit LXT Mode0 Q�ick Start1 Low-power

Afterpoweron,theLXTLPbitwillbeautomaticallyclearedtozeroensuringthattheLXToscillatoris in theQuickStartoperatingmode.IntheQuickStartModetheLXToscillatorwillpowerupandstabilisequickly.However,after theLXToscillatorhas fullypoweredup itcanbeplacedintotheLow-powermodebysettingtheLXTLPbithigh.Theoscillatorwillcontinuetorunbutwithreducedcurrentconsumption,asthehighercurrentconsumptionisonlyrequiredduringtheLXToscillatorstart-up.Inpowersensitiveapplications,suchasbatteryapplications,wherepowerconsumptionmustbekepttoaminimum,itisthereforerecommendedthattheapplicationprogramsetstheLXTLPbithighabout2secondsafterpower-on.

Itshouldbenotedthat,nomatterwhatconditiontheLXTLPbit issetto, theLXToscillatorwillalwaysfunctionnormally,theonlydifferenceisthatitwilltakemoretimetostartupifintheLow-powermode.

Internal 32kHz Oscillator – LIRC TheInternal32kHzSystemOscillator isoneof the lowfrequencyoscillatorchoices,which isselectedviaconfigurationoption.It isafullyintegratedRCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsfor its implementation.Device trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.Asaresult,atapowersupplyof5Vandatatemperatureof25°Cdegrees,thefixedoscillationfrequencyof32kHzwillhaveatolerancewithin10%.

Supplementary Oscillators Thelowspeedoscillators,inadditiontoprovidingasystemclocksourcearealsousedtoprovideaclocksource to twootherdevicefunctions.Theseare theWatchdogTimerandtheTimeBaseInterrupts.

Rev. 1.20 42 ��st 2�� 201� Rev. 1.20 43 ��st 2�� 201�



Operating Modes and System Clocks Presentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcoursevice-versa, lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthedevicewithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically, theusercanoptimisetheoperationof theirmicrocontrollertoachievethebestperformance/powerratio.

System Clocks ThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingconfigurationoptionsandregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.

Themainsystemclock,cancomefromeitherahighfrequencyfHorlowfrequencyfSUBsource,andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.ThehighspeedsystemclockcanbesourcedfromeitheranHXTorHIRCoscillator,selectedviaaconfigurationoption.ThelowspeedsystemclocksourcecanbesourcedfrominternalclockfSUB.IffSUBisselectedthenitcanbesourcedbyeithertheLXTorLIRCoscillator,selectedviaaconfigurationoption.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.

Therearetwoadditionalinternalclocksfor theperipheralcircuits, thesubstituteclock,fSUB,andtheTimeBaseclock, fTBC.Eachof these internalclocks issourcedbyeither theLXTorLIRCoscillators,selectedviaconfigurationoptions.ThefSUBclockisusedtoprovideasubstituteclockforthemicrocontrollerjustafterawake-uphasoccurredtoenablefasterwake-uptimes.

HIRCPrescaler

fH

LXT

Hi�h Speed Oscillation

Low Speed Oscillation

fH/2

fH/16

fH/64

fH/8

fH/4

fH/32

HLCLK�CKS2~CKS0

fSYS

fSUBfSUB

LIRC

HXT

fH

Hi�h Speed Oscillator Confi��ration Option

Low Speed Oscillator Confi��ration Option

Fast Wake-�p from IDLE or SLEEP Mode Control

(for HXT only )

fSUB

IDLENfTBC

fSYS/4

TBCK

fTB Time Base

WDTfSUB

fTBC

Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillationwillstoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.

Rev. 1.20 44 ��st 2�� 201� Rev. 1.20 45 ��st 2�� 201�



System Operation Modes There are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller, theNORMALModeandSLOWMode.Theremainingfourmodes,theSLEEP0,SLEEP1, IDLE0andIDLE1Modeareusedwhen themicrocontrollerCPUisswitchedoff toconservepower.

Operating ModeDescription

CPU fSYS fSUB fTBC

NORM�L Mode on fH~fH/64 on onSLOW Mode on fSUB on onIDLE0 Mode off off on onIDLE1 Mode off on on onSLEEP0 Mode off off off offSLEEP1 Mode off off on off

NORMAL ModeAsthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallofitsfunctionsoperationalandwherethesystemclockisprovidedbyoneofthehighspeedoscillators.Thismodeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefromoneofthehighspeedoscillators,eithertheHXTorHIRCoscillators.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbits in theSMODregister.Althoughahighspeedoscillator isused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.

SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.Theclocksourceusedwillbefromoneofthelowspeedoscillators,eithertheLXTortheLIRC.Runningthemicrocontrollerinthismodeallowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.

SLEEP0 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregister is low.IntheSLEEP0modetheCPUwillbestopped,andthefSUBclockwillbestoppedtoo,andtheWatchdogTimerfunctionisdisabled.Inthismode,theLVDENismustsetto“0”.IftheLVDENissetto“1”,itwon’tentertheSLEEP0Mode.

SLEEP1 ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterislow.IntheSLEEP1modetheCPUwillbestopped.HoweverthefSUBclockwillcontinuetooperateiftheWatchdogTimerfunctionisenabledwithitsclocksourcecomingfromthefSUB.

IDLE0 Mode TheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitintheSMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutsomeperipheralfunctionswillremainoperationalsuchastheWatchdogTimer,TMsandSIM.IntheIDLE0Mode,thesystemoscillatorwillbestopped.

Rev. 1.20 44 ��st 2�� 201� Rev. 1.20 45 ��st 2�� 201�



IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbit intheSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocksourcetokeepsomeperipheralfunctionsoperationalsuchastheWatchdogTimer,TMsandSIM.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybehighspeedorlowspeedsystemoscillator.

Control RegistersAsingleregister,SMOD,isusedforoverallcontroloftheinternalclockswithinthedevice.

SMOD Register

Bit 7 6 5 4 3 2 1 0Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLKR/W R/W R/W R/W R/W R R R/W R/WPOR 0 0 0 0 0 0 1 1

Bit7~5 CKS2~CKS0:ThesystemclockselectionwhenHLCLKis“0”000:fSUB(fLXTorfLIRC)001:fSUB(fLXTorfLIRC)010:fH/64011:fH/32100:fH/16101:fH/8110:fH/4111:fH/2

Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.Inadditiontothesystemclocksource,whichcanbeeithertheLXTorLIRC,adividedversionof thehighspeedsystemoscillatorcanalsobechosenas thesystemclocksource.

Bit4 FSTEN:FastWake-upControl(onlyforHXT)0:Disable1:Enable

This is theFastWake-upControlbitwhichdetermines if the fSUBclocksource isinitiallyusedafterthedevicewakesup.Whenthebitishigh,thefSUBclocksourcecanbeusedasatemporarysystemclocktoprovideafasterwakeuptimeasthefSUBclockisavailable.

Bit3 LTO:Lowspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthelowspeedsystemoscillatorreadyflagwhichindicateswhenthelowspeedsystemoscillator isstableafterpoweronresetorawake-uphasoccurred.TheflagwillbelowwhenintheSLEEP0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter128clockcycles if theLXToscillator isusedand1~2clockcyclesiftheLIRCoscillatorisused.

Bit2 HTO:Highspeedsystemoscillatorreadyflag0:Notready1:Ready

Thisisthehighspeedsystemoscillatorreadyflagwhichindicateswhenthehighspeedsystemoscillatorisstable.Thisflagisclearedto“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafterthehighspeedsystemoscillatorisstable.

Rev. 1.20 46 ��st 2�� 201� Rev. 1.20 4� ��st 2�� 201�



Thereforethisflagwillalwaysbereadas“1”bytheapplicationprogramafterdevicepower-on.TheflagwillbelowwhenintheSLEEPorIDLE0Modebutafterawake-uphasoccurred,theflagwillchangetoahighlevelafter512clockcyclesiftheHXToscillatorisusedandafter15~16clockcyclesiftheHIRCoscillatorisused.

Bit1 IDLEN:IDLEModecontrol0:Disable1:Enable

This is theIDLEModeControlbitanddetermineswhathappenswhentheHALTinstructionisexecuted.If thisbit ishigh,whenaHALTinstructionisexecutedthedevicewillenter theIDLEMode. In theIDLE1Mode theCPUwillstoprunningbut thesystemclockwillcontinue tokeep theperipheral functionsoperational, ifFSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstopinIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALTinstructionisexecuted.

Bit0 HLCLK:systemclockselection0:fH/2~fH/64orfSUB

1:fH

Thisbit isused toselect if the fHclockor the fH/2~fH/64or fSUBclock isusedasthesystemclock.Whenthebit ishigh thefHclockwillbeselectedandif lowthefH/2~fH/64or fSUBclockwillbeselected.WhensystemclockswitchesfromthefHclocktothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.

CTRL Register

Bit 7 6 5 4 3 2 1 0Name FSYSON — — — — LVRF LRF WRFR/W R/W — — — — R/W R/W R/WPOR 0 — — — — x 0 0

“x”: �nknownBit7 FSYSON:fSYSControlinIDLEMode

0:Disable1:Enable

ThisbitisusedtocontrolwhetherthesystemclockisswitchedonornotintheIDLEMode.Ifthisbitissetto“0”,thesystemclockwillbeswitchedoffintheIDLEMode.However,thesystemclockwillbeswitchedonintheIDLEModewhentheFSYSONbitissetto“1”.

Bit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

Describedelsewhere.Bit1 LRF:LVRcontrolregistersoftwareresetflag

Describedelsewhere.Bit0 WRF:WDTcontrolregistersoftwareresetflag

Describedelsewhere.

Rev. 1.20 46 ��st 2�� 201� Rev. 1.20 4� ��st 2�� 201�



Fast Wake-up TominimisepowerconsumptionthedevicecanentertheSLEEPorIDLE0Mode,wherethesystemclocksourcetothedevicewillbestopped.Howeverwhenthedeviceiswokenupagain,itcantakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.ToensurethedeviceisupandrunningasfastaspossibleaFastWake-upfunctionisprovided,whichallowsfSUB,namelyeithertheLXTorLIRCoscillator,toactasatemporaryclocktofirstdrivethesystemuntil theoriginalsystemoscillatorhasstabilised.AstheclocksourcefortheFastWake-upfunctionisfSUB, theFastWake-upfunctionisonlyavailableintheSLEEP1andIDLE0modes.WhenthedeviceiswokenupfromtheSLEEP0mode,theFastWake-upfunctionhasnoeffectbecausethefSUBclockisstopped.TheFastWake-upenable/disablefunctioniscontrolledusingtheFSTENbitintheSMODregister.

If theHXToscillator isselectedas theNORMALModesystemclock,andif theFastWake-upfunctionisenabled,thenitwilltakeonetotwotSUBclockcyclesoftheLIRCorLXToscillatorforthesystemtowake-up.ThesystemwilltheninitiallyrununderthefSUBclocksourceuntil512HXTclockcycleshaveelapsed,atwhichpointtheHTOflagwillswitchhighandthesystemwillswitchovertooperatingfromtheHXToscillator.

If theHIRCoscillatororLIRCoscillator isusedasthesystemoscillator thenitwill take15~16clockcyclesof theHIRCor1~2cyclesof theLIRCtowakeupthesystemfromtheSLEEPorIDLE0Mode.TheFastWake-upbit,FSTENwillhavenoeffectinthesecases.

System Oscillator

FSTEN Bit

Wake-up Time(SLEEP0 Mode)

Wake-up Time(SLEEP1 Mode)

Wake-up Time(IDLE0 Mode)

Wake-up Time(IDLE1 Mode)

HXT

0 128 128 HXT cycles 1~2 HXT cycles

1 128 HXT cycles1~2 fSUB cycles(System r�ns with fSUB first for 512 HXT cycles and then switches over to r�n with the HXT clock)

1~2 HXT cycles

HIRC x 15~16 HIRC cycles 15~16 HIRC cycles 1~2 HIRC cyclesLIRC x 1~2 LIRC cycles 1~2 LIRC cycles 1~2 LIRC cyclesLXT x 128 LXT cycles 128 LXT cycles 1~2 LXT cycles

“x”: don’t careWake-Up Times

NotethatiftheWatchdogTimerisdisabled,whichmeansthattheLXTandLIRCareallbothoff,thentherewillbenoFastWake-upfunctionavailablewhenthedevicewake-upfromtheSLEEP0Mode.

Rev. 1.20 48 ��st 2�� 201� Rev. 1.20 4� ��st 2�� 201�



Operating Mode Switching Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.

Insimple terms,ModeSwitchingbetween theNORMALModeandSLOWMode isexecutedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromtheNORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenaHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONbitintheCTRLregister.

WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthehighspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,thehighspeedclocksourcewillstoprunningtoconservepower.WhenthishappensitmustbenotedthatthefH/16andfH/64internalclocksourceswillalsostoprunning,whichmayaffecttheoperationofother internal functionssuchas theTMsandSIM.Theaccompanyingflowchartshowswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.

NORMALfSYS=fH~fH/64

fH onCPU r�nfSYS onfSUB onfTBC on

SLOWfSYS=fSUBfSUB on

CPU r�nfSYS onfH off

fTBC on

IDLE0H�LT instr�ction exec�ted

CPU stopIDLEN=1

FSYSON=0fSYS offfSUB onfTBC on

IDLE1H�LT instr�ction exec�ted

CPU stopIDLEN=1

FSYSON=1fSYS onfSUB onfTBC on

SLEEP1H�LT instr�ction exec�ted

CPU stopIDLEN=0

fSYS offfSUB onfTBC off

WDT on

SLEEP0H�LT instr�ction exec�ted

CPU stopIDLEN=0

fSYS offfSUB offfTBC off

WDT & LVD off

Rev. 1.20 48 ��st 2�� 201� Rev. 1.20 4� ��st 2�� 201�



NORMAL Mode to SLOW Mode Switching WhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andthereforeconsumesmorepower,thesystemclockcanswitchtorunintheSLOWModebysettheHLCLKbitto“0”andsettheCKS2~CKS0bitsto“000”or“001”intheSMODregister.Thiswillthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.

TheSLOWModeissourcedfromtheLXTor theLIRCoscillatorsandthereforerequires theseoscillatorstobestablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.

NORMAL Mode

SLOW Mode

CKS2~CKS0 = 00xB &HLCLK = 0

SLEEP0 Mode

IDLEN=0H�LT instr�ction is exec�ted

SLEEP1 Mode

IDLE0 Mode

IDLE1 Mode

WDT and LVD are all off

IDLEN=0H�LT instr�ction is exec�ted

WDT is on

IDLEN=1� FSYSON=0H�LT instr�ction is exec�ted

IDLEN=1� FSYSON=1H�LT instr�ction is exec�ted

Rev. 1.20 50 ��st 2�� 201� Rev. 1.20 51 ��st 2�� 201�



SLOW Mode to NORMAL Mode Switching InSLOWModethesystemuseseither theLXTorLIRClowspeedsystemoscillator.ToswitchbacktotheNORMALMode,wherethehighspeedsystemoscillatorisused,theHLCLKbitshouldbeset to“1”orHLCLKbit is“0”,butCKS2~CKS0isset to“010”,“011”,“100”,“101”,“110”or“111”.Asacertainamountof timewillberequiredfor thehighfrequencyclocktostabilise,thestatusoftheHTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilizationdependsuponwhichhighspeedsystemoscillatortypeisused.

NORMAL Mode

SLOW Mode

CKS2~CKS0 ≠ 000B or 001B as HLCLK = 0 or HLCLK = 1

SLEEP0 Mode

IDLEN=0HALT instruction is executed

SLEEP1 Mode

IDLE0 Mode

IDLE1 Mode

WDT and LVD are all off

IDLEN=0HALT instruction is executed

WDT is on

IDLEN=1, FSYSON=0HALT instruction is executed

IDLEN=1, FSYSON=1HALT instruction is executed

Entering the SLEEP0 Mode ThereisonlyonewayforthedevicetoentertheSLEEP0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTandLVDbothoff.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclock,WDTclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction.

• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.

• TheWDTwillbeclearedandstoppednomatter if theWDTclocksourceorginatesfromtheLXTorLIRCoscillator.

• TheI/Oportswillmaintaintheirpresentconditions.

• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.

Rev. 1.20 50 ��st 2�� 201� Rev. 1.20 51 ��st 2�� 201�



Entering the SLEEP1 Mode ThereisonlyonewayforthedevicetoentertheSLEEP1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”andtheWDTon.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopatthe“HALT”instruction,buttheWDTwillremainwiththeclocksourcecomingfromthefSUBclock.


• TheWDTwillbeclearedandresumecountingiftheWDTfunctionisenabled.



Entering the IDLE0 Mode ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• The systemclockwill be stoppedand the applicationprogramwill stopat the “HALT”instruction,buttheTimeBaseclockandfSUBclockwillbeon.





Entering the IDLE1 Mode ThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andtheFSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:

• Thesystemclock,TimeBaseclockandfSUBclockwillbeonandtheapplicationprogramwillstopatthe“HALT”instruction.





Rev. 1.20 52 ��st 2�� 201� Rev. 1.20 53 ��st 2�� 201�



Standby Current Considerations AsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptintheIDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestothedevicewhichhasdifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.

Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuits thatdonotdrawcurrent,suchasotherCMOSinputs.Alsonote thatadditionalstandbycurrentwillalsoberequiredif theconfigurationoptionshaveenabledtheLXTorLIRCoscillator.

IntheIDLE1Modethesystemoscillatorison,ifthesystemoscillatorisfromthehighspeedsystemoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.

Wake-up AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:

• AnexternalfallingedgeonPortA

• Asysteminterrupt

• AWDToverflow

Whenthedeviceexecutesthe“HALT”instruction,thePDFflagwillbesetto1.ThePDFflagwillbeclearedto0ifthedeviceexperiencesasystempower-uporexecutestheclearWatchdogTimerinstruction.IfthesystemiswokenupbyaWDToverflow,aWatchdogTimerresetwillbeinitiatedandtheTOflagwillbesetto1.TheTOflagissetifaWDTtime-outoccursandcausesawake-upthatonlyresetstheProgramCounterandStackPointer,otherflagsremainintheiroriginalstatus.

EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepintowake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.If thesystemiswokenupbyaninterrupt, thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterruptisdisabledortheinterruptisenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequestflag issethighbeforeentering theSLEEPorIDLEMode, thewake-upfunctionof therelatedinterruptwillbedisabled.

Rev. 1.20 52 ��st 2�� 201� Rev. 1.20 53 ��st 2�� 201�



Programming Considerations ThehighspeedandlowspeedoscillatorsbothusethesameSSTcounter.Forexample,ifthesystemiswokenupfromtheSLEEP0ModeandboththeHIRCandLXToscillatorsneedtostart-upfromanoffstate.TheLXToscillatoruses theSSTcounterafterHIRCoscillatorhasfinisheditsSSTperiod.

• IfthedeviceiswokenupfromtheSLEEP0ModetotheNORMALMode,thehighspeedsystemoscillatorneedsanSSTperiod.ThedevicewillexecutefirstinstructionafterHTOis“1”.Atthistime,theLXToscillatormaynotbestabilityiffSUBisfromLXToscillator.Thesamesituationoccursinthepower-onstate.TheLXToscillatorisnotreadyyetwhenthefirstinstructionisexecuted.

• If thedeviceiswokenupfromtheSLEEP1ModetoNORMALMode,andthesystemclocksourceisfromHXToscillatorandFSTENis“1”,thesystemclockcanbeswitchedtotheLIRCoscillatorafterwakeup.

• Thereareperipheralfunctions,suchasWDT,TMsandSIM,forwhichthefSYSisused.IfthesystemclocksourceisswitchedfromfH tofSUB, theclocksourcetotheperipheralfunctionsmentionedabovewillchangeaccordingly.

• Theon/offconditionoffSUBdependsuponwhethertheWDTisenabledordisabledastheWDTclocksourceisselectedfromfSUB.

Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.

Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fSUB,whichisinturnsuppliedbytheLIRCorLXToscillator.TheLXToscillatorissuppliedbyanexternal32.768kHzcrystal.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.However,itshouldbenotedthatthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.

Watchdog Timer Control RegisterAsingle register,WDTC,controls the required timeoutperiodaswell as theenable/disableoperation.ThisregistercontrolstheoveralloperationoftheWatchdogTimer.

Rev. 1.20 54 ��st 2�� 201� Rev. 1.20 55 ��st 2�� 201�



WDTC Register

Bit 7 6 5 4 3 2 1 0Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1

Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol10101:Disable01010:EnableOther:ResetMCU

Whenthesebitsarechangedbytheenvironmentalnoiseorsoftwaresettingtoresetthemicrocontroller,theresetoperationwillbeactivatedafter2~3LIRCclockcyclesandtheWRFbitintheCTRLregisterwillbesetto1.

Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fSUB

001:210/fSUB

010:212/fSUB

011:214/fSUB

100:215/fSUB

101:216/fSUB

110:217/fSUB

111:218/fSUB

CTRL Register



DescribedelsewhereBit6~3 Unimplemented,readas“0”Bit2 LVRF:LVRfunctionresetflag

DescribedelsewhereBit1 LRF:LVRControlregistersoftwareresetflag

DescribedelsewhereBit0 WRF:WDTControlregistersoftwareresetflag

0:Notoccur1:Occurred

Thisbit isset to1by theWDTControlregistersoftwareresetandclearedby theapplicationprogram.Note that thisbitcanonlybecleared to0by theapplicationprogram.

Rev. 1.20 54 ��st 2�� 201� Rev. 1.20 55 ��st 2�� 201�



Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.WithregardtotheWatchdogTimerenable/disablefunction,therearefivebits,WE4~WE0,intheWDTCregistertoofferadditionalenable/disableandresetcontrolof theWatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalueof10101B.TheWDTfunctionwillbeenablediftheWE4~WE0bitsvalueisequalto01010B.IftheWE4~WE0bitsaresettoanyothervaluesbytheenvironmentalnoiseorsoftwaresetting,except01010Band10101B,itwillresetthedeviceafter2~3LIRCclockcycles.Afterpoweronthesebitswillhavethevalueof01010B.

WE4~WE0 Bits WDT Function10101B Disable01010B Enable

�ny other val�e Reset MCU

Watchdog Timer Enable/Disable Control

Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bitfiled, thesecondisusingtheWatchdogTimersoftwareclear instructionsandthethirdisviaaHALTinstruction.

ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle“CLRWDT”instructiontocleartheWDT.

Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.

“CLR WDT”Instr�ction

8-sta�e Divider WDT Prescaler

WE4~WE0 bitsWDTC Re�ister Reset MCU

LXT fSUBfSUB/28

8-to-1 MUX

CLR

WS2~WS0 WDT Time-o�t(28/fSUB ~ 218/fSUB)

LIRC

MUX

Low Speed Oscillator Confi��ration option

“H�LT”Instr�ction

Watchdog Timer

Rev. 1.20 56 ��st 2�� 201� Rev. 1.20 5� ��st 2�� 201�



Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawell-definedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.

AnothertypeofresetiswhentheWatchdogTimeroverflowsandresets.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullreset, is implementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.

Reset Functions Thereareseveralwaysinwhicharesetcanoccur,eachofwhichwillbedescribedasfollows.

Power-on Reset Themostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/OportandportcontrolregisterswillpowerupinahighconditionensuringthatallI/Oportswillbefirstsettoinputs.

VDD

Power-on Reset

SST Time-o�t

tRSTD

Note:tRSTDispower-ondelaywithtypicaltime=50msPower-On Reset Timing Chart

Low Voltage Reset — LVR Themicrocontrollercontainsalowvoltageresetcircuit inordertomonitorthesupplyvoltageofthedevice.TheLVRfunctionisalwaysenabledwithaspecificLVRvoltageVLVR.If thesupplyvoltageof thedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery, theLVRwillautomaticallyreset thedeviceinternallyandtheLVRFbit intheCTRLregisterwillalsobesetto1.ForavalidLVRsignal,alowsupplyvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforatimegreaterthanthatspecifiedbytLVRintheA.C.ElectricalCharacteristics.Ifthelowsupplyvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRvaluecanbeselectedbytheLVSbitsintheLVRCregister.IftheLVS7~LVS0bitsarechangedtosomecertainvaluesbytheenvironmentalnoiseorsoftwaresetting,theLVRwillresetthedeviceafter2~3LIRCclockcycles.Whenthishappens,theLRFbitintheCTRLregisterwillbesetto1.Afterpowerontheregisterwillhavethevalueof01010101B.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceentersthepowerdownmode.

Rev. 1.20 56 ��st 2�� 201� Rev. 1.20 5� ��st 2�� 201�



LVR

Internal ResettRSTD + tSST

Note:tRSTDispower-ondelaywithtypicaltime=50msLow Voltage Reset Timing Chart

• LVRC Register

Bit 7 6 5 4 3 2 1 0Name LVS� LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~0 LVS7~LVS0:LVRvoltageselect01010101:2.1V(Default)00110011:2.55V10011001:3.15V10101010:3.8VOthervalues:GeneratesaMCUreset–registerisresettoPORvalue

Whenanactuallowvoltageconditionoccurs,asspecifiedbyoneofthefourdefinedLVRvoltagevaluesabove,anMCUresetwillbegenerated. In this situation theregistercontentswillremainthesameaftersucharesetoccurs.Anyregistervalue,otherthanthefourdefinedLVRvaluesabove,willalsoresultinthegenerationofanMCUreset.Theresetoperationwillbeactivatedafter2~3LIRCclockcycles.HoweverinthissituationtheregistercontentswillberesettothePORvalue.

• CTRL Register



DescribedelsewhereBit6~3 Unimplemented,readas"0"Bit2 LVRF:LVRfunctionresetflag

0:Notoccur1:Occurred

Thisbitissetto1whenaspecificLowVoltageResetsituationconditionoccurs.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit1 LRF:LVRControlregistersoftwareresetflag0:Notoccur1:Occurred

Thisbitissetto1iftheLVRCregistercontainsanynon-definedLVRvoltageregistervalues.Thisineffectactslikeasoftware-resetfunction.Thisbitcanonlybeclearedto0bytheapplicationprogram.

Bit0 WRF:WDTControlregistersoftwareresetflagDescribedelsewhere

Rev. 1.20 58 ��st 2�� 201� Rev. 1.20 5� ��st 2�� 201�



Watchdog Time-out Reset during Normal Operation TheWatchdogtime-outResetduringnormaloperationisthesameasthehardwareLVRresetexceptthattheWatchdogtime-outflagTOwillbesetto"1".

WDT Time-o�t

Internal ResettRSTD + tSST

Note:tRSTDispower-ondelaywithtypicaltime=16.7msWDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode TheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto“0”andtheTOflagwillbesetto“1”.RefertotheA.C.CharacteristicsfortSSTdetails.

WDT Time-o�t

Internal ResettSST

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Reset Initial Conditions Thedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:

TO PDF Reset Conditions0 0 Power-on reset� � LVR reset d�rin� Normal or SLOW Mode operation1 � WDT time-o�t reset d�rin� Normal or SLOW Mode operation1 1 WDT time-o�t reset d�rin� IDLE or SLEEP Mode operation

“�” stands for �nchan�edThefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.

Item Condition after ResetPro�ram Co�nter Reset to zeroInterr�pts �ll interr�pts will be disabledWDT� Time Base Clear after reset� WDT be�ins co�ntin�Timer Mod�les Timer Mod�les will be t�rned offInp�t/O�tp�t Ports I/O ports will be set�p as inp�tsStack Pointer Stack Pointer will point to the top of the stack

Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.

Rev. 1.20 58 ��st 2�� 201� Rev. 1.20 5� ��st 2�� 201�



Register Reset (Power On)

LVR Reset (Normal Operation)

WDT Time-out (Normal Operation)

WDT Time-out (HALT)*

I�R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �I�R1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP1H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � ��CC x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �TBLH x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �TBHP x x x x x x x x � � � � � � � � � � � � � � � � � � � � � � � �ST�TUS x x 0 0 x x x x x x � � � � � � x x 1 � � � � � � � 11 � � � �I�R2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP2L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MP2H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �INTC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MFI0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - � � - - � �MFI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �MFI2 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - � � - - � �P� 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �P�C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �P�PU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �P�WU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PRM - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �TMPC 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 � - - - - � � �WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 � � � � � � � �TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 � � � � � � � �CTRL 0 - - - - x 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 � - - - - � � �LVRC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 � � � � � � � �EE� - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - � � � � � �EED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �S�DOL (�DRFS=0) x x x x - - - - x x x x - - - - x x x x - - - - � � � � - - - -S�DOL (�DRFS=1) x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �S�DOH (�DRFS=0) x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �S�DOH (�DRFS=1) - - - - x x x x - - - - x x x x - - - - x x x x - - - - � � � �S�DC0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 � � � � - � � �S�DC1 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 � � � - - � � �S�DC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PBPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM1C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -STM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM1DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM1�L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM1�H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM1RP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM0C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -STM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �

Rev. 1.20 60 ��st 2�� 201� Rev. 1.20 61 ��st 2�� 201�



Register Reset (Power On)

LVR Reset (Normal Operation)

WDT Time-out (Normal Operation)

WDT Time-out (HALT)*

STM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM0DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM0�L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM0�H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �STM0RP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PTMC0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - � � � � � - - -PTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PTMDH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �PTM�L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PTM�H - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �PTMRPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PTMRPH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - � �CPC 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 � � � � � � � ��CERL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PCC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PCPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PDC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PDPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PEC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 � � � � � � � �PEPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �PF - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - � � � � � �PFC - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - 1 1 1 1 1 1 - - � � � � � �PFPU - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - � � � � � �SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 � � � � � � � �LVDC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - � � - � � �INTEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - � � � �INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �SCOMC - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � �SIMC0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 � � � - � � � �SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 � � � � � � � �SIMD x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �SIM� 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - � � � � � � � -SIMC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �SIMTOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �SLEDC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 � � � � � � � �SLEDC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 � � � � � � � �SLEDC2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 � � � � � � � �USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 � � � � � � � �UCR1 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 � � � � � � � �UCR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 � � � � � � � �BRG x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �TXR_RXR x x x x x x x x x x x x x x x x x x x x x x x x � � � � � � � �EEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - � � � �

Note:“u”standsforunchanged“x”standsforunknown“-”standsforunimplemented

Rev. 1.20 60 ��st 2�� 201� Rev. 1.20 61 ��st 2�� 201�



Input/Output Ports HoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.

Thedeviceprovidesbidirectionalinput/outputlineslabeledwithportnamesPA~PF.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

Register Name

Bit

7 6 5 4 3 2 1 0P� P�� P�6 P�5 P�4 P�3 P�2 P�1 P�0

P�C P�C� P�C6 P�C5 P�C4 P�C3 P�C2 P�C1 P�C0P�PU P�PU� P�PU6 P�PU5 P�PU4 P�PU3 P�PU2 P�PU1 P�PU0P�WU P�WU� P�WU6 P�WU5 P�WU4 P�WU3 P�WU2 P�WU1 P�WU0

PB PB� PB6 PB5 PB4 PB3 PB2 PB1 PB0PBC PBC� PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0

PBPU PBPU� PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0PC PC� PC6 PC5 PC4 PC3 PC2 PC1 PC0

PCC PCC� PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0PCPU PCPU PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0

PD PD� PD6 PD5 PD4 PD3 PD2 PD1 PD0PDC PDC� PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0

PDPU PDPU� PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0PE PE� PE6 PE5 PE4 PE3 PE2 PE1 PE0

PEC PEC� PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0PEPU PEPU� PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0

PF — — PF5 PF4 PF3 PF2 PF1 PF0PFC — — PFC5 PFC4 PFC3 PFC2 PFC1 PFC0

PFPU — — PFPU5 PFPU4 PFPU3 PFPU2 PFPU1 PFPU0

I/O Registers List

“—”:Unimplemented,readas“0”PAWUn:PortAPinwake-upfunctioncontrol

0:Disable1:Enable

PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn:I/OPinpull-highfunctioncontrol0:Disable1:Enable

PAn/PBn/PCn/PDn/PEn/PFn:I/OPortDatabit0:Data01:Data1

PACn/PBCn/PCCn/PDCn/PECn/PFCn:I/OPintypeselection0:Output1:Input

Rev. 1.20 62 ��st 2�� 201� Rev. 1.20 63 ��st 2�� 201�



Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PFPU,andare implementedusingweakPMOStransistors.

Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.

I/O Port Control RegistersEach I/Oport has itsowncontrol registerknownasPAC~PFC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.

I/O Port Source Current ControlThedevice supports different source currentdriving capability for each I/Oport.With thecorrespondingselectionregister,SLEDC0,SLEDC1andSLEDC2,eachI/Oportcansupportfourlevelsofthesourcecurrentdrivingcapability.UsersshouldrefertotheD.C.characteristicssectiontoselectthedesiredsourcecurrentfordifferentapplications.

Register Name

Bit

7 6 5 4 3 2 1 0SLEDC0 PBPS3 PBPS2 PBPS1 PBPS0 P�PS3 P�PS2 P�PS1 P�PS0SLEDC1 PDPS3 PDPS2 PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0SLEDC2 PFPS3 PFPS2 PFPS1 PFPS0 PEPS3 PEPS2 PEPS1 PEPS0

I/O Port Source Current Control Registers List

Rev. 1.20 62 ��st 2�� 201� Rev. 1.20 63 ��st 2�� 201�



SLEDC0 Register

Bit 7 6 5 4 3 2 1 0Name PBPS3 PBPS2 PBPS1 PBPS0 P�PS3 P�PS2 P�PS1 P�PS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~6 PBPS3~PBPS2:PB7~PB4sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit5~4 PBPS1~PBPS0:PB3~PB0sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit3~2 PAPS3~PAPS2:PA7~PA4sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit1~0 PAPS1~PAPS0:PA3~PA0sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

SLEDC1 Register

Bit 7 6 5 4 3 2 1 0Name PDPS3 PDPS2 PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~6 PDPS3~PDPS2:PD7~PD4sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit5~4 PDPS1~PDPS0:PD3~PD0sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit3~2 PCPS3~PCPS2:PC7~PC4sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit1~0 PCPS1~PCPS0:PC3~PC0sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Rev. 1.20 64 ��st 2�� 201� Rev. 1.20 65 ��st 2�� 201�



SLEDC2 Register

Bit 7 6 5 4 3 2 1 0Name PFPS3 PFPS2 PFPS1 PFPS0 PEPS3 PEPS2 PEPS1 PEPS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1

Bit7~6 PFPS3~PFPS2:PF5~PF4sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit5~4 PFPS1~PFPS0:PF3~PF0sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit3~2 PEPS3~PEPS2:PE7~PE4sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Bit1~0 PEPS1~PEPS0:PE3~PE0sourcecurrentselection00:Sourcecurrent=Level0(min.)01:Sourcecurrent=Level110:Sourcecurrent=Level211:Sourcecurrent=Level3(max.)

Pin-remapping FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyof thesedifficultiescanbeovercome.Thewayinwhichthepinfunctionofeachpinisselectedisdifferentforeachfunctionandapriorityorderisestablishedwheremorethanonepinfunctionisselectedsimultaneously.Additionally there isaregister,PRM,toestablishcertainpinfunctions.

Thelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoeven relativelysmallpackagesizes. If thepin-sharedpin functionhavemultipleoutputssimultaneously,itspinnamesattherightsideofthe“/”signcanbeusedforhigherpriority.

Rev. 1.20 64 ��st 2�� 201� Rev. 1.20 65 ��st 2�� 201�



PRM Register

Bit 7 6 5 4 3 2 1 0Name — PRMS6 PRMS5 PRMS4 PRMS3 PRMS2 PRMS1 PRMS0R/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 PRMS6:UARTpin-remappingselection

0:TXonPB4,RXonPC3(default)1:TXonPE5,RXonPE4

Bit5 PRMS5:INT1pin-remappingselection0:INT1onPD0(default)1:INT1onPD5

Bit4 PRMS4:INT0pin-remappingselection0:INT0onPF1(default)1:INT0onPF2

Bit3 PRMS3:STM1pin-remappingselection0:STP1onPB5,STP1IonPB7,STCK1onPE7(default)1:STP1onPE3,STP1IonPA7,STCK1onPE5

Bit2 PRMS2:PTMpin-remappingselection0:PTPonPE2,PTPIonPB6,PTCKonPC3(default)1:PTPonPD1,PTPIonPD4,PTCKonPD2

Bit1 PRMS1:STM0pin-remappingselection0:STP0onPC2,STP0IonPA5,STCK0onPA6(default)1:STP0onPD3,STP0IonPD6,STCK0onPE4

Bit0 PRMS0:SCOMpin-remappingselection0:SCOM3onPC7,SCOM2onPC6,SCOM1onPC5,SCOM0onPC4(default)1:SCOM3onPD3,SCOM2onPD2,SCOM1onPD1,SCOM0onPD0

I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.

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Generic Input/Output Structure

Rev. 1.20 66 ��st 2�� 201� Rev. 1.20 6� ��st 2�� 201�



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A/D Input/Output Structure

Programming Considerations Withintheuserprogram,oneofthefirstthingstoconsiderisportinitialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoaninputstate, thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregisters,PAC~PFC,arethenprogrammedtosetupsomepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregisters,PA~PF,arefirstprogrammed.Selectingwhichpinsare inputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrolregisterorbyprogrammingindividualbits intheportcontrolregisterusingthe“SET[m].i”and“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.

Thepower-onresetconditionof theA/Dconvertercontrolregistersensures thatanyA/Dinputpins,whicharealwayssharedwithotherI/Ofunctions,willbesetupasanaloginputsafterareset.AlthoughthesepinswillbeconfiguredasA/Dinputsafterareset, theA/Dconverterwillnotbeswitchedon.It is thereforeimportant tonotethat if it isrequiredtousethesepinsasI/Odigitalinputpinsorasotherfunctions,theA/DconvertercontrolregistersmustbecorrectlyprogrammedtoremovetheA/Dfunction.Notealsothatas theA/Dchannelisenabled,anyinternalpull-highresistorconnectionswillberemoved.

PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.

Rev. 1.20 66 ��st 2�� 201� Rev. 1.20 6� ��st 2�� 201�



Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasuretime.Toimplement timerelatedfunctionseachdeviceincludesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.

ThecommonfeaturesofthedifferentTMtypesaredescribedherewithmoredetailedinformationprovidedintheindividualStandardandPeriodicTMsections.

IntroductionThedevicecontainsthreeTMsandeachindividualTMcanbecategorisedasacertaintype,namelyStandardTypeTMorPeriodicTypeTM.Althoughsimilarinnature,thedifferentTMtypesvaryintheirfeaturecomplexity.ThecommonfeaturestotheStandardandPeriodicTMswillbedescribedin thissectionand thedetailedoperation regardingeachof theTMtypeswillbedescribed inseparatesections.ThemainfeaturesanddifferencesbetweenthetwotypesofTMsaresummarisedintheaccompanyingtable.

Function STM PTMTimer/Co�nter √ √I/P Capt�re √ √Compare Match O�tp�t √ √PWM Channels 1 1Sin�le P�lse O�tp�t 1 1PWM �li�nment Ed�e Ed�ePWM �dj�stment Period & D�ty D�ty or Period D�ty or Period

STM PTM16-bit STM0 16-bit STM1 10-bit PTM

TM Name/Type Reference

TM OperationThetwodifferent typesofTMofferadiverserangeoffunctions,fromsimpletimingoperationstoPWMsignalgeneration.ThekeytounderstandinghowtheTMoperatesistoseeitintermsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.

Rev. 1.20 68 ��st 2�� 201� Rev. 1.20 6� ��st 2�� 201�



TM Clock SourceTheclocksourcewhichdrivesthemaincounterineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingthexTnCK2~xTnCK0bitsintheTMcontrolregisters.TheclocksourcecanbearatioofthesystemclockfSYSortheinternalhighclockfH,thefSUBclocksourceortheexternalxTCKnpin.Notethatsettingthesebitstothevalue101willselectareservedclockinput, ineffectdisconnectingtheTMclocksource.ThexTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.

TM InterruptsTheStandardTypeandPeriodicTypeTMseachhavetwointernalinterrupts,oneforeachoftheinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerateditcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.

TM External Pins Eachof theTMs, irrespectiveofwhat type,hasoneTMinputpin,with the labelxTCKn.ThexTMn,xTCKn inputpin isessentiallyaclocksource for thexTMnand is selectedusing thexTnCK2~xTnCK0bitsinthexTMnC0register.ThisexternalTMinputpinallowsanexternalclocksourcetodrivetheinternalTM.ThexTCKninputpincanbechosentohaveeitherarisingorfallingactiveedge.TheSTCKnandPTCKpinsarealsousedastheexternal trigger inputpininsinglepulseoutputmodefortheSTMnandPTMrespectively.

TheotherxTMninputpin,xTPnI, is thecaptureinputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingthexTnIO1~xTnIO0bitsinthexTMnC1registerrespectively.Thereisanothercaptureinput,PTCK,forPTMcaptureinputmode,whichcanbeusedastheexternaltriggerinputsourceexceptthePTPIpin.

TheTMseachhaveoneoutputpinwiththelabelxTPn.WhentheTMis intheCompareMatchOutputMode,thesepinscanbecontrolledbytheTMtoswitchtoahighorlowlevelortotogglewhenacomparematchsituationoccurs.TheexternalxTPnoutputpin isalso thepinwhere theTMgeneratesthePWMoutputwaveform.ThexTPnpinactsasaninputwhentheTMissetuptooperateintheCaptureInputMode.AsthexTPnpinsarepin-sharedwithotherfunctions,thexTPnpinfunctionisenabledordisabledaccordingtotheinternalTMon/offcontrol,operationmodeandoutputcontrolsettings.WhenthecorrespondingTMconfigurationselectsthexTPnpintobeusedasanoutputpin,theassociatedpinwillbesetupasanexternalTMoutputpin.IftheTMconfigurationselectsthexTPnpintobesetupasaninputpin,theinputsignalsuppliedontheassociatedpincanbederivedfromanexternalsignalandotherpin-sharedoutputfunction.If theTMconfigurationdetermines that thexTPnpinfunctionisnotused, theassociatedpinwillbecontrolledbyotherpin-sharedfunctions.ThedetailsofthexTPnpinforeachTMtypeanddeviceareprovidedintheaccompanyingtable.

STM0 STM1 PTM RegisterSTCK0STP0ISTP0

STCK1STP1ISTP1

PTCKPTPIPTP

TMPC

TM External Pins

Rev. 1.20 68 ��st 2�� 201� Rev. 1.20 6� ��st 2�� 201�



TM Input/Output Pin Control RegistersSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingtherelevantpin-sharedfunctionselectionregisters,withthecorrespondingselectionbits ineachpin-sharedfunctionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.

Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0TMPC CLOP — — — — ST1CP PT0CP ST0CP

TM Pin Control Register

STM0 Pin Control

STM0

PC2/STP0

ST0CP

PC2 O�tp�t F�nction 0

1

O�tp�t

Capt�re Inp�t

P�6/STCK0TCK Inp�t

0

1

PC2

1

0

P�5/STP0I

STM0 Function Pin Control Block Diagram (PRMS1=0)

STM0

PD3/STP0

ST0CP

PD3 O�tp�t F�nction 0

1

O�tp�t

Capt�re Inp�t

PE4/STCK0TCK Inp�t

0

1

PD3

1

0

PD6/STP0I


Rev. 1.20 �0 ��st 2�� 201� Rev. 1.20 �1 ��st 2�� 201�



STM1 Pin Control

STM1

PB5/STP1

ST1CP

PB5 O�tp�t F�nction 0

1

O�tp�t

Capt�re Inp�t

PE�/STCK1TCK Inp�t

0

1

PB5

1

0

PB�/STP1I


STM1

PE3/STP1

ST1CP

PE3 O�tp�t F�nction 0

1

O�tp�t

Capt�re Inp�t

PE5/STCK1TCK Inp�t

0

1

PE3

1

0

P��/STP1I


Rev. 1.20 �0 ��st 2�� 201� Rev. 1.20 �1 ��st 2�� 201�



PTM0 Pin Control

PTM0

PE2/PTP0

PT0CP

PE2 O�tp�t F�nction 0

1

O�tp�t

Capt�re Inp�t

PT0C�PTS

PC3/PTCK0TCK Inp�t

0

1

PE2

0

1

1

0

PB6/PTP0I

PTM0 Function Pin Control Block Diagram (PRMS2=0)

PTM0

PD1/PTP0

PT0CP

PD1 O�tp�t F�nction 0

1

O�tp�t

Capt�re Inp�t

PT0C�PTS

PD2/PTCK0TCK Inp�t

0

1

PD1

0

1

1

0

PD4/PTP0I

PTM0 Function Pin Control Block Diagram (PRMS2=1)

TMPC Register

Bit 7 6 5 4 3 2 1 0Name CLOP — — — — ST1CP PTCP ST0CPR/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0

Bit7 CLOP:CLOpincontrol0:Disable1:Enable

Bit6~3 Unimplemented,readas“0”Bit2 ST1CP:STP1pincontrol

0:Disable1:Enable

Bit1 PTCP:PTPpincontrol0:Disable1:Enable

Bit0 ST0CP:STP0pincontrol0:Disable1:Enable

Rev. 1.20 �2 ��st 2�� 201� Rev. 1.20 �3 ��st 2�� 201�



Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAandCCRPregisters,beingeither10-bitor16-bit,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.

As theCCRA register andPTMCCRP registers are implemented in theway shown in thefollowingdiagramandaccessingtheregisteriscarriedoutinaspecificwaydescribedabove,itisrecommendedtousethe“MOV”instructiontoaccesstheCCRAorPTMCCRPlowbyteregister,namedxTMnALorPTMRPL,using the followingaccessprocedures.Accessing theCCRAorPTMCCRPlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.

Data B�s

8-bit B�ffer

xTMnDHxTMnDL

PTMRPHPTMRPL

xTMn�HxTMn�L

TM Co�nter Re�ister (Read only)

TM CCR� Re�ister (Read/Write)

PTM CCRP Re�ister (Read/Write)

Thefollowingstepsshowthereadandwriteprocedures:

• WritingDatatoCCRAorPTMCCRP♦ Step1.WritedatatoLowBytexTMnALorPTMRPL

– Notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighBytexTMnAHorPTMRPH

– Heredataiswrittendirectlytothehighbyteregistersandsimultaneouslydatais latchedfromthe8-bitbuffertotheLowByteregisters.

• ReadingDatafromtheCounterRegistersandCCRAorPTMCCRP♦ Step1.ReaddatafromtheHighBytexTMnDH,xTMnAHorPTMRPH

– HeredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.

♦ Step2.ReaddatafromtheLowBytexTMnDL,xTMnALorPTMRPL– Thisstepreadsdatafromthe8-bitbuffer.

Rev. 1.20 �2 ��st 2�� 201� Rev. 1.20 �3 ��st 2�� 201�



Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanalsobecontrolledwithtwoexternalinputpinandcandriveoneexternaloutputpin.

STM core STM Input Pin STM Output Pin

16-bit STM (STM0� STM1) STCK0�STP0ISTCK1�STP1I STP0� STP1

Standard TM OperationThere isa16-bitwideSTM.At thecore isa16-bitcount-upcounterwhich isdrivenbyauserselectableinternalorexternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.Thesecomparatorswillcomparethevaluein thecounterwithCCRPandCCRAregisters.TheCCRPcomparatoris8-bitwidewhosevalueiscomparedwiththehighest8bitsinthecounterwhiletheCCRAisthe16bitsandthereforecomparesallcounterbits.

Theonlywayofchanging thevalueof the16-bitcounterusing theapplicationprogram, is toclearthecounterbychangingtheSTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aSTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

fSYS

fSYS/4

fH/64fH/16

fSUB

STCKn

000001010011100101110111

STnCK2~STnCK0

16-bit Co�nt-�p Co�nter

8-bit Comparator P

CCRP

b8~b15

b0~b15

16-bit Comparator �

STnONSTnP�U

Comparator � Match

Comparator P Match

Co�nter Clear 01

O�tp�t Control

PolarityControl STPn

STnOC

STnM1� STnM0STnIO1� STnIO0

STMn�F Interr�pt

STMnPF Interr�pt

STnPOL

CCR�

STnCCLR

Ed�e Detector STPnI

STnIO1� STnIO0

fH/8

PinControl

STnCP

Standard Type TM Block Digram (n=0 or 1)

Standard Type TM Register Description OveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal16-bitCCRAvalue.Thereisalsoaread/writeregisterusedtostoretheinternal8-bitCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

Rev. 1.20 �4 ��st 2�� 201� Rev. 1.20 �5 ��st 2�� 201�



Register Name

Bit

7 6 5 4 3 2 1 0STMnC0 STnP�U STnCK2 STnCK1 STnCK0 STnON — — —STMnC1 STnM1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLRSTMnDL D� D6 D5 D4 D3 D2 D1 D0STMnDH D15 D14 D13 D12 D11 D10 D� D8STMn�L D� D6 D5 D4 D3 D2 D1 D0STMn�H D15 D14 D13 D12 D11 D10 D� D8STMnRP D� D6 D5 D4 D3 D2 D1 D0

16-bit Standard TM Registers List (n=0 or 1)

STMnC0 Register (n=0 or 1)

Bit 7 6 5 4 3 2 1 0Name STnP�U STnCK2 STnCK1 STnCK0 STnON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 STnPAU:STMnCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMnwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 STnCK2~STnCK0:SelectSTMnCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:fH/8110:STCKnrisingedgeclock111:STCKnfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 STnON:STMnCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter torun,clearingthebitdisables theSTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theSTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwill retain its residualvalue. If theSTMis in theCompareMatchOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTnOCbit,whentheSTnONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

Rev. 1.20 �4 ��st 2�� 201� Rev. 1.20 �5 ��st 2�� 201�



STMnC1 Register (n=0 or 1)

Bit 7 6 5 4 3 2 1 0Name STnM1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 STnM1~STnM0:SelectSTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodefortheSTM.ToensurereliableoperationtheSTMshouldbeswitchedoffbeforeanychangesaremade to theSTnM1andSTnM0bits.IntheTimer/CounterMode,theSTMoutputpincontrolwillbedisabled.

Bit5~4 STnIO1~STnIO0:SelectSTMexternalpin(STPnorSTPnI)functionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofSTPnI01:InputcaptureatfallingedgeofSTPnI10:Inputcaptureatfalling/risingedgeofSTPnI11:Inputcapturedisabled

Timer/CounterModeUnused

ThesetwobitsareusedtodeterminehowtheSTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheSTMisrunning.IntheCompareMatchOutputMode,theSTnIO1andSTnIO0bitsdeterminehowtheSTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheSTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheSTMoutputpinshouldbesetupusingtheSTnOCbitintheSTMnC1register.NotethattheoutputlevelrequestedbytheSTnIO1andSTnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheSTnOCbitotherwisenochangewilloccurontheSTMoutputpinwhenacomparematchoccurs.AftertheSTMoutputpinchangesstate,itcanberesettoitsinitiallevelbychangingtheleveloftheSTnONbitfromlowtohigh.In thePWMMode, theSTnIO1andSTnIO0bitsdeterminehowtheSTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits. It isnecessarytoonlychangethevaluesof theSTnIO1andSTnIO0bitsonlyafter theSTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurif theSTnIO1andSTnIO0bitsarechangedwhentheSTMisrunning.

Rev. 1.20 �6 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Bit3 STnOC:STPnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for theSTMoutputpin. ItsoperationdependsuponwhetherSTMisbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogicleveloftheSTMoutputpinbeforeacomparematchoccurs.In thePWMMode/SinglePulseOutputModeitdeterminesifthePWMsignalisactivehighoractivelow.

Bit2 STnPOL:STPnOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityoftheSTPnoutputpin.WhenthebitissethightheSTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheSTMisintheTimer/CounterMode.

Bit1 STnDPX:STMnPWMperiod/dutyControl0:CCRP-period;CCRA-duty1:CCRP-duty;CCRA-period

Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.

Bit0 STnCCLR:SelectSTMnCounterclearcondition0:STMnComparatrorPmatch1:STMnComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththeSTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheSTnCCLRbitisnotusedinthePWMOutput,SinglePulseOutputorCaptureInputMode.

Rev. 1.20 �6 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



STMnDL Register (n=0 or 1)

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D2 D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D7~D0:STMnCounterLowByteRegisterbit7~bit0STMn16-bitCounterbit7~bit0

STMnDH Register (n=0 or 1)

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D12 D11 D10 D� D8R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:STMnCounterHighByteRegisterbit7~bit0STMn16-bitCounterbit15~bit8

STMnAL Register (n=0 or 1)


Bit7~0 D7~D0:STMnCCRALowByteRegisterbit7~bit0STMn16-bitCCRAbit7~bit0

STMnAH Register (n=0 or 1)

Bit 7 6 5 4 3 2 1 0Name D15 D14 D13 D12 D11 D10 D� D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~0 D15~D8:STMnCCRAHighByteRegisterbit7~bit0STMn16-bitCCRAbit15~bit8

STMnRP Register (n=0 or 1)


Bit7~0 D7~D0:STMnCCRP8-bitRegister,comparedwiththeSTMnCounterbit15~bit8.ComparatorPMatchPeriod0:65536STMnclocks1~255:256×(1~255)STMnclocks

TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheSTnCCLRbitissettozero.SettingtheSTnCCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.

Rev. 1.20 �8 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Standard Type TM Operating Modes TheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheSTnM1andSTnM0bitsintheSTMnC1register.

Compare Match Output Mode To select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheSTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMnAFandSTMnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IftheSTnCCLRbitintheSTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly theSTMnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenSTnCCLRishighnoSTMnPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameofthemodesuggests,afteracomparisonismade,theSTMoutputpin,willchangestate.TheSTMoutputpinconditionhoweveronlychangesstatewhenaSTMnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheSTMoutputpin.ThewayinwhichtheSTMoutputpinchangesstatearedeterminedbytheconditionoftheSTnIO1andSTnIO0bitsintheSTMnC1register.TheSTMoutputpincanbeselectedusingtheSTnIO1andSTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheSTMoutputpin,whichissetupaftertheSTnONbitchangesfromlowtohigh,issetupusingtheSTnOCbit.NotethatiftheSTnIO1andSTnIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.20 �8 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Co�nter Val�e

0xFFFF

CCRP

CCR�

STnON

STnP�U

STnPOL

CCRP Int. fla� STMnPF

CCR� Int. fla� STMn�F

STMn O/P Pin

Time

CCRP=0

CCRP > 0

Co�nter overflowCCRP > 0Co�nter cleared by CCRP val�e

Pa�se

Res�me

Stop

Co�nter Restart

STnCCLR = 0; STnM [1:0] = 00

O�tp�t pin set to initial Level Low if STnOC=0

O�tp�t To��le with STMn�F fla�

Note STnIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere STnIO [1:0] = 11

To��le O�tp�t select

O�tp�t not affected by STMn�F fla�. Remains Hi�h �ntil reset by STnON bit

O�tp�t PinReset to Initial val�e

O�tp�t controlled by other pin-shared f�nction

O�tp�t Invertswhen STnPOL is hi�h

Compare Match Output Mode – STnCCLR=0 Note:1.WithSTnCCLR=0aComparatorPmatchwillclearthecounter

2.TheSTMoutputpiniscontrolledonlybytheSTMnAFflag3.TheoutputpinisresettoitsinitialstatebyaSTnONbitrisingedge4.n=0or1

Rev. 1.20 80 ��st 2�� 201� Rev. 1.20 81 ��st 2�� 201�



Co�nter Val�e

0xFFFF

CCRP

CCR�

STnON

STnP�U

STnPOL



STMn O/P Pin

Time

CCR�=0

CCR� = 0Co�nter overflowCCR� > 0 Co�nter cleared by CCR� val�e

Pa�se

Res�me

Stop Co�nter Restart

STnCCLR = 1; STnM [1:0] = 00

O�tp�t pin set to initial Level Low if STnOC=0

O�tp�t To��le with STMn�F fla�

Note STnIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere STnIO [1:0] = 11


O�tp�t not affected by STMn�F fla�. Remains Hi�h �ntil reset by STnON bit



O�tp�t Invertswhen STnPOL is hi�h

STMnPF not �enerated

No STMn�F fla� �enerated on CCR� overflow

O�tp�t does not chan�e

Compare Match Output Mode – STnCCLR=1 Note:1.WithSTnCCLR=1aComparatorAmatchwillclearthecounter

2.TheSTMoutputpiniscontrolledonlybytheSTMnAFflag3.TheoutputpinisresettoitsinitialstatebyaSTnONbitrisingedge4.ASTMnPFflagisnotgeneratedwhenSTnCCLR=15.n=0or1

Rev. 1.20 80 ��st 2�� 201� Rev. 1.20 81 ��st 2�� 201�



Timer/Counter Mode To select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheSTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheSTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output Mode Toselectthismode,bitsSTnM1andSTnM0intheSTMnC1registershouldbesetto10respectivelyandalsotheSTnIO1andSTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithintheSTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheSTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMmode,theSTnCCLRbithasnoeffectasthePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.WhichregisterisusedtocontroleitherfrequencyordutycycleisdeterminedusingtheSTnDPXbitintheSTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheSTnOCbitintheSTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoSTnIO1andSTnIO0bitsareusedtoenablethePWMoutputortoforcetheSTMoutputpintoafixedhighorlowlevel.TheSTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 16-bit STM, PWM Mode, Edge-aligned Mode, STnDPX=0

CCRP 1~255 0Period CCRP×256 65536D�ty CCR�

IffSYS=16MHz,STMclocksourceselectfSYS/4,CCRP=2andCCRA=128,

TheSTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,duty=128/(2×256)=25%.

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

• 16-bit STM, PWM Mode, Edge-aligned Mode, STnDPX=1

CCRP 1~255 0Period CCR�D�ty CCRP×256 65536

ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMclockwhilethePWMdutycycleisdefinedbythe(CCRP×256)exceptwhentheCCRPvalueisequalto000b.

Rev. 1.20 82 ��st 2�� 201� Rev. 1.20 83 ��st 2�� 201�



Co�nter Val�e

CCRP

CCR�

STnON

STnP�U

STnPOL



STMn O/P Pin(STnOC=1)

Time

Co�nter cleared by CCRP

Pa�se Res�me Co�nter Stop if STnON bit low

Co�nter Reset when STnON ret�rns hi�h

STnDPX = 0; STnM [1:0] = 10

PWM D�ty Cycle set by CCR�

PWM res�mes operation

O�tp�t controlled by other pin-shared f�nction O�tp�t Inverts

when STnPOL = 1PWM Period set by CCRP


PWM Mode – STnDPX=0 Note:1.HereSTnDPX=0–CounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenSTnIO[1:0]=00or014.TheSTnCCLRbithasnoinfluenceonPWMoperation5.n=0or1

Rev. 1.20 82 ��st 2�� 201� Rev. 1.20 83 ��st 2�� 201�



Co�nter Val�e

CCRP

CCR�

STnON

STnP�U

STnPOL



STMn O/P Pin (STnOC=1)

Time

Co�nter cleared by CCR�

Pa�se Res�me Co�nter Stop if STnON bit low

STnDPX = 1; STnM [1:0] = 10

PWM D�ty Cycle set by CCRP



when STnPOL = 1PWM Period set by CCR�

STMn O/P Pin (STnOC=0)


PWM Mode – STnDPX=1 Note:1.HereSTnDPX=1–CounterclearedbyCCRA

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenSTnIO[1:0]=00or014.TheSTnCCLRbithasnoinfluenceonPWMoperation5.n=0or1

Rev. 1.20 84 ��st 2�� 201� Rev. 1.20 85 ��st 2�� 201�



Single Pulse Output Mode To select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 10respectivelyandalsotheSTnIO1andSTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheSTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheSTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theSTnONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalSTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhentheSTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheSTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheSTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

STnON bit0 1

S/W Command SET“STnON”

orSTCKn Pin

Transition

STnON bit1 0

CCR� Trailin� Ed�e

S/W Command CLR“STnON”

orCCR� Compare Match

STPn O�tp�t Pin

P�lse Width = CCR� Val�e

CCR�Leadin� Ed�e

Single Pulse Generation (n=0 or 1)

HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheSTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaSTMinterrupt.ThecountercanonlyberesetbacktozerowhentheSTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheSTnCCLRandSTnDPXbitsarenotusedinthisMode.

Rev. 1.20 84 ��st 2�� 201� Rev. 1.20 85 ��st 2�� 201�



Co�nter Val�e

CCRP

CCR�

STnON

STnP�U

STnPOL

CCRP Int. Fla� STMnPF

CCR� Int. Fla� STMn�F


Time

Co�nter stopped by CCR�

Pa�seRes�me Co�nter Stops

by software


STnM [1:0] = 10 ; STnIO [1:0] = 11

P�lse Width set by CCR�

O�tp�t Invertswhen STnPOL = 1

No CCRP Interr�pts �enerated


STCKn pin

Software Tri��er

Cleared by CCR� match

STCKn pin Tri��er

��to. set by STCKn pin


Software Clear

Software Tri��erSoftware

Tri��er

Single Pulse Mode Note:1.CounterstoppedbyCCRA

2.CCRPisnotused3.ThepulseistriggeredbytheSTCKnpinorbysettingtheSTnONbithigh4.ASTCKnpinactiveedgewillautomaticallysettheSTnONbithigh5.IntheSinglePulseMode,STnIO[1:0]mustbesetto“11”andcannotbechanged.6.n=0or1

Rev. 1.20 86 ��st 2�� 201� Rev. 1.20 8� ��st 2�� 201�



Capture Input Mode ToselectthismodebitsSTnM1andSTnM0intheSTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheSTPnIpin,whoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheSTnIO1andSTnIO0bitsintheSTMnC1register.ThecounterisstartedwhentheSTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.

WhentherequirededgetransitionappearsontheSTPnIpinthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaSTMinterruptgenerated.IrrespectiveofwhateventsoccurontheSTPnIpinthecounterwillcontinuetofreerununtil theSTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aSTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheSTnIO1andSTnIO0bitscanselecttheactivetriggeredgeontheSTPnIpintobearisingedge,fallingedgeorbothedgetypes.IftheSTnIO1andSTnIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensontheSTPnIpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AstheSTPnIpinispinsharedwithotherfunctions,caremustbetakeniftheSTMisintheInputCaptureMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.TheSTnCCLRandSTnDPXbitsarenotusedinthisMode.

Rev. 1.20 86 ��st 2�� 201� Rev. 1.20 8� ��st 2�� 201�



Co�nter Val�e

YY

CCRP

STnON

STnP�U

CCRP Int. Fla� STMnPF

CCR� Int. Fla� STMn�F

CCR� Val�e

Time


Pa�seRes�me

Co�nter Reset

STnM [1:0] = 01

STMn capt�re pin STPnI

XX

Co�nter Stop

STnIO [1:0] Val�e

XX YY XX YY

�ctive ed�e �ctive

ed�e�ctive ed�e

00 – Risin� ed�e 01 – Fallin� ed�e 10 – Both ed�es 11 – Disable Capt�re

Capture Input Mode Note:1.STnM[1:0]=01andactiveedgesetbytheSTnIO[1:0]bits

2.ASTMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.STnCCLRbitnotused4.Nooutputfunction–STnOCandSTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.

6.n=0or1

Rev. 1.20 88 ��st 2�� 201� Rev. 1.20 8� ��st 2�� 201�



Periodic Type TM – PTMThePeriodicTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.ThePeriodicTMcanalsobecontrolledwithtwoexternalinputpinandcandriveoneexternaloutputpin.

PTM core PTM Input Pin PTM Output Pin10-bit PTM PTCK� PTPI PTP

Periodic TM OperationAtitscoreisa10-bitcount-upcounterwhichisdrivenbyauserselectableinternalorexternalclocksource.Therearetwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwiththeCCRAandCCRPregisters.

Theonlywayofchanging thevalueof the10-bitcounterusing theapplicationprogram, is toclear thecounterbychangingthePTONbit fromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aPTMinterruptsignalwillalsousuallybegenerated.ThePeriodicTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesincludinganinputpinandcanalsocontroltheoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.

fSYS

fSYS/4

fH/64fH/16

fSUB

PTCK

000001010011100101110111

PTCK2~PTCK0

10-bit Co�nt-�p Co�nter

10-bit Comparator P

CCRP

b0~b�

b0~b�

10-bit Comparator �

PTONPTP�U

Comparator � Match

Comparator P Match

Co�nter Clear 01

O�tp�tControl

Polarity Control

Pin Control PTP

PTOC

PTM1� PTM0PTIO1� PTIO0

PTM�F Interr�pt

PTMPF Interr�pt

PTPOL PTCP

CCR�

PTCCLR

Ed�eDetector

PTPI

PTIO1� PTIO0

fH

10

PTC�PTS

Periodic Type TM Block Diagram

Periodic Type TM Register DescriptionOveralloperationofthePeriodicTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitvalue,whiletworead/writeregisterpairsexisttostoretheinternal10-bitCCRAandCCRPvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.

Rev. 1.20 88 ��st 2�� 201� Rev. 1.20 8� ��st 2�� 201�



Register Name

Bit

7 6 5 4 3 2 1 0PTMC0 PTP�U PTCK2 PTCK1 PTCK0 PTON — — —PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTC�PTS PTCCLRPTMDL D� D6 D5 D4 D3 D2 D1 D0PTMDH — — — — — — D� D8PTM�L D� D6 D5 D4 D3 D2 D1 D0PTM�H — — — — — — D� D8PTMRPL D� D6 D5 D4 D3 D2 D1 D0PTMRPH — — — — — — D� D8

10-bit Periodic TM Registers List

PTMC0 Register

Bit 7 6 5 4 3 2 1 0Name PTP�U PTCK2 PTCK1 PTCK0 PTON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —

Bit7 PTPAU:PTMCounterPauseControl0:Run1:Pause

Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditionthePTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.

Bit6~4 PTCK2~PTCK0:SelectPTMCounterclock000:fSYS/4001:fSYS

010:fH/16011:fH/64100:fSUB

101:fH

110:PTCKrisingedgeclock111:PTCKfallingedgeclock

ThesethreebitsareusedtoselecttheclocksourceforthePTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.

Bit3 PTON:PTMCounterOn/OffControl0:Off1:On

Thisbitcontrolstheoverallon/offfunctionofthePTM.Settingthebithighenablesthecounter torun,clearingthebitdisables thePTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff thePTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.If thePTMis in theCompareMatchOutputMode then thePTMoutputpinwillbereset to its initialcondition,asspecifiedbythePTOCbit, ,whenthePTONbitchangesfromlowtohigh.

Bit2~0 Unimplemented,readas“0”

Rev. 1.20 �0 ��st 2�� 201� Rev. 1.20 �1 ��st 2�� 201�



PTMC1 Register

Bit 7 6 5 4 3 2 1 0Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTC�PTS PTCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 PTM1~PTM0:SelectPTMOperationMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMModeorSinglePulseOutputMode11:Timer/CounterMode

ThesebitssetuptherequiredoperatingmodeforthePTM.ToensurereliableoperationthePTMshouldbeswitchedoffbeforeanychangesaremadetothePTM1andPTM0bits.IntheTimer/CounterMode,thePTMoutputpincontrolmustbedisabled.

Bit5~4 PTIO1~PTIO0:SelectPTMexternalpinPTP,PTCKorPTPIfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput

PWMMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput

CaptureInputMode00:InputcaptureatrisingedgeofPTCKorPTPI01:InputcaptureatfallingedgeofPTCKorPTPI10:Inputcaptureatfalling/risingedgeofPTCKorPTPI11:Inputcapturedisabled

Timer/counterModeUnused

ThesetwobitsareusedtodeterminehowthePTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodethePTMisrunning.IntheCompareMatchOutputMode,thePTIO1andPTIO0bitsdeterminehowthePTMoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.ThePTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.Whenthesebitsarebothzero,thennochangewilltakeplaceontheoutput.TheinitialvalueofthePTMoutputpinshouldbesetupusingthePTOCbit.NotethattheoutputlevelrequestedbythePTIO1andPTIO0bitsmustbedifferentfromtheinitialvaluesetupusingthePTOCbitotherwisenochangewilloccuron thePTMoutputpinwhenacomparematchoccurs.AfterthePTMoutputpinchangesstate, itcanberesettoits initial levelbychangingthelevelofthePTONbitfromlowtohigh.InthePWMMode, thePTIO1andPTIO0bitsdeterminehowthePTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesofthePTIO1andPTIO0bitsonlyafterthePTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccurifthePTIO1andPTIO0bitsarechangedwhenthePTMisrunning.

Rev. 1.20 �0 ��st 2�� 201� Rev. 1.20 �1 ��st 2�� 201�



Bit3 PTOC:PTPOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh

PWMMode/SinglePulseOutputMode0:Activelow1:Activehigh

This is theoutputcontrolbit for thePTMoutputpin. ItsoperationdependsuponwhetherPTMisbeingused in theCompareMatchOutputModeor in thePWMMode/SinglePulseOutputMode.IthasnoeffectifthePTMisintheTimer/CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelofthePTMoutputpinbeforeacomparematchoccurs. In thePWMModeitdetermines if thePWMsignalisactivehighoractivelow.

Bit2 PTPOL:PTPOutputpolarityControl0:Non-invert1:Invert

ThisbitcontrolsthepolarityofthePTPoutputpin.WhenthebitissethighthePTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectifthePTMisintheTimer/CounterMode.

Bit1 PTCAPTS:PTMcapturetriggersourceselect0:FromPTPIpin1:FromPTCKpin

Bit0 PTCCLR:SelectPTMCounterclearcondition0:PTMComparatrorPmatch1:PTMComparatrorAmatch

Thisbit isused toselect themethodwhichclears thecounter.Remember that thePeriodicTMcontains twocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtoclear theinternalcounter.With thePTCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.ThePTCCLRbitisnotusedinthePWMOutput,SinglePulseOutputorCaptureInputMode.

PTMDL Register

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D2 D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0

Bit7~0 PTMDL:PTMCounterLowByteRegisterbit7~bit0PTM10-bitCounterbit7~bit0

PTMDH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D� D8R/W — — — — — — R RPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 PTMDH:PTMCounterHighByteRegisterbit1~bit0

PTM10-bitCounterbit9~bit8

Rev. 1.20 �2 ��st 2�� 201� Rev. 1.20 �3 ��st 2�� 201�



PTMAL Register


Bit7~0 PTMAL:PTMCCRALowByteRegisterbit7~bit0PTM10-bitCCRAbit7~bit0

PTMAH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 PTMAH:PTMCCRAHighByteRegisterbit1~bit0

PTM10-bitCCRAbit9~bit8

PTMRPL Register


Bit7~0 PTMRPL:PTMCCRPLowByteRegisterbit7~bit0PTM10-bitCCRPbit7~bit0

PTMRPH Register

Bit 7 6 5 4 3 2 1 0Name — — — — — — D� D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0

Bit7~2 Unimplemented,readas“0”Bit1~0 PTMRPH:PTMCCRPHighByteRegisterbit1~bit0

PTM10-bitCCRPbit9~bit8

Rev. 1.20 �2 ��st 2�� 201� Rev. 1.20 �3 ��st 2�� 201�



Periodic Type TM Operating ModesThePeriodicTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingthePTM1andPTM0bitsinthePTMC1register.

Compare Match Output ModeToselect thismode,bitsPTM1andPTM0in thePTMC1register, shouldbeallcleared to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhenthePTCCLRbit is low, thereare twoways inwhichthecountercanbecleared.OneiswhenacomparematchoccursfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HereboththePTMAFandPTMPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.

IfthePTCCLRbitinthePTMC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonlythePTMAFinterruptrequestflagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenPTCCLRishighnoPTMPFinterruptrequestflagwillbegenerated.IntheCompareMatchOutputMode,theCCRAcannotbesetto“0”.

Asthenameofthemodesuggests,afteracomparisonismade,thePTMoutputpin,willchangestate.ThePTMoutputpinconditionhoweveronlychangesstatewhenaPTMAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.ThePTMPFinterruptrequestflag,generatedfromacomparematchfromComparatorP,willhavenoeffectonthePTMoutputpin.ThewayinwhichthePTMoutputpinchangesstatearedeterminedbytheconditionof thePTIO1andPTIO0bitsinthePTMC1register.ThePTMoutputpincanbeselectedusingthePTIO1andPTIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.Theinitialconditionof thePTMoutputpin,whichissetupafter thePTONbitchangesfromlowtohigh,issetupusingthePTOCbit.NotethatifthePTIO1,PTIO0bitsarezerothennopinchangewilltakeplace.

Rev. 1.20 �4 ��st 2�� 201� Rev. 1.20 �5 ��st 2�� 201�



Co�nter Val�e

0x3FF

CCRP

CCR�

PTON

PTP�U

PTPOL

CCRP Int. Fla� PTMPF

CCR� Int. Fla� PTM�F

PTM O/P Pin

Time

CCRP=0

CCRP > 0

Co�nter overflowCCRP > 0Co�nter cleared by CCRP val�e

Pa�se

Res�me

Stop

Co�nter Restart

PTCCLR = 0; PTM [1:0] = 00

O�tp�t pin set to initial Level Low if PTOC=0

O�tp�t To��le with PTM�F fla�

Note PTIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere PTIO [1:0] = 11


O�tp�t not affected by PTM�F fla�. Remains Hi�h �ntil reset by PTON bit



O�tp�t Invertswhen PTPOL is hi�h

Compare Match Output Mode – PTCCLR=0 Note:1.WithPTCCLR=0–aComparatorPmatchwillclearthecounter

2.ThePTMoutputpiniscontrolledonlybythePTMAFflag3.TheoutputpinisresettoinitialstatebyaPTONbitrisingedge

Rev. 1.20 �4 ��st 2�� 201� Rev. 1.20 �5 ��st 2�� 201�



Co�nter Val�e

0x3FF

CCRP

CCR�

PTON

PTP�U

PTPOL



PTM O/P Pin

Time

CCR�=0

CCR� = 0Co�nter overflowCCR� > 0 Co�nter cleared by CCR� val�e

Pa�se

Res�me

Stop Co�nter Restart

PTCCLR = 1; PTM [1:0] = 00

O�tp�t pin set to initial Level Low if PTOC=0

O�tp�t To��le with PTM�F fla�

Note PTIO [1:0] = 10 �ctive Hi�h O�tp�t selectHere PTIO [1:0] = 11


O�tp�t not affected by PTM�F fla�. Remains Hi�h �ntil reset by PTON bit



O�tp�t Invertswhen PTPOL is hi�h

PTMPF not �enerated

No PTM�F fla� �enerated on CCR� overflow

O�tp�t does not chan�e

Compare Match Output Mode – PTCCLR=1Note:1.WithPTCCLR=1–aComparatorAmatchwillclearthecounter

2.ThePTMoutputpiniscontrolledonlybythePTMAFflag3.TheoutputpinisresettoinitialstatebyaPTONrisingedge4.ThePTMPFflagisnotgeneratedwhenPTCCLR=1

Rev. 1.20 �6 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Timer/Counter ModeTo select thismode, bitsPTM1andPTM0 in thePTMC1 register should all be set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModethePTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AsthePTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction.

PWM Output ModeToselectthismode,bitsPTM1andPTM0inthePTMC1registershouldbesetto10respectivelyandalso thePTIO1andPTIO0bitsshouldbeset to10respectively.ThePWMfunctionwithinthePTMisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleonthePTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.

AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.In thePWMmode, thePTCCLRbithasnoeffectas thePWMperiod.BothoftheCCRPandCCRAregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrolthedutycycle.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.

Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.ThePTOCbitinthePTMC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoPTIO1andPTIO0bitsareusedtoenablethePWMoutputortoforcethePTMoutputpintoafixedhighorlowlevel.ThePTPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.

• 10-bit PTM, PWM Mode

CCRP 1~1023 0Period 1~1023 1024D�ty CCR�

IffSYS=16MHz,PTMclocksourceselectfSYS/4,CCRP=512andCCRA=128,

ThePTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz,duty=128/512=25%,

IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.

Rev. 1.20 �6 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Co�nter Val�e

CCRP

CCR�

PTON

PTP�U

PTPOL



PTM O/P Pin(PTOC=1)

Time


Pa�se Res�me Co�nter Stop if PTON bit low

Co�nter Reset when PTON ret�rns hi�h

PTM [1:0] = 10

PWM D�ty Cycle set by CCR�



When PTPOL = 1PWM Period set by CCRP

PTM O/P Pin(PTOC=0)

PWM Mode Note:1.HereCounterclearedbyCCRP

2.AcounterclearsetsthePWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenPTIO[1:0]=00or014.ThePTCCLRbithasnoinfluenceonPWMoperation

Rev. 1.20 �8 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Single Pulse Output ModeToselectthismode,therequiredbitpairs,PTM1andPTM0shouldbesetto10respectivelyandalsothecorrespondingPTIO1andPTIO0bitsshouldbeset to11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseonthePTMoutputpin.

ThetriggerforthepulseoutputleadingedgeisalowtohightransitionofthePTONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,thePTONbitcanalsobemadetoautomaticallychangefromlowtohighusingtheexternalPTCKpin,whichwillinturninitiatetheSinglePulseoutput.WhenthePTONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.ThePTONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhenthePTONbit isclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.

HoweveracomparematchfromComparatorAwillalsoautomaticallyclearthePTONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogeneratePTMinterrupts.Thecountercanonlyberesetback tozerowhen thePTONbitchangesfromlowtohighwhen thecounterrestarts.IntheSinglePulseModeCCRPisnotused.ThePTCCLRbitisalsonotused.

PTON bit0 1

S/W Command SET“PTON”

orPTCK Pin Transition

PTON bit1 0

CCR�Trailin� Ed�e

S/W Command CLR“PTON”

orCCR� Compare Match

PTP O�tp�t Pin

P�lse Width = CCR� Val�e

CCR� Leadin� Ed�e

Single Pulse Generation

Rev. 1.20 �8 ��st 2�� 201� Rev. 1.20 �� st 2�� 201�



Co�nter Val�e

CCRP

CCR�

PTON

PTP�U

PTPOL



PTM O/P Pin(PTOC=1)

Time

Co�nter stopped by CCR�

Pa�seRes�me Co�nter Stops

by software

Co�nter Reset when PTON ret�rns hi�h

PTM [1:0] = 10 ; PTIO [1:0] = 11

P�lse Width set by CCR�

O�tp�t Invertswhen PTPOL = 1

No CCRP Interr�pts �enerated

PTM O/P Pin(PTOC=0)

PTCK pin


Cleared by CCR� match

PTCK pin Tri��er

��to. set by PTCK pin


Software Clear

Software Tri��erSoftware

Tri��er

Single Pulse Mode Note:1.CounterstoppedbyCCRA

2.CCRPisnotused3.ThepulseistriggeredbythePTCKpinorbysettingthePTONbithigh4.APTCKpinactiveedgewillautomaticallysetthePTONbithigh5.IntheSinglePulseMode,PTIO[1:0]mustbesetto“11”andcannotbechanged.

Rev. 1.20 100 ��st 2�� 201� Rev. 1.20 101 ��st 2�� 201�



Capture Input ModeToselectthismodebitsPTM1andPTM0inthePTMC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedonthePTPIorPTCKpin,selectedbythePTCAPTSbitinthePTMC0register.Theinputpinactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingthePTIO1andPTIO0bitsinthePTMC1register.ThecounterisstartedwhenthePTONbitchangesfromlowtohighwhich is initiatedusing theapplicationprogram.

WhentherequirededgetransitionappearsonthePTPIorPTCKpinthepresentvalueinthecounterwillbelatchedintotheCCRAregisterandaPTMinterruptgenerated.IrrespectiveofwhateventsoccuronthePTPIorPTCKpinthecounterwillcontinuetofreerununtil thePTONbitchangesfromhightolow.WhenaCCRPcomparematchoccursthecounterwillresetbacktozero;inthiswaytheCCRPvaluecanbeusedtocontrolthemaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aPTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.ThePTIO1andPTIO0bitscanselecttheactivetriggeredgeonthePTPIorPTCKpintobearisingedge,fallingedgeorbothedgetypes.IfthePTIO1andPTIO0bitsarebothsethigh,thennocaptureoperationwilltakeplaceirrespectiveofwhathappensonthePTPIorPTCKpin,howeveritmustbenotedthatthecounterwillcontinuetorun.

AsthePTPIorPTCKpinispinsharedwithotherfunctions,caremustbetakenifthePTMisintheCaptureInputMode.Thisisbecauseifthepinissetupasanoutput,thenanytransitionsonthispinmaycauseaninputcaptureoperationtobeexecuted.ThePTCCLR,PTOCandPTPOLbitsarenotusedinthisMode.

Rev. 1.20 100 ��st 2�� 201� Rev. 1.20 101 ��st 2�� 201�



Co�nter Val�e

YY

CCRP

PTON

PTP�U



CCR� Val�e

Time


Pa�seRes�me

Co�nter Reset

PTM [1:0] = 01

PTM capt�re pinPTPI or PTCK

XX

Co�nter Stop

PTIO [1:0] Val�e

XX YY XX YY

�ctive ed�e �ctive

ed�e�ctive ed�e

00 – Risin� ed�e 01 – Fallin� ed�e 10 – Both ed�es 11 – Disable Capt�re

Capture Input ModeNote:1.PTM[1:0]=01andactiveedgesetbythePTIO[1:0]bits

2.APTMCaptureinputpinactiveedgetransferscountervaluetoCCRA3.ThePTCCLRbitisnotused4.Nooutputfunction–PTOCandPTPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero

Rev. 1.20 102 ��st 2�� 201� Rev. 1.20 103 ��st 2�� 201�



Analog to Digital Converter – ADCTheneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.

A/D OverviewThedevicecontainsamulti-channelanalog todigital converterwhichcandirectly interfacetoexternalanalogsignals, suchas that fromsensorsorothercontrolsignalsandconvert thesesignalsdirectlyintoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSAINS2~SAINS0bitstogetherwiththeSACS2~SACS0bits.Notethatwhentheexternalandinternalanalogsignalsaresimultaneouslyselectedtobeconverted,theinternalanalogsignalwillhavethepriority.Inthemeantimetheexternalanalogsignalwilltemporarilybeswitchedoffuntil the internalanalogsignal isdeselected.Moredetailed informationabout theA/Dinputsignal isdescribedin the“A/DConverterControlRegisters”and“A/DConverterInputSignal”sectionsrespectively.

External Input Channel Internal Analog Signals A/D Signal Select Bits�N0~�N� VDD� VDD/2� VDD/4� VR� VR/2� VR/4 S�INS2~S�INS0; S�CS2~S�CS0

TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.

�CE�~�CE0 S�CS2~S�CS0

S�INS2~S�INS0

�/D Converter

ST�RT �DBZ EN�DC

VSS

�/D Clock

÷ 2N

(N=0~�)

fSYS

S�CKS2~S�CKS0

VDD

EN�DC

S�DOL

S�DOH

�N0

�N1

�N� �/D Reference Volta�e

�/D DataRe�isters

VDD

VDD/2VDD/4VR

VR/2VR/4

�DRFS

OP�(Gain=1~4)

VRI

VREFI

VBG (1.04V)

S�VRS3~S�VRS0

ENOP�

VREF

VR

VDD

VREFPS

VREFIPS

A/D Converter Structure

Rev. 1.20 102 ��st 2�� 201� Rev. 1.20 103 ��st 2�� 201�



A/D Converter Register DescriptionOveralloperationof theA/Dconverteriscontrolledusingsixregisters.AreadonlyregisterpairexiststostoretheADCdata12-bitvalue.Oneregister,ACERL,isusedtoconfiguretheexternalanalog inputpin function.The remaining three registersarecontrol registerswhichsetup theoperatingandcontrolfunctionoftheA/Dconverter.

Register NameBit

7 6 5 4 3 2 1 0S�DOL(�DRFS=0) D3 D2 D1 D0 — — — —S�DOL(�DRFS=1) D� D6 D5 D4 D3 D2 D1 D0S�DOH(�DRFS=0) D11 D10 D� D8 D� D6 D5 D4S�DOH(�DRFS=1) — — — — D11 D10 D� D8S�DC0 ST�RT �DBZ EN�DC �DRFS — S�CS2 S�CS1 S�CS0S�DC1 S�INS2 S�INS1 S�INS0 — — S�CKS2 S�CKS1 S�CKS0S�DC2 ENOP� VBGEN VREFIPS VREFPS S�VRS3 S�VRS2 S�VRS1 S�VRS0�CERL �CE� �CE6 �CE5 �CE4 �CE3 �CE2 �CE1 �CE0

A/D Converter Register List

A/D Converter Data Registers – SADOL, SADOHAsthedevicecontainsaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasSADOH,andalowbyteregister,knownasSADOL.After theconversionprocess takesplace, theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theSADC0registerasshownin theaccompanying table.D0~D11are theA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.NotethattheA/DconverterdataregistercontentswillkeepunchangediftheA/Dconverterisdisabled.

ADRFSSADOH SADOL

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D� D8 D� D6 D5 D4 D3 D2 D1 D0 0 0 0 01 0 0 0 0 D11 D10 D� D8 D� D6 D5 D4 D3 D2 D1 D0

A/D Data Registers

Rev. 1.20 104 ��st 2�� 201� Rev. 1.20 105 ��st 2�� 201�



A/D Converter Control Registers – SADC0, SADC1, SADC2, ACERLTocontrol thefunctionandoperationof theA/Dconverter,severalcontrol registersknownasSADC0,SADC1,SADC2andACERLareprovided.These8-bit registersdefinefunctionssuchastheselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter, thedigitiseddataformat,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterbusystatus.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit, eachof theexternaland internalanalogsignalsmustbe routed to theconverter.TheSACS2~SACS0bitsintheSADC0registerareusedtodeterminewhichexternalchannelinputisselectedtobeconverted.TheSAINS2~SAINS0bitsintheSADC1registerareusedtodeterminethat theanalogsignal tobeconvertedcomesfromthe internalanalogsignalorexternalanalogchannelinput.IftheSAINS2~SAINS0bitsaresetto“000”or“100”,theexternalanalogchannelinputisselectedtobeconvertedandtheSACS2~SACS0bitscandeterminewhichexternalchannelisselectedtobeconverted.If theSAINS2~SAINS0bitsareset toanyothervaluesexcept“000”and“100”,oneoftheinternalanalogsignalsisselectedtobeconverted.TheinternalanalogsignalscanbederivedfromtheA/Dconvertersupplypower,VDD,orinternalreferencevoltage,VR,withaspecificratioof1,1/2or1/4.Iftheinternalanalogsignalisselectedtobeconverted,theexternalchannelsignalinputwillautomaticallybeswitchedofftoavoidthesignalcontention.

TheACERLcontrolregistercontainstheACE7~ACE0bitswhichdeterminewhichpinsonI/OPortareusedasanaloginputsfortheA/DconverterinputandwhichpinsarenottobeusedastheA/Dconverterinput.SettingthecorrespondingbithighwillselecttheA/Dinputfunction,clearingthebittozerowillselecteithertheI/Oorotherpin-sharedfunction.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorsconnectedtothesepinswillbeautomaticallyremovedifthepinisselectedtobeanA/Dinput.

SAINS [2:0] SACS [2:0] Input Signals Description000� 100 000~111 �N0~�N� External channel analo� inp�t

001 xxx VDD �/D converter power s�pply volta�e010 xxx VDD/2 �/D converter power s�pply volta�e/2011 xxx VDD/4 �/D converter power s�pply volta�e/4101 xxx VR Internal reference volta�e110 xxx VR/2 Internal reference volta�e/2111 xxx VR/4 Internal reference volta�e/4

A/D Converter Input Signal Selection

Rev. 1.20 104 ��st 2�� 201� Rev. 1.20 105 ��st 2�� 201�



SADC0 Register

Bit 7 6 5 4 3 2 1 0Name ST�RT �DBZ EN�DC �DRFS — S�CS2 S�CS1 S�CS0R/W R/W R R/W R/W — R/W R/W R/WPOR 0 0 0 0 — 0 0 0

Bit7 START:StarttheA/Dconversion0→1→0:StartA/Dconversion0→1:ResettheA/DconverterandsetADBZto01→0:StartA/DconversionandsetADBZto1

ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.

Bit6 ADBZ:A/DConverterbusyflag0:NoA/Dconversionisinprogress1:A/Dconversionisinprogress

ThisreadonlyflagisusedtoindicatewhethertheA/Dconversionis inprogressornot.WhentheSTARTbitissetfromlowtohighandthentolowagain,theADBZflagwillbesethightoindicatethattheA/Dconversionisinitiated.TheADBZflagwillbeclearedtozeroaftertheA/Dconversioniscomplete.

Bit5 ENADC:A/DConverterfunctionenablecontrol0:Disable1:Enable

ThisbitcontrolstheA/Dinternalfunction.ThisbitshouldbesethightoenabletheA/Dconverter.Ifthebitissetlow,thentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.WhentheA/Dconverterfunctionisdisabled,thecontentsoftheA/Ddataregisterpair,SADOHandSADOL,willkeepunchanged.

Bit4 ADRFS:A/DConverterdataformatcontrol0:ADCoutputdataformat→SADOH=D[11:4];SADOL=D[3:0]1:ADCoutputdataformat→SADOH=D[11:8];SADOL=D[7:0]

Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Dconverterdataregistersection.

Bit3 Unimplemented,readas“0”Bit2~0 SACS2~SACS0:A/Dconverterexternalanaloginputchannelselection

000:AN0001:AN1010:AN2011:AN3100:AN4101:AN5110:AN6111:AN7

Rev. 1.20 106 ��st 2�� 201� Rev. 1.20 10� ��st 2�� 201�



SADC1 Register

Bit 7 6 5 4 3 2 1 0Name S�INS2 S�INS1 S�INS0 — — S�CKS2 S�CKS1 S�CKS0R/W R/W R/W R/W — — R/W R/W R/WPOR 0 0 0 — — 0 0 0

Bit7~5 SAINS2~SAINS0:A/Dconverterinputsignalselection000,100:Externalsignal–Externalanalogchannelinput001:Internalsignal–InternalA/DconverterpowersupplyvoltageVDD

010:Internalsignal–InternalA/DconverterpowersupplyvoltageVDD/2011:Internalsignal–InternalA/DconverterpowersupplyvoltageVDD/4101:Internalsignal–InternalA/DconverterpowersupplyvoltageVR

110:Internalsignal–InternalA/DconverterpowersupplyvoltageVR/2111:Internalsignal–InternalA/DconverterpowersupplyvoltageVR/4

Whentheinternalanalogsignalisselectedtobeconverted,theexternalchannelinputsignalwillautomaticallybeswitchedoffregardlessof theSACS2~SACS0bitfieldvalue.TheinternalreferencevoltagecanbederivedfromvarioussourcesselectedusingtheSAVRS3~SAVRS0bitsintheSADC2register.

Bit4~3 Unimplemented,readas“0”Bit2~0 SACKS2~SACKS0:A/Dconversionclocksourceselection

000:fSYS

001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:fSYS/128

ThesebitsareusedtoselecttheclocksourcefortheA/Dconverter.

Rev. 1.20 106 ��st 2�� 201� Rev. 1.20 10� ��st 2�� 201�



SADC2 Register

Bit 7 6 5 4 3 2 1 0Name ENOP� VBGEN VREFIPS VREFPS S�VRS3 S�VRS2 S�VRS1 S�VRS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 ENOPA:A/DconverterOPAenable/disablecontrol0:Disable1:Enable

Thisbitcontrols theinternalOPAfunctiontoprovidevariousreferencevoltagefortheA/Dconverter.Whenthebitissethigh,theinternalreferencevoltage,VR,canbeusedastheinternalconvertersignalorreferencevoltagebytheA/Dconverter.Iftheinternalreferencevoltage isnotusedbytheA/Dconverter, thentheOPAfunctionshouldbeproperlyconfiguredtoconservepower.

Bit6 VBGEN:InternalBandgapreferencevoltageenablecontrol0:Disable1:Enable

ThiscontrolstheinternalBandgapcircuiton/offfunctiontotheA/Dconverter.Whenthebitissethigh,theBandgapreferencevoltagecanbeusedbytheA/Dconverter.IftheBandgapreferencevoltageisnotusedbytheA/DconverterandtheLVDorLVRfunctionisdisabled,thenthebandgapreferencecircuitwillbeautomaticallyswitchedofftoconservepower.WhentheBandgapreferencevoltageisswitchedonforusebytheA/Dconverter,atime,tBGS,shouldbeallowedfortheBandgapcircuittostabilisebeforeimplementinganA/Dconversion.

Bit5 VREFIPS:VREFIinputcontrol0:Disable–VREFIpinisnotselected1:Enable–VREFIpinisselected

Bit4 VREFPS:VREFoutputcontrol0:Disable1:Enable

Bit3~0 SAVRS3~SAVRS0:A/Dconverterreferencevoltageselection0000:VDD

0001:VREFI

0010:VREFI×20011:VREFI×30100:VREFI×41001:Reserved,cannotbeused1010:VBG×21011:VBG×31100:VBG×4Others:VDD

When theA/Dconverter referencevoltagesource is selected toderive from theinternalVBGvoltage,thereferencevoltagewhichcomesfromtheVDDorVREFIpinwillbeautomaticallyswitchedoff.

Rev. 1.20 108 ��st 2�� 201� Rev. 1.20 10� ��st 2�� 201�



ACERL Register

Bit 7 6 5 4 3 2 1 0Name �CE� �CE6 �CE5 �CE4 �CE3 �CE2 �CE1 �CE0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7 ACE7:DefinePB7isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN7

Bit6 ACE6:DefinePF1isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN6

Bit5 ACE5:DefinePA1isA/Dinputornot0:NotA/Dinput1:A/Dinput,AN5






A/D OperationTheSTARTbit in theSADC0register isused tostartand reset theA/Dconverter.When themicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbe initiated.WhentheSTARTbit isbroughtfromlowtohighbutnot lowagain, theADBZbitintheSADC0registerwillbeclearedtozeroandtheanalogtodigitalconverterwillbereset.ItistheSTARTbitthatisusedtocontroltheoverallstartoperationoftheinternalanalogtodigitalconverter.

TheADBZbit intheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversionprocessis inprocessornot.WhentheA/Dconverter isresetbysettingtheSTARTbitfromlowtohigh, theADBZflagwillbecleared to“0”.Thisbitwillbeautomaticallyset to“1”by themicrocontrollerafteranA/Dconversion issuccessfully initiated.When theA/Dconversion iscomplete,theADBZwillbeclearedto“0”.Inaddition,thecorrespondingA/Dinterruptrequestflagwillbesetintheinterruptcontrolregister,andiftheinterruptsareenabled,anappropriateinternalinterruptsignalwillbegenerated.ThisA/DinternalinterruptsignalwilldirecttheprogramflowtotheassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanbeusedtopolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.

Rev. 1.20 108 ��st 2�� 201� Rev. 1.20 10� ��st 2�� 201�



TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theSACKS2~SACKS0bits intheSADC1register.AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYS,andbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedvalueofpermissibleA/Dclockperiod,tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,ifthesystemclockoperatesatafrequencyof8MHz,theSACKS2~SACKS0bitsshouldnotbesetto“000”,“001”or“111”.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumA/Dclockperiodorgreater thanthemaximumA/Dclockperiodwhichmayresult ininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessthanthespecifiedminimumA/DClockPeriod.

fSYS

A/D Clock Period (tADCK)SACKS2,SACKS1,SACKS0

=000(fSYS)

SACKS2,SACKS1,SACKS0

=001(fSYS/2)

SACKS2,SACKS1, SACKS0

=010(fSYS/4)

SACKS2,SACKS1, SACKS0

=011(fSYS/8)


=100(fSYS/16)


=101(fSYS/32)


=110(fSYS/64)


=111(fSYS/128)

1MHz 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* 128μs*2MHz 500ns 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs*4MHz 250ns* 500ns 1μs 2μs 4μs 8μs 16μs* 32μs*8MHz 125ns* 250ns* 500ns 1μs 2μs 4μs 8μs 16μs*

12MHz 83ns* 167ns* 333ns* 66�ns 1.33μs 2.67μs 5.33μs 10.67μs*16MHz 62.5ns* 125ns* 250ns* 500ns 1μs 2μs 4μs 8μs20MHz 50ns* 100ns* 200ns* 400ns* 800ns 1.6μs 3.2μs 6.4μs

A/D Clock Period Examples

Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theENADCbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheENADCbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedin the timingdiagram,mustbeallowedbeforeanA/Dconversionis initiated.EvenifnopinsareselectedforuseasA/Dinputsbyconfiguringthecorrespondingpincontrolbits,iftheENADCbitishighthensomepowerwillstillbeconsumed.Inpowerconsciousapplicationsit isthereforerecommendedthat theENADCisset lowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.

A/D Reference VoltageThereferencevoltagesupplytotheA/DConvertercanbesuppliedfromthepositivepowersupplypin,VDD,anexternal referencesourcesuppliedonpinVREFIoran internal referencesourcederivedfromtheBandgapcircuit.Then theselectedreferencevoltagesourcecanbeamplifiedthroughanoperationalamplifierexcepttheonesourcedfromVDD.TheOPAgaincanbeequalto1,2,3or4.ThedesiredselectionismadeusingtheSAVRS3~SAVRS0bitsintheSADC2registerandrelevantpinfunctioncontrolbits.NotethatthedesiredselectedreferencevoltagewillbeoutputontheVREFpinwhichispin-sharedwithotherfunctions.AstheVREFIandVREFpinsbotharepin-sharedwithotherfunctions,whentheVREFIorVREFpinisselectedasthereferencevoltagesupplypin,thepinfunctioncontrolbitVREFIPSorVREFPSshouldbesethightodisableotherpin-sharedfunctions.WhenVREFIorVBGisselectedbyADCinputorADCreferencevoltage,theOPAneedstobeenabledbysettingtheENOPAbit to“1”.Inaddition, if theprogramsselectexternalreferencevoltageVREFIandtheinternalreferencevoltageVBGasADCreferencevoltage, thenthehardwarewillonlychoosetheinternalreferencevoltageVBGasanADCreferencevoltageinput.

Rev. 1.20 110 ��st 2�� 201� Rev. 1.20 111 ��st 2�� 201�



SAVRS[3:0] Reference Description0000/others VDD �DC Reference Volta�e comes from VDD

0001 VREFI �DC Reference Volta�e comes from External VREFI

0010 VREFI×2 �DC Reference Volta�e comes from External VREFI×20011 VREFI×3 �DC Reference Volta�e comes from External VREFI×30100 VREFI×4 �DC Reference Volta�e comes from External VREFI×41010 VBG×2 �DC Reference Volta�e comes from VBG×21011 VBG×3 �DC Reference Volta�e comes from VBG×31100 VBG×4 �DC Reference Volta�e comes from VBG×4

A/D Converter Reference Voltage Selection

A/D Converter Input SignalAlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortA,PortBandPortFaswellasotherfunctions.ThecorrespondingselectionbitintheACERLregister,determineswhethertheinputpinissetupasA/Dconverteranaloginputorwhetherithasotherfunctions.IfthecontrolbitconfiguresitscorrespondingpinasanA/Danalogchannelinput,thepinwillbesetuptobeanA/Dconverterexternalchannelinputandtheoriginalpinfunctionsdisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionbetweenA/Dinputsandotherfunctions.Allpull-high resistors,whichare setup through registerprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputinthePAC,PBCandPFCportcontrolregistertoenabletheA/DinputaswhenthecontrolbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.

TheA/Dconverterhasitsownreferencevoltagepin,VREFI.HoweverthereferencevoltagecanalsobesuppliedfromthepowersupplypinoraninternalBandgapcircuit,achoicewhichismadethrough theSAVRS3~SAVRS0bits in theSADC2register.TheselectedA/DreferencevoltagecanbeoutputontheVREFpin.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF.Notethat theVREFIorVREFpinfunctionselectionbit intheSADC2registermustbeproperlyconfiguredbeforethereferencevoltagepinfunctionisused.

Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforanA/DconversionwhichisdefinedastADCarenecessary.

MaximumsingleA/Dconversionrate=A/Dclockperiod/16

Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKclockcycleswheretADCKisequaltotheA/Dclockperiod.

Rev. 1.20 110 ��st 2�� 201� Rev. 1.20 111 ��st 2�� 201�



EN�DC

ST�RT

�DBZ

S�CS[2:0]S�INS[2:0]=000B

off on off ontON2ST

t�DS

�/D samplin� timet�DS

�/D samplin� time

Start of �/D conversion Start of �/D conversion Start of �/D conversion

End of �/D conversion

End of �/D conversion

t�DC�/D conversion time



011B 010B 000B 001B

�/D channel switch

A/D Conversion Timing

Summary of A/D Conversion StepsThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.

• Step1SelecttherequiredA/DconversionclockbyproperlyprogrammingtheSACKS2~SACKS0bitsintheSADC1register.

• Step2EnabletheA/DconverterbysettingtheENADCbitintheSADC0registerto“1”.

• Step3SelectwhichsignalistobeconnectedtotheinternalA/DconverterbycorrectlyconfiguringtheSAINS2~SAINS0bits.Selecttheexternalchannelinputtobeconverted,gotoStep4.Selecttheinternalanalogsignaltobeconverted,gotoStep5.

• Step4IftheA/DinputsignalcomesfromtheexternalchannelinputselectingbyconfiguringtheSAINSbitfield,thecorrespondingpinshouldfirstbeconfiguredasA/Dinputfunctionbyconfiguringtherelevantpincontrolbit intheACERLregister.ThedesiredanalogchannelthenshouldbeselectedbyconfiguringtheSACSbitfield.Afterthisstep,gotoStep6.

• Step5If theA/D input signal is selected tocomefrom the internalanalogsignal, theSAINSbitfieldshouldbeproperlyconfiguredandthentheexternalchannel inputwillautomaticallybedisconnectedregardlessoftheSACSbitfieldvalue.Afterthisstep,gotoStep6.

• Step6SelectthereferencevoltagesourcebyconfiguringtheSAVRS3~SAVRS0bits.Note:IfselectVREFIpinasthereferencevoltage,theVREFIPSbitmustbesethigh.

• Step7SelectA/DconverteroutputdataformatbyconfiguringtheADRFSbit.

• Step8IfA/Dconversioninterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconverterinterruptbits,ADE,mustbothsethighinadvance.

Rev. 1.20 112 ��st 2�� 201� Rev. 1.20 113 ��st 2�� 201�



• Step9TheA/DconversionprocedurecannowbeinitialisedbysettingtheSTARTbitfromlowtohighandthenlowagain.

• Step10IfA/Dconversion is inprogress, theADBZflagwillbesethigh.After theA/Dconversionprocess iscompleted, theADBZflagwillgo lowandthenoutputdatacanbereadfromtheSADOHandSADOLregisters.IftheADCinterruptisenabledandthestackisnotfull,datacanbeacquiredbyinterruptserviceprogram.

Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheADBZbitintheSADC0registerisused,theinterruptenablestepabovecanbeomitted.

Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff to reducepowerconsumption,byclearing theENADCbit in theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Os,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.

A/D Transfer FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequal totheVREFvoltage, thisgivesasinglebitanaloginputvalueofVREFdividedby4096.

1LSB=VREF/4096

TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:

A/Dinputvoltage=A/Doutputdigitalvalue×VREF/4096

Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVDDlevel.

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Ideal A/D Transfer Function

Rev. 1.20 112 ��st 2�� 201� Rev. 1.20 113 ��st 2�� 201�



A/D Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheADBZbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.

Example: using an ADBZ polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ; select fSYS/8 as A/D clock set ENADCmov a,01h ; setup ACERL to configure pin AN0mov ACERL,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converter:start_conversion:clr START ; high pulse on start bit to initiate conversionset START ; reset A/Dclr START ; start A/Dpolling_EOC:sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversionjmp polling_EOC ; continue pollingmov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ; save result to user defined register:jmp start_conversion ; start next A/D conversion

Rev. 1.20 114 ��st 2�� 201� Rev. 1.20 115 ��st 2�� 201�



Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,0BHmov SADC1,a ; select fSYS/8 as A/D clock and switch off the bandgap reference ; voltageset ENADCmov a,01h ; setup ACERL to configure pin AN0mov ACERL,amov a,20hmov SADC0,a ; enable and connect AN0 channel to A/D converterStart_conversion:clr START ; high pulse on START bit to initiate conversionset START ; reset A/Dclr START ; start A/Dclr ADF ; clear ADC interrupt request flagset ADE ; enable ADC interruptset EMI ; enable global interrupt:: ; ADC interrupt service routineADC_ISR:mov acc_stack,a ; save ACC to user defined memorymov a,STATUSmov status_stack,a ; save STATUS to user defined memory::mov a,SADOL ; read low byte conversion result valuemov SADOL_buffer,a ; save result to user defined registermov a,SADOH ; read high byte conversion result valuemov SADOH_buffer,a ; save result to user defined register::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ; restore STATUS from user defined memorymov a,acc_stack ; restore ACC from user defined memoryreti

Rev. 1.20 114 ��st 2�� 201� Rev. 1.20 115 ��st 2�� 201�



Serial Interface Module – SIMThedevicecontainsaSerialInterfaceModule,whichincludesboththefour-lineSPIinterfaceortwo-lineI2Cinterfacetypes, toallowaneasymethodofcommunicationwithexternalperipheralhardware.Havingrelativelysimplecommunicationprotocols, theseserial interface typesallowthemicrocontroller to interface toexternalSPIorI2Cbasedhardwaresuchassensors,FlashorEEPROMmemory,etc.TheSIMinterfacepinsarepin-sharedwithotherI/OpinsandthereforetheSIMinterfacefunctionalpinsmustfirstbeselectedusingthecorrespondingpin-sharedfunctionselectionbits.Asbothinterfacetypessharethesamepinsandregisters, thechoiceofwhethertheSPIorI2CtypeisusedismadeusingtheSIMoperatingmodecontrolbits,namedSIM2~SIM0,intheSIMC0register.Thesepull-highresistorsoftheSIMpin-sharedI/Opinsareselectedusingpull-highcontrolregisterswhentheSIMfunctionisenabledandthecorrespondingpinsareusedasSIMinputpins.

SPI InterfaceTheSPIinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,FlashorEEPROMmemorydevices,etc.OriginallydevelopedbyMotorola, the four lineSPIinterfaceisasynchronousserialdatainterfacethathasarelativelysimplecommunicationprotocolsimplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.

Thecommunicationisfullduplexandoperatesasaslave/mastertype,wherethedevicescanbeeithermasterorslave.AlthoughtheSPIinterfacespecificationcancontrolmultipleslavedevicesfromasinglemaster, thesedevicesprovidedonlyoneSCSpin. If themasterneeds tocontrolmultipleslavedevicesfromasinglemaster,themastercanuseI/Opintoselecttheslavedevices.

SPI Interface OperationTheSPIinterfaceisafullduplexsynchronousserialdatalink.It isafourlineinterfacewithpinnamesSDI,SDO,SCKandSCS.PinsSDIandSDOare theSerialData InputandSerialDataOutputlines,SCKistheSerialClocklineandSCSistheSlaveSelectline.AstheSPIinterfacepinsarepin-sharedwithnormalI/OpinsandwiththeI2Cfunctionpins,theSPIinterfacepinsmustfirstbeselectedbyconfiguringthepin-sharedfunctionselectionbitsandsettingthecorrectbitsintheSIMC0andSIMC2registers.AfterthedesiredSPIconfigurationhasbeensetitcanbedisabledorenabledusingtheSIMENbit in theSIMC0register.Communicationbetweendevicesconnectedto theSPI interface iscarriedout inaslave/mastermodewithalldata transfer initiationsbeingimplementedbythemaster.TheMasteralsocontrolstheclocksignal.AsthedeviceonlycontainsasingleSCSpinonlyoneslavedevicecanbeutilized.TheSCSpiniscontrolledbysoftware,setCSENbitto1toenableSCSpinfunction,setCSENbitto0theSCSpinwillbefloatingstate.

TheSPIfunctioninthisdeviceoffersthefollowingfeatures:

• Fullduplexsynchronousdatatransfer

• BothMasterandSlavemodes

• LSBfirstorMSBfirstdatatransmissionmodes

• Transmissioncompleteflag

• Risingorfallingactiveclockedge

ThestatusoftheSPIinterfacepinsisdeterminedbyanumberoffactorssuchaswhetherthedeviceis in themasterorslavemodeandupontheconditionofcertaincontrolbitssuchasCSENandSIMEN.

Rev. 1.20 116 ��st 2�� 201� Rev. 1.20 11� ��st 2�� 201�



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SPI Master/Slave Connection

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SPI Block Diagram

SPI RegistersTherearethreeinternalregisterswhichcontroltheoveralloperationoftheSPIinterface.ThesearetheSIMDdataregisterandtworegistersSIMC0andSIMC2.NotethattheSIMC1registerisonlyusedbytheI2Cinterface.

Register Name

Bit

7 6 5 4 3 2 1 0SIMC0 SIM2 SIM1 SIM0 — SIMDBNC1 SIMDBNC0 SIMEN SIMICFSIMC2 D� D6 CKPOLB CKEG MLS CSEN WCOL TRFSIMD D� D6 D5 D4 D3 D2 D1 D0

SPI Registers List

SIMD RegisterTheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedevicewritesdatatotheSPIbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,thedevicecanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbusmustbemadeviatheSIMDregister.

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: �nknown

Rev. 1.20 116 ��st 2�� 201� Rev. 1.20 11� ��st 2�� 201�



TherearealsotwocontrolregistersfortheSPIinterface,SIMC0andSIMC2.NotethattheSIMC2registeralsohasthenameSIMAwhichisusedbytheI2Cfunction.TheSIMC1registerisnotusedbytheSPIfunction,onlybytheI2Cfunction.RegisterSIMC0isusedtocontroltheenable/disablefunctionandtosetthedatatransmissionclockfrequency.RegisterSIMC2isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionflag,etc.

SIMC0 Register

Bit 7 6 5 4 3 2 1 0Name SIM2 SIM1 SIM0 — SIMDBNC1 SIMDBNC0 SIMEN SIMICFR/W R/W R/W R/W — R/W R/W R/W R/WPOR 1 1 1 — 0 0 0 0

Bit7~5 SIM2~SIM0:SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfSUB

100:SPImastermode;SPIclockisPTMCCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:NonSIMfunction

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionof thesystemclockorfSUBbutcanalsobechosentobesourcedfromPTM.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 Unimplemented,readas“0”Bit3~2 SIMDBNC1~SIMDBNC0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclockdebounce1x:4systemclockdebounce

Bit1 SIMEN:SIMEnableControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAandSCLlineswill losetheirSPIorI2CfunctionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.IftheSIMisconfiguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.IftheSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirst initialisedbytheapplicationprogramwhile therelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Rev. 1.20 118 ��st 2�� 201� Rev. 1.20 11� ��st 2�� 201�



Bit0 SIMICF:SIMIncompleteFlag0:SIMincompleteconditionnotoccurred1:SIMincompleteconditionoccured

ThisbitisonlyavailablewhentheSIMisconfiguredtooperateinanSPIslavemode.IftheSPIoperatesintheslavemodewiththeSIMENandCSENbitsbothbeingsetto1buttheSCSlineispulledhighbytheexternalmasterdevicebeforetheSPIdatatransferiscompletelyfinished,theSIMICFbitwillbesetto1togetherwiththeTRFbit.Whenthisconditionoccurs,thecorrespondinginterruptwilloccuriftheinterruptfunctionisenabled.However,theTRFbitwillnotbesetto1iftheSIMICFbitissetto1bysoftwareapplicationprogram.

SIMC2 Register

Bit 7 6 5 4 3 2 1 0Name D� D6 CKPOLB CKEG MLS CSEN WCOL TRFR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7~6 UndefinedbitsThesebitscanbereadorwrittenbytheapplicationprogram.

Bit5 CKPOLB:SPIclocklinebaseconditionselection0:TheSCKlinewillbehighwhentheclockisinactive.1:TheSCKlinewillbelowwhentheclockisinactive.

TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockisinactive.

Bit4 CKEG:SPISCKclockactiveedgetypeselectionCKPOLB=00:SCKishighbaselevelanddatacaptureatSCKrisingedge1:SCKishighbaselevelanddatacaptureatSCKfallingedge

CKPOLB=10:SCKislowbaselevelanddatacaptureatSCKfallingedge1:SCKislowbaselevelanddatacaptureatSCKrisingedge

TheCKEGandCKPOLBbitsareusedtosetupthewaythattheclocksignaloutputsandinputsdataontheSPIbus.Thesetwobitsmustbeconfiguredbeforedatatransferisexecutedotherwiseanerroneousclockedgemaybegenerated.TheCKPOLBbitdeterminesthebaseconditionoftheclockline, if thebit ishigh,thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCKlinewillbehighwhentheclockis inactive.TheCKEGbitdeterminesactiveclockedgetypewhichdependsupontheconditionofCKPOLBbit.

Bit3 MLS:SPIdatashiftorder0:LSBfirst1:MSBfirst

Thisisthedatashiftselectbitandisusedtoselecthowthedataistransferred,eitherMSBorLSBfirst.SettingthebithighwillselectMSBfirstandlowforLSBfirst.

Bit2 CSEN:SPISCSpincontrol0:Disable1:Enable

TheCSENbitisusedasanenable/disablefortheSCSpin.Ifthisbitislow,thentheSCSpinwillbedisabledandplacedintoI/Opinorotherpin-sharedfunctions.Ifthebitishigh,theSCSpinwillbeenabledandusedasaselectpin.

Rev. 1.20 118 ��st 2�� 201� Rev. 1.20 11� ��st 2�� 201�



Bit1 WCOL:SPIwritecollisionflag0:Nocollision1:Collision

TheWCOLflagisusedtodetectwhetheradatacollisionhasoccurredornot.Ifthisbit ishigh,itmeansthatdatahasbeenattemptedtobewrittentotheSIMDregisterdutingadatatransferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.Thisbitcanbeclearedbytheapplicationprogram.

Bit0 TRF:SPITransmit/Receivecompleteflag0:SPIdataisbeingtransferred1:SPIdatatransferiscompleted

TheTRFbitistheTransmit/ReceiveCompleteflagandissetto1automaticallywhenanSPIdatatransferiscompleted,butmustclearedto0bytheapplicationprogram.Itcanbeusedtogenerateaninterrupt.

SPI CommunicationAftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,whendataiswrittentotheSIMDregister, transmission/receptionwillbeginsimultaneously.Whenthedata transfer iscomplete, theTRFflagwillbesetautomatically,butmustbeclearedusing theapplicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedintotheSIMDregister.ThemastershouldoutputaSCSsignal toenable theslavedevicesbeforeaclocksignalisprovided.TheslavedatatobetransferredshouldbewellpreparedattheappropriatemomentrelativetotheSCSsignaldependingupontheconfigurationsoftheCKPOLBbitandCKEGbit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignalforvariousconfigurationsoftheCKPOLBandCKEGbits.

TheSPImastermodewillcontinuetofunctionevenintheIDLEModeif theselectedSPIclocksourceisrunning.

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SPI Master Mode Timing

Rev. 1.20 120 ��st 2�� 201� Rev. 1.20 121 ��st 2�� 201�



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SPI Slave Mode Timing – CKEG=0

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SPI Slave Mode Timing – CKEG=1

Rev. 1.20 120 ��st 2�� 201� Rev. 1.20 121 ��st 2�� 201�



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SPI Transfer Control Flow Chart

Rev. 1.20 122 ��st 2�� 201� Rev. 1.20 123 ��st 2�� 201�



I2C InterfaceThe I2C interface isused to communicatewith externalperipheraldevices suchas sensors,EEPROMmemoryetc.OriginallydevelopedbyPhilips,it isatwolinelowspeedserialinterfaceforsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relativelysimplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebushasmadeitanextremelypopularinterfacetypeformanyapplications.

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I2C Master/Slave Bus Connection

I2C interface OperationTheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.Asmanydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Notethatnochipselectlineexists,aseachdeviceontheI2CbusisidentifiedbyauniqueaddresswhichwillbetransmittedandreceivedontheI2Cbus.

WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthemasterdeviceandoneas theslavedevice.Bothmasterandslavecantransmitandreceivedata,however, it isthemasterdevicethathasoverallcontrolofthebus.Forthesedevices,whichonlyoperateinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmitmodeandtheslavereceivemode.

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Rev. 1.20 122 ��st 2�� 201� Rev. 1.20 123 ��st 2�� 201�



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TheSIMDBNC1andSIMDBNC0bitsdeterminethedebouncetimeoftheI2Cinterface.Thisusesthesystemclockto ineffectaddadebouncetimeto theexternalclocktoreducethepossibilityofglitchesontheclocklinecausingerroneousoperation.Thedebouncetime, ifselected,canbechosen tobeeither2or4systemclocks.Toachieve therequiredI2Cdata transferspeed, thereexistsarelationshipbetweenthesystemclock,fSYS,andtheI2Cdebouncetime.ForeithertheI2CStandardorFastmodeoperation,usersmusttakecareoftheselectedsystemclockfrequencyandtheconfigureddebouncetimetomatchthecriterionshowninthefollowingtable.

I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz)No Devo�nce fSYS > 2 MHz fSYS > 5 MHz2 system clock debo�nce fSYS > 4 MHz fSYS > 10 MHz4 system clock debo�nce fSYS > 8 MHz fSYS > 20 MHz

I2C Minimum fSYS Frequency

I2C RegistersThereare threecontrolregistersassociatedwiththeI2Cbus,SIMC0,SIMC1andSIMTOC,oneslaveaddressregister,SIMA,andonedataregister,SIMD.TheSIMDregister,whichisshownintheaboveSPIsection,isusedtostorethedatabeingtransmittedandreceivedontheI2Cbus.BeforethemicrocontrollerwritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,themicrocontrollercanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.

NotethattheSIMAregisteralsohasthenameSIMC2whichisusedbytheSPIfunction.BitSIMENandbitsSIM2~SIM0inregisterSIMC0areusedbytheI2Cinterface.

Register Name

Bit

7 6 5 4 3 2 1 0SIMC0 SIM2 SIM1 SIM0 — SIMDBNC1 SIMDBNC0 SIMEN SIMICFSIMC1 HCF H��S HBB HTX TX�K SRW I�MWU RX�KSIM� �6 �5 �4 �3 �2 �1 �0 —SIMD D� D6 D5 D4 D3 D2 D1 D0

SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0

I2C Registers List

Rev. 1.20 124 ��st 2�� 201� Rev. 1.20 125 ��st 2�� 201�



SIMD RegisterTheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.ThesameregisterisusedbyboththeSPIandI2Cfunctions.BeforethedevicewritesdatatotheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,thedevicecanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.

Bit 7 6 5 4 3 2 1 0Name D� D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: �nknown

SIMA RegisterTheSIMAregisterisalsousedbytheSPIinterfacebuthasthenameSIMC2.TheSIMAregisteristhelocationwherethe7-bitslaveaddressoftheslavedeviceisstored.Bits7~1oftheSIMAregisterdefinethedeviceslaveaddress.Bit0isnotdefined.

Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,whichmatchestheslaveaddressintheSIMAregister,theslavedevicewillbeselected.NotethattheSIMAregisteristhesameregisteraddressasSIMC2whichisusedbytheSPIinterface.

Bit 7 6 5 4 3 2 1 0Name �6 �5 �4 �3 �2 �1 �0 —R/W R/W R/W R/W R/W R/W R/W R/W —POR 0 0 0 0 0 0 0 —

Bit7~1 A6~A0:I2CslaveaddressA6~A0istheI2Cslaveaddressbit6~bit0

Bit0 Unimplemented,readas“0”

Therearealso threecontrol registers for the I2Cinterface,SIMC0,SIMC1andSIMTOC.TheregisterSIMC0isused tocontrol theenable/disable functionand toset thedata transmissionclockfrequency.TheSIMC1registercontainstherelevantflagswhichareusedtoindicatetheI2Ccommunicationstatus.TheSIMTOCregisterisusedtocontroltheI2Cbustime-outfunctionwhichisdescribedintheI2CTime-outControlsection.

Rev. 1.20 124 ��st 2�� 201� Rev. 1.20 125 ��st 2�� 201�



SIMC0 Register

Bit 7 6 5 4 3 2 1 0Name SIM2 SIM1 SIM0 — SIMDBNC1 SIMDBNC0 SIMEN SIMICFR/W R/W R/W R/W — R/W R/W R/W R/WPOR 1 1 1 — 0 0 0 0

Bit7~5 SIM2~SIM0:SIMOperatingModeControl000:SPImastermode;SPIclockisfSYS/4001:SPImastermode;SPIclockisfSYS/16010:SPImastermode;SPIclockisfSYS/64011:SPImastermode;SPIclockisfSUB

100:SPImastermode;SPIclockisPTMCCRPmatchfrequency/2101:SPIslavemode110:I2Cslavemode111:NonSIMfunction

ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.AswellasselectingiftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/SlaveselectionandtheSPIMasterclockfrequency.TheSPIclockisafunctionof thesystemclockorfSUBbutcanalsobechosentobesourcedfromPTM.IftheSPISlaveModeisselectedthentheclockwillbesuppliedbyanexternalMasterdevice.

Bit4 Unimplemented,readas“0”Bit3~2 SIMDBNC1~SIMDBNC0:I2CDebounceTimeSelection

00:Nodebounce01:2systemclockdebounce1x:4systemclockdebounce

Bit1 SIMEN:SIMEnableControl0:Disable1:Enable

Thebit is theoverallon/offcontrolfor theSIMinterface.WhentheSIMENbit isclearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDAandSCLlineswill losetheirSPIorI2CfunctionandtheSIMoperatingcurrentwillbereducedtoaminimumvalue.WhenthebitishightheSIMinterfaceisenabled.TheSIMconfigurationoptionmusthavefirstenabledtheSIMinterfaceforthisbittobeeffective.IftheSIMisconfiguredtooperateasanSPIinterfaceviatheSIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevioussettingswhentheSIMENbitchangesfromlowtohighandshouldthereforebefirst initialisedbytheapplicationprogram.IftheSIMisconfiguredtooperateasanI2CinterfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,thecontentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevioussettingsandshouldthereforebefirst initialisedbytheapplicationprogramwhile therelevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheirdefaultstates.

Bit0 SIMICF:SIMIncompleteFlag0:SIMincompleteconditionnotoccurred1:SIMincompleteconditionoccured

ThisbitisonlyavailablewhentheSIMisconfiguredtooperateinanSPIslavemode.IftheSPIoperatesintheslavemodewiththeSIMENandCSENbitsbothbeingsetto1buttheSCSlineispulledhighbytheexternalmasterdevicebeforetheSPIdatatransferiscompletelyfinished,theSIMICFbitwillbesetto1togetherwiththeTRFbit.Whenthisconditionoccurs,thecorrespondinginterruptwilloccuriftheinterruptfunctionisenabled.However,theTRFbitwillnotbesetto1iftheSIMICFbitissetto1bysoftwareapplicationprogram.

Rev. 1.20 126 ��st 2�� 201� Rev. 1.20 12� ��st 2�� 201�



SIMC1 Register

Bit 7 6 5 4 3 2 1 0Name HCF H��S HBB HTX TX�K SRW I�MWU RX�KR/W R R R R/W R/W R/W R/W RPOR 1 0 0 0 0 0 0 1

Bit7 HCF:I2CBusdatatransfercompletionflag0:Dataisbeingtransferred1:Completionofan8-bitdatatransfer

TheHCFflag is thedata transfer flag.This flagwillbezerowhendata isbeingtransferred.Uponcompletionofan8-bitdata transfer theflagwillgohighandaninterruptwillbegenerated.

Bit6 HAAS:I2CBusdatatransfercompletionflag0:Notaddressmatch1:Addressmatch

TheHAASflagistheaddressmatchflag.Thisflagisusedtodetermineiftheslavedeviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthenthisbitwillbehigh,ifthereisnomatchthentheflagwillbelow.

Bit5 HBB:I2CBusbusyflag0:I2CBusisnotbusy1:I2CBusisbusy

TheHBBflagis theI2Cbusyflag.Thisflagwillbe“1”whentheI2CbusisbusywhichwilloccurwhenaSTARTsignalisdetected.Theflagwillbesetto“0”whenthebusisfreewhichwilloccurwhenaSTOPsignalisdetected.

Bit4 HTX:I2Cslavedevicetransmitter/receiverselection0:Slavedeviceisthereceiver1:Slavedeviceisthetransmitter

Bit3 TXAK:I2Cbustransmitacknowledgeflag0:Slavesendacknowledgeflag1:Slavedoesnotsendacknowledgeflag

TheTXAKbitisthetransmitacknowledgeflag.Aftertheslavedevicereceiptof8-bitsofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.TheslavedevicemustalwayssetTXAKbitto“0”beforefurtherdataisreceived.

Bit2 SRW:I2Cslaveread/writeflag0:Slavedeviceshouldbeinreceivemode1:Slavedeviceshouldbeintransmitmode

TheSRWflag is the I2CSlaveRead/Write flag.This flagdetermineswhetherthemasterdevicewishes to transmitor receivedata fromthe I2Cbus.When thetransmittedaddressandslaveaddressismatch,thatiswhentheHAASflagissethigh,theslavedevicewillchecktheSRWflagtodeterminewhetheritshouldbeintransmitmodeorreceivemode.IftheSRWflagishigh,themasterisrequestingtoreaddatafromthebus,so theslavedeviceshouldbe in transmitmode.WhentheSRWflagiszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbeinreceivemodetoreadthisdata.

Bit1 IAMWU:I2CAddressMatchWake-Upcontrol0:Disable1:Enable–mustbeclearedbytheapplicationprogramafterwake-up

Thisbitshouldbesetto1toenabletheI2CaddressmatchwakeupfromtheSLEEPorIDLEMode.IftheIAMWUbithasbeensetbeforeenteringeithertheSLEEPorIDLEmodetoenabletheI2Caddressmatchwakeup,thenthisbitmustbeclearedbytheapplicationprogramafterwake-uptoensurecorrectiondeviceoperation.

Rev. 1.20 126 ��st 2�� 201� Rev. 1.20 12� ��st 2�� 201�



Bit0 RXAK:I2Cbusreceiveacknowledgeflag0:Slavereceivesacknowledgeflag1:Slavedoesnotreceiveacknowledgeflag

TheRXAKflag is thereceiveracknowledgeflag.WhentheRXAKflag is“0”, itmeansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdatahavebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevicecheckstheRXAKflagtodetermineifthemasterreceiverwishestoreceivethenextbyte.Theslavetransmitterwill thereforecontinuesendingoutdatauntil theRXAKflagis“1”.Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.

I2C Bus CommunicationCommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddresstransmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignal isplacedontheI2Cbus,alldevicesonthebuswillreceivethissignalandbenotifiedoftheimminentarrivalofdataonthebus.ThefirstsevenbitsofthedatawillbetheslaveaddresswiththefirstbitbeingtheMSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress,theHAASbitintheSIMC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptserviceroutine,theslavedevicemustfirstchecktheconditionoftheHAASandSIMTOFbitstodeterminewhether the interruptsourceoriginatesfromanaddressmatch,8-bitdata transfercompletionorI2Cbustime-outoccurrence.Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheSRWbit.Thisbitwillbecheckedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.BeforeanytransferofdatatoorfromtheI2Cbus,themicrocontrollermustinitialisethebus,thefollowingarestepstoachievethis:

• Step1SettheSIM2~SIM0bitsto“110”andSIMENbitto“1”intheSIMC0registertoenabletheI2Cbus.

• Step2WritetheslaveaddressofthedevicetotheI2CbusaddressregisterSIMA.

• Step3SettheSIMEinterruptenablebitoftheinterruptcontrolregistertoenabletheSIMinterrupt.

Rev. 1.20 128 ��st 2�� 201� Rev. 1.20 12� ��st 2�� 201�



Set SIM[2:0]=110Set SIMEN

Write Slave �ddress to SIM�

I2C B�sInterr�pt=?

CLR SIMEPoll SIMF to decide when

to �o to I2C B�s ISR

No Yes

SET SIME andWait for Interr�pt

Goto Main Pro�ram Goto Main Pro�ram

Start

I2C Bus Initialisation Flow Chart

I2C Bus Start SignalTheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotbytheslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.Whendetected, this indicates that theI2Cbusisbusyandtherefore theHBBbitwillbeset.ASTARTconditionoccurswhenahigh to lowtransitionon theSDAline takesplacewhentheSCLlineremainshigh.

I2C Slave AddressThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslavedevicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceivingthis7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutbythemastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbusinterruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,definestheread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewillthentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.TheslavedevicewillalsosetthestatusflagHAASwhentheaddressesmatch.

Asan I2Cbus interruptcancome from three sources,when theprogramenters the interruptsubroutine,theHAASandSIMTOFbitsshouldbeexaminedtoseewhethertheinterruptsourcehascomefromamatchingslaveaddress,thecompletionofadatabytetransferortheI2Cbustime-outoccurrence.Whenaslaveaddressismatched,thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Bus Read/Write SignalTheSRWbitintheSIMC1registerdefineswhetherthemasterdevicewishestoreaddatafromtheI2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifitistobeatransmitterorareceiver.IftheSRWflagis“1”thenthisindicatesthatthemasterdevicewishestoreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusasatransmitter.IftheSRWflagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI2Cbus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.

Rev. 1.20 128 ��st 2�� 201� Rev. 1.20 12� ��st 2�� 201�



I2C Bus Slave Address Acknowledge SignalAfter themasterhas transmitted a calling address, any slavedeviceon the I2Cbus,whoseown internaladdressmatches thecallingaddress,mustgenerateanacknowledgesignal.Theacknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.IfnoacknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemastertoendthecommunication.WhentheHAASflagishigh,theaddresseshavematchedandtheslavedevicemustchecktheSRWflagtodetermineifitistobeatransmitterorareceiver.IftheSRWflagishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1registershouldbesetto“1”.IftheSRWflagislow,thenthemicrocontrollerslavedeviceshouldbesetupasareceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.

I2C Bus Data and Acknowledge SignalThe transmitteddata is8-bitswideand is transmittedafter theslavedevicehasacknowledgedreceiptofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.Afterreceiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level“0”,beforeitcanreceivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfromthemasterreceiver, thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosendaSTOPsignaltoreleasetheI2CBus.ThecorrespondingdatawillbestoredintheSIMDregister.Ifsetupasatransmitter,theslavedevicemustfirstwritethedatatobetransmittedintotheSIMDregister.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMDregister.

Whentheslavereceiver receives thedatabyte, itmustgenerateanacknowledgebit,knownasTXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbitintheSIMC1registertodetermineifit istosendanotherdatabyte,ifnotthenitwillreleasetheSDAlineandawaitthereceiptofaSTOPsignalfromthemaster.

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Note:*Whenaslaveaddressismatched, thedevicesmustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregistertoreleasetheSCLline.

I2C Communication Timing Diagram

Rev. 1.20 130 ��st 2�� 201� Rev. 1.20 131 ��st 2�� 201�



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I2C Bus ISR Flow Chart

I2C Time-out ControlInordertoreducetheI2Clockupproblemduetoreceptionoferroneousclocksources,atime-outfunctionisprovided.IftheclocksourceconnectedtotheI2Cbusisnotreceivedforawhile,thentheI2Ccircuitryandregisterswillberesetafteracertaintime-outperiod.Thetime-outcounterstartstocountonanI2Cbus“START”&“addressmatch”condition,andisclearedbyanSCLfallingedge.Before thenextSCLfallingedgearrives, if the timeelapsedisgreater than the time-outperiodspecifiedbytheSIMTOCregister,thenatime-outconditionwilloccur.Thetime-outfunctionwillstopwhenanI2C“STOP”conditionoccurs.

Rev. 1.20 130 ��st 2�� 201� Rev. 1.20 131 ��st 2�� 201�



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I2C Time-out

WhenanI2Ctime-outcounteroverflowoccurs, thecounterwillstopandtheSIMTOENbitwillbeclearedtozeroandtheSIMTOFbitwillbesethightoindicate thata time-outconditionhasoccurred.Thetime-outconditionwillalsogenerateaninterruptwhichusestheI2Cinterrruptvector.WhenanI2Ctime-outoccurs,theI2Cinternalcircuitrywillberesetandtheregisterswillberesetintothefollowingcondition:

Register After I2C Time-outSIMD� SIM�� SIMC0 No chan�e

SIMC1 Reset to POR condition

I2C Register after Time-out

TheSIMTOFflagcanbeclearedbytheapplicationprogram.Thereare64time-outperiodselectionswhichcanbeselectedusingtheSIMTOSbits in theSIMTOCregister.Thetime-outduration iscalculatedbytheformula:((1~64)×(32/fSUB)).Thisgivesa time-outperiodwhichrangesfromabout1msto64ms.

SIMTOC Register

Bit 7 6 5 4 3 2 1 0Name SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 SIMTOEN:SIMI2CTime-outfunctioncontrol0:Disable1:Enable

Bit6 SIMTOF:SIMI2CTime-outflag0:Notime-outoccurred1:Time-outoccurred

Bit5~0 SIMTOS5~SIMTOS0:SIMI2CTime-outperiodselectionI2CTime-outclocksourceisfSUB/32I2CTime-outperiodisequalto(SIMTOS[5:0]+1)×(32/fSUB)

Rev. 1.20 132 ��st 2�� 201� Rev. 1.20 133 ��st 2�� 201�



ComparatorAnanalogcomparator iscontainedwithin thedevice.Thecomparatorfunctionoffersflexibilityviatheirregistercontrolledfeaturessuchaspower-down,polarityselect,hysteresisetc.InsharingtheirpinswithnormalI/OpinsthecomparatorsdonotwastepreciousI/Opinsiftherefunctionsareotherwiseunused.

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Comparator

Comparator OperationThedevicecontainsacomparator functionwhich isused tocompare twoanalogvoltagesandprovideanoutputbasedontheirdifference.FullcontrolovertheinternalcomparatorsisprovidedviathecontrolregisterCPCassignedtothecomparator.Thecomparatoroutputisrecordedviaabitinthecontrolregister,butcanalsobetransferredoutontoasharedI/Opin.Additionalcomparatorfunctionsinclude,outputpolarity,hysteresisfunctionsandpowerdowncontrol.

Anypull-high resistorsconnected to the sharedcomparator inputpinswillbeautomaticallydisconnectedwhenthecomparatorisenabled.Asthecomparatorinputsapproachtheirswitchinglevel,somespuriousoutputsignalsmaybegeneratedonthecomparatoroutputdueto theslowrisingor fallingnatureof the inputsignals.Thiscanbeminimisedbyselecting thehysteresisfunctionwillapplyasmallamountofpositivefeedbacktothecomparator.Ideallythecomparatorshouldswitchat thepointwherethepositiveandnegativeinputssignalsareat thesamevoltagelevel,however,unavoidableinputoffsetsintroducesomeuncertaintieshere.Thehysteresisfunction,ifenabled,alsoincreasestheswitchingoffsetvalue.

Comparator InterruptThecomparatorpossessesitsowninterruptfunction.Whenthecomparatoroutputbitchangesstate,itsrelevantinterruptflagwillbeset,andifthecorrespondinginterruptenablebitisset,thenajumptoitsrelevantinterruptvectorwillbeexecuted.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeracomparatorinterrupt.NotethatitisthechangingstateoftheCOUTbitandnottheoutputpinwhichgeneratesaninterrupt.IfthemicrocontrollerisintheSLEEPorIDLEModeandtheComparatorisenabled,theniftheexternalinputlinescausetheComparatoroutputtochangestate,theresultinggeneratedinterruptflagwillalsogenerateawake-up.Ifitisrequiredtodisableawake-upfromoccurring,thentheinterruptflagshouldbefirstsethighbeforeenteringtheSLEEPorIDLEMode.

Programming ConsiderationsIf thecomparator isenabled, itwillremainactivewhenthemicrocontrollerenters theSLEEPorIDLEMode,howeverasitwillconsumeacertainamountofpower,theusermaywishtoconsiderdisablingitbeforetheSLEEPorIDLEModeisentered.AscomparatorpinsaresharedwithnormalI/OpinstheI/Oregistersforthesepinswillbereadaszero(portcontrolregisteris“1”)orreadasportdataregistervalue(portcontrolregisteris“0”)ifthecomparatorfunctionisenabled.

Rev. 1.20 132 ��st 2�� 201� Rev. 1.20 133 ��st 2�� 201�



CPC Register

Bit 7 6 5 4 3 2 1 0Name CSEL CEN CPOL COUT COS CINTE1 CINTE0 CHYENR/W R/W R/W R/W R R/W R/W R/W R/WPOR 1 0 0 0 0 0 0 1

Bit7 CSEL:SelectComparatorpinsorI/Opins0:I/Opinselected1:ComparatorinputpinC+andC-selected

ThisistheComparatorinputpinorI/Opinselectbit.Ifthebitishighthecomparatorinputpinswillbeenabled.Asaresult,thesetwopinswilllosetheirI/Opinfunctions.Anypull-highconfigurationoptionsassociatedwiththecomparatorsharedpinswillalsobeautomaticallydisconnected.

Bit6 CEN:ComparatorOn/Offcontrol0:Off1:On

This is theComparatoron/offcontrolbit. If thebit iszero thecomparatorwillbeswitchedoffandnopowerconsumedevenifanalogvoltagesareappliedtoitsinputs.ForpowersensitiveapplicationsthisbitshouldbeclearedtozeroifthecomparatorisnotusedorbeforethedeviceenterstheSLEEPorIDLEmode.

Bit5 CPOL:Comparatoroutputpolarity0:outputnotinverted1:outputinverted

This is thecomparatorpolaritybit. If thebit iszerothentheCOUTbitwillreflectthenon-invertedoutputconditionofthecomparator.IfthebitishighthecomparatorCOUTbitwillbeinverted.

Bit4 COUT:ComparatoroutputbitCPOL=00:C+<C-1:C+>C-

CPOL=10:C+>C-1:C+<C-

Thisbitstoresthecomparatoroutputbit.ThepolarityofthebitisdeterminedbythevoltagesonthecomparatorinputsandbytheconditionoftheCPOLbit.

Bit3 COS:Outputpathselect0:CXpin(compareoutputcanoutputtoCXpin)1:I/Opinselect(compareoutputonlyinternaluse)

Bit2~1 CINTE1~CINTE0:Interruptedgecontrol00:Risingedge→comparatorinterrupttriggersignalgeneratedifCOUTchangedstatefrom0to1

01:Fallingedge→comparatorinterrupttriggersignalgeneratedifCOUTchangedstatefrom1to0

1x:Risingedgeandfallingedge→comparatorinterrupttriggersignalgeneratedifCOUTchangedstatefrom0to1or1to0

Bit0 CHYEN:HysteresisControl0:Off1:On

This is thehysteresis controlbit and if sethighwill applya limitedamountofhysteresistothecomparator,asspecifiedintheComparatorElectricalCharacteristicstable.Thepositive feedback inducedbyhysteresis reduces theeffectofspuriousswitchingnearthecomparatorthreshold.

Rev. 1.20 134 ��st 2�� 201� Rev. 1.20 135 ��st 2�� 201�



SCOM Function for LCDThedevicehasthecapabilityofdrivingexternalLCDpanels.ThecommonpinsforLCDdriving,SCOM0~SCOM3,arepinsharedwiththeI/Opins.TheLCDsignals(COMandSEG)aregeneratedusingtheapplicationprogram.

LCD OperationAnexternalLCDpanelcanbedrivenusingthisdevicebyconfiguringtheI/Opinsascommonpinsandusingotheroutputportslinesassegmentpins.TheLCDdriverfunctioniscontrolledusingtheSCOMCregisterwhichinadditiontocontrollingtheoverallon/offfunctionalsocontrolsthebiasvoltagesetupfunction.ThisenablestheLCDCOMdrivertogeneratethenecessaryVDD/2voltagelevelsforLCD1/2biasoperation.

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LCD COM Bias

TheSCOMENbitintheSCOMCregisteristheoverallmastercontrolfortheLCDdriver;howeverthisbit isusedinconjunctionwiththeCOMnENbits toselectwhichI/OpinsareusedforLCDdriving.NotethatthePortControlregisterdoesnotneedtofirstsetupthepinsasoutputstoenabletheLCDdriveroperation.

SCOMEN COMnEN Pin Function O/P Level0 x I/O 0 or 11 0 I/O 0 or 11 1 SCOMn VDD/2

Output Control

LCD Bias ControlTheLCDCOMdriverenablesarangeofselectionstobeprovidedtosuit therequirementoftheLCDpanelwhichisbeingused.ThebiasresistorchoiceisimplementedusingtheISEL1andISEL0bitsintheSCOMCregister.

Rev. 1.20 134 ��st 2�� 201� Rev. 1.20 135 ��st 2�� 201�



SCOMC Register

Bit 7 6 5 4 3 2 1 0Name — ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0ENR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6~5 ISEL1~ISEL0:SelectRtypeLCDtypicalbiascurrent(VDD=5V)

00:25μA01:50μA10:100μA11:200μA

Bit4 SCOMEN:LCDcontrolbit0:Disable1:Enable

WhenSCOMENisset,itwillturnontheDCpathofresistortogenerate1/2VDDbiasvoltage.

Bit3 COM3EN:SCOM3orotherpinfunctionselection0:Otherpin-sharedfunctions1:SCOM3




Rev. 1.20 136 ��st 2�� 201� Rev. 1.20 13� ��st 2�� 201�



UART InterfaceThedevicecontainsanintegratedfull-duplexasynchronousserialcommunicationsUARTinterfacethatenablescommunicationwithexternaldevicesthatcontainaserialinterface.TheUARTfunctionhasmanyfeaturesandcantransmitandreceivedataseriallybytransferringaframeofdatawitheightorninedatabitsper transmissionaswellasbeingable todetecterrorswhen thedata isoverwrittenorincorrectlyframed.TheUARTfunctionpossessesitsowninternal interruptwhichcanbeusedtoindicatewhenareceptionoccursorwhenatransmissionterminates.

TheintegratedUARTfunctioncontainsthefollowingfeatures:

• Full-duplex,asynchronouscommunication

• 8or9bitscharacterlength

• Even,oddornoparityoptions

• Oneortwostopbits

• Baudrategeneratorwith8-bitprescaler

• Parity,framing,noiseandoverrunerrordetection

• Supportforinterruptonaddressdetect(lastcharacterbit=1)

• Separatelyenabledtransmitterandreceiver

• 2-byteDeepFIFOReceiveDataBuffer

• Transmitandreceiveinterrupts

• Interruptscanbeinitializedbythefollowingconditions:♦ TransmitterEmpty♦ TransmitterIdle♦ ReceiverFull♦ ReceiverOverrun♦ AddressModeDetect♦ RXenable,RXfallingedge

MSB LSB…………………………

Transmitter Shift Re�ister (TSR)MSB LSB…………………………

Receiver Shift Re�ister (RSR)TX Pin RX Pin

Ba�d Rate Generator

TX Re�ister (TXR) RX Re�ister (RXR)

Data to be transmitted Data received

B�fferfSYS

MCU Data B�s

UART Data Transfer Block Diagram

Rev. 1.20 136 ��st 2�� 201� Rev. 1.20 13� ��st 2�� 201�



UART External PinsTocommunicatewithanexternalserialinterface,theinternalUARThastwoexternalpinsknownasTXandRX.TheTXpinistheUARTtransmitterpin,whichcanbeusedasageneralpurposeI/Oorotherpin-sharedfunctionsifthepinisnotconfiguredasaUARTtransmitterpin,whichoccurswhentheTXENbitintheUCR2controlregisterisequaltozero.Similarly,theRXpinistheUARTreceiverpin,whichcanalsobeusedasageneralpurposeI/Opin,ifthepinisnotconfiguredasareceiverpin,whichoccursif theRXENbit intheUCR2registerisequaltozero.AlongwiththeUARTENbit,theTXENandRXENbits,ifset,willautomaticallysetuptheseI/Opinsorotherpin-sharedfunctionaltotheirrespectiveTXoutputandRXinputconditionsanddisableanypull-highresistoroptionwhichmayexistontheTXandRXpins.WhentheTXorRXpinfunctionisdisabledbyclearingtheUARTEN,TXENorRXENbit,theTXorRXpinwillbeusedasI/Oorotherpin-sharedfunctionalpindependinguponthepin-sharedfunctionpriority.

UART Data Transfer SchemeTheblockdiagramshowstheoveralldatatransferstructurearrangementfortheUARTinterface.Theactualdata tobe transmittedfromtheMCUis first transferred to theTXRregisterby theapplicationprogram.ThedatawillthenbetransferredtotheTransmitShiftRegisterfromwhereitwillbeshiftedout,LSBfirst,ontotheTXpinataratecontrolledbytheBaudRateGenerator.OnlytheTXRregisterismappedontotheMCUDataMemory,theTransmitShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.

DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereit isshiftedin,LSBfirst, to theReceiverShiftRegisterataratecontrolledbytheBaudRateGenerator.Whentheshiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternalRXRregister,whereit isbufferedandcanbemanipulatedbytheapplicationprogram.OnlytheRXRregisterismappedontotheMCUDataMemory,theReceiverShiftRegisterisnotmappedandisthereforeinaccessibletotheapplicationprogram.

Itshouldbenotedthattheactualregisterfordatatransmissionandreception,althoughreferredtointhetext,andinapplicationprograms,asseparateTXRandRXRregisters,onlyexistsasasinglesharedregisterintheDataMemory.ThissharedregisterknownastheTXR_RXRregisterisusedforbothdatatransmissionanddatareception.

UART Status and Control RegistersTherearefivecontrolregistersassociatedwiththeUARTfunction.TheUSR,UCR1andUCR2registerscontroltheoverallfunctionoftheUART,whiletheBRGregistercontrolstheBaudrate.TheactualdatatobetransmittedandreceivedontheserialinterfaceismanagedthroughtheTXR_RXRdataregister.

Register Name

Bit

7 6 5 4 3 2 1 0USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF

UCR1 U�RTEN BNO PREN PRT STOPS TXBRK RX8 TX8UCR2 TXEN RXEN BRGH �DDEN W�KE RIE TIIE TEIE

TXR_RXR TXRX� TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0BRG BRG� BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0

UART Registers List

Rev. 1.20 138 ��st 2�� 201� Rev. 1.20 13� ��st 2�� 201�



TXR_RXR RegisterTheTXR_RXRregisteristhedataregisterwhichisusedtostorethedatatobetransmittedontheTXpinorbeingreceivedfromtheRXpin.

Bit 7 6 5 4 3 2 1 0Name TXRX� TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: �nknownBit7~0 TXRX7~TXRX0:UARTTransmit/ReceiveDatabits

USR RegisterTheUSR register is the status register for theUART,whichcanbe readby theprogram todeterminethepresentstatusoftheUART.AllflagswithintheUSRregisterarereadonlyandfurtherexplanationsaregivenbelow:

Bit 7 6 5 4 3 2 1 0Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIFR/W R R R R R R R RPOR 0 0 0 0 1 0 1 1

Bit7 PERR:Parityerrorflag0:Noparityerrorisdetected1:Parityerrorisdetected

ThePERRflagistheparityerrorflag.Whenthisreadonlyflagis“0”,itindicatesaparityerrorhasnotbeendetected.Whentheflagis“1”,itindicatesthattheparityofthereceivedwordisincorrect.ThiserrorflagisapplicableonlyifParitymode(oddoreven)isselected.TheflagcanalsobeclearedbyasoftwaresequencewhichinvolvesareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit6 NF:Noiseflag0:Nonoiseisdetected1:Noiseisdetected

TheNFflagis thenoiseflag.Whenthisreadonlyflagis“0”, it indicatesnonoisecondition.Whentheflagis“1”,itindicatesthattheUARThasdetectednoiseonthereceiverinput.TheNFflagissetduringthesamecycleastheRXIFflagbutwillnotbesetinthecaseofasoverrun.TheNFflagcanbeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit5 FERR:Framingerrorflag0:Noframingerrorisdetected1:Framingerrorisdetected

TheFERRflagistheframingerrorflag.Whenthisreadonlyflagis“0”,itindicatesthat thereisnoframingerror.Whentheflagis“1”, it indicates thataframingerrorhasbeendetectedforthecurrentcharacter.TheflagcanalsobeclearedbyasoftwaresequencewhichwillinvolveareadtothestatusregisterUSRfollowedbyanaccesstotheRXRdataregister.

Bit4 OERR:Overrunerrorflag0:Nooverrunerrorisdetected1:Overrunerrorisdetected

TheOERRflagistheoverrunerrorflagwhichindicateswhenthereceiverbufferhasoverflowed.Whenthisreadonlyflagis“0”,itindicatesthatthereisnooverrunerror.Whentheflagis“1”,itindicatesthatanoverrunerroroccurswhichwillinhibitfurthertransferstotheRXRreceivedataregister.Theflagisclearedbyasoftwaresequence,which isa read to thestatusregisterUSRfollowedbyanaccess to theRXRdataregister.

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Bit3 RIDLE:Receiverstatus0:Datareceptionisinprogress(databeingreceived)1:Nodatareceptionisinprogress(receiverisidle)

TheRIDLEflagisthereceiverstatusflag.Whenthisreadonlyflagis“0”,itindicatesthatthereceiverisbetweentheinitialdetectionofthestartbitandthecompletionofthestopbit.Whentheflagis“1”, it indicates that thereceiver is idle.Betweenthecompletionofthestopbitandthedetectionofthenextstartbit,theRIDLEbitis“1”indicatingthattheUARTreceiverisidleandtheRXpinstaysinlogichighcondition.

Bit2 RXIF:ReceiveRXRdataregisterstatus0:RXRdataregisterisempty1:RXRdataregisterhasavailabledata

TheRXIFflagisthereceivedataregisterstatusflag.Whenthisreadonlyflagis“0”,itindicatesthattheRXRreaddataregisterisempty.Whentheflagis“1”,itindicatesthat theRXRreaddataregistercontainsnewdata.When thecontentsof theshiftregisteraretransferredtotheRXRregister,aninterruptisgeneratedifRIE=1intheUCR2register.Ifoneormoreerrorsaredetectedinthereceivedword,theappropriatereceive-relatedflagsNF,FERR,and/orPERRaresetwithinthesameclockcycle.TheRXIFflagisclearedwhentheUSRregisterisreadwithRXIFset,followedbyareadfromtheRXRregister,andiftheRXRregisterhasnodataavailable.

Bit1 TIDLE:Transmissionstatus0:Datatransmissionisinprogress(databeingtransmitted)1:Nodatatransmissionisinprogress(transmitterisidle)

TheTIDLEflag isknownas the transmissioncompleteflag.Whenthis readonlyflagis“0”,it indicatesthatatransmissionisinprogress.Thisflagwillbesetto“1”whentheTXIFflagis“1”andwhenthereisnotransmitdataorbreakcharacterbeingtransmitted.WhenTIDLEisequalto1, theTXpinbecomesidlewiththepinstateinlogichighcondition.TheTIDLEflagisclearedbyreadingtheUSRregisterwithTIDLEsetandthenwritingtotheTXRregister.Theflagisnotgeneratedwhenadatacharacterorabreakisqueuedandreadytobesent.

Bit0 TXIF:TransmitTXRdataregisterstatus0:Characterisnottransferredtothetransmitshiftregister1:Characterhastransferredtothetransmitshiftregister(TXRdataregisterisempty)

TheTXIFflagisthetransmitdataregisteremptyflag.Whenthisreadonlyflagis“0”,itindicatesthatthecharacterisnottransferredtothetransmittershiftregister.Whentheflagis“1”,it indicatesthatthetransmittershiftregisterhasreceivedacharacterfromtheTXRdataregister.TheTXIFflag isclearedbyreadingtheUARTstatusregister(USR)withTXIFsetandthenwriting to theTXRdataregister.Note thatwhentheTXENbit isset, theTXIFflagbitwillalsobesetsincethetransmitdataregisterisnotyetfull.

Rev. 1.20 140 ��st 2�� 201� Rev. 1.20 141 ��st 2�� 201�



UCR1 RegisterTheUCR1registertogetherwiththeUCR2registerarethetwoUARTcontrolregistersthatareusedtosetthevariousoptionsfortheUARTfunctionsuchasoverallon/offcontrol,paritycontrol,datatransferbitlength,etc.Furtherexplanationoneachofthebitsisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name U�RTEN BNO PREN PRT STOPS TXBRK RX8 TX8R/W R/W R/W R/W R/W R/W R/W R WPOR 0 0 0 0 0 0 x 0

“x”: �nknownBit7 UARTEN:UARTfunctionenablecontrol

0:DisableUART.TXandRXpinsareusedasI/Oorotherpin-sharedfunctionalpins1:EnableUART.TXandRXpinsfunctionasUARTpins

TheUARTENbit is theUARTenablebit.Whenthisbit isequalto“0”,theUARTwillbedisabledandtheRXpinaswellastheTXpinwillbesetasI/Oorotherpin-sharedfunctionalpins.Whenthebit isequal to“1”, theUARTwillbeenabledandtheTXandRXpinswillfunctionasdefinedbytheTXENandRXENenablecontrolbits.WhentheUARTisdisabled,itwillemptythebuffersoanycharacterremaininginthebufferwillbediscarded.Inaddition,thevalueofthebaudratecounterwillbereset.IftheUARTisdisabled,allerrorandstatusflagswillbereset.AlsotheTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbitswillbecleared,whiletheTIDLE,TXIFandRIDLEbitswillbeset.Othercontrolbits inUCR1,UCR2andBRGregisterswillremainunaffected.IftheUARTisactiveandtheUARTENbitiscleared,allpendingtransmissionsandreceptionswillbeterminatedandthemodulewillberesetasdefinedabove.WhentheUARTisre-enabled, itwill restart in thesameconfiguration.

Bit6 BNO:Numberofdatatransferbitsselection0:8-bitdatatransfer1:9-bitdatatransfer

Thisbit isusedtoselect thedata lengthformat,whichcanhaveachoiceofeither8-bitor9-bitformat.Whenthisbitisequalto“1”,a9-bitdatalengthformatwillbeselected.Ifthebitisequalto“0”,thenan8-bitdatalengthformatwillbeselected.If9-bitdatalengthformatisselected,thenbitsRX8andTX8willbeusedtostorethe9thbitofthereceivedandtransmitteddatarespectively.Note:1.IfBNO=1(9-bitdatatransferformat)andwhentheparityfunctionisenabled,

the9thdataisaparitybitsinceitwillnotbetransferredtoRX8.2.IfBNO=0(8-bitdatatransferformat)andwhentheparityfunctionisenabled,

the8thdataisaparitybitsinceitwillnotbetransferredtoRX7.Bit5 PREN:Parityfunctionenablecontrol

0:Parityfunctionisdisabled1:Parityfunctionisenabled

Thisbitistheparityfunctionenablebit.Whenthisbitisequalto1,theparityfunctionwillbeenabled.Ifthebitisequalto0,thentheparityfunctionwillbedisabled.

Bit4 PRT:Paritytypeselectionbit0:Evenparityforparitygenerator1:Oddparityforparitygenerator

Thisbitistheparitytypeselectionbit.Whenthisbitisequalto1,oddparitytypewillbeselected.Ifthebitisequalto0,thenevenparitytypewillbeselected.

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Bit3 STOPS:Numberofstopbitsselection0:Onestopbitformatisused1:Twostopbitsformatisused

ThisbitdeterminesifoneortwostopbitsaretobeusedforTX.Whenthisbitisequalto“1”,twostopbitsformatareused.Ifthebitisequalto“0”,thenonlyonestopbitformatisused.

Bit2 TXBRK:Transmitbreakcharacter0:Nobreakcharacteristransmitted1:Breakcharacterstransmit

TheTXBRKbit is theTransmitBreakCharacterbit.Whenthisbit isequal to“0”,therearenobreakcharactersand theTXpinoperatesnormally.When thebit isequal to“1”, therearetransmitbreakcharactersandthetransmitterwillsendlogiczeros.Whenthisbitisequalto“1”,afterthebuffereddatahasbeentransmitted,thetransmitteroutputisheldlowforaminimumofa13-bitlengthanduntiltheTXBRKbitisreset.

Bit1 RX8:Receivedatabit8for9-bitdatatransferformat(readonly)Thisbitisonlyusedif9-bitdatatransfersareused,inwhichcasethisbitlocationwillstorethe9thbitofthereceiveddataknownasRX8.TheBNObitisusedtodeterminewhetherdatatransfersarein8-bitor9-bitformat.

Bit0 TX8:Transmitdatabit8for9-bitdatatransferformat(writeonly)Thisbit isonlyusedif9-bitdata transfersareused, inwhichcasethisbit locationwillstorethe9thbitofthetransmitteddataknownasTX8.TheBNObitisusedtodeterminewhetherdatatransfersarein8-bitor9-bitformat.

UCR2 RegisterTheUCR2registeris thesecondoftheUARTcontrolregistersandservesseveralpurposes.Oneofitsmainfunctionsistocontrolthebasicenable/disableoperationif theUARTTransmitterandReceiveraswellasenablingthevariousUARTinterruptsources.Theregisteralsoservestocontrolthebaudratespeed, receiverwake-upfunctionenableand theaddressdetect functionenable.Furtherexplanationoneachofthebitsisgivenbelow:

Bit 7 6 5 4 3 2 1 0Name TXEN RXEN BRGH �DDEN W�KE RIE TIIE TEIER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TXEN:UARTTransmitterenablecontrol0:UARTTransmitterisdisabled1:UARTTransmitterisenabled

ThebitnamedTXENistheTransmitterEnableBit.Whenthisbitisequalto“0”,thetransmitterwillbedisabledwithanypendingdata transmissionsbeingaborted. Inadditionthebufferswillbereset.InthissituationtheTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.IftheTXENbitisequalto“1”andtheUARTENbitisalsoequalto1,thetransmitterwillbeenabledandtheTXpinwillbecontrolledbytheUART.ClearingtheTXENbitduringatransmissionwillcausethedatatransmissiontobeabortedandwillresetthetransmitter.Ifthissituationoccurs,theTXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.

Rev. 1.20 142 ��st 2�� 201� Rev. 1.20 143 ��st 2�� 201�



Bit6 RXEN:UARTReceiverenablecontrol0:UARTReceiverisdisabled1:UARTReceiverisenabled

ThebitnamedRXENistheReceiverEnableBit.Whenthisbit isequalto“0”,thereceiverwillbedisabledwithanypendingdatareceptionsbeingaborted.Inadditionthereceiverbufferswillbereset.InthissituationtheRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.IftheRXENbitisequalto“1”andtheUARTENbitisalsoequalto1,thereceiverwillbeenabledandtheRXpinwillbecontrolledbytheUART.ClearingtheRXENbitduringareceptionwillcausethedatareceptiontobeabortedandwillresetthereceiver.Ifthissituationoccurs,theRXpinwillbeusedasanI/Oorotherpin-sharedfunctionalpin.

Bit5 BRGH:BaudRatespeedselection0:Lowspeedbaudrate1:Highspeedbaudrate

ThebitnamedBRGHselectsthehighorlowspeedmodeoftheBaudRateGenerator.Thisbit, togetherwiththevalueplacedinthebaudrateregister,BRG,controls thebaudrateoftheUART.Ifthebitisequalto0,thelowspeedmodeisselected.

Bit4 ADDEN:Addressdetectfunctionenablecontrol0:Addressdetectionfunctionisdisabled1:Addressdetectionfunctionisenabled

ThebitnamedADDENistheaddressdetectionfunctionenablecontrolbit.Whenthisbitisequalto1,theaddressdetectionfunctionisenabled.Whenitoccurs,ifthe8thbit,whichcorrespondstoRX7ifBNO=0,orthe9thbit,whichcorrespondstoRX8ifBNO=1,hasavalueof“1”,thenthereceivedwordwillbeidentifiedasanaddress,ratherthandata.Ifthecorrespondinginterruptisenabled,aninterruptrequestwillbegeneratedeachtimethereceivedwordhastheaddressbitset,whichisthe8thor9thbitdependingonthevalueoftheBNObit.Iftheaddressbitknownasthe8thor9thbitofthereceivedwordis“0”withtheaddressdetectionfunctionbeingenabled,aninterruptwillnotbegeneratedandthereceiveddatawillbediscarded.

Bit3 WAKE:RXpinfallingedgewake-upfunctionenablecontrol0:RXpinwake-upfunctionisdisabled1:RXpinwake-upfunctionisenabled

Thebitenablesordisablesthereceiverwake-upfunction.Ifthisbitisequalto1andthedeviceisinIDLE0orSLEEPmode,afallingedgeontheRXpinwillwakeupthedevice.Ifthisbitisequalto0andthedeviceisintheIDLEorSLEEPmode,anyedgetransitionsontheRXpinwillnotwakeupthedevice.

Bit2 RIE:Receiverinterruptenablecontrol0:Receiverrelatedinterruptisdisabled1:Receiverrelatedinterruptisenabled

Thebitenablesordisablesthereceiverinterrupt.Ifthisbitisequalto1andwhenthereceiveroverrunflagOERRorreceiveddataavailableflagRXIFisset, theUARTinterruptrequestflagwillbeset.Ifthisbitisequalto0,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheOERRorRXIFflags.

Bit1 TIIE:TransmitterIdleinterruptenablecontrol0:Transmitteridleinterruptisdisabled1:Transmitteridleinterruptisenabled

Thebitenablesordisablesthetransmitteridleinterrupt.If thisbit isequalto1andwhenthetransmitter idleflagTIDLEisset,duetoa transmitter idlecondition, theUARTinterruptrequestflagwillbeset.If thisbit isequalto0,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTIDLEflag.

Rev. 1.20 142 ��st 2�� 201� Rev. 1.20 143 ��st 2�� 201�



Bit0 TEIE:TransmitterEmptyinterruptenablecontrol0:Transmitteremptyinterruptisdisabled1:Transmitteremptyinterruptisenabled

Thebitenablesordisablesthetransmitteremptyinterrupt.Ifthisbitisequalto1andwhenthetransmitteremptyflagTXIFisset,duetoatransmitteremptycondition,theUARTinterruptrequestflagwillbeset.If thisbit isequalto0,theUARTinterruptrequestflagwillnotbeinfluencedbytheconditionoftheTXIFflag.

Baud Rate GeneratorTosetupthespeedoftheserialdatacommunication,theUARTfunctioncontainsitsowndedicatedbaudrategenerator.Thebaudrateiscontrolledbyitsowninternalfreerunning8-bitcounter, theperiodofwhichisdeterminedbytwofactors.Thefirstof these is thevalueplacedin theBRGregisterandthesecondisthevalueoftheBRGHbitwithintheUCR2controlregister.TheBRGHbitdecides,ifthebaudrategeneratoristobeusedinahighspeedmodeorlowspeedmode,whichinturndeterminestheformulathatisusedtocalculatethebaudrate.ThevalueintheBRGregister,N,whichisusedinthefollowingbaudratecalculationformuladeterminesthedivisionfactor.NotethatNisthedecimalvalueplacedintheBRGregisterandhasarangeofbetween0and255.

UCR2 BRGH Bit 0 1

Ba�d Rate (BR)fSYS

[64(N+1)]fSYS

[16(N+1)]

ByprogrammingtheBRGHbitwhichallowsselectionoftherelatedformulaandprogrammingtherequiredvalueintheBRGregister,therequiredbaudratecanbesetup.Notethatbecausetheactualbaudrateisdeterminedusingadiscretevalue,N,placedintheBRGregister,therewillbeanerrorassociatedbetweentheactualandrequestedvalue.ThefollowingexampleshowshowtheBRGregistervalueNandtheerrorvaluecanbecalculated.

BRG Register

Bit 7 6 5 4 3 2 1 0Name BRG� BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR x x x x x x x x

“x”: �nknownBit7~0 BRG7~BRG0:BaudRatevalues

ByprogrammingtheBRGHbit intheUCR2registerwhichallowsselectionof therelatedformuladescribedaboveandprogramming therequiredvalue in theBRGregister,therequiredbaudratecanbesetup.

Rev. 1.20 144 ��st 2�� 201� Rev. 1.20 145 ��st 2�� 201�



Calculating the Baud Rate and Error ValuesForaclockfrequencyof4MHz,andwithBRGHsetto0determinetheBRGregistervalueN,theactualbaudrateandtheerrorvalueforadesiredbaudrateof4800.

FromtheabovetablethedesiredbaudrateBR=fSYS

[64(N+1)]

Re-arrangingthisequationgivesN=fSYS

(BR×64) -1

GivingavalueforN=4000000(4800×64) -1=12.0208

Toobtaintheclosestvalue,adecimalvalueof12shouldbeplacedintotheBRGregister.ThisgivesanactualorcalculatedbaudratevalueofBR=

4000000[64(12+1)] =4808

Thereforetheerrorisequalto4808-4800

4800 =0.16%Thefollowing tablesshowtheactualvaluesofbaudrateanderrorvaluesfor the twovalueofBRGH.

BaudRate

K/BPS

Baud Rates for BRGH=0

fSYS=4MHz fSYS=3.579545MHz fSYS=7.159MHz

BRG Kbaud Error(%) BRG Kbaud Error(%) BRG Kbaud Error(%)0.3 20� 0.300 0.16 185 0.300 0.00 — — —1.2 51 1.202 0.16 46 1.1�0 -0.83 �2 1.203 0.232.4 25 2.404 0.16 22 2.432 1.32 46 2.380 -0.834.8 12 4.808 0.16 11 4.661 -2.�0 22 4.863 1.32�.6 6 8.�2� -6.�� 5 �.321 -2.�0 11 �.322 -2.�0

1�.2 2 20.833 8.51 2 18.643 -2.�0 5 18.643 -2.�038.4 — — — — — — 2 32.286 -2.�05�.6 0 62.500 8.51 0 55.�30 -2.�0 1 55.�30 -2.�0115.2 — — — — — — 0 111.85� -2.�0

Baud Rates and Error Values for BRGH=0

BaudRate

K/BPS

Baud Rates for BRGH=1

fSYS=4MHz fSYS=3.579545MHz fSYS=7.159MHz

BRG Kbaud Error(%) BRG Kbaud Error(%) BRG Kbaud Error(%)0.3 — — — — — — — — —1.2 20� 1.202 0.16 185 1.203 0.23 — — —2.4 103 2.404 0.16 �2 2.406 0.23 185 2.406 0.234.8 51 4.808 0.16 46 4.�6 -0.83 �2 4.811 0.23�.6 25 �.615 0.16 22 �.�2� 1.32 46 �.520 -0.83

1�.2 12 1�.231 0.166 11 18.643 -2.�0 22 1�.454 1.3238.4 6 35.�14 -6.�� 5 3�.286 -2.�0 11 3�.286 -2.�05�.6 3 62.5 8.51 3 55.�30 -2.�0 � 55.�30 -2.�0115.2 1 125 8.51 1 111.86 -2.�0 3 111.86 -2.�0250 0 250 0 — — — — — —

Baud Rates and Error Values for BRGH=1

Rev. 1.20 144 ��st 2�� 201� Rev. 1.20 145 ��st 2�� 201�



UART Setup and ControlFordatatransfer,theUARTfunctionutilizesanon-return-to-zero,morecommonlyknownasNRZ,format.Thisiscomposedofonestartbit,eightorninedatabitsandoneor twostopbits.ParityissupportedbytheUARThardwareandcanbesetuptobeeven,oddornoparity.Forthemostcommondataformat,8databitsalongwithnoparityandonestopbit,denotedas8,N,1,isusedasthedefaultsetting,whichisthesettingatpower-on.Thenumberofdatabitsandstopbits,alongwiththeparity,aresetupbyprogrammingthecorrespondingBNO,PRT,PRENandSTOPSbitsintheUCR1register.Thebaudrateusedtotransmitandreceivedataissetupusingtheinternal8-bitbaudrategenerator,whilethedataistransmittedandreceivedLSBfirst.AlthoughthetransmitterandreceiveroftheUARTarefunctionallyindependent,theybothusethesamedataformatandbaudrate.Inallcasesstopbitswillbeusedfordatatransmission.

Enabling/Disabling the UART InterfaceThebasicon/offfunctionoftheinternalUARTfunctioniscontrolledusingtheUARTENbitintheUCR1register.IftheUARTEN,TXENandRXENbitsareset,thenthesetwoUARTpinswillactasnormalTXoutputpinandRXinputpinrespectively.IfnodataisbeingtransmittedontheTXpin,thenitwilldefaulttoalogichighvalue.

ClearingtheUARTENbitwilldisabletheTXandRXpinsandthesetwopinswillbeusedasanI/Oorotherpin-sharedfunctionalpin.WhentheUARTfunction isdisabled, thebufferwillberesettoanemptycondition,atthesametimediscardinganyremainingresidualdata.DisablingtheUARTwillalsoresettheenablecontrol,theerrorandstatusflagswithbitsTXEN,RXEN,TXBRK,RXIF,OERR,FERR,PERRandNFbeingclearedwhilebitsTIDLE,TXIFandRIDLEwillbeset.Theremainingcontrolbits in theUCR1,UCR2andBRGregisterswill remainunaffected.If theUARTENbit in theUCR1register isclearedwhile theUARTisactive, thenallpendingtransmissionsand receptionswillbe immediatelysuspendedand theUARTwillbe reset toaconditionasdefinedabove.IftheUARTisthensubsequentlyre-enabled,itwillrestartagaininthesameconfiguration.

Data, Parity and Stop Bit SelectionTheformatof thedata tobe transferred iscomposedofvariousfactorssuchasdatabit length,parityon/off,paritytype,addressbitsandthenumberofstopbits.ThesefactorsaredeterminedbythesetupofvariousbitswithintheUCR1register.TheBNObitcontrols thenumberofdatabitswhichcanbesettoeither8or9.ThePRTbitcontrolsthechoiceifoddorevenparity.ThePRENbitcontrolstheparityon/offfunction.TheSTOPSbitdecideswhetheroneortwostopbitsaretobeused.Thefollowingtableshowsvariousformatsfordatatransmission.Theaddressdetectmodecontrolbitidentifiestheframeasanaddresscharacter.Thenumberofstopbits,whichcanbeeitheroneortwo,isindependentofthedatalength.

Start Bit Data Bits Address Bits Parity Bit Stop BitExample of 8-bit Data Formats

1 8 0 0 11 � 0 1 11 � 1 0 1

Example of 9-bit Data Formats1 � 0 0 11 8 0 1 11 8 1 0 1

Transmitter Receiver Data Format

Thefollowingdiagramshows the transmitandreceivewaveformsforboth8-bitand9-bitdataformats.

Rev. 1.20 146 ��st 2�� 201� Rev. 1.20 14� ��st 2�� 201�



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UART TransmitterDatawordlengthsofeither8or9bitscanbeselectedbyprogrammingtheBNObitintheUCR1register.WhenBNObitisset,thewordlengthwillbesetto9bits.Inthiscasethe9thbit,whichistheMSB,needstobestoredintheTX8bitintheUCR1register.AtthetransmittercoreliestheTransmitterShiftRegister,morecommonlyknownas theTSR,whosedata isobtainedfromthetransmitdataregister,whichisknownas theTXRregister.Thedata tobe transmittedis loadedintothisTXRregisterbytheapplicationprogram.TheTSRregisterisnotwrittentowithnewdatauntilthestopbitfromtheprevioustransmissionhasbeensentout.Assoonasthisstopbithasbeentransmitted,theTSRcanthenbeloadedwithnewdatafromtheTXRregister, ifit isavailable.ItshouldbenotedthattheTSRregister,unlikemanyotherregisters, isnotdirectlymappedintotheDataMemoryareaandassuch isnotavailable to theapplicationprogramfordirect read/writeoperations.AnactualtransmissionofdatawillnormallybeenabledwhentheTXENbitisset,butthedatawillnotbetransmitteduntiltheTXRregisterhasbeenloadedwithdataandthebaudrategeneratorhasdefinedashiftclocksource.However,thetransmissioncanalsobeinitiatedbyfirstloadingdataintotheTXRregister,afterwhichtheTXENbitcanbeset.Whenatransmissionofdatabegins,theTSRisnormallyempty,inwhichcaseatransfertotheTXRregisterwillresultinanimmediatetransfertotheTSR.IfduringatransmissiontheTXENbitiscleared,thetransmissionwillimmediatelyceaseandthetransmitterwillbereset.TheTXoutputpinwillthenreturntotheI/Oorotherpin-sharedfunction.

Transmitting DataWhentheUARTistransmittingdata,thedataisshiftedontheTXpinfromtheshiftregister,withtheleastsignificantbitLSBfirst.Inthetransmitmode,theTXRregisterformsabufferbetweentheinternalbusandthetransmittershiftregister.Itshouldbenotedthatif9-bitdataformathasbeenselected,thentheMSBwillbetakenfromtheTX8bitintheUCR1register.Thestepstoinitiateadatatransfercanbesummarizedasfollows:

• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodefinetherequiredwordlength,paritytypeandnumberofstopbits.

• SetuptheBRGregistertoselectthedesiredbaudrate.

• Set theTXENbit toensurethat theUARTtransmitterisenabledandtheTXpinisusedasaUARTtransmitterpin.

• AccesstheUSRregisterandwritethedatathatistobetransmittedintotheTXRregister.NotethatthisstepwillcleartheTXIFbit.

Thissequenceofeventscannowberepeatedtosendadditionaldata.ItshouldbenotedthatwhenTXIF=0,datawillbeinhibitedfrombeingwrittentotheTXRregister.ClearingtheTXIFflagisalwaysachievedusingthefollowingsoftwaresequence:

1.AUSRregisteraccess

2.ATXRregisterwriteexecution

Rev. 1.20 146 ��st 2�� 201� Rev. 1.20 14� ��st 2�� 201�



Theread-onlyTXIFflagissetbytheUARThardwareandifsetindicatesthattheTXRregisterisemptyandthatotherdatacannowbewrittenintotheTXRregisterwithoutoverwritingthepreviousdata.IftheTEIEbitisset,thentheTXIFflagwillgenerateaninterrupt.Duringadatatransmission,awrite instruction to theTXRregisterwillplace thedata into theTXRregister,whichwillbecopiedtotheshiftregisterattheendofthepresenttransmission.Whenthereisnodatatransmissioninprogress,awriteinstructiontotheTXRregisterwillplacethedatadirectlyintotheshiftregister,resultinginthecommencementofdatatransmission,andtheTXIFbitbeingimmediatelyset.Whenaframetransmissioniscomplete,whichhappensafterstopbitsaresentorafterthebreakframe,theTIDLEbitwillbeset.TocleartheTIDLEbitthefollowingsoftwaresequenceisused:


2.ATXRregisterwriteexecution

NotethatboththeTXIFandTIDLEbitsareclearedbythesamesoftwaresequence.

Transmitting BreakIf theTXBRKbit isset, then thebreakcharacterswillbesenton thenext transmission.Breakcharacter transmissionconsistsofastartbit, followedby13xN“0”bits,whereN=1,2,etc. ifabreakcharacteristobetransmitted,thentheTXBRKbitmustbefirstsetbytheapplicationprogramandthenclearedtogeneratethestopbits.Transmittingabreakcharacterwillnotgenerateatransmitinterrupt.Notethatabreakconditionlengthisatleast13bitslong.IftheTXBRKbitiscontinuallykeptatalogichighlevel, thenthetransmittercircuitrywill transmitcontinuousbreakcharacters.AftertheapplicationprogramhasclearedtheTXBRKbit,thetransmitterwillfinishtransmittingthelastbreakcharacterandsubsequentlysendoutoneortwostopbits.Theautomaticlogichighattheendofthelastbreakcharacterwillensurethatthestartbitofthenextframeisrecognized.

UART ReceiverTheUARTiscapableofreceivingwordlengthsofeither8or9bitscanbeselectedbyprogrammingtheBNObit intheUCR1register.WhenBNObit isset, thewordlengthwillbeset to9bits.Inthiscasethe9thbit,whichistheMSB,willbestoredintheRX8bitintheUCR1register.AtthereceivercoreliestheReceiverShiftRegistermorecommonlyknownastheRSR.ThedatawhichisreceivedontheRXexternalinputpinissenttothedatarecoveryblock.Thedatarecoveryblockoperatingspeedis16timesthatofthebaudrate,whilethemainreceiveserialshifteroperatesatthebaudrate.AftertheRXpinissampledforthestopbit,thereceiveddatainRSRistransferredtothereceivedataregister,iftheregisterisempty.ThedatawhichisreceivedontheexternalRXinputpinissampledthreetimesbyamajoritydetectcircuittodeterminethelogiclevelthathasbeenplacedontotheRXpin.ItshouldbenotedthattheRSRregister,unlikemanyotherregisters,isnotdirectlymappedintotheDataMemoryareaandassuchisnotavailabletotheapplicationprogramfordirectread/writeoperations.

Receiving DataWhentheUARTreceiverisreceivingdata,thedataisseriallyshiftedinontheexternalRXinputpintotheshiftregister,withtheleastsignificantbitLSBfirst.TheRXRregisterisatwobytedeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOwhilethethirdbytecancontinuetobereceived.NotethattheapplicationprogrammustensurethatthedataisreadfromRXRbeforethethirdbytehasbeencompletelyshiftedin,otherwisethethirdbytewillbediscardedandanoverrunerrorOERRwillbesubsequentlyindicated.Thestepstoinitiateadatatransfercanbesummarizedasfollows:

Rev. 1.20 148 ��st 2�� 201� Rev. 1.20 14� ��st 2�� 201�



• MakethecorrectselectionoftheBNO,PRT,PRENandSTOPSbitstodefinetherequiredwordlength,paritytypeandnumberofstopbits.

• SetuptheBRGregistertoselectthedesiredbaudrate.

• SettheRXENbittoensurethattheUARTreceiverisenabledandtheRXpinisusedasaUARTreceiverpin.

Atthispointthereceiverwillbeenabledwhichwillbegintolookforastartbit.

Whenacharacterisreceived,thefollowingsequenceofeventswilloccur:

• TheRXIFbitintheUSRregisterwillbesetthenRXRregisterhasdataavailable,atleastonemorecharactercanberead.

• WhenthecontentsoftheshiftregisterhavebeentransferredtotheRXRregisterandiftheRIEbitisset,thenaninterruptwillbegenerated.

• Ifduringreception,aframeerror,noiseerror,parityerrororanoverrunerrorhasbeendetected,thentheerrorflagscanbeset.

TheRXIFbitcanbeclearedusingthefollowingsoftwaresequence:


2.ARXRregisterreadexecution

Receiving BreakAnybreakcharacterreceivedbytheUARTwillbemanagedasaframingerror.ThereceiverwillcountandexpectacertainnumberofbittimesasspecifiedbythevaluesprogrammedintotheBNOandSTOPSbits.Ifthebreakismuchlongerthan13bittimes,thereceptionwillbeconsideredascompleteafterthenumberofbittimesspecifiedbyBNOandSTOPS.TheRXIFbitisset,FERRisset,zerosareloadedintothereceivedataregister,interruptsaregeneratedifappropriateandtheRIDLEbitisset.Ifalongbreaksignalhasbeendetectedandthereceiverhasreceivedastartbit,thedatabitsandtheinvalidstopbit,whichsetstheFERRflag,thereceivermustwaitforavalidstopbitbefore lookingfor thenextstartbit.Thereceiverwillnotmaketheassumptionthat thebreakconditiononthelineisthenextstartbit.AbreakisregardedasacharacterthatcontainsonlyzeroswiththeFERRflagset.Thebreakcharacterwillbeloadedintothebufferandnofurtherdatawillbereceiveduntilstopbitsarereceived.ItshouldbenotedthattheRIDLEreadonlyflagwillgohighwhenthestopbitshavenotyetbeenreceived.ThereceptionofabreakcharacterontheUARTregisterswillresultinthefollowing:

• Theframingerrorflag,FERR,willbeset.

• Thereceivedataregister,RXR,willbecleared.

• TheOERR,NF,PERR,RIDLEorRXIFflagswillpossiblybeset.

Idle StatusWhenthereceiverisreadingdata,whichmeansitwillbeinbetweenthedetectionofastartbitandthereadingofastopbit,thereceiverstatusflagintheUSRregister,otherwiseknownastheRIDLEflag,willhaveazerovalue.Inbetweenthereceptionofastopbitandthedetectionofthenextstartbit,theRIDLEflagwillhaveahighvalue,whichindicatesthereceiverisinanidlecondition.

Receiver InterruptThereadonlyreceiveinterruptflagRXIFintheUSRregister issetbyanedgegeneratedbythereceiver.Aninterrupt isgenerated ifRIE=1,whenawordis transferredfromtheReceiveShiftRegister,RSR,totheReceiveDataRegister,RXR.AnoverrunerrorcanalsogenerateaninterruptifRIE=1.

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Managing Receiver ErrorsSeveraltypesofreceptionerrorscanoccurwithintheUARTmodule,thefollowingsectiondescribesthevarioustypesandhowtheyaremanagedbytheUART.

Overrun Error – OERRTheRXRregisteriscomposedofatwobytedeepFIFOdatabuffer,wheretwobytescanbeheldintheFIFOregister,whileathirdbytecancontinuetobereceived.Beforethethirdbytehasbeenentirelyshiftedin,thedatashouldbereadfromtheRXRregister.If thisisnotdone,theoverrunerrorflagOERRwillbeconsequentlyindicated.

Intheeventofanoverrunerroroccurring,thefollowingwillhappen:

• TheOERRflagintheUSRregisterwillbeset.

• TheRXRcontentswillnotbelost.

• Theshiftregisterwillbeoverwritten.

• AninterruptwillbegeneratediftheRIEbitisset.

TheOERRflagcanbeclearedbyanaccess to theUSRregisterfollowedbyareadto theRXRregister.

Noise Error – NFOver-sampling isusedfordata recovery to identifyvalid incomingdataandnoise. Ifnoise isdetectedwithinaframe,thefollowingwilloccur:

• Thereadonlynoiseflag,NF,intheUSRregisterwillbesetontherisingedgeoftheRXIFbit.

• DatawillbetransferredfromtheshiftregistertotheRXRregister.

• Nointerruptwillbegenerated.Howeverthisbitrisesat thesametimeastheRXIFbitwhichitselfgeneratesaninterrupt.

NotethattheNFflagisresetbyaUSRregisterreadoperationfollowedbyanRXRregisterreadoperation.

Framing Error – FERRThereadonlyframingerrorflag,FERR,intheUSRregister,issetifazeroisdetectedinsteadofstopbits.Iftwostopbitsareselected,onlyfirststopbitisdetected,itmustbehigh.Iffirststopbitislow,theFERRflagwillbeset.TheFERRflagisbufferedalongwiththereceiveddataandisclearedinanyreset.

Parity Error – PERRThereadonlyparityerrorflag,PERR,intheUSRregister,issetiftheparityofthereceivedwordisincorrect.Thiserrorflagisonlyapplicableiftheparityfunctionisenabled,PREN=1,andiftheparitytype,oddoreven,isselected.ThereadonlyPERRflagisbufferedalongwiththereceiveddatabytes.Itisclearedonanyreset,itshouldbenotedthattheFERRandPERRflagsarebufferedalongwiththecorrespondingwordandshouldbereadbeforereadingthedataword.

Rev. 1.20 150 ��st 2�� 201� Rev. 1.20 151 ��st 2�� 201�



UART Interrupt StructureSeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist,a lowpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsareatransmitterdataregisterempty, transmitter idle,receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Whenanyof theseconditionsarecreated, if itscorrespondinginterruptcontrol isenabledandthestackisnotfull, theprogramwill jumpto itscorrespondinginterruptvectorwhere itcanbeservicedbefore returning to themainprogram.Fourof theseconditionshavethecorrespondingUSRregisterflagswhichwillgenerateaUARTinterruptif itsassociated interruptenablecontrolbit in theUCR2register isset.The twotransmitter interruptconditionshave theirowncorrespondingenablecontrolbits,while the two receiver interruptconditionshaveasharedenablecontrolbit.TheseenablebitscanbeusedtomaskoutindividualUARTinterruptsources.

Theaddressdetectcondition,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptwhenanaddressdetectconditionoccurs if itsfunctionisenabledbysettingtheADDENbit in theUCR2register.AnRXpinwake-up,whichisalsoaUARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptifthemicrocontrolleriswokenupfromIDLE0orSLEEPmodebyafallingedgeontheRXpin,if theWAKEandRIEbitsintheUCR2registerareset.NotethatintheeventofanRXwake-upinterruptoccurring,therewillbeacertainperiodofdelay,commonlyknownastheSystemStart-upTime,fortheoscillatortorestartandstabilizebeforethesystemresumesnormaloperation.

Note that theUSRregister flagsare readonlyandcannotbeclearedorsetby theapplicationprogram,neitherwill theybeclearedwhen theprogramjumps to thecorresponding interruptservicing routine, as is the case for someof theother interrupts.The flagswill be clearedautomaticallywhencertainactionsare takenbytheUART,thedetailsofwhicharegivenintheUARTregistersection.TheoverallUARTinterruptcanbedisabledorenabledby the relatedinterruptenablecontrolbitsintheinterruptcontrolregistersofthemicrocontrollertodecidewhethertheinterruptrequestedbytheUARTmoduleismaskedoutorallowed.

Transmitter EmptyFla� TXIF

USR Re�ister

Transmitter IdleFla� TIDLE

Receiver Overr�nFla� OERR

Receiver Data�vailable RXIF

�DDEN

RX PinWake-�p

W�KE 01

01

RX� if BNO=0RX8 if BNO=1UCR2 Re�ister

OR RIE 01

TIIE 01

TEIE 01

U�RT Interr�pt Req�est Fla�

U�RTF

UCR2 Re�ister

U�RTE EMI

INTC0To MCUinterr�pt Circ�itry

01

INTC2INTC2

UART Interrupt Structure

Rev. 1.20 150 ��st 2�� 201� Rev. 1.20 151 ��st 2�� 201�



Address Detect ModeSettingtheAddressDetectfunctionenablecontrolbit,ADDEN,intheUCR2register,enablesthisspecialfunction.Ifthisbitissetto1,thenanadditionalqualifierwillbeplacedonthegenerationofaReceiverDataAvailable interrupt,which isrequestedbytheRXIFflag. If theADDENbitisequal to1, thenwhenthedata isavailable,an interruptwillonlybegenerated, if thehighestreceivedbithasahighvalue.NotethattherelatedinterruptenablecontrolbitandtheEMIbitofthemicrocontrollermustalsobeenabledforcorrectinterruptgeneration.Thehighestaddressbitisthe9thbitifthebitBNO=1orthe8thbitifthebitBNO=0.Ifthehighestbitishigh,thenthereceivedwordwillbedefinedasanaddressrather thandata.ADataAvailableinterruptwillbegeneratedeverytimethelastbitofthereceivedwordisset.IftheADDENbitisequalto0,thenaReceiveDataAvailableinterruptwillbegeneratedeachtimetheRXIFflagisset,irrespectiveofthedatalastbutstatus.Theaddressdetectionandparityfunctionsaremutuallyexclusivefunctions.Therefore,iftheaddressdetectfunctionisenabled,thentoensurecorrectoperation,theparityfunctionshouldbedisabledbyresettingtheparityfunctionenablebitPRENtozero.

ADDEN Bit 9 if BNO=1Bit 8 if BNO=0 UART Interrupt Generated

00 √1 √

10 X1 √

ADDEN Bit Function

UART Wake-upWhenthefSYSisoff,theUARTwillceasetofunction,allclocksourcestothemoduleareshutdown.IfthefSYSisoffwhileatransmissionisstillinprogress,thenthetransmissionwillbepauseduntiltheUARTclocksourcederivedfromthemicrocontroller isactivated. Inasimilarway, if theMCUentersthePowerDownModewhilereceivingdata,thenthereceptionofdatawilllikewisebepaused.WhentheMCUenters theIDLEorSLEEPMode,notethat theUSR,UCR1,UCR2,transmitandreceiveregisters,aswellastheBRGregisterwillnotbeaffected.Itisrecommendedtomakesure first that theUARTdata transmissionor receptionhasbeen finishedbefore themicrocontrollerentersthePowerDownmode.

TheUARTfunctioncontainsareceiverRXpinwake-upfunction,which isenabledordisabledbytheWAKEbitintheUCR2register.Ifthisbit,alongwiththeUARTenablebit,UARTEN,thereceiverenablebit,RXENandthereceiverinterruptbit,RIE,areallsetbeforetheMCUenterstheIDLE0orSLEEPMode,thenafallingedgeontheRXpinwillwakeuptheMCUfromtheIDLE0orSLEEPMode.Notethatasit takescertainsystemclockcyclesafterawake-up,beforenormalmicrocontrolleroperationresumes,anydatareceivedduringthistimeontheRXpinwillbeignored.

ForaUARTwake-upinterrupttooccur,inadditiontothebitsforthewake-upbeingset,theglobalinterruptenablebit,EMI,andtheUARTinterruptenablebit,UARTE,mustalsobeset.Ifthesetwobitsarenotsetthenonlyawakeupeventwilloccurandnointerruptwillbegenerated.Notealsothatasittakescertainsystemclockcyclesafterawake-upbeforenormalmicrocontrollerresumes,theUARTinterruptwillnotbegenerateduntilafterthistimehaselapsed.

BelowtwotablesillustratetheUARTRXwake-upfunctionsindifferentoperatingmode.

IfthemainsystemclockcancomefrombothhighfrequencyfHandlowfrequencyfSUB:

Rev. 1.20 152 ��st 2�� 201� Rev. 1.20 153 ��st 2�� 201�



OperationMode

DescriptionRX wake-up function

CPU fH fSUB

IDLE0 Mode Off (H�LT) Off On When the UCR2.2(RIE)=1� UCR2.3(W�KE)=1 and the CPU is entered in

IDLE0 mode� a fallin� ed�e on the RX pin will t�rn on fSYS and wake-�p CPU.

IDLE1 Mode Off (H�LT) On On

When the UCR2.2(RIE)=1� UCR2.3(W�KE)=1 and the CPU is entered in IDLE1 mode:1. If the U�RT is not transfer and a fallin� ed�e occ�rred on the RX pin� the

fSYS is kept on r�nnin� and CPU is still off. If the U�RT transmission is on �oin�� CPU will wake �p in the end of transfer.

2. If the U�RT transmission is on �oin�� the CPU will wake �p in the end of transfer.

Note: If RIE=0� W�KE=1 and the U�RT transmission is on �oin�� the CPU will not wake �p in the end of receive.

SLEEP Mode Off (H�LT) Off Off When the UCR2.2(RIE)=1� UCR2.3(W�KE)=1 and the CPU is entered in

SLEEP mode� a fallin� ed�e on the RX pin will t�rn on fSYS and wake-�p CPU.

Low Voltage Detector – LVDEachdevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.

LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.

LVDC Register

Bit 7 6 5 4 3 2 1 0Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0R/W — — R R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas“0”Bit5 LVDO:LVDOutputFlag

0:NoLowVoltageDetect1:LowVoltageDetect

Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable

Rev. 1.20 152 ��st 2�� 201� Rev. 1.20 153 ��st 2�� 201�



Bit3 Unimplemented,readas“0”Bit2~0 VLVD2~VLVD0:SelectLVDVoltage

000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V

LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD,fallsbelowthispre-determinedvalue,theLVDObitwillbesethighindicatinga lowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbyareferencevoltagewhichwillbeautomaticallyenabled.WhenthedeviceisSLEEP0theLowVoltageDetectorwilldisable,even if theLVDENbit ishigh.Afterenabling theLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.

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LVD Operation

TheLowVoltageDetectoralsohasitsowninterruptwhichiscontainedwithinoneoftheMulti-functioninterrupts,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.WhenthedeviceispowereddowntheLowVoltageDetectorwillremainactiveiftheLVDENbitishigh.Inthiscase,theLVFinterruptrequestflagwillbeset,causinganinterrupttobegeneratedifVDDfallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheSLEEPorIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceenterstheSLEEPorIDLEMode.

WhenLVDfunctionisenabled,itisrecommencedtoclearLVDflagfirst,andthenenablesinterruptfunctiontoavoidmistakeaction.

Rev. 1.20 154 ��st 2�� 201� Rev. 1.20 155 ��st 2�� 201�



InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontroller todirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptsfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalINTnpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchasTMs,Comparator,TimeBases,LVD,EEPROM,SIM,UARTandtheA/Dconverter.

Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshownintheaccompanyingtable.ThefirstistheINTC0~INTC2registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI2registerswhichsetuptheMulti-functioninterrupts.

Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestflag.

Function Enable Bit Request Flag NotesGlobal EMI — —INTn Pin INTnE INTnF n=0 or 1Comparator CPE CPF —M�lti-f�nction MFnE MFnF n=0~2�/D Converter �DE �DF —Time Base TBnE TBnF n=0 or 1LVD LVE LVF —EEPROM DEE DEF —

STMSTMnPE STMnPF

n=0 or 1STMn�E STMn�F

PTMPTMPE PTMPF

—PTM�E PTM�F

SIM SIME SIMF —U�RT U�RTE U�RTF —

Interrupt Register Bit Naming Conventions

Register Name

Bit

7 6 5 4 3 2 1 0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0INTC0 — MF0F CPF INT0F MF0E CPE INT0E EMIINTC1 TB0F �DF MF2F MF1F TB0E �DE MF2E MF1EINTC2 U�RTF SIMF INT1F TB1F U�RTE SIME INT1E TB1EMFI0 — — STM0�F STM0PF — — STM0�E STM0PEMFI1 STM1�F STM1PF PTM�F PTMPF STM1�E STM1PE PTM�E PTMPEMFI2 — — DEF LVF — — DEE LVE

Interrupt Registers List

Rev. 1.20 154 ��st 2�� 201� Rev. 1.20 155 ��st 2�� 201�



INTEG Register

Bit 7 6 5 4 3 2 1 0Name — — — — INT1S1 INT1S0 INT0S1 INT0S0R/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0

Bit7~4 Unimplemented,readas“0”Bit3~2 INT1S1~INT1S0:interruptedgecontrolforINT1pin

00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedges

Bit1~0 INT0S1~INT0S0:interruptedgecontrolforINT0pin00:Disable01:Risingedge10:Fallingedge11:Bothrisingandfallingedges

INTC0 Register

Bit 7 6 5 4 3 2 1 0Name — MF0F CPF INT0F MF0E CPE INT0E EMIR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas“0”Bit6 MF0F:Multi-functionInterrupt0RequestFlag

0:Norequest1:Interruptrequest

Bit5 CPF:Comparatorinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 INT0F:INT0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 MF0E:Multi-function0InterruptControl0:Disable1:Enable

Bit2 CPE:Comparatorinterruptcontrol0:Disable1:Enable

Bit1 INT0E:INT0InterruptControl0:Disable1:Enable

Bit0 EMI:GlobalInterruptControl0:Disable1:Enable

Rev. 1.20 156 ��st 2�� 201� Rev. 1.20 15� ��st 2�� 201�



INTC1 Register

Bit 7 6 5 4 3 2 1 0Name TB0F �DF MF2F MF1F TB0E �DE MF2E MF1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 TB0F:TimeBase0InterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 ADF:A/DConverterInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 MF2F:Multi-functionInterrupt2RequestFlag0:Norequest1:Interruptrequest

Bit4 MF1F:Multi-functionInterrupt1RequestFlag0:Norequest1:Interruptrequest

Bit3 TB0E:TimeBase0InterruptControl0:Disable1:Enable

Bit2 ADE:A/DConverterInterruptControl0:Disable1:Enable



Rev. 1.20 156 ��st 2�� 201� Rev. 1.20 15� ��st 2�� 201�



INTC2 Register

Bit 7 6 5 4 3 2 1 0Name U�RTF SIMF INT1F TB1F U�RTE SIME INT1E TB1ER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 UARTF:UARTInterruptRequestFlag0:Norequest1:Interruptrequest

Bit6 SIMF:SIMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit5 INT1F:INT1pininterruptrequestflag0:Norequest1:Interruptrequest

Bit4 TB1F:TimeBase1InterruptRequestFlag0:Norequest1:Interruptrequest

Bit3 UARTE:UARTInterruptRequestFlag0:Norequest1:Interruptrequest

Bit2 SIME:SIMInterruptRequestFlag0:Norequest1:Interruptrequest

Bit1 INT1E:INT1pininterruptcontrol0:Disable1:Enable

Bit0 TB1E:TimeBase1InterruptControl0:Disable1:Enable

MFI0 Register

Bit 7 6 5 4 3 2 1 0Name — — STM0�F STM0PF — — STM0�E STM0PER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 STM0AF:STM0ComparatorAmatchinterruptrequestflag


Bit4 STM0PF:STM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 STM0AE:STM0ComparatorAmatchinterruptcontrol

0:Disable1:Enable

Bit0 STM0PE:STM0ComparatorPmatchinterruptcontrol0:Disable1:Enable

Rev. 1.20 158 ��st 2�� 201� Rev. 1.20 15� ��st 2�� 201�



MFI1 Register

Bit 7 6 5 4 3 2 1 0Name STM1�F STM1PF PTM�F PTMPF STM1�E STM1PE PTM�E PTMPER/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 STM1AF:STM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit6 STM1PF:STM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit5 PTMAF:PTMComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit4 PTMPF:PTMComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest

Bit3 STM1AE:STM1ComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit2 STM1PE:STM1ComparatorPmatchinterruptcontrol0:Disable1:Enable

Bit1 PTMAE:PTMComparatorAmatchinterruptcontrol0:Disable1:Enable

Bit0 PTMPE:PTMComparatorPmatchinterruptcontrol0:Disable1:Enable

MFI2 Register

Bit 7 6 5 4 3 2 1 0Name — — DEF LVF — — DEE LVER/W — — R/W R/W — — R/W R/WPOR — — 0 0 — — 0 0

Bit7~6 Unimplemented,readas“0”Bit5 DEF:DataEEPROMinterruptrequestflag


Bit4 LVF:LVDinterruptrequestflag0:Norequest1:Interruptrequest

Bit3~2 Unimplemented,readas“0”Bit1 DEE:DataEEPROMInterruptControl

0:Disable1:Enable

Bit0 LVE:LVDInterruptControl0:Disable1:Enable

Rev. 1.20 158 ��st 2�� 201� Rev. 1.20 15� ��st 2�� 201�



Interrupt OperationWhen theconditions foran interrupteventoccur, suchasaTMComparatorP,ComparatorAmatchorA/Dconversioncompletionetc., therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector, if theenablebit iszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.

Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha“RETI”,whichretrieves theoriginalProgramCounteraddressfromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.

Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theAccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.

Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.

Rev. 1.20 160 ��st 2�� 201� Rev. 1.20 161 ��st 2�� 201�



INT0 Pin

INT1 Pin

INT0F

INT1F

INT0E

INT1E

EMI 04H

EMI 08H

EMI 0CH

EMI 10H

Time Base 0 TB0F TB0E

STM1P STM1PF STM1PE

EMI 1CH

Interr�pt Name

Req�estFla�s

Enable Bits

Master Enable Vector

EMI a�to disabled in ISR

PriorityHi�h

Low

STM0P STM0PF STM0PE

STM0� STM0�F STM0�E

M. F�nct. 0 MF0F MF0E

Interr�pts contained within M�lti-F�nction Interr�pts

xxE Enable Bits

xxF Req�est Fla�� a�to reset in ISR

LegendxxF Req�est Fla�� no a�to reset in ISR

EMI 20H

EMI 24H

Comparator CPF CPE


Time Base 1 TB1F TB1E

STM1� STM1�F STM1�E

�/D �DF �DE EMI 18H

EMI 14H

LVD LVF LVE


EEPROM DEF DEE

PTMP PTMPF PTMPE

PTM� PTM�F PTM�E

U�RT U�RTF U�RTE

EMI 28H

EMI 2CH

SIM SIMF SIME

Interrupt Structure

External InterruptTheexternal interrupt iscontrolledbysignal transitionsontheINTnpins.Anexternal interruptrequestwill takeplacewhentheexternal interruptrequestflag, INTnF, isset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpin.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveexternalinterruptenablebit,INTnE,mustfirstbeset.Additionallythecorrect interruptedge typemustbeselectedusing therelatedregister toenable theexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinispin-sharedwithI/Opin,itcanonlybeconfiguredasexternalinterruptpiniftheexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflag,INTnF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinwillremainvalidevenifthepinisusedasanexternalinterruptinput.

TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.

Rev. 1.20 160 ��st 2�� 201� Rev. 1.20 161 ��st 2�� 201�



Comparator InterruptThecomparator interrupt iscontrolledbytheinternalcomparator.Acomparator interruptrequestwill takeplacewhenthecomparatorinterruptrequestflag,CPF,isset,asituationthatwilloccurwhenthecomparatoroutputbitchangesstate.Toallowtheprogramtobranch to its respectiveinterruptvectoraddress, theglobalinterruptenablebit,EMI,andcomparatorinterruptenablebit,CPE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandthecomparatorinputsgenerateacomparatoroutput transition,asubroutinecall tothecomparator interruptvector,willtakeplace.Whentheinterruptisserviced,thecomparatorinterruptrequestflagwillbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.

Multi-function InterruptWithin thedevice thereareup to threeMulti-function interrupts.Unlike theother independentinterrupts, theseinterruptshavenoindependentsource,butratherareformedfromotherexistinginterruptsources,namelytheTMInterrupts,LVDinterruptandEEPROMinterrupt.

AMulti-functioninterruptrequestwill takeplacetheMulti-functioninterruptrequestflag,MFnFisset.TheMulti-functioninterruptflagwillbesetwhenanyofitsincludedfunctionsgenerateaninterruptrequestflag.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress,whentheMulti-functioninterruptisenabledandthestackisnotfullandeitheroneoftheinterruptscontainedwithineachofMulti-function interruptoccurs,asubroutinecall to theMulti-functioninterruptvectorwill takeplace.Whentheinterruptisserviced,therelatedMulti-Functionrequestflagwillbeautomaticallyresetand theEMIbitwillbeautomaticallycleared todisableotherinterrupts.

However, itmustbenotedthat,althoughtheMulti-functionInterruptflagswillbeautomaticallyresetwhen the interrupt is serviced, the requestflags from theoriginal sourceof theMulti-functioninterrupts,namelytheTMInterrupts,LVDinterruptandEEPROMinterrupt,willnotbeautomaticallyresetandmustbemanuallyresetbytheapplicationprogram.

A/D Converter InterruptThedevicecontainsanA/Dconverterwhichhasitsownindependentinterrupt.TheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwill takeplacewhentheA/DConverterInterruptrequestflag,ADF, isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Rev. 1.20 162 ��st 2�� 201� Rev. 1.20 163 ��st 2�� 201�



Time Base InterruptThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappens their respective interrupt request flags,TB0ForTB1Fwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TB0EorTB1E,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecall totheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TB0ForTB1F,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.

ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.TheirclocksourcesoriginatefromtheinternalclocksourcefTB.ThisfTB inputclockpasses throughadivider, thedivisionratioofwhich isselectedbyprogrammingtheappropriatebits in theTBCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTB,whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,asshownintheSystemOperatingModesection.

TBC Register

Bit 7 6 5 4 3 2 1 0Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 1 1 0 1 1 1

Bit7 TBON:TB0andTB1functionenableControl0:Disable1:Enable

Bit6 TBCK:SelectfTBClock0:fTBC1:fSYS/4

Bit5~4 TB11~TB10:SelectTimeBase1Time-outPeriod00:212/fTB01:213/fTB10:214/fTB11:215/fTB

Bit3 LXTLP:LXTLowPowerControl0:Disable(LXTquickstart-up)1:Enable(LXTslowstart-up)

Bit2~0 TB02~TB00:SelectTimeBase0Time-outPeriod000:28/fTB001:29/fTB010:210/fTB011:211/fTB100:212/fTB101:213/fTB110:214/fTB111:215/fTB

Rev. 1.20 162 ��st 2�� 201� Rev. 1.20 163 ��st 2�� 201�



��

��

� � �

� � � �

� � � � � ��

� � � � � � � ��

� � � � � � � � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � � ��

� � � � � � �

� � � � � � � � �

� � ��

Time Base Interrupt

EEPROM InterruptTheEEPROMinterrupt iscontainedwithintheMulti-functionInterrupt.AnEEPROMInterruptrequestwill takeplacewhen theEEPROMInterrupt request flag,DEF, is set,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecall totherespectiveEEPROMInterruptvector,will takeplace.When theEEPROMInterrupt isserviced, theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheDEFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

LVD Interrupt TheLowVoltageDetector Interrupt iscontainedwithin theMulti-function Interrupt.ALVDInterruptrequestwill takeplacewhentheLVDInterruptrequest flag,LVF, isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,LowVoltageInterruptenablebit,LVE,andassociatedMulti-functioninterruptenablebit,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheMulti-functionInterruptvector,willtakeplace.WhentheLowVoltageInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytheMulti-functioninterruptrequestflagwillbealsoautomaticallycleared.AstheLVFflagwillnotbeautomaticallycleared,ithastobeclearedbytheapplicationprogram.

TM Interrupts TheStandardandPeriodicTypeTMshave two interruptseach.Allof theTMinterruptsarecontainedwithintheMulti-functionInterrupts.FortheStandardandPeriodictherearetwointerruptrequestflagsxTMnPFandxTMnAF,andtwoenablebitsxTMnPEandxTMnAE.ATMinterruptrequestwilltakeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorAmatchsituationhappens.

Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,respectiveTMInterruptenablebit,andrelevantMulti-functionInterruptenablebit,MFnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherelevantMulti-functionInterruptvectorlocations,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts,howeveronlytherelatedMFnFflagwillbeautomaticallycleared.AstheTMinterruptrequestflagswillnotbeautomaticallycleared,theyhavetobeclearedbytheapplicationprogram.

Rev. 1.20 164 ��st 2�� 201� Rev. 1.20 165 ��st 2�� 201�



SIM InterruptTheSerialInterfaceModuleInterrupt,alsoknownastheSIMinterrupt,iscontrolledbytheSPIorI2Cdatatransfer.ASIMInterruptrequestwilltakeplacewhentheSIMInterruptrequestflag,SIMF,isset,whichoccurswhenabyteofdatahasbeenreceivedor transmittedbytheSIMinterface,anI2CslaveaddressmatchorI2Cbustime-outoccurrence.Toallowtheprogramtobranchtoitsrespective interruptvectoraddress, theglobal interruptenablebit,EMIandtheSerial InterfaceInterruptenablebit,SIME,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanyoftheabovedescribedsituationsoccurs,asubroutinecalltotherespectiveSIMInterruptvector,will takeplace.WhentheSerialInterfaceInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.TheSIMFflagwillalsobeautomaticallycleared.

UART Transfer InterruptTheUARTTransferInterruptiscontrolledbyseveralUARTtransferconditions.Whenoneoftheseconditionsoccurs,aninterruptpulsewillbegeneratedtoget theattentionof themicrocontroller.Theseconditionsarea transmitterdata registerempty, transmitter idle, receiverdataavailable,receiveroverrun,addressdetectandanRXpinwake-up.Toallowtheprogramtobranchto itsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andUARTInterruptenablebit,UARTE,mustfirstbeset.Whentheinterrupt isenabled, thestackisnotfullandanyof theconditionsdescribedaboveoccurs,asubroutinecalltotheUARTInterruptvector,willtakeplace.Whentheinterruptisserviced,theUARTInterruptflag,UARTF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.

Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchangemaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.Caremust thereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.

Rev. 1.20 164 ��st 2�� 201� Rev. 1.20 165 ��st 2�� 201�



Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.

Whereacertain interrupt iscontainedwithinaMulti-function interrupt, thenwhenthe interruptservice routine isexecuted,asonly theMulti-function interrupt request flags,MFnF,willbeautomaticallycleared, the individual request flag for the functionneeds tobeclearedby theapplicationprogram.

It isrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.

Everyinterrupthasthecapabilityofwakingupthemicrocontrollerwhenit isinSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeenterSLEEPorIDLEMode.

AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.

Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.

Rev. 1.20 166 ��st 2�� 201� Rev. 1.20 16� ��st 2�� 201�



Configuration OptionConfigurationoptionsrefertocertainoptionswithintheMCUthatareprogrammedintothedeviceduringtheprogrammingprocess.Duringthedevelopmentprocess,theseoptionsareselectedusingtheHT-IDEsoftwaredevelopment tools.Astheseoptionsareprogrammedintothedeviceusingthehardwareprogrammingtools,once theyareselectedtheycannotbechangedlaterusingtheapplicationprogram.Alloptionsmustbedefinedforpropersystemfunction,thedetailsofwhichareshowninthetable.

No. OptionsOscillator Options

1Hi�h Speed System Oscillator Selection – fH:

1. HXT2. HIRC

2Low Speed System Oscillator Selection – fSUB:

1. LXT2. LIRC

3

HIRC Freq�ency Selection: 1. 8MHz 2. 12MHz3. 16MHz

Application Circuits

VDD

VSS

VDD

PC0/OSC1

PC1/OSC2OSC

Circ�it

PB0/XT1

PB1/XT2OSC

Circ�it

See Oscillator Section

See Oscillator Section

�N0~�N�

SCOM0~SCOM3

P�0~P��

PB0~PB�

PC0~PC�

PD0~PD�

0.1µF

PE0~PE�

PF0~PF5

TX

RX

Rev. 1.20 166 ��st 2�� 201� Rev. 1.20 16� ��st 2�� 201�



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.20 168 ��st 2�� 201� Rev. 1.20 16� ��st 2�� 201�



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.20 168 ��st 2�� 201� Rev. 1.20 16� ��st 2�� 201�



Instruction Set SummaryTheinstructionsrelated to thedatamemoryaccess in thefollowingtablecanbeusedwhenthedesireddatamemoryislocatedinDataMemorysector0.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmetic�DD ��[m] �dd Data Memory to �CC 1 Z� C� �C� OV� SC�DDM ��[m] �dd �CC to Data Memory 1Note Z� C� �C� OV� SC�DD ��x �dd immediate data to �CC 1 Z� C� �C� OV� SC�DC ��[m] �dd Data Memory to �CC with Carry 1 Z� C� �C� OV� SC�DCM ��[m] �dd �CC to Data memory with Carry 1Note Z� C� �C� OV� SCSUB ��x S�btract immediate data from the �CC 1 Z� C� �C� OV� SC� CZSUB ��[m] S�btract Data Memory from �CC 1 Z� C� �C� OV� SC� CZSUBM ��[m] S�btract Data Memory from �CC with res�lt in Data Memory 1Note Z� C� �C� OV� SC� CZSBC ��x S�btract immediate data from �CC with Carry 1 Z� C� �C� OV� SC� CZSBC ��[m] S�btract Data Memory from �CC with Carry 1 Z� C� �C� OV� SC� CZSBCM ��[m] S�btract Data Memory from �CC with Carry� res�lt in Data Memory 1Note Z� C� �C� OV� SC� CZD�� [m] Decimal adj�st �CC for �ddition with res�lt in Data Memory 1Note CLogic Operation�ND ��[m] Lo�ical �ND Data Memory to �CC 1 ZOR ��[m] Lo�ical OR Data Memory to �CC 1 ZXOR ��[m] Lo�ical XOR Data Memory to �CC 1 Z�NDM ��[m] Lo�ical �ND �CC to Data Memory 1Note ZORM ��[m] Lo�ical OR �CC to Data Memory 1Note ZXORM ��[m] Lo�ical XOR �CC to Data Memory 1Note Z�ND ��x Lo�ical �ND immediate Data to �CC 1 ZOR ��x Lo�ical OR immediate Data to �CC 1 ZXOR ��x Lo�ical XOR immediate Data to �CC 1 ZCPL [m] Complement Data Memory 1Note ZCPL� [m] Complement Data Memory with res�lt in �CC 1 ZIncrement & DecrementINC� [m] Increment Data Memory with res�lt in �CC 1 ZINC [m] Increment Data Memory 1Note ZDEC� [m] Decrement Data Memory with res�lt in �CC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRR� [m] Rotate Data Memory ri�ht with res�lt in �CC 1 NoneRR [m] Rotate Data Memory ri�ht 1Note NoneRRC� [m] Rotate Data Memory ri�ht thro��h Carry with res�lt in �CC 1 CRRC [m] Rotate Data Memory ri�ht thro��h Carry 1Note CRL� [m] Rotate Data Memory left with res�lt in �CC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLC� [m] Rotate Data Memory left thro��h Carry with res�lt in �CC 1 CRLC [m] Rotate Data Memory left thro��h Carry 1Note C

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Mnemonic Description Cycles Flag AffectedData MoveMOV ��[m] Move Data Memory to �CC 1 NoneMOV [m]�� Move �CC to Data Memory 1Note NoneMOV ��x Move immediate data to �CC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationJMP addr J�mp �nconditionally 2 NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZ� [m] Skip if Data Memory is zero with data movement to �CC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m] Skip if Data Memory is not zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZ� [m] Skip if increment Data Memory is zero with res�lt in �CC 1Note NoneSDZ� [m] Skip if decrement Data Memory is zero with res�lt in �CC 1Note NoneC�LL addr S�bro�tine call 2 NoneRET Ret�rn from s�bro�tine 2 NoneRET ��x Ret�rn from s�bro�tine and load immediate data to �CC 2 NoneRETI Ret�rn from interr�pt 2 NoneTable Read OperationT�BRD [m] Read table (specific page) to TBLH and Data Memory 2Note NoneT�BRDL [m] Read table (last pa�e) to TBLH and Data Memory 2Note NoneIT�BRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None

IT�BRDL [m] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Memory 2Note None

MiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdo� Timer 1 TO� PDFSW�P [m] Swap nibbles of Data Memory 1Note NoneSW�P� [m] Swap nibbles of Data Memory with res�lt in �CC 1 NoneH�LT Enter power down mode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptothreecyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.Forthe“CLRWDT”instructiontheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterthe“CLRWDT”instructionsisexecuted.OtherwisetheTOandPDFflagsremainunchanged.

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Extended Instruction SetTheextendedinstructionsareusedtosupport thefullrangeaddressaccessfor thedatamemory.When theaccesseddatamemory is located inanydatamemorysectionsexcept sector0, theextendedinstructioncanbeusedtoaccessthedatamemoryinsteadofusingtheindirectaddressingaccesstoimprovetheCPUfirmwareperformance.

Mnemonic Description Cycles Flag AffectedArithmeticL�DD ��[m] �dd Data Memory to �CC 2 Z� C� �C� OV� SCL�DDM ��[m] �dd �CC to Data Memory 2Note Z� C� �C� OV� SCL�DC ��[m] �dd Data Memory to �CC with Carry 2 Z� C� �C� OV� SCL�DCM ��[m] �dd �CC to Data memory with Carry 2Note Z� C� �C� OV� SCLSUB ��[m] S�btract Data Memory from �CC 2 Z� C� �C� OV� SC� CZLSUBM ��[m] S�btract Data Memory from �CC with res�lt in Data Memory 2Note Z� C� �C� OV� SC� CZLSBC ��[m] S�btract Data Memory from �CC with Carry 2 Z� C� �C� OV� SC� CZLSBCM ��[m] S�btract Data Memory from �CC with Carry� res�lt in Data Memory 2Note Z� C� �C� OV� SC� CZLD�� [m] Decimal adj�st �CC for �ddition with res�lt in Data Memory 2Note CLogic OperationL�ND ��[m] Lo�ical �ND Data Memory to �CC 2 ZLOR ��[m] Lo�ical OR Data Memory to �CC 2 ZLXOR ��[m] Lo�ical XOR Data Memory to �CC 2 ZL�NDM ��[m] Lo�ical �ND �CC to Data Memory 2Note ZLORM ��[m] Lo�ical OR �CC to Data Memory 2Note ZLXORM ��[m] Lo�ical XOR �CC to Data Memory 2Note ZLCPL [m] Complement Data Memory 2Note ZLCPL� [m] Complement Data Memory with res�lt in �CC 2 ZIncrement & DecrementLINC� [m] Increment Data Memory with res�lt in �CC 2 ZLINC [m] Increment Data Memory 2Note ZLDEC� [m] Decrement Data Memory with res�lt in �CC 2 ZLDEC [m] Decrement Data Memory 2Note ZRotateLRR� [m] Rotate Data Memory ri�ht with res�lt in �CC 2 NoneLRR [m] Rotate Data Memory ri�ht 2Note NoneLRRC� [m] Rotate Data Memory ri�ht thro��h Carry with res�lt in �CC 2 CLRRC [m] Rotate Data Memory ri�ht thro��h Carry 2Note CLRL� [m] Rotate Data Memory left with res�lt in �CC 2 NoneLRL [m] Rotate Data Memory left 2Note NoneLRLC� [m] Rotate Data Memory left thro��h Carry with res�lt in �CC 2 CLRLC [m] Rotate Data Memory left thro��h Carry 2Note CData MoveLMOV ��[m] Move Data Memory to �CC 2 NoneLMOV [m]�� Move �CC to Data Memory 2Note NoneBit OperationLCLR [m].i Clear bit of Data Memory 2Note NoneLSET [m].i Set bit of Data Memory 2Note None

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Mnemonic Description Cycles Flag AffectedBranchLSZ [m] Skip if Data Memory is zero 2Note NoneLSZ� [m] Skip if Data Memory is zero with data movement to �CC 2Note NoneLSNZ [m] Skip if Data Memory is not zero 2Note NoneLSZ [m].i Skip if bit i of Data Memory is zero 2Note NoneLSNZ [m].i Skip if bit i of Data Memory is not zero 2Note NoneLSIZ [m] Skip if increment Data Memory is zero 2Note NoneLSDZ [m] Skip if decrement Data Memory is zero 2Note NoneLSIZ� [m] Skip if increment Data Memory is zero with res�lt in �CC 2Note NoneLSDZ� [m] Skip if decrement Data Memory is zero with res�lt in �CC 2Note NoneTable ReadLT�BRD [m] Read table to TBLH and Data Memory 3Note NoneLT�BRDL [m] Read table (last pa�e) to TBLH and Data Memory 3Note NoneLIT�BRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None

LIT�BRDL [m] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Memory 3Note None

MiscellaneousLCLR [m] Clear Data Memory 2Note NoneLSET [m] Set Data Memory 2Note NoneLSW�P [m] Swap nibbles of Data Memory 2Note NoneLSW�P� [m] Swap nibbles of Data Memory with res�lt in �CC 2 None

Note:1.Fortheseextendedskipinstructions,iftheresultofthecomparisoninvolvesaskipthenuptofourcyclesarerequired,ifnoskiptakesplacetwocyclesisrequired.

2.AnyextendedinstructionwhichchangesthecontentsofthePCLregisterwillalsorequirethreecyclesforexecution.

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Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C,SC

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

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CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

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DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

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NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

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RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

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RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

SBC A, x SubtractimmediatedatafromACCwithCarryDescription Theimmediatedataandthecomplementofthecarryflagaresubtractedfromthe Accumulator.TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionis negative,theCflagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflag willbesetto1.Operation ACC←ACC-[m]-CAffectedflag(s) OV,Z,AC,C,SC,CZ

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

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SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SNZ [m] SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

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SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C,SC,CZ

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

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TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBLPandTBHP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

ITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

ITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.20 182 ��st 2�� 201� Rev. 1.20 183 ��st 2�� 201�



Extended Instruction DefinitionTheextendedinstructionsareusedtodirectlyaccessthedatastoredinanydatamemorysections.

LADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

LADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C,SC

LADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

LADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C,SC

LAND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

LANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

LCLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

LCLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

Rev. 1.20 182 ��st 2�� 201� Rev. 1.20 183 ��st 2�� 201�



LCPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

LCPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

LDAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

LDEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

LDECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

LINC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

LINCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.20 184 ��st 2�� 201� Rev. 1.20 185 ��st 2�� 201�



LMOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

LMOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

LOR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

LORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

LRL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

LRLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

LRLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

LRLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

Rev. 1.20 184 ��st 2�� 201� Rev. 1.20 185 ��st 2�� 201�



LRR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

LRRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

LRRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

LRRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

LSBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

LSBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C,SC,CZ

Rev. 1.20 186 ��st 2�� 201� Rev. 1.20 18� ��st 2�� 201�



LSDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

LSDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

LSET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

LSET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

LSIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

LSIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

LSNZ [m].i SkipifDataMemoryisnot0Description IfthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthisrequiresthe insertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

Rev. 1.20 186 ��st 2�� 201� Rev. 1.20 18� ��st 2�� 201�



LSNZ [m] SkipifDataMemoryisnot0Description IfthecontentofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.As thisrequirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisa twocycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]≠0Affectedflag(s) None

LSUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

LSUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C,SC,CZ

LSWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

LSWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

LSZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

LSZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

Rev. 1.20 188 ��st 2�� 201� Rev. 1.20 18� ��st 2�� 201�



LSZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

LTABRD [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LTABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LITABRD [m] IncrementtablepointerlowbytefirstandreadtabletoTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthentheprogramcodeaddressedbythe tablepointer(TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbyte movedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)

Affectedflag(s) None

LITABRDL [m] Incrementtablepointerlowbytefirstandreadtable(lastpage)toTBLHandDataMemoryDescription Incrementtablepointerlowbyte,TBLP,firstandthenthelowbyteoftheprogramcode (lastpage)addressedbythetablepointer(TBLP)ismovedtothespecifiedDataMemoryand thehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

LXOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

LXORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

Rev. 1.20 188 ��st 2�� 201� Rev. 1.20 18� ��st 2�� 201�



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Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

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Rev. 1.20 1�0 ��st 2�� 201� Rev. 1.20 1�1 ��st 2�� 201�



44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions

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Min. Nom. Max.� — 0.4�2 BSC —B — 0.3�4 BSC —C — 0.4�2 BSC —D — 0.3�4 BSC —E — 0.032 BSC —F 0.012 0.015 0.018G 0.053 0.055 0.05�H — — 0.063I 0.002 — 0.006J 0.018 0.024 0.030K 0.004 — 0.008α 0° — �°

SymbolDimensions in mm

Min. Nom. Max.� — 12.00 BSC —B — 10.00 BSC —C — 12.00 BSC —D — 10.00 BSC —E — 0.80 BSC —F 0.30 0.3� 0.45G 1.35 1.40 1.45H — — 1.60I 0.05 — 0.15J 0.45 0.60 0.�5K 0.0� — 0.20α 0° — �°

Rev. 1.20 1�0 ��st 2�� 201� Rev. 1.20 1�1 ��st 2�� 201�



48-pin LQFP (7mm×7mm) Outline Dimensions

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Min. Nom. Max.� — 0.354 BSC —B — 0.2�6 BSC —C — 0.354 BSC —D — 0.2�6 BSC —E — 0.020 BSC —F 0.00� 0.00� 0.011G 0.053 0.055 0.05�H — — 0.063I 0.002 — 0.006J 0.018 0.024 0.030K 0.004 — 0.008α 0° — �°

SymbolDimensions in mm

Min. Nom. Max.� — �.00 BSC —B — �.00 BSC —C — �.00 BSC —D — �.00 BSC —E — 0.50 BSC —F 0.1� 0.22 0.2�G 1.35 1.40 1.45H — — 1.60

I 0.05 — 0.15

J 0.45 0.60 0.�5K 0.0� — 0.20α 0° — �°

Rev. 1.20 1�2 ��st 2�� 201� Rev. 1.20 PB ��st 2�� 201�



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A/D Flash MCU with EEPROM - Home - Holtek...Configuration Option..... 166 Application Circuits........

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