ACTIVE GATE DRIVERS FOR MOTOR CONTROL ...ewh.ieee.org/soc/pels/pdf/pesc01_gatedrive.pdfDORIN O....

ACTIVE GATE DRIVERS FOR MOTOR CONTROL APPLICATIONS

By

DORIN O. NEACSUCorrespondence Address: Satcon Technology Center

161 First Street, Cambridge, MA 02142Phone (617) 349-0834, Fax (617) 661-3373, Email [email protected]

Tutorial previously presented at IEEE PESC 2001

Copyright © 2001 IEEE. Reprinted with permission. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from

the IEEE by sending a blank email message to [email protected].

© 2001 IEEE * ACTIVE GATE DRIVERS FOR MOTOR

CONTROL APPLICATIONS

About SpeakerDorin O. Neacsu (M'95, SM'00) was born in Suceava, Romania, in 1964.

He received the MS and PhD degrees in electrical engineering from the Technical University of Iasi, Iasi, Romania, in 1988 and 1994,

respectively. He was with TAGCM-SUT Iasi, Romania, from 1988 to 1990. Since 1990, he has been with the faculty of the Department of

Electronics, Technical University of Iasi. In 1995, he has been a Post-Doctoral Fellow at Universite du Quebec a Trois Rivieres, Canada.

Between February 1997 and August 1998, he has been at Delphi-Energy and Engine Management Systems, Indianapolis, USA, working on

advanced DSP control of electrical drives for propulsion systems. In August 1999, he has joined International Rectifier, in El Segundo, CA,

USA and has worked in the Power IC Group.

Since January 2001, Dr.Neacsu is with Satcon Technology Center, Cambridge, MA, USA. Along with about 50 papers or research notes published in journals or conference proceedings, Dr. Neacsu

has co-written several university textbooks in Canada and Romania and a book on simulation-modelling of power converters in Romanian language. Dr. Neacsu has served as a Reviewer or Session Chairman for several IEEE Transactions or conferences. His research areas are in gate drivers and static power converters, PWM algorithms, microprocessor control, modeling and

simulation of power converters and emerging control technologies as fuzzy logic.



3PLAN OF PRESENTATION

1. IGBT/MOSFET SWITCHINGS

2. LIMITS OF OPERATION. PROTECTION

3. GATE DRIVER REQUIREMENTS

4. LOSSES

5. EMI

6. COMPUTER BASED DESIGN

7. GATE CONTROL OF SERIES CONNECTED IGBTs

8. ACTIVE PROTECTION CIRCUITS

9. ADVANCED METHODS OF ACTIVE GATE CONTROL

10. CONCLUSION

PESC 2001VANCOUVER, CANADA

JUNE 17-21,2001



41. IGBT/MOSFET SWITCHINGS- POWER MOSFET CIRCUIT MODELS

• Faster than bipolar transistors since they do not have excess minority carrier that should be moved during turn-on and turn-off

• Electrical charges are moved through the stray capacitances or depletion layer capacitances;

• Equivalent circuit model for transient analysis in cut-off and active regions:

Id=f(Vgs)

S

DCgd

Cgs

G


JUNE 17-21,2001



• When vDS<vGS -VGSth the MOSFET enters the ohmic region.

• In power switching converters, vGS>> VGSth and the boundary for the ohmic region becomes vDS < vGS

• The equivalent circuit model for the ohmic region:



JUNE 17-21,2001

• RDS(on) represents the ohmic losses mostly arising from drain drift region.

RDS(on)Cgd

Cgs

D

S

G




• The capacitances Cgd and Cgs are varying with the voltage across them with a substantial change in Cgd that can be approximated with a 2-step variation. This nonlinearity is hard to deal with even if smaller than Cgs.

vDS

Cgd

Cgd - 0.02nF

Cgd - 0.2nF Model Approximation Cgd

Possible experimental variation of Cgd@100V

NOTE: Numerical values are of example only.

Cgd effect is alike the “Miller” effect in any feedback circuit (path between OUT & IN). This was first studied by John Miller for vacuum tube triode amplifier.


JUNE 17-21,2001

VARIATION RANGE OF 10 OR 20



vGS

Cgs

Cgs1 - 0.6nF

Cgs2 - 2.2nF

Constant Cgs on third interval(increased by GD overlap oxide capacitance)

Constant Cgs on first interval

NOTE: Numerical values are of example only



JUNE 17-21,2001

∆C=Gate Oxide Capacitance of drain overlap



• IGBT combines the advantages of Bipolar Transistors such as low conduction losses with the merits of MOSFETs such as shorter switching times.

• Equivalent circuitry:

• Switching behaviour of IGBTs can be analyzed based on MOSFET models

81. IGBT/MOSFET SWITCHINGS- IGBT VERSUS MOSFET

Collector

Emitter

Body layer spreading resistance

Parasitic transistor with negative effects on latch-up

Drift region resistance

Gate

Unlike conventional Darlington, MOSFET carries most of current


JUNE 17-21,2001



• Turn-on and turn-off behavior are analyzed with a simple circuit including a free-wheeling diode.

• This case is modeling very well the large majority of motor drive applications

91. IGBT/MOSFET SWITCHINGS- SWITCHING WAVEFORMS

DL

M

Rg


JUNE 17-21,2001





JUNE 17-21,2001

I0

VDS(on)vD

vGG

vGS

iG

iD

Irr

vGS(Io)

vGS(th)

RG*(Cgd1+Cgs)

RG*(Cgd2+Cgs)

Miller plateau

Charge on Cgd

Charge onCgs and Cgd

Adding free-wheeling diodereverse recovery current

Drain current rise establishing

(di/dt)

Peak to be considered at gate circuit

design

TURN-ON





JUNE 17-21,2001

I0

vD

vGG

vGS

iG

iD

vGS(Io)

RG*(Cgd1+Cgs) RG*(Cgd2+Cgs)Miller plateau

Charge onCgs and Cgd

vGS(th)

Charge on Cgd

MOSFET current

Bipolar transistor current

TURN-OFF



• Main parameters are herein quoted as a nomenclature for equations

• IGBT maximum ratings:

VCES Collector-to-Emitter Breakdown voltage

IC @ TC=25ºC and 100 ºC Continuous Collector Current

ICM Pulsed Collector Current

ILM Clamped Inductive Load Current

IFM diode maximum Forward Current

VGE Gate-to-Emitter Voltage

PD @ TC=25ºC Maximum Power Dissipation

121. IGBT/MOSFET SWITCHINGS- IGBT/MOSFET CHARACTERISTICS


JUNE 17-21,2001



• Maximal values on the market:

131. IGBT/MOSFET SWITCHINGS- IGBT Maximum Ratings

VCE

IC

2400A1700V

1200A3300V

600A6500V

HIGH POWER EUPEC IGBTs MODULES ON

THE MARKET


JUNE 17-21,2001



• Design of gate drivers is depending on the switching characteristics.• The switching times given in datasheets as electrical characteristics

are for resistive load switching.Qg Total gate charge (turn-on) td(off) Turn-off delay timeQge gate-emitter charge (turn-on) tf fall timeQgc gate-collector charge (turn-on) Ets Total switching losstd(on) Turn-on delay time LE internal emitter inductancetr Rise Time Cies Input Capacitancetd(off) Turn-Off Delay Time Coes Output Capacitancetf Fall Time Cres Reverse Transfer CapacitanceEon Turn-On Switching Loss trr Diode Peak Reverse Recovery TimeEoff Turn-Off Switching Loss Irr Diode Peak Reverse Recovery CrtEts Total Switching Loss Qrr Diode Reverse Recovery Chargetd(on) Turn-On Delay Time di(rec)M/dt tr Rise Time Diode Peak Rate of Fall of Recovery

• The performance curves are for half-bridge inductive load since the inductive loads are the most prevalent application for IGBTs

141. IGBT/MOSFET SWITCHINGS- IGBT switching characteristics


JUNE 17-21,2001



V(BR)CES Collector-to-Emitter Breakdown Voltage

∆V(BR)CES/∆TJ Temperature coefficient of breakdown voltage

VCE(on) Collector-to-Emitter saturation voltage

VGE(th) Gate threshold voltage

VGE(th)/∆TJ temperature coefficient of threshold voltage

gfe Forward transconductance

ICES Zero Gate voltage collector current

VFM Diode forward voltage drop

IGES Gate-to-emitter leakage current

151. IGBT/MOSFET SWITCHINGS- Electrical characteristics

- Thermal characteristics

Are not of interest for this presentation


JUNE 17-21,2001



• Modern gate drivers incorporate many protection features. In order to design with these, the IGBT/MOSFET limits of operation and the need of protection circuitry is outlined herein.

• Limits of operation:– Maximum collector current is set up to avoid latch-up.

IGBTs are easy to be paralleled.– Maximum gate-emitter voltage is set by the gate oxide

breakdown considerations. The maximum current that can flow under short-circuit with a maximum gate-emitter voltage is 4-10 times the nominal rated collector current. IGBT will work in active region with VCE=off-state voltage.

– Maximum collector-emitter voltage is set by the breakdown voltage of the internal pnp transistor.

– Maximum junction temperature is 150°C.



JUNE 17-21,2001



• Safe operating area:

Both IGBT and Power MOSFET have square SOA for short switching times. Modern IGBT devices withstand operation at the corners of the SOA for 10us.


Thermal limit for longer switching times

Thermal limit for DC equivalent

VCE

IC

FORWARD

BIAS SOA

VCE

IC

REVERSE

BIAS SOA

Higher dv/dt

Limit by reapplied dVCE/dt


JUNE 17-21,2001



→ Icg flowing into the gate circuit is increasing the gate voltage→ If this voltage exceeds the gate threshold level, collector current

starts to flow→ This current depends on the level of dv/dt and gate off-state

resistance.Negative off-state control voltage and appropriate gate resistance

can prevent occuring cross-conduction. Limited dv/dt can also be a solution, but this can increase losses.


- CROSS-CONDUCTION

When T1 turns-on => VCE1 drops from

Vdc to almost 0

T1

T2

VCE2

VCE1

Vdc

=>(dv/dt)>0 across T2

Cge

RgOFF

Cgc Ico

Icg

Cce

(dv/dt)>0 across T2

Ice

VgOFF


JUNE 17-21,2001



• In a real circuit, the operation points are along the following trajectory due to the switched inductance. These points should be considered as being inside the datasheet SOA.

• These trajectories depend upon stray inductances, parasitic capacitances and switching performance as di/dt, dv/dt. The IGBT package itself has a stray inductance of about 15nH.

• Factors as di/dt, dv/dt can be adjusted through the gate circuit and the OA can be minimized inside the datasheet SOA.


- REAL OPERATION TRAJECTORY

Idealized switching curve

VCE

IC

Overvoltage at turn-off

Overcurrent at turn-on

Turn-off

Turn-on


JUNE 17-21,2001



• Basically a gate driver circuit can be reduced at a voltage supply, a gate driving power module and a gate resistor


• Both supply power and switching control information should be sent to the gate circuitry. These should be done with or withoutpotential separation.

• Moreover, given the power converter topologies with floating power devices, the high side device should be separated from the low-side.

Power +

Power -

Control

signalsIGBT


JUNE 17-21,2001



Possible configurations:• Gate drivers with potential separation:

– Gate driver with inductive transfer of power (power supply at up to 1MHz intermediate frequency) and a direct information transfer;

– Gate driver with inductive transfer of energy (power supply with up to 20kHz intermediate frequency) and optocoupler transfer of information;

• Gate drivers without potential separation:– Gate driver with bootstrap for power supply of high-side and level

shifter of switching control of information.Another classification can be made based on the number of channels

to be controlled:• Simple gate driver with input and output on the same ground level• Simple gate driver for high-side with input and output at different

ground levels• Dual gate driver (or half-bridge) with both low-side and high-side

(level-shift)• Three-Phase gate drivers with 6 independent channels.



JUNE 17-21,2001



• When high-side devices are considered (drivers or High Voltage ICs), the level of the insulation voltage of the level shifter makes the difference. Within IC technologies, the level shifter transistor has a large size and minimizes the possibilities for a high output power.


• To supply the high-side circuitry, a charge pump topology is used, most typically being a bootstrap circuit. => Special need for start-up sequence to charge the bootstrap

Max.gate current

Max.insulation voltage

3A; 100Vxxx

1A; 300Vxxx

0.2A; 1200VIR22xx

AVAILABLE GATE DRIVER ICs


JUNE 17-21,2001



• A positive voltage must be applied on the gate-emitter circuit to turn-on the device.

• The maximum of this voltage is specified in datasheets, usually as 20V. If short-circuit survival is required, this limit should be restricted.

• The minimum value is defined by the condition to have the devicefully saturated when conducting its maximum peak current. [Usually 11.5V]


- GATE VOLTAGE


JUNE 17-21,2001



• To reduce the switching losses at turn-off, a negative voltage should be applied. This is mandatory at high power IGBTs and can be avoided at low power devices. IGBTs usually require a larger negative voltage than power MOSFETs due to:– IGBTs operate at higher voltages => increased dv/dt coupling of

noise

– Ratio of reverse transfer capacitance to input capacitance is larger for IGBTs (Cres/Cies) => increased Miller effect => larger noise coupled from collector to gate.

– High power IGBTs are constructed by paralleling devices and have internal gate resistors =>Drawback: voltage can develop on gateeven with input shorted to emitter.

NOTE Some low-power IGBTs do not need negative voltage by using Cres (reverse transfer) minimization.


- GATE VOLTAGE


JUNE 17-21,2001



• Series gate resistor(s) is employed at both turn-on or turn-off. It is usually implemented by only a passive resistor. Advanced gate control implies one resistor for turn-on and another one for turn-off.

• Different effects of the value of the series gate resistor make room to custom design for different objective functions.

• IGBT/MOSFET Manufacturers are usually suggesting a range of gate resistor values.


- SERIES RESISTOR

LARGE VALUE OF GATE RESISTOR

SMALL VALUE OF GATE RESISTOR

Limit diode lossesAvoid ringing

Limit of the diode recovery voltage

Improve di/dtLimit IGBT switching losses

Avoid cross-conduction


JUNE 17-21,2001



• After establishing the gate control voltages and gate resistors,the design of the gate driver continues with defining the power level of the control signal. The necessary power is a function of operating frequency, bias control voltages and total gate charge. The total gate charge is published in IGBT/MOSFET datasheets, depending on gate control voltage.

• The average current can be calculated by: iS = Q • freq. The total power can be estimated as P = iS • (VG+ - VG-). Usually this power is small.

• The tougher criteria for design is ensuring the peak gate current that can be roughly estimated as: IG(Peak) = (VG+ - VG-)/RG when a single gate resistor is used.


- GATE DRIVER OUTPUT


JUNE 17-21,2001



• Datasheets present the gate charge characteristics versus the gate-emitter voltage. The gate charge necessary for switching is very important for establishing the switching performance of a MOSFET or IGBT. The lower the charge, the lower is the gate drive current needed for a given switching time.

273. GATE DRIVER REQUIREMENTS-GD DEFINITION BASED ON CHARGE


JUNE 17-21,2001

First slope is determined by the input

capacitance that is higher for the second

device

DEVICE WITH SMALLER INPUT CAPACITANCE IS

NOT ALWAYS FASTER

Second device has a higher

transconductance and therefore requires less voltage on its gate for the given amount of

collector current

t1(>t2) t2(<t1)Vge Vge

Qgate Qgate

See different transconductance versus different

input capacitance



• Designer should minimize the parasitic inductances.

• To reduce magnetic fields, all current loops with switching transients should be made to have as small area as possible. The magnetic field is best reduced when using a twisted pair of wires.

• To reduce stray capacitances, the designer should minimize the area of the metal exposed at the switching potential.


- GATE DRIVER CIRCUITRY



• Observing the collector current and voltage waveforms, switching losses can be derived by calculation of the areas of VI regions.

• Switching loss energy at IGBT turn-on:

294.LOSSES-SWITCHING LOSSES


JUNE 17-21,2001

( )

on

DCL

on

RML

onstDCTon

dtdvV

I

dtdi

IIdtdi

LVE

⋅⋅+

+⋅

⋅−⋅=

22

5.05.0

Ic

Vce

IRM also depends on di/dt



• Switching loss energy at IGBT turn-off



JUNE 17-21,2001

tailLDCt

off

L

offstDCL

off

DCToff tIVk

dtdiI

dtdi

LVI

dtdvV

E ��

�ôÖ

��

·

ÙÙä

È�ô

Ö��

�ôÖ

� 5.025.05.022

Ic Vce

Current tail

Technology dependent,

nothing to do on the gate

control!



• Switching loss energy at diode turn-off



JUNE 17-21,2001

diode

L

diodestDCDoff

dtdi

Idtdi

LVE

�ôÖ

��

·Ùä

È�ô

Ö��

2

25.0

ID

VD

Diode recovery depends on (di/dt)



• Conduction losses for diode:

324.LOSSES-CONDUCTION LOSSES


JUNE 17-21,2001

� ��Tf

LonCOND dttitvT

P0

)()(1

� ��Tf

LBDLDiodeoDiode

fDiodeCOND dttitirV

TP

0,,0, )()(

1

where BD is a curve-fitted parameter for diode. Integral across the fundamental period Tf can be reduced to integrals on small conduction

intervals of each diode

• Conduction losses for IGBT/MOSFET:

� ��Tf

LBTLIGBToIGBT

fIGBTCOND dttitirV

TP

0,,0, )()(

1

where BT is a curve-fitted parameter for IGBT/MOSFET. Integral across the fundamental period Tf can be reduced to integrals on small

conduction intervals of each IGBT/MOSFET

• Conduction losses are not very sensitive to gate control.



• Total losses can be calculated by adding up the switching and conduction losses while taking account of the inverter topology,the modulation function for each device and the operation mode or load power factor.

• This calculus can usually be done by computer programs and it is approximate since it does not take into account parasitics and actual gate or DC voltage levels of fluctuation.

• It can be seen that the gate drive circuit (especially Rgate) influences the switching losses by di/dt, dv/dt, IRM, and overvoltage.

334.LOSSES-TOTAL LOSSES


JUNE 17-21,2001



• Steep switching waveforms with up to 15 V/ns or 5A/ns are sources of EMI.

• EMI emissions can appear as:– Conducted (towards the main supply conductors);– Radiated (in form of E- or H-fields).

• Switching power converters are generating conducted EMI in two modes:– Differential (symmetrical) mode currents flowing into connecting line

due to the IGBTs/diodes switching current (di/dt);– Common (asymmetrical) mode interference produced by the high

rate (dv/dt) and parasitic capacitances to the earth ground or connecting lines.

• EMI performance is determined by:– The power stage behavior;– The influence of the gate drive with its components: processing

module, its power supply and its gate driving output block.

345. EMI PESC 2001

VANCOUVER, CANADAJUNE 17-21,2001



• The conducted EMI emission is regulated by different standards, for commercial or military applications (IEC, VDE, FCC, CISPR, so on).

• VDE standards are next presented

355. EMI- EMI STANDARDS FOR MOTOR DRIVE APPLICATIONS


JUNE 17-21,2001

• Various agencies are also specifying standards for radiated EMI.

Noise Voltage[dB]90

60

80

45

VDE upper limit

VDE lower limit

100kHz 1MHz 10MHz 100MHz



• High switching dv/dt and/or di/dt power circuits produce more EMIThese depend on the shape of the gate current and voltage

Rgate; type of power supply (its regulation and -15V versus 0V for switching-off); type of the gate driving output block.

• Diode reverse-recovery current. This is also depending on Rgateon switching off state.

• Spreading paths depend on gate driver realization:– Reference point on earth ground

– Reference point on DC link minus.

as well as parasitic coupling between conductors.

365. EMI-INFLUENCE OF THE GATE DRIVER


JUNE 17-21,2001



NOTE: The stray inductance LE is much important than the term CR/gfe

375. EMI-MATHEMATICAL EXPRESSIONS OF di/dt AND dv/dtThese are approximate relationships that neglect parameters’ variations and the complex operation modes. Example: switching at zero current !-IGBT TURN-ONdiC/dt


JUNE 17-21,2001

ies

gatefe

GEfe

ON

c

C

Ig

dtdv

gdtdi

��ôÖ

Efe

GONies

RMLGEG

Efe

GONies

MillerG

ON

c

Lg

RC

IIVV

Lg

RC

VVdtdi

��

ôôÖ

��

ôôÖ

��ô

Ö

)(

dv/dt

GCGON

LGEG

GC

gate

ON

CE

CRIVV

C

i

dtdv

��ô

Ö

)(



385. EMI- IGBT TURN-OFFdv/dt


JUNE 17-21,2001

GCGoff

LGEG

GC

gate

ON

CE

OFF

GC

CRIVV

C

i

dtdv

dtdv

��ô

Ö�ô

Ö

)(min



• At IGBT turn-on, the complementary freewheeling diode is turning-off and presents reverse recovery current

• Considering the load constant during switching yields:

iDiode+iIGBT=IL => (di/dt)on=-(di/dt)diode

• After diode current reaches the negative peak value, it starts to decrease to zero with a speed (di/dt)Rec depending on the first slope (di/dt) and the diode snap factor (ks):

395. EMI- DIODE TURN-OFF


JUNE 17-21,2001

onsDiodesc dtdi

abskdt

dikdt

di�ô

Ö��ô

Ö��ô

Ö

11

Re• Peak recovery current can be derived from the following eq.:

CONCLUSION On inverter leg topology, diode recovery depends on IGBT turn-on

�

·

ÙÙÙÙ

ä

È

��

ôôôô

Ö��ô

Ö

��ôÖ

diode

RMLrr

DiodeRM

dtdi

IIdtdi

I exp1][



• The connection of the gate control to the DC minus is better than the connection to the earth ground. When the earth ground connection is used, the interference currents are closed throughthe main line. The common mode interferences are the main component in the EMI.

• Controlling EMI emissions requires control of the switching rateand the form of voltages and currents based on the values of gate resistance and the switching off voltage (-15V or 0). Active control of the gate can reduce di/dt thus improving EMI interference.

• In general, reverse recovery dv/dt of the forward diode is large when IGBT’s turn-on current is small instead of large currents. Therefore, the EMI noise level is high with small current in thecases of drive with the same resistance.

• Turn-off di/dt becomes large proportionally to the turn-off current. The surge voltage generated at the turn-off operation is large when the current is large as compared to small current.

405. EMI

-COMPARATIVE ANALYSIS


JUNE 17-21,2001



• Usually, the gate driver is designed based on experiments. This is necessary due to variation of different parameters within theactual inverter building (Lbusbar, Cooling, s.o.)

• Computer models are available for transient analysis

• Gate control circuit can be optimized by computer calculations to have an input value for the experimental tests. The mathematical optimization provides a set of possible values optimizing at different current levels. The designer should select one gate resistor value to cover more or less the entire operation range.



JUNE 17-21,2001



• Optimization criteria can be:– Losses. Analytical expressions of the conduction and switching losses

are grouped within the PWM algorithm equation to provide a way to optimize the gate resistors for overall loss minimization. To improve this optimization, one can define special performance functions able to take account of the difference between the thermal conductivity of the diode and IGBT (there can be a difference factor of 2). The optimization results are provided for each current level and load power factor.

– Operation Range and Cost. Low power inverters (used in appliances or some servo applications) are more sensitive at cost. Optimization criteria can be set-up to allow proper operation without negative gate control voltage, snubbers, less protection at overvoltage peak due to diode recovery. These features are achieved by imposing mathematical constraints for: minimum obtainable (dv/dt)on at highest current, maximum allowable peak voltage due to diode recovery, minimum obtainable (dv/dt)off avoiding cross-conduction.



JUNE 17-21,2001



• The roots of active gate control resides in control of series connected IGBTs

• Series operation of high current IGBTs enlarges the limit of available DC-link voltage of converters. The drawbacks are:

– Unequal voltage sharing across the IGBTs due to:

different delay times small parameter deviation among different devices different reverse recovery behavior of the freewheeling

diodes.

– Increased dv/dt with the number of series connected devices at the

terminals of the inverter leg (larger voltage to be switched).

43



JUNE 17-21,2001



• Balancing is traditionally achieved by passively snubbering each IGBT individually

• To reduce the passive component count and volume, modern activesnubbering methods have been reported. They assume an active control of the gate in order to limit dv/dt and overvoltage.

• The direct control of the collector voltage is achieved within a local feedback loop. Stability requirements imply design of a controller with poles at a higher frequency than the gate circuitry which has a pole at about 1-10MHz. Control bandwidth of 50-90MHz is achieved by high-performance operational amplifiers.

44



JUNE 17-21,2001



• Active control of the voltage slope is achieved by a simple feedback topology:

45



JUNE 17-21,2001

REFERENCE

+

-

POWER DRIVER

Rg

OpAmp

• Implementation can be achieved with Op-Amp such as 5539.

• At high currents, a significant loss reduction can be achieved by controlling the IGBT voltage in closed loop only near the peak rating. The open-loop operation can be considered for the rest of the operation rang. At small currents, overshoot at turn-off is not large.



46



JUNE 17-21,2001

• Possible Drawback: At inductive loads, the IGBT voltage cannot respond to the gate voltage turn-on control until the freewheeling diode has turned-off. The closed loop approach would charge the gate quickly producing a very high di/dt. Additional passive or activedi/dt control is suggested or the reference slope should be limited.

• This solution is not unique. Enabling fixed current sources is also a possibility.



• Another application of active control consists in short-circuit protection. The equivalent gate resistance is modified to turn-off the IGBT with soft shutdown. This avoids the large di/dt and appropriate voltage overshoot present in a simple protection following up a short circuit.

• Examples:

– soft shutdown feature of International Rectifier IR2137

– Powerex trench gate IGBTs with RTC circuit and M57160AL gate driver

• Voltage overshoot protection can be achieved by including an additional stage in the gate driver. At turn-off, Qprot is turned-on and the gate is discharged through it. When the collector voltage reaches the breakdown voltage of the Zener diode, a current will flow through the gate of Qprot and will turn it off. The remaining current would flow through Roff slowing down the dv/dt rate.

• Next solution can reduce switching losses by half while the overshoot is limited very much.

47

8. ACTIVE PROTECTION CIRCUITS


JUNE 17-21,2001



• CONCLUSION: From the expertise acquired by these traditional applications (series connection of IGBTs and gate protection), modern gate drivers adjust di/dt and/or dv/dt independently according to criteria such as EMI emission control.

48 PESC 2001VANCOUVER, CANADA

JUNE 17-21,2001

Vcc=15V

Rgate(ON)

Rgate(Off)

Q3

Q4 Qprot



• The gate resistor can be rated to reduce EMI emission, but such fixed value would increase losses.These different constraints would lead to different values of the gate resistors during operation. Influence of different gate resistor values on (di/dt) is next presented:

49

9. ADVANCED METHODS OF ACTIVE GATE CONTROL- PRINCIPLE


JUNE 17-21,2001

Rgateincreases

Rg=10 Rg=100

Rg=1k

t

Ic[turn-on] Ic[turn-off]

t

Rg=10Rg=100

Rg=1k

Rgateincreases

NOTE: Numerical values are of example only.



• Different constraints shown over the switching waveforms:

50



JUNE 17-21,2001

t

t

t

Need Small Rg to reduce losses

Vgate

Collectorcurrent

Collectorvoltage

Need Small Rg to speed up switching and reduce losses

Need large Rg to limit di/dt

Need Small Rg to speed-up charging to threshold

Need small Rg to increase dv/dt



• Active di/dt and dv/dt control is achieved in modern research by feedback control of the gate current based on the device currentor voltage slopes.

• Sensing current or voltage slopes is carried out by:– direct sensing [shunt resistor or Kelvin emitter]

– using an information resulted from Miller effect sensing [does not need galvanical separation]

• The goal of this active control can be– Reduction of the EMI emission

– Reduction of snubber circuits

51



JUNE 17-21,2001



• Circuit idea for di/dt control:

52

9. ADVANCED METHODS OF ACTIVE GATE CONTROL- METHODS BASED ON DIRECT SENSING


JUNE 17-21,2001

Regular gate control

1/Rgate

d/dtIsense

+

-

Regular current

Feedback current

Gate current



• Circuit idea for dv/dt control:

53

9. ADVANCED METHODS OF ACTIVE GATE CONTROL- METHODS BASED ON DIRECT SENSING


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Regular gate control

1/Rgate

d/dt VCsense

+ -

Regular current

Feedback current

Gate current

• This method is derived from series connected IGBTs• Main constraints against an easy implementation:

– Fast event time scale that does not allow too much delays within the circuit

– Feedback dependence on IGBT parameters.



549. ADV. METHODS OF ACTIVE GATE CONTROL- THEORETICAL METHOD OF MODIFYING THE GATE

CONTROL VOLTAGE. SOLUTION 1: Idir-Franchaud-Bausiere


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• Turn-on waveforms are adjusted through a gate control voltage waveform. An intermediate voltage level is introduced in order to decrease the gate current level on the first slope of turn-on. The voltage level and the length of the time interval with this voltage level can be adjusted.

Vs

Vgate

tst t

Ic Vs=6.1V

Vs=5.3V

Vs=4.6V

Covers the time interval when

current is rising



559. ADV. METHODS OF ACTIVE GATE CONTROL- THEORETICAL METHOD OF MODIFYING THE GATE

CONTROL VOLTAGE. SOLUTION 1: Idir-Franchaud-Bausiere


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• The collector current can be limited beyond a maximum rate of rise by selecting an appropriate Vs. The IGBT/MOSFET would behave as an inductor with variable inductance.

• Measured radiated EMI is proving the advantage of reducing the di/dt slope.

• However, this simple experiment is not very easy to be implemented.



569. ADV. METHODS OF ACTIVE GATE CONTROL- METHOD USING THE MILLER EFFECT VOLTAGE.

SOLUTION 2: Musumeci-Raciti-Testa-Galuzzo-Melito


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Vcc=15V

Rgate(ON)

Rgate(Off)

Regular Gate Control

Miller effect sensing

Enable at turn-on

Enable at turn-off

Current generator

Current sink

Kd/dt

Can be achievedby RC network with C<<Ciss






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• The most difficult part consists in detection of the Miller effect and synchronization of the appropriate current source with this moment.– Simple solution: derivative with high gain;– Evolved solution implies PLL circuit to synchronize the pulses on

the next pulse basis by compensation of any processing delay. Turn-on circuit:

Vin

Delay

S QR

-

Phasecomparator

LPF

Threshold voltage

Ramp generator

Miller effect

sensing

Kd/dt

Power stage buffer

Start current generator after 20%

of Miller time






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• Synchronization of the current generator with the beginning of the Miller plateau, the signal representing detection of the Miller effect is used to set the FF. This FF is reset at turn-off to avoid incorrect operation.

• The output of this FF is phase compared with a signal obtained by delaying the signal enabling the current generator.

• The output of this is generating the variable threshold Vt, that is compared with a ramp voltage synchronized with the input controlsignal.

• After a small number of cycles related to the characteristics of the low-pass filter, the control signal is properly synchronized.



599. ADV. METHODS OF ACTIVE GATE CONTROL- METHOD USING THE SENSED COLLECTOR CURRENT

SOLUTION 3: Takizawa-Igarashi-Kuroki


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• Ensures control of di/dt• The actual implementation considers an unique control circuitry. The

presentation is herein simplified by describing two circuits for turn-on and turn-off.

RESULTS• The advantage of modifying the gate resistor during collector current

rise or fall in order to improve di/dt instead of keeping a single resistor rated for a given di/dt provides advantages on total losses.

• Comparative results at 150A:– Conventional system with snubber => 100% losses– di/dt reduction by a single gate resistor rated for the given di/dt

=> 127% losses– Proposed system with different resistor values when applied

=> 95% losses




SOLUTION 3: Takizawa-Igarashi-Kuroki TURN-ON


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• When turn-on is desired, Sw1 is turned-on and gate is fed through small R1

• When collector current is rising, Sw1 is turned-off by a threshold comparator

• The gate resistance is thus increased to the value of R3

• Turn-on losses are minimized if compared to a conventional system.

Detect d/dt>0[current rise]

Threshold comparator

Ion

S/HIGBT

IgR1 R2 R3

VCC

Comparator

Sw1Sw2

R1||R3

R3

R2||R3 VTH

The goal is to limit di/dt to improve EMI.




SOLUTION 3: Takizawa-Igarashi-Kuroki TURN-ON


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• The di/dt control is executed only at the time of small current with high dv/dt (see EMI description).

• The second comparator judges if supression is executed based on the last value of the IGBT current. When this is less than Ion => algorithm is executed (enable AND and turn-off Sw2), otherwise usual control is involved.

Igate di/dt control

Ic




SOLUTION 3: Takizawa-Igarashi-Kuroki TURN-OFF


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• Turn-off di/dt of the IGBT is less when the gate discharge current is small

• Conventionally, R7 serves as gate discharge path

• When the collector current is falling, the threshold comparator turns-on Sw4

• C1 is discharged through R5 into the gate to increase gate current

• This circuit is more effective at large currents rather than small currents.

Detect d/dt<0[current fall]

Threshold comparator

IoFF

S/HIIGBT

Ig

R8

R5 R6

VCC

Comparator

Sw4

R7

-VCC

C




SOLUTION 3: Takizawa-Igarashi-Kuroki TURN-OFF


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• The di/dt control is executed only AT LARGE CURRENTS. The threshold comparator establishes when di/dt control is employed.

Igate di/dt control

Ic

VCE




SOLUTION 4: V.John-Suh-Lipo


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• A three stage active gate drive is proposed for high-power IGBTs• Design is based on:

– Reduced delay time at both turn-on and turn-off– Reduced turn-on di/dt and the associated reverse recovery effects– Controlled overvoltage at turn-off– Reduced total switching losses at both turn-on and turn-off

• Three intervals are defined for both turn-on and turn-off






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Vgate

Ic

Vc

III III

Vgate

Ic

Vc

III III

Ic,tail

TURN-ON

TURN-OFF



TURN-ON

• First interval: Follows the turn-on command. IGBT should be charged fast by a large gate current in order to minimize the delay time.

• Second interval: Starts when the gate voltage reaches the IGBT’s threshold level. The current injected into the gate is reduced to minimize the effects of the reverse recovery current,the associated overvoltage and the generated EMI. This interval ends when the collector current reaches the load current plus the peak reverse recovery current.

• Third interval: Gate is again rapidly charged to reduce the tail voltage thus reducing the power losses at turn-on.




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First interval: Gate-emitter capacitor should be discharged fast until the rising instant of the collector voltage. Turn-off delay and the power switching loss are reduced. This large gate current pushesthe gate voltage below the threshold level producing a large dv/dtwith low powerloss

• Second interval: Starts when the collector voltage starts to rise by reducing the gate current. The rise of the collector voltage produces a displacement current through the gate-collector capacitance. The gate voltage tends to go up. This reduces turn-off di/dt and accordingly the turn-off overvoltage.

• Third interval: starts at the end of the falling of the collector current. During this interval, the gate voltage should rapidly reach its final negative level. This is achieved by a low gate resistance. The switching time is reduced as well as the noise immunity during the off-state.

NOTE:This 3-interval approach prevents from any IGBT re-turn-on since the gate current is negative throughout the turn-off intervals


SOLUTION 4: V.John-Suh-Lipo TURN-OFF


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SOLUTION 4: V.John-Suh-Lipo IMPLEMENTATION


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To gate

B1

B2

Controlled at turn-on during the second

interval, in the active region (current source)

by the instantaneous load current

Controlled at turn-off during second interval in the active region (current

source) by the instantaneous load

current

M2

M1

Controlled at turn-on during the intervals I

and III to feed the gate through small

R1

Controlled at turn-off during the intervals I

and III to feed the gate through small

R2

MOSFETs allow larger gate current by

operating with rail-to-rail voltage



• This tutorial presents a review of the active gate drivers for motor control applications.

• The first part of the presentation has reminded the basics of IGBT/MOSFET operation and the base requirements for gate driver design.

• The influence of the gate circuit and gate equivalent resistanceon losses and EMI emissions is outlined by theoretical and mathematical considerations.

• Active gate drivers are historically emerging from applications of series connection of IGBT/MOSFET devices or active protection circuitry. Some examples are quoted to show the path towards the active gate control.

6910. CONCLUSION


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• The principle of active gate control to improving losses and EMIemissions in power converters used for motor drive applications is explained.

• A complete review of the most known advanced methods of active gate control is finally included. Merits and demerits of these methods are discussed and it is concluded that they have a nice future in control of intelligent power modules.

• Despite their research flavor, simplified versions of these methods are already in the phase of implementation within industrial gate drivers.

7010. CONCLUSION


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I.Zverev, S.Konrad, H. Voelker, J. Petzoldt, F. Klotz, “Influence of the Gate Drive Technique on the Conducted EMI Behaviors of a Power Converter”, IEEE PESC 1997, vol. 2, pp. 1522-1528

Mitsubishi Electric - “Using IGBT modules”, Sept. 1998E.Motto, “Gate Drive Techniquesfor Large IGBT Modules”, PCIM Magazine, 1996N. McNeil, K. Sheng, B. W. Williams, S. J. Finley, “Assessment of OFF-State Negative Gate Voltage for IGBTs”, IEEE

Transactions on Power Electronics, vol. 13, no. 3, May 1998, pp. 436-440A. R. Hefner, “An Investigation of the Drive Circuit Requirement for the Power Insulated Gate Bipolar Transistor”, IEEE

Transactions on Power Electronics, vol. 4, no. 2, April 1991, pp. 208-218F. Blaabjerg, J. K. Pedersen, “Optimized Design of a Complete Three- Phase PWM-VSI Inverter”, IEEE Transactions on

Power Electronics, vol.12, no.3, May 1997, pp. 567-576D. Neacsu, T. Takahashi, “Computer-Aided Design of a Low-Cost Low-Power Snubberless Three-Phase Inverter”,

COMPEL2000J.P.Ferrieux, F. Forest, P. Lienart, “The Insulated Gate Bipolar Transistor: Switching Mode”, EPE Conference, Aachen,

1989, pp. 171-175Ch. Gerster, P. Hofer-Noser “Gate Controlled dv/dt and di/dt - Limitation in High Power IGBT Converters”, EPE Journal,

vol. 5, no. 3/4, Jan. 1996S. Musumeci, A. Raciti, A. Testa, A. Galluzo, M. Melito, “Switching Behavior Improvement of Insulated Gate-Controlled

Devices”, IEEE Transactions on Power Electronics, vol. 12, no. 4, July 1997S. Takizawa, S. Igarashi, K.Kuroki, “A New di/dt Control Gate Drive Circuit for IGBTs to Reduce EMI Noise and

Switching Losses” IEEE Conference 1998Hwang-Geol Lee, Yo-Han Lee, Bum-Seok Suh, Dong-Seek Hyun, “An Improved Gate Control Scheme for Snubberless

Operation of High Power IGBTs”, Industry Applications Conference, 1997, vol.2, pp. 975-982Soonwook Hong, Yong-Geun Lee, “Active Gate Control Strategy of Series connected IGBTs for High Power PWM

Inverter”, PEDS 1999, vol. 2, pp. 646-452C. Gerster, P. Hofer, N. Karrer, “Gate-Control Strategies for Snubberless Operation of Series Connected IGBTs”, PESC

1996, vol. 2, pp. 1739-1742D.Heath, P.Wood, “Overshoot voltage reduction using IGBT modules with special drivers”, IR Design Tip 99-1D.Neacsu,T.Takahashi,HHNguyen, “Using IR 2137”, IR Design Tip 00-1Idir, Fraunchaud, Bausiere, “How to reduce EMI generated by IGBTs and MOSFETs”, PCIM magazineV.John, B.S.Suh, TA Lipo, “High performance Active Gate Drive for High Power IGBTs”, IAS 1998.

FOR A COMPLETE LIST OF REFERENCES, PLEASE CONTACT THE AUTHOR.

71 SELECTIVE REFERENCESPESC 2001

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